./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.08.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.08.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:22:02,534 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:22:02,539 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:22:02,568 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:22:02,568 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:22:02,572 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:22:02,574 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:22:02,578 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:22:02,580 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:22:02,584 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:22:02,585 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:22:02,586 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:22:02,586 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:22:02,588 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:22:02,589 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:22:02,590 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:22:02,590 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:22:02,591 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:22:02,594 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:22:02,599 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:22:02,601 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:22:02,601 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:22:02,603 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:22:02,603 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:22:02,605 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:22:02,605 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:22:02,605 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:22:02,606 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:22:02,607 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:22:02,607 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:22:02,608 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:22:02,608 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:22:02,609 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:22:02,610 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:22:02,611 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:22:02,611 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:22:02,612 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:22:02,612 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:22:02,612 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:22:02,612 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:22:02,613 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:22:02,614 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:22:02,644 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:22:02,644 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:22:02,644 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:22:02,644 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:22:02,645 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:22:02,646 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:22:02,646 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:22:02,646 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:22:02,646 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:22:02,646 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:22:02,647 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:22:02,647 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:22:02,647 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:22:02,647 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:22:02,647 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:22:02,648 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:22:02,648 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:22:02,648 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:22:02,648 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:22:02,648 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:22:02,648 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:22:02,648 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:22:02,649 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:22:02,649 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:22:02,649 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:22:02,649 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:22:02,649 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:22:02,649 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:22:02,650 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:22:02,650 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:22:02,650 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:22:02,651 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:22:02,651 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 42e706fd1a5bd201d46dd2f3322f156b6d900789b8c9ace16cba5458f69fdc62 [2022-02-21 04:22:02,839 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:22:02,856 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:22:02,858 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:22:02,858 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:22:02,859 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:22:02,860 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2022-02-21 04:22:02,915 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8831a7844/01e47bff7c574fefab383d1378d09b88/FLAG916af00e0 [2022-02-21 04:22:03,301 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:22:03,302 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-1.c [2022-02-21 04:22:03,322 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8831a7844/01e47bff7c574fefab383d1378d09b88/FLAG916af00e0 [2022-02-21 04:22:03,330 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8831a7844/01e47bff7c574fefab383d1378d09b88 [2022-02-21 04:22:03,336 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:22:03,338 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:22:03,339 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:03,339 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:22:03,342 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:22:03,345 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,346 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ce385dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03, skipping insertion in model container [2022-02-21 04:22:03,346 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,351 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:22:03,388 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:22:03,518 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2022-02-21 04:22:03,626 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:03,644 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:22:03,653 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-1.c[671,684] [2022-02-21 04:22:03,688 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:03,702 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:22:03,703 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03 WrapperNode [2022-02-21 04:22:03,703 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:03,704 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:03,705 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:22:03,705 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:22:03,710 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,732 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,806 INFO L137 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 157, statements flattened = 2358 [2022-02-21 04:22:03,807 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:03,808 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:22:03,808 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:22:03,808 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:22:03,814 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,814 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,824 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,825 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,846 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,895 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,898 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,911 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:22:03,912 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:22:03,912 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:22:03,912 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:22:03,913 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (1/1) ... [2022-02-21 04:22:03,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:22:03,926 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:22:03,936 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:22:03,955 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:22:03,969 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:22:03,969 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:22:03,969 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:22:03,969 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:22:04,095 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:22:04,096 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:22:05,162 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:22:05,179 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:22:05,179 INFO L299 CfgBuilder]: Removed 11 assume(true) statements. [2022-02-21 04:22:05,181 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:05 BoogieIcfgContainer [2022-02-21 04:22:05,181 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:22:05,182 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:22:05,182 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:22:05,184 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:22:05,185 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:05,185 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:22:03" (1/3) ... [2022-02-21 04:22:05,185 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bfa9d47 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:05, skipping insertion in model container [2022-02-21 04:22:05,186 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:05,186 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:03" (2/3) ... [2022-02-21 04:22:05,186 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bfa9d47 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:05, skipping insertion in model container [2022-02-21 04:22:05,186 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:05,186 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:05" (3/3) ... [2022-02-21 04:22:05,187 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-1.c [2022-02-21 04:22:05,227 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:22:05,227 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:22:05,227 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:22:05,227 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:22:05,227 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:22:05,227 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:22:05,228 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:22:05,228 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:22:05,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2022-02-21 04:22:05,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:05,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:05,406 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,407 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,407 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:22:05,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,469 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 880 [2022-02-21 04:22:05,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:05,469 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:05,471 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,471 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,477 INFO L791 eck$LassoCheckResult]: Stem: 479#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 910#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25#L1266true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41#L590true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 845#L597true assume !(1 == ~m_i~0);~m_st~0 := 2; 430#L597-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 974#L602-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 163#L607-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 474#L612-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 132#L617-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 277#L622-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 960#L627-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 258#L632-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 550#L637-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 484#L854true assume !(0 == ~M_E~0); 319#L854-2true assume !(0 == ~T1_E~0); 616#L859-1true assume !(0 == ~T2_E~0); 69#L864-1true assume !(0 == ~T3_E~0); 125#L869-1true assume !(0 == ~T4_E~0); 858#L874-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 792#L879-1true assume !(0 == ~T6_E~0); 311#L884-1true assume !(0 == ~T7_E~0); 10#L889-1true assume !(0 == ~T8_E~0); 172#L894-1true assume !(0 == ~E_M~0); 970#L899-1true assume !(0 == ~E_1~0); 489#L904-1true assume !(0 == ~E_2~0); 268#L909-1true assume !(0 == ~E_3~0); 421#L914-1true assume 0 == ~E_4~0;~E_4~0 := 1; 444#L919-1true assume !(0 == ~E_5~0); 218#L924-1true assume !(0 == ~E_6~0); 117#L929-1true assume !(0 == ~E_7~0); 812#L934-1true assume !(0 == ~E_8~0); 256#L939-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19#L418true assume !(1 == ~m_pc~0); 893#L418-2true is_master_triggered_~__retres1~0#1 := 0; 692#L429true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 898#L430true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 601#L1061true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 511#L1061-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 875#L437true assume 1 == ~t1_pc~0; 963#L438true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 609#L448true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 554#L449true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 191#L1069true assume !(0 != activate_threads_~tmp___0~0#1); 803#L1069-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593#L456true assume !(1 == ~t2_pc~0); 419#L456-2true is_transmit2_triggered_~__retres1~2#1 := 0; 864#L467true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 364#L468true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 636#L1077true assume !(0 != activate_threads_~tmp___1~0#1); 345#L1077-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67#L475true assume 1 == ~t3_pc~0; 290#L476true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95#L486true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897#L487true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 773#L1085true assume !(0 != activate_threads_~tmp___2~0#1); 193#L1085-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 688#L494true assume !(1 == ~t4_pc~0); 215#L494-2true is_transmit4_triggered_~__retres1~4#1 := 0; 401#L505true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 358#L506true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 944#L1093true assume !(0 != activate_threads_~tmp___3~0#1); 441#L1093-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93#L513true assume 1 == ~t5_pc~0; 567#L514true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 904#L524true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241#L525true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74#L1101true assume !(0 != activate_threads_~tmp___4~0#1); 881#L1101-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53#L532true assume !(1 == ~t6_pc~0); 393#L532-2true is_transmit6_triggered_~__retres1~6#1 := 0; 293#L543true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 354#L544true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 829#L1109true assume !(0 != activate_threads_~tmp___5~0#1); 176#L1109-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 641#L551true assume 1 == ~t7_pc~0; 650#L552true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 447#L562true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 669#L563true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 998#L1117true assume !(0 != activate_threads_~tmp___6~0#1); 935#L1117-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 284#L570true assume 1 == ~t8_pc~0; 365#L571true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 729#L581true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 491#L582true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 361#L1125true assume !(0 != activate_threads_~tmp___7~0#1); 64#L1125-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 613#L952true assume 1 == ~M_E~0;~M_E~0 := 2; 42#L952-2true assume !(1 == ~T1_E~0); 577#L957-1true assume !(1 == ~T2_E~0); 885#L962-1true assume !(1 == ~T3_E~0); 376#L967-1true assume !(1 == ~T4_E~0); 847#L972-1true assume !(1 == ~T5_E~0); 642#L977-1true assume !(1 == ~T6_E~0); 941#L982-1true assume !(1 == ~T7_E~0); 128#L987-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 133#L992-1true assume !(1 == ~E_M~0); 343#L997-1true assume !(1 == ~E_1~0); 797#L1002-1true assume !(1 == ~E_2~0); 334#L1007-1true assume !(1 == ~E_3~0); 11#L1012-1true assume !(1 == ~E_4~0); 547#L1017-1true assume !(1 == ~E_5~0); 336#L1022-1true assume !(1 == ~E_6~0); 355#L1027-1true assume 1 == ~E_7~0;~E_7~0 := 2; 800#L1032-1true assume !(1 == ~E_8~0); 468#L1037-1true assume { :end_inline_reset_delta_events } true; 569#L1303-2true [2022-02-21 04:22:05,488 INFO L793 eck$LassoCheckResult]: Loop: 569#L1303-2true assume !false; 602#L1304true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 890#L829true assume !true; 563#L844true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28#L590-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 455#L854-3true assume 0 == ~M_E~0;~M_E~0 := 1; 436#L854-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 955#L859-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 917#L864-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 785#L869-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 294#L874-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 344#L879-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 375#L884-3true assume !(0 == ~T7_E~0); 330#L889-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 112#L894-3true assume 0 == ~E_M~0;~E_M~0 := 1; 480#L899-3true assume 0 == ~E_1~0;~E_1~0 := 1; 130#L904-3true assume 0 == ~E_2~0;~E_2~0 := 1; 309#L909-3true assume 0 == ~E_3~0;~E_3~0 := 1; 99#L914-3true assume 0 == ~E_4~0;~E_4~0 := 1; 123#L919-3true assume 0 == ~E_5~0;~E_5~0 := 1; 707#L924-3true assume !(0 == ~E_6~0); 517#L929-3true assume 0 == ~E_7~0;~E_7~0 := 1; 422#L934-3true assume 0 == ~E_8~0;~E_8~0 := 1; 644#L939-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 552#L418-30true assume !(1 == ~m_pc~0); 370#L418-32true is_master_triggered_~__retres1~0#1 := 0; 564#L429-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 304#L430-10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 817#L1061-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147#L1061-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 217#L437-30true assume 1 == ~t1_pc~0; 458#L438-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 360#L448-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 535#L449-10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 901#L1069-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 865#L1069-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 196#L456-30true assume !(1 == ~t2_pc~0); 884#L456-32true is_transmit2_triggered_~__retres1~2#1 := 0; 506#L467-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 874#L468-10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 87#L1077-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 278#L1077-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743#L475-30true assume !(1 == ~t3_pc~0); 33#L475-32true is_transmit3_triggered_~__retres1~3#1 := 0; 435#L486-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 796#L487-10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 888#L1085-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 207#L1085-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 989#L494-30true assume !(1 == ~t4_pc~0); 101#L494-32true is_transmit4_triggered_~__retres1~4#1 := 0; 4#L505-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 716#L506-10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 909#L1093-30true assume !(0 != activate_threads_~tmp___3~0#1); 673#L1093-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 947#L513-30true assume !(1 == ~t5_pc~0); 281#L513-32true is_transmit5_triggered_~__retres1~5#1 := 0; 327#L524-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 872#L525-10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 532#L1101-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 772#L1101-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 287#L532-30true assume 1 == ~t6_pc~0; 948#L533-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66#L543-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75#L544-10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 605#L1109-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 106#L1109-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135#L551-30true assume !(1 == ~t7_pc~0); 685#L551-32true is_transmit7_triggered_~__retres1~7#1 := 0; 620#L562-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98#L563-10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12#L1117-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 194#L1117-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 736#L570-30true assume 1 == ~t8_pc~0; 611#L571-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 134#L581-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108#L582-10true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40#L1125-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 232#L1125-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254#L952-3true assume 1 == ~M_E~0;~M_E~0 := 2; 949#L952-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 732#L957-3true assume !(1 == ~T2_E~0); 745#L962-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 592#L967-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 776#L972-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 488#L977-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 985#L982-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 965#L987-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 224#L992-3true assume 1 == ~E_M~0;~E_M~0 := 2; 350#L997-3true assume !(1 == ~E_1~0); 222#L1002-3true assume 1 == ~E_2~0;~E_2~0 := 2; 445#L1007-3true assume 1 == ~E_3~0;~E_3~0 := 2; 119#L1012-3true assume 1 == ~E_4~0;~E_4~0 := 2; 171#L1017-3true assume 1 == ~E_5~0;~E_5~0 := 2; 310#L1022-3true assume 1 == ~E_6~0;~E_6~0 := 2; 335#L1027-3true assume 1 == ~E_7~0;~E_7~0 := 2; 27#L1032-3true assume 1 == ~E_8~0;~E_8~0 := 2; 416#L1037-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 141#L650-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 744#L697-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 91#L698-1true start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 809#L1322true assume !(0 == start_simulation_~tmp~3#1); 244#L1322-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 62#L650-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 733#L697-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 852#L698-2true stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 20#L1277true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 490#L1284true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 786#L1285true start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 647#L1335true assume !(0 != start_simulation_~tmp___0~1#1); 569#L1303-2true [2022-02-21 04:22:05,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:05,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2022-02-21 04:22:05,499 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:05,500 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637334140] [2022-02-21 04:22:05,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:05,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:05,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:05,670 INFO L290 TraceCheckUtils]: 0: Hoare triple {1003#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {1003#true} is VALID [2022-02-21 04:22:05,671 INFO L290 TraceCheckUtils]: 1: Hoare triple {1003#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {1005#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:05,672 INFO L290 TraceCheckUtils]: 2: Hoare triple {1005#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1005#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:05,672 INFO L290 TraceCheckUtils]: 3: Hoare triple {1005#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1005#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:05,673 INFO L290 TraceCheckUtils]: 4: Hoare triple {1005#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,673 INFO L290 TraceCheckUtils]: 5: Hoare triple {1004#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1004#false} is VALID [2022-02-21 04:22:05,673 INFO L290 TraceCheckUtils]: 6: Hoare triple {1004#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,673 INFO L290 TraceCheckUtils]: 7: Hoare triple {1004#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,673 INFO L290 TraceCheckUtils]: 8: Hoare triple {1004#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,673 INFO L290 TraceCheckUtils]: 9: Hoare triple {1004#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,674 INFO L290 TraceCheckUtils]: 10: Hoare triple {1004#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,674 INFO L290 TraceCheckUtils]: 11: Hoare triple {1004#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,674 INFO L290 TraceCheckUtils]: 12: Hoare triple {1004#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,674 INFO L290 TraceCheckUtils]: 13: Hoare triple {1004#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1004#false} is VALID [2022-02-21 04:22:05,674 INFO L290 TraceCheckUtils]: 14: Hoare triple {1004#false} assume !(0 == ~M_E~0); {1004#false} is VALID [2022-02-21 04:22:05,675 INFO L290 TraceCheckUtils]: 15: Hoare triple {1004#false} assume !(0 == ~T1_E~0); {1004#false} is VALID [2022-02-21 04:22:05,675 INFO L290 TraceCheckUtils]: 16: Hoare triple {1004#false} assume !(0 == ~T2_E~0); {1004#false} is VALID [2022-02-21 04:22:05,675 INFO L290 TraceCheckUtils]: 17: Hoare triple {1004#false} assume !(0 == ~T3_E~0); {1004#false} is VALID [2022-02-21 04:22:05,675 INFO L290 TraceCheckUtils]: 18: Hoare triple {1004#false} assume !(0 == ~T4_E~0); {1004#false} is VALID [2022-02-21 04:22:05,675 INFO L290 TraceCheckUtils]: 19: Hoare triple {1004#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1004#false} is VALID [2022-02-21 04:22:05,676 INFO L290 TraceCheckUtils]: 20: Hoare triple {1004#false} assume !(0 == ~T6_E~0); {1004#false} is VALID [2022-02-21 04:22:05,676 INFO L290 TraceCheckUtils]: 21: Hoare triple {1004#false} assume !(0 == ~T7_E~0); {1004#false} is VALID [2022-02-21 04:22:05,676 INFO L290 TraceCheckUtils]: 22: Hoare triple {1004#false} assume !(0 == ~T8_E~0); {1004#false} is VALID [2022-02-21 04:22:05,676 INFO L290 TraceCheckUtils]: 23: Hoare triple {1004#false} assume !(0 == ~E_M~0); {1004#false} is VALID [2022-02-21 04:22:05,676 INFO L290 TraceCheckUtils]: 24: Hoare triple {1004#false} assume !(0 == ~E_1~0); {1004#false} is VALID [2022-02-21 04:22:05,676 INFO L290 TraceCheckUtils]: 25: Hoare triple {1004#false} assume !(0 == ~E_2~0); {1004#false} is VALID [2022-02-21 04:22:05,677 INFO L290 TraceCheckUtils]: 26: Hoare triple {1004#false} assume !(0 == ~E_3~0); {1004#false} is VALID [2022-02-21 04:22:05,677 INFO L290 TraceCheckUtils]: 27: Hoare triple {1004#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1004#false} is VALID [2022-02-21 04:22:05,677 INFO L290 TraceCheckUtils]: 28: Hoare triple {1004#false} assume !(0 == ~E_5~0); {1004#false} is VALID [2022-02-21 04:22:05,677 INFO L290 TraceCheckUtils]: 29: Hoare triple {1004#false} assume !(0 == ~E_6~0); {1004#false} is VALID [2022-02-21 04:22:05,677 INFO L290 TraceCheckUtils]: 30: Hoare triple {1004#false} assume !(0 == ~E_7~0); {1004#false} is VALID [2022-02-21 04:22:05,677 INFO L290 TraceCheckUtils]: 31: Hoare triple {1004#false} assume !(0 == ~E_8~0); {1004#false} is VALID [2022-02-21 04:22:05,678 INFO L290 TraceCheckUtils]: 32: Hoare triple {1004#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1004#false} is VALID [2022-02-21 04:22:05,678 INFO L290 TraceCheckUtils]: 33: Hoare triple {1004#false} assume !(1 == ~m_pc~0); {1004#false} is VALID [2022-02-21 04:22:05,678 INFO L290 TraceCheckUtils]: 34: Hoare triple {1004#false} is_master_triggered_~__retres1~0#1 := 0; {1004#false} is VALID [2022-02-21 04:22:05,678 INFO L290 TraceCheckUtils]: 35: Hoare triple {1004#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1004#false} is VALID [2022-02-21 04:22:05,678 INFO L290 TraceCheckUtils]: 36: Hoare triple {1004#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {1004#false} is VALID [2022-02-21 04:22:05,679 INFO L290 TraceCheckUtils]: 37: Hoare triple {1004#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1004#false} is VALID [2022-02-21 04:22:05,679 INFO L290 TraceCheckUtils]: 38: Hoare triple {1004#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1004#false} is VALID [2022-02-21 04:22:05,679 INFO L290 TraceCheckUtils]: 39: Hoare triple {1004#false} assume 1 == ~t1_pc~0; {1004#false} is VALID [2022-02-21 04:22:05,679 INFO L290 TraceCheckUtils]: 40: Hoare triple {1004#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1004#false} is VALID [2022-02-21 04:22:05,679 INFO L290 TraceCheckUtils]: 41: Hoare triple {1004#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1004#false} is VALID [2022-02-21 04:22:05,680 INFO L290 TraceCheckUtils]: 42: Hoare triple {1004#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1004#false} is VALID [2022-02-21 04:22:05,680 INFO L290 TraceCheckUtils]: 43: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___0~0#1); {1004#false} is VALID [2022-02-21 04:22:05,680 INFO L290 TraceCheckUtils]: 44: Hoare triple {1004#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1004#false} is VALID [2022-02-21 04:22:05,680 INFO L290 TraceCheckUtils]: 45: Hoare triple {1004#false} assume !(1 == ~t2_pc~0); {1004#false} is VALID [2022-02-21 04:22:05,680 INFO L290 TraceCheckUtils]: 46: Hoare triple {1004#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1004#false} is VALID [2022-02-21 04:22:05,680 INFO L290 TraceCheckUtils]: 47: Hoare triple {1004#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1004#false} is VALID [2022-02-21 04:22:05,681 INFO L290 TraceCheckUtils]: 48: Hoare triple {1004#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1004#false} is VALID [2022-02-21 04:22:05,681 INFO L290 TraceCheckUtils]: 49: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___1~0#1); {1004#false} is VALID [2022-02-21 04:22:05,681 INFO L290 TraceCheckUtils]: 50: Hoare triple {1004#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1004#false} is VALID [2022-02-21 04:22:05,681 INFO L290 TraceCheckUtils]: 51: Hoare triple {1004#false} assume 1 == ~t3_pc~0; {1004#false} is VALID [2022-02-21 04:22:05,681 INFO L290 TraceCheckUtils]: 52: Hoare triple {1004#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1004#false} is VALID [2022-02-21 04:22:05,682 INFO L290 TraceCheckUtils]: 53: Hoare triple {1004#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1004#false} is VALID [2022-02-21 04:22:05,682 INFO L290 TraceCheckUtils]: 54: Hoare triple {1004#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1004#false} is VALID [2022-02-21 04:22:05,682 INFO L290 TraceCheckUtils]: 55: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___2~0#1); {1004#false} is VALID [2022-02-21 04:22:05,682 INFO L290 TraceCheckUtils]: 56: Hoare triple {1004#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1004#false} is VALID [2022-02-21 04:22:05,682 INFO L290 TraceCheckUtils]: 57: Hoare triple {1004#false} assume !(1 == ~t4_pc~0); {1004#false} is VALID [2022-02-21 04:22:05,683 INFO L290 TraceCheckUtils]: 58: Hoare triple {1004#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1004#false} is VALID [2022-02-21 04:22:05,683 INFO L290 TraceCheckUtils]: 59: Hoare triple {1004#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1004#false} is VALID [2022-02-21 04:22:05,683 INFO L290 TraceCheckUtils]: 60: Hoare triple {1004#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1004#false} is VALID [2022-02-21 04:22:05,683 INFO L290 TraceCheckUtils]: 61: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___3~0#1); {1004#false} is VALID [2022-02-21 04:22:05,683 INFO L290 TraceCheckUtils]: 62: Hoare triple {1004#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1004#false} is VALID [2022-02-21 04:22:05,683 INFO L290 TraceCheckUtils]: 63: Hoare triple {1004#false} assume 1 == ~t5_pc~0; {1004#false} is VALID [2022-02-21 04:22:05,684 INFO L290 TraceCheckUtils]: 64: Hoare triple {1004#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1004#false} is VALID [2022-02-21 04:22:05,684 INFO L290 TraceCheckUtils]: 65: Hoare triple {1004#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1004#false} is VALID [2022-02-21 04:22:05,684 INFO L290 TraceCheckUtils]: 66: Hoare triple {1004#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1004#false} is VALID [2022-02-21 04:22:05,684 INFO L290 TraceCheckUtils]: 67: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___4~0#1); {1004#false} is VALID [2022-02-21 04:22:05,684 INFO L290 TraceCheckUtils]: 68: Hoare triple {1004#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1004#false} is VALID [2022-02-21 04:22:05,685 INFO L290 TraceCheckUtils]: 69: Hoare triple {1004#false} assume !(1 == ~t6_pc~0); {1004#false} is VALID [2022-02-21 04:22:05,685 INFO L290 TraceCheckUtils]: 70: Hoare triple {1004#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1004#false} is VALID [2022-02-21 04:22:05,685 INFO L290 TraceCheckUtils]: 71: Hoare triple {1004#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1004#false} is VALID [2022-02-21 04:22:05,685 INFO L290 TraceCheckUtils]: 72: Hoare triple {1004#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1004#false} is VALID [2022-02-21 04:22:05,685 INFO L290 TraceCheckUtils]: 73: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___5~0#1); {1004#false} is VALID [2022-02-21 04:22:05,685 INFO L290 TraceCheckUtils]: 74: Hoare triple {1004#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1004#false} is VALID [2022-02-21 04:22:05,686 INFO L290 TraceCheckUtils]: 75: Hoare triple {1004#false} assume 1 == ~t7_pc~0; {1004#false} is VALID [2022-02-21 04:22:05,686 INFO L290 TraceCheckUtils]: 76: Hoare triple {1004#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1004#false} is VALID [2022-02-21 04:22:05,686 INFO L290 TraceCheckUtils]: 77: Hoare triple {1004#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1004#false} is VALID [2022-02-21 04:22:05,686 INFO L290 TraceCheckUtils]: 78: Hoare triple {1004#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1004#false} is VALID [2022-02-21 04:22:05,686 INFO L290 TraceCheckUtils]: 79: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___6~0#1); {1004#false} is VALID [2022-02-21 04:22:05,687 INFO L290 TraceCheckUtils]: 80: Hoare triple {1004#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1004#false} is VALID [2022-02-21 04:22:05,687 INFO L290 TraceCheckUtils]: 81: Hoare triple {1004#false} assume 1 == ~t8_pc~0; {1004#false} is VALID [2022-02-21 04:22:05,687 INFO L290 TraceCheckUtils]: 82: Hoare triple {1004#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1004#false} is VALID [2022-02-21 04:22:05,687 INFO L290 TraceCheckUtils]: 83: Hoare triple {1004#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1004#false} is VALID [2022-02-21 04:22:05,687 INFO L290 TraceCheckUtils]: 84: Hoare triple {1004#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1004#false} is VALID [2022-02-21 04:22:05,688 INFO L290 TraceCheckUtils]: 85: Hoare triple {1004#false} assume !(0 != activate_threads_~tmp___7~0#1); {1004#false} is VALID [2022-02-21 04:22:05,688 INFO L290 TraceCheckUtils]: 86: Hoare triple {1004#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1004#false} is VALID [2022-02-21 04:22:05,688 INFO L290 TraceCheckUtils]: 87: Hoare triple {1004#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,688 INFO L290 TraceCheckUtils]: 88: Hoare triple {1004#false} assume !(1 == ~T1_E~0); {1004#false} is VALID [2022-02-21 04:22:05,688 INFO L290 TraceCheckUtils]: 89: Hoare triple {1004#false} assume !(1 == ~T2_E~0); {1004#false} is VALID [2022-02-21 04:22:05,688 INFO L290 TraceCheckUtils]: 90: Hoare triple {1004#false} assume !(1 == ~T3_E~0); {1004#false} is VALID [2022-02-21 04:22:05,689 INFO L290 TraceCheckUtils]: 91: Hoare triple {1004#false} assume !(1 == ~T4_E~0); {1004#false} is VALID [2022-02-21 04:22:05,689 INFO L290 TraceCheckUtils]: 92: Hoare triple {1004#false} assume !(1 == ~T5_E~0); {1004#false} is VALID [2022-02-21 04:22:05,689 INFO L290 TraceCheckUtils]: 93: Hoare triple {1004#false} assume !(1 == ~T6_E~0); {1004#false} is VALID [2022-02-21 04:22:05,689 INFO L290 TraceCheckUtils]: 94: Hoare triple {1004#false} assume !(1 == ~T7_E~0); {1004#false} is VALID [2022-02-21 04:22:05,689 INFO L290 TraceCheckUtils]: 95: Hoare triple {1004#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,689 INFO L290 TraceCheckUtils]: 96: Hoare triple {1004#false} assume !(1 == ~E_M~0); {1004#false} is VALID [2022-02-21 04:22:05,690 INFO L290 TraceCheckUtils]: 97: Hoare triple {1004#false} assume !(1 == ~E_1~0); {1004#false} is VALID [2022-02-21 04:22:05,690 INFO L290 TraceCheckUtils]: 98: Hoare triple {1004#false} assume !(1 == ~E_2~0); {1004#false} is VALID [2022-02-21 04:22:05,690 INFO L290 TraceCheckUtils]: 99: Hoare triple {1004#false} assume !(1 == ~E_3~0); {1004#false} is VALID [2022-02-21 04:22:05,690 INFO L290 TraceCheckUtils]: 100: Hoare triple {1004#false} assume !(1 == ~E_4~0); {1004#false} is VALID [2022-02-21 04:22:05,690 INFO L290 TraceCheckUtils]: 101: Hoare triple {1004#false} assume !(1 == ~E_5~0); {1004#false} is VALID [2022-02-21 04:22:05,691 INFO L290 TraceCheckUtils]: 102: Hoare triple {1004#false} assume !(1 == ~E_6~0); {1004#false} is VALID [2022-02-21 04:22:05,691 INFO L290 TraceCheckUtils]: 103: Hoare triple {1004#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1004#false} is VALID [2022-02-21 04:22:05,691 INFO L290 TraceCheckUtils]: 104: Hoare triple {1004#false} assume !(1 == ~E_8~0); {1004#false} is VALID [2022-02-21 04:22:05,691 INFO L290 TraceCheckUtils]: 105: Hoare triple {1004#false} assume { :end_inline_reset_delta_events } true; {1004#false} is VALID [2022-02-21 04:22:05,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:05,693 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:05,693 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637334140] [2022-02-21 04:22:05,693 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637334140] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:05,693 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:05,694 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:05,695 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766493900] [2022-02-21 04:22:05,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:05,698 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:05,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:05,699 INFO L85 PathProgramCache]: Analyzing trace with hash -1450389818, now seen corresponding path program 1 times [2022-02-21 04:22:05,699 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:05,699 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117614076] [2022-02-21 04:22:05,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:05,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:05,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:05,752 INFO L290 TraceCheckUtils]: 0: Hoare triple {1006#true} assume !false; {1006#true} is VALID [2022-02-21 04:22:05,752 INFO L290 TraceCheckUtils]: 1: Hoare triple {1006#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1006#true} is VALID [2022-02-21 04:22:05,753 INFO L290 TraceCheckUtils]: 2: Hoare triple {1006#true} assume !true; {1007#false} is VALID [2022-02-21 04:22:05,753 INFO L290 TraceCheckUtils]: 3: Hoare triple {1007#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1007#false} is VALID [2022-02-21 04:22:05,753 INFO L290 TraceCheckUtils]: 4: Hoare triple {1007#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1007#false} is VALID [2022-02-21 04:22:05,753 INFO L290 TraceCheckUtils]: 5: Hoare triple {1007#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,753 INFO L290 TraceCheckUtils]: 6: Hoare triple {1007#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,753 INFO L290 TraceCheckUtils]: 7: Hoare triple {1007#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 8: Hoare triple {1007#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 9: Hoare triple {1007#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 10: Hoare triple {1007#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 11: Hoare triple {1007#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 12: Hoare triple {1007#false} assume !(0 == ~T7_E~0); {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 13: Hoare triple {1007#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 14: Hoare triple {1007#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,754 INFO L290 TraceCheckUtils]: 15: Hoare triple {1007#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 16: Hoare triple {1007#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 17: Hoare triple {1007#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 18: Hoare triple {1007#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 19: Hoare triple {1007#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 20: Hoare triple {1007#false} assume !(0 == ~E_6~0); {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 21: Hoare triple {1007#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 22: Hoare triple {1007#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 23: Hoare triple {1007#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1007#false} is VALID [2022-02-21 04:22:05,755 INFO L290 TraceCheckUtils]: 24: Hoare triple {1007#false} assume !(1 == ~m_pc~0); {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 25: Hoare triple {1007#false} is_master_triggered_~__retres1~0#1 := 0; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 26: Hoare triple {1007#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 27: Hoare triple {1007#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 28: Hoare triple {1007#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 29: Hoare triple {1007#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 30: Hoare triple {1007#false} assume 1 == ~t1_pc~0; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 31: Hoare triple {1007#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 32: Hoare triple {1007#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1007#false} is VALID [2022-02-21 04:22:05,756 INFO L290 TraceCheckUtils]: 33: Hoare triple {1007#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 34: Hoare triple {1007#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 35: Hoare triple {1007#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 36: Hoare triple {1007#false} assume !(1 == ~t2_pc~0); {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 37: Hoare triple {1007#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 38: Hoare triple {1007#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 39: Hoare triple {1007#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 40: Hoare triple {1007#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 41: Hoare triple {1007#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1007#false} is VALID [2022-02-21 04:22:05,757 INFO L290 TraceCheckUtils]: 42: Hoare triple {1007#false} assume !(1 == ~t3_pc~0); {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 43: Hoare triple {1007#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 44: Hoare triple {1007#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 45: Hoare triple {1007#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 46: Hoare triple {1007#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 47: Hoare triple {1007#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 48: Hoare triple {1007#false} assume !(1 == ~t4_pc~0); {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 49: Hoare triple {1007#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 50: Hoare triple {1007#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 51: Hoare triple {1007#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1007#false} is VALID [2022-02-21 04:22:05,758 INFO L290 TraceCheckUtils]: 52: Hoare triple {1007#false} assume !(0 != activate_threads_~tmp___3~0#1); {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 53: Hoare triple {1007#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 54: Hoare triple {1007#false} assume !(1 == ~t5_pc~0); {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 55: Hoare triple {1007#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 56: Hoare triple {1007#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 57: Hoare triple {1007#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 58: Hoare triple {1007#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 59: Hoare triple {1007#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 60: Hoare triple {1007#false} assume 1 == ~t6_pc~0; {1007#false} is VALID [2022-02-21 04:22:05,759 INFO L290 TraceCheckUtils]: 61: Hoare triple {1007#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 62: Hoare triple {1007#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 63: Hoare triple {1007#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 64: Hoare triple {1007#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 65: Hoare triple {1007#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 66: Hoare triple {1007#false} assume !(1 == ~t7_pc~0); {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 67: Hoare triple {1007#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 68: Hoare triple {1007#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 69: Hoare triple {1007#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1007#false} is VALID [2022-02-21 04:22:05,760 INFO L290 TraceCheckUtils]: 70: Hoare triple {1007#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 71: Hoare triple {1007#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 72: Hoare triple {1007#false} assume 1 == ~t8_pc~0; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 73: Hoare triple {1007#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 74: Hoare triple {1007#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 75: Hoare triple {1007#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 76: Hoare triple {1007#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 77: Hoare triple {1007#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 78: Hoare triple {1007#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,761 INFO L290 TraceCheckUtils]: 79: Hoare triple {1007#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 80: Hoare triple {1007#false} assume !(1 == ~T2_E~0); {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 81: Hoare triple {1007#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 82: Hoare triple {1007#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 83: Hoare triple {1007#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 84: Hoare triple {1007#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 85: Hoare triple {1007#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 86: Hoare triple {1007#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 87: Hoare triple {1007#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,762 INFO L290 TraceCheckUtils]: 88: Hoare triple {1007#false} assume !(1 == ~E_1~0); {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 89: Hoare triple {1007#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 90: Hoare triple {1007#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 91: Hoare triple {1007#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 92: Hoare triple {1007#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 93: Hoare triple {1007#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 94: Hoare triple {1007#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 95: Hoare triple {1007#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 96: Hoare triple {1007#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {1007#false} is VALID [2022-02-21 04:22:05,763 INFO L290 TraceCheckUtils]: 97: Hoare triple {1007#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 98: Hoare triple {1007#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 99: Hoare triple {1007#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 100: Hoare triple {1007#false} assume !(0 == start_simulation_~tmp~3#1); {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 101: Hoare triple {1007#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 102: Hoare triple {1007#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 103: Hoare triple {1007#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 104: Hoare triple {1007#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 105: Hoare triple {1007#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1007#false} is VALID [2022-02-21 04:22:05,764 INFO L290 TraceCheckUtils]: 106: Hoare triple {1007#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1007#false} is VALID [2022-02-21 04:22:05,765 INFO L290 TraceCheckUtils]: 107: Hoare triple {1007#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {1007#false} is VALID [2022-02-21 04:22:05,765 INFO L290 TraceCheckUtils]: 108: Hoare triple {1007#false} assume !(0 != start_simulation_~tmp___0~1#1); {1007#false} is VALID [2022-02-21 04:22:05,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:05,765 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:05,765 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117614076] [2022-02-21 04:22:05,766 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117614076] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:05,766 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:05,766 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:05,766 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003472110] [2022-02-21 04:22:05,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:05,768 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:05,768 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:05,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:05,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:05,792 INFO L87 Difference]: Start difference. First operand has 999 states, 998 states have (on average 1.5140280561122244) internal successors, (1511), 998 states have internal predecessors, (1511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:06,607 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2022-02-21 04:22:06,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:06,609 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,700 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:06,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2022-02-21 04:22:06,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:06,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 993 states and 1481 transitions. [2022-02-21 04:22:06,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:06,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:06,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1481 transitions. [2022-02-21 04:22:06,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:06,790 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-02-21 04:22:06,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1481 transitions. [2022-02-21 04:22:06,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:06,828 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:06,831 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1481 transitions. Second operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,849 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1481 transitions. Second operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,852 INFO L87 Difference]: Start difference. First operand 993 states and 1481 transitions. Second operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:06,887 INFO L93 Difference]: Finished difference Result 993 states and 1481 transitions. [2022-02-21 04:22:06,887 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1481 transitions. [2022-02-21 04:22:06,891 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:06,891 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:06,893 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1481 transitions. [2022-02-21 04:22:06,895 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1481 transitions. [2022-02-21 04:22:06,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:06,921 INFO L93 Difference]: Finished difference Result 993 states and 1481 transitions. [2022-02-21 04:22:06,921 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1481 transitions. [2022-02-21 04:22:06,923 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:06,923 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:06,923 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:06,923 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:06,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4914400805639476) internal successors, (1481), 992 states have internal predecessors, (1481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1481 transitions. [2022-02-21 04:22:06,952 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-02-21 04:22:06,952 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1481 transitions. [2022-02-21 04:22:06,952 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:22:06,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1481 transitions. [2022-02-21 04:22:06,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:06,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:06,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:06,957 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:06,957 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:06,959 INFO L791 eck$LassoCheckResult]: Stem: 2766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2053#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2054#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2091#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 2717#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2718#L602-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2339#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2340#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2280#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2281#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2524#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2497#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2498#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2770#L854 assume !(0 == ~M_E~0); 2584#L854-2 assume !(0 == ~T1_E~0); 2585#L859-1 assume !(0 == ~T2_E~0); 2155#L864-1 assume !(0 == ~T3_E~0); 2156#L869-1 assume !(0 == ~T4_E~0); 2269#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2969#L879-1 assume !(0 == ~T6_E~0); 2572#L884-1 assume !(0 == ~T7_E~0); 2023#L889-1 assume !(0 == ~T8_E~0); 2024#L894-1 assume !(0 == ~E_M~0); 2354#L899-1 assume !(0 == ~E_1~0); 2777#L904-1 assume !(0 == ~E_2~0); 2513#L909-1 assume !(0 == ~E_3~0); 2514#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2708#L919-1 assume !(0 == ~E_5~0); 2434#L924-1 assume !(0 == ~E_6~0); 2252#L929-1 assume !(0 == ~E_7~0); 2253#L934-1 assume !(0 == ~E_8~0); 2494#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2041#L418 assume !(1 == ~m_pc~0); 2013#L418-2 is_master_triggered_~__retres1~0#1 := 0; 2012#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2928#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2877#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2802#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2803#L437 assume 1 == ~t1_pc~0; 2986#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2885#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2838#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2389#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 2390#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2868#L456 assume !(1 == ~t2_pc~0); 2305#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2304#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2643#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2644#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 2619#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2149#L475 assume 1 == ~t3_pc~0; 2150#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2210#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2211#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2964#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 2393#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2394#L494 assume !(1 == ~t4_pc~0); 2429#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2430#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2634#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2635#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 2731#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2205#L513 assume 1 == ~t5_pc~0; 2206#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2431#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2468#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2166#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 2167#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2118#L532 assume !(1 == ~t6_pc~0); 2119#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2270#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2549#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2628#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 2359#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2360#L551 assume 1 == ~t7_pc~0; 2906#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2735#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2736#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2917#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 2995#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2533#L570 assume 1 == ~t8_pc~0; 2534#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2645#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2779#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2639#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 2143#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2144#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 2092#L952-2 assume !(1 == ~T1_E~0); 2093#L957-1 assume !(1 == ~T2_E~0); 2850#L962-1 assume !(1 == ~T3_E~0); 2655#L967-1 assume !(1 == ~T4_E~0); 2656#L972-1 assume !(1 == ~T5_E~0); 2907#L977-1 assume !(1 == ~T6_E~0); 2908#L982-1 assume !(1 == ~T7_E~0); 2272#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2273#L992-1 assume !(1 == ~E_M~0); 2282#L997-1 assume !(1 == ~E_1~0); 2617#L1002-1 assume !(1 == ~E_2~0); 2605#L1007-1 assume !(1 == ~E_3~0); 2025#L1012-1 assume !(1 == ~E_4~0); 2026#L1017-1 assume !(1 == ~E_5~0); 2606#L1022-1 assume !(1 == ~E_6~0); 2607#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2629#L1032-1 assume !(1 == ~E_8~0); 2754#L1037-1 assume { :end_inline_reset_delta_events } true; 2755#L1303-2 [2022-02-21 04:22:06,960 INFO L793 eck$LassoCheckResult]: Loop: 2755#L1303-2 assume !false; 2845#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2036#L829 assume !false; 2799#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2414#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2342#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2745#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2723#L712 assume !(0 != eval_~tmp~0#1); 2724#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2060#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2061#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2726#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2727#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2993#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2967#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2550#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2551#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2618#L884-3 assume !(0 == ~T7_E~0); 2599#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2243#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2244#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2276#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2277#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2217#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2218#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2265#L924-3 assume !(0 == ~E_6~0); 2807#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2709#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2710#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2836#L418-30 assume 1 == ~m_pc~0; 2107#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2108#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2562#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2563#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2306#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2307#L437-30 assume !(1 == ~t1_pc~0); 2432#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2637#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2638#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2825#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2984#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2398#L456-30 assume !(1 == ~t2_pc~0); 2400#L456-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2796#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2797#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2191#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2192#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2525#L475-30 assume 1 == ~t3_pc~0; 2900#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2074#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2725#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2970#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2416#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2417#L494-30 assume 1 == ~t4_pc~0; 2410#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2009#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2010#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2941#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 2920#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2921#L513-30 assume !(1 == ~t5_pc~0); 2530#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2531#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2595#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2821#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2822#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2541#L532-30 assume !(1 == ~t6_pc~0); 2542#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2147#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2148#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2169#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2231#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2232#L551-30 assume 1 == ~t7_pc~0; 2284#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2344#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2216#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2027#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2028#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2395#L570-30 assume 1 == ~t8_pc~0; 2886#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2283#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2235#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2089#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2090#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2456#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2491#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2948#L957-3 assume !(1 == ~T2_E~0); 2949#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2866#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2867#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2775#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2776#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2998#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2444#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2445#L997-3 assume !(1 == ~E_1~0); 2440#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2441#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2256#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2257#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2353#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2571#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2058#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2059#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2296#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2297#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2201#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2202#L1322 assume !(0 == start_simulation_~tmp~3#1); 2470#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2137#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2138#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2950#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 2042#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2043#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2778#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2910#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 2755#L1303-2 [2022-02-21 04:22:06,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:06,961 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2022-02-21 04:22:06,961 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:06,961 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004080367] [2022-02-21 04:22:06,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:06,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:06,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:07,006 INFO L290 TraceCheckUtils]: 0: Hoare triple {4988#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {4988#true} is VALID [2022-02-21 04:22:07,006 INFO L290 TraceCheckUtils]: 1: Hoare triple {4988#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {4990#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:07,007 INFO L290 TraceCheckUtils]: 2: Hoare triple {4990#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {4990#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:07,007 INFO L290 TraceCheckUtils]: 3: Hoare triple {4990#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {4990#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:07,007 INFO L290 TraceCheckUtils]: 4: Hoare triple {4990#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {4990#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:07,008 INFO L290 TraceCheckUtils]: 5: Hoare triple {4990#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {4990#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:07,008 INFO L290 TraceCheckUtils]: 6: Hoare triple {4990#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,008 INFO L290 TraceCheckUtils]: 7: Hoare triple {4989#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,008 INFO L290 TraceCheckUtils]: 8: Hoare triple {4989#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,009 INFO L290 TraceCheckUtils]: 9: Hoare triple {4989#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,009 INFO L290 TraceCheckUtils]: 10: Hoare triple {4989#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,009 INFO L290 TraceCheckUtils]: 11: Hoare triple {4989#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,009 INFO L290 TraceCheckUtils]: 12: Hoare triple {4989#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,010 INFO L290 TraceCheckUtils]: 13: Hoare triple {4989#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {4989#false} is VALID [2022-02-21 04:22:07,010 INFO L290 TraceCheckUtils]: 14: Hoare triple {4989#false} assume !(0 == ~M_E~0); {4989#false} is VALID [2022-02-21 04:22:07,010 INFO L290 TraceCheckUtils]: 15: Hoare triple {4989#false} assume !(0 == ~T1_E~0); {4989#false} is VALID [2022-02-21 04:22:07,010 INFO L290 TraceCheckUtils]: 16: Hoare triple {4989#false} assume !(0 == ~T2_E~0); {4989#false} is VALID [2022-02-21 04:22:07,010 INFO L290 TraceCheckUtils]: 17: Hoare triple {4989#false} assume !(0 == ~T3_E~0); {4989#false} is VALID [2022-02-21 04:22:07,010 INFO L290 TraceCheckUtils]: 18: Hoare triple {4989#false} assume !(0 == ~T4_E~0); {4989#false} is VALID [2022-02-21 04:22:07,011 INFO L290 TraceCheckUtils]: 19: Hoare triple {4989#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {4989#false} is VALID [2022-02-21 04:22:07,011 INFO L290 TraceCheckUtils]: 20: Hoare triple {4989#false} assume !(0 == ~T6_E~0); {4989#false} is VALID [2022-02-21 04:22:07,011 INFO L290 TraceCheckUtils]: 21: Hoare triple {4989#false} assume !(0 == ~T7_E~0); {4989#false} is VALID [2022-02-21 04:22:07,011 INFO L290 TraceCheckUtils]: 22: Hoare triple {4989#false} assume !(0 == ~T8_E~0); {4989#false} is VALID [2022-02-21 04:22:07,012 INFO L290 TraceCheckUtils]: 23: Hoare triple {4989#false} assume !(0 == ~E_M~0); {4989#false} is VALID [2022-02-21 04:22:07,018 INFO L290 TraceCheckUtils]: 24: Hoare triple {4989#false} assume !(0 == ~E_1~0); {4989#false} is VALID [2022-02-21 04:22:07,018 INFO L290 TraceCheckUtils]: 25: Hoare triple {4989#false} assume !(0 == ~E_2~0); {4989#false} is VALID [2022-02-21 04:22:07,019 INFO L290 TraceCheckUtils]: 26: Hoare triple {4989#false} assume !(0 == ~E_3~0); {4989#false} is VALID [2022-02-21 04:22:07,019 INFO L290 TraceCheckUtils]: 27: Hoare triple {4989#false} assume 0 == ~E_4~0;~E_4~0 := 1; {4989#false} is VALID [2022-02-21 04:22:07,020 INFO L290 TraceCheckUtils]: 28: Hoare triple {4989#false} assume !(0 == ~E_5~0); {4989#false} is VALID [2022-02-21 04:22:07,021 INFO L290 TraceCheckUtils]: 29: Hoare triple {4989#false} assume !(0 == ~E_6~0); {4989#false} is VALID [2022-02-21 04:22:07,022 INFO L290 TraceCheckUtils]: 30: Hoare triple {4989#false} assume !(0 == ~E_7~0); {4989#false} is VALID [2022-02-21 04:22:07,022 INFO L290 TraceCheckUtils]: 31: Hoare triple {4989#false} assume !(0 == ~E_8~0); {4989#false} is VALID [2022-02-21 04:22:07,023 INFO L290 TraceCheckUtils]: 32: Hoare triple {4989#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4989#false} is VALID [2022-02-21 04:22:07,025 INFO L290 TraceCheckUtils]: 33: Hoare triple {4989#false} assume !(1 == ~m_pc~0); {4989#false} is VALID [2022-02-21 04:22:07,025 INFO L290 TraceCheckUtils]: 34: Hoare triple {4989#false} is_master_triggered_~__retres1~0#1 := 0; {4989#false} is VALID [2022-02-21 04:22:07,025 INFO L290 TraceCheckUtils]: 35: Hoare triple {4989#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4989#false} is VALID [2022-02-21 04:22:07,025 INFO L290 TraceCheckUtils]: 36: Hoare triple {4989#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4989#false} is VALID [2022-02-21 04:22:07,025 INFO L290 TraceCheckUtils]: 37: Hoare triple {4989#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {4989#false} is VALID [2022-02-21 04:22:07,026 INFO L290 TraceCheckUtils]: 38: Hoare triple {4989#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4989#false} is VALID [2022-02-21 04:22:07,026 INFO L290 TraceCheckUtils]: 39: Hoare triple {4989#false} assume 1 == ~t1_pc~0; {4989#false} is VALID [2022-02-21 04:22:07,026 INFO L290 TraceCheckUtils]: 40: Hoare triple {4989#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {4989#false} is VALID [2022-02-21 04:22:07,026 INFO L290 TraceCheckUtils]: 41: Hoare triple {4989#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4989#false} is VALID [2022-02-21 04:22:07,026 INFO L290 TraceCheckUtils]: 42: Hoare triple {4989#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4989#false} is VALID [2022-02-21 04:22:07,031 INFO L290 TraceCheckUtils]: 43: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___0~0#1); {4989#false} is VALID [2022-02-21 04:22:07,031 INFO L290 TraceCheckUtils]: 44: Hoare triple {4989#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4989#false} is VALID [2022-02-21 04:22:07,031 INFO L290 TraceCheckUtils]: 45: Hoare triple {4989#false} assume !(1 == ~t2_pc~0); {4989#false} is VALID [2022-02-21 04:22:07,031 INFO L290 TraceCheckUtils]: 46: Hoare triple {4989#false} is_transmit2_triggered_~__retres1~2#1 := 0; {4989#false} is VALID [2022-02-21 04:22:07,031 INFO L290 TraceCheckUtils]: 47: Hoare triple {4989#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 48: Hoare triple {4989#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 49: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___1~0#1); {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 50: Hoare triple {4989#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 51: Hoare triple {4989#false} assume 1 == ~t3_pc~0; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 52: Hoare triple {4989#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 53: Hoare triple {4989#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 54: Hoare triple {4989#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 55: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___2~0#1); {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 56: Hoare triple {4989#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 57: Hoare triple {4989#false} assume !(1 == ~t4_pc~0); {4989#false} is VALID [2022-02-21 04:22:07,032 INFO L290 TraceCheckUtils]: 58: Hoare triple {4989#false} is_transmit4_triggered_~__retres1~4#1 := 0; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 59: Hoare triple {4989#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 60: Hoare triple {4989#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 61: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___3~0#1); {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 62: Hoare triple {4989#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 63: Hoare triple {4989#false} assume 1 == ~t5_pc~0; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 64: Hoare triple {4989#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 65: Hoare triple {4989#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 66: Hoare triple {4989#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 67: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___4~0#1); {4989#false} is VALID [2022-02-21 04:22:07,033 INFO L290 TraceCheckUtils]: 68: Hoare triple {4989#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 69: Hoare triple {4989#false} assume !(1 == ~t6_pc~0); {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 70: Hoare triple {4989#false} is_transmit6_triggered_~__retres1~6#1 := 0; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 71: Hoare triple {4989#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 72: Hoare triple {4989#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 73: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___5~0#1); {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 74: Hoare triple {4989#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 75: Hoare triple {4989#false} assume 1 == ~t7_pc~0; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 76: Hoare triple {4989#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 77: Hoare triple {4989#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 78: Hoare triple {4989#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {4989#false} is VALID [2022-02-21 04:22:07,034 INFO L290 TraceCheckUtils]: 79: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___6~0#1); {4989#false} is VALID [2022-02-21 04:22:07,035 INFO L290 TraceCheckUtils]: 80: Hoare triple {4989#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {4989#false} is VALID [2022-02-21 04:22:07,035 INFO L290 TraceCheckUtils]: 81: Hoare triple {4989#false} assume 1 == ~t8_pc~0; {4989#false} is VALID [2022-02-21 04:22:07,035 INFO L290 TraceCheckUtils]: 82: Hoare triple {4989#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {4989#false} is VALID [2022-02-21 04:22:07,035 INFO L290 TraceCheckUtils]: 83: Hoare triple {4989#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {4989#false} is VALID [2022-02-21 04:22:07,035 INFO L290 TraceCheckUtils]: 84: Hoare triple {4989#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {4989#false} is VALID [2022-02-21 04:22:07,035 INFO L290 TraceCheckUtils]: 85: Hoare triple {4989#false} assume !(0 != activate_threads_~tmp___7~0#1); {4989#false} is VALID [2022-02-21 04:22:07,035 INFO L290 TraceCheckUtils]: 86: Hoare triple {4989#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4989#false} is VALID [2022-02-21 04:22:07,039 INFO L290 TraceCheckUtils]: 87: Hoare triple {4989#false} assume 1 == ~M_E~0;~M_E~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,039 INFO L290 TraceCheckUtils]: 88: Hoare triple {4989#false} assume !(1 == ~T1_E~0); {4989#false} is VALID [2022-02-21 04:22:07,040 INFO L290 TraceCheckUtils]: 89: Hoare triple {4989#false} assume !(1 == ~T2_E~0); {4989#false} is VALID [2022-02-21 04:22:07,040 INFO L290 TraceCheckUtils]: 90: Hoare triple {4989#false} assume !(1 == ~T3_E~0); {4989#false} is VALID [2022-02-21 04:22:07,040 INFO L290 TraceCheckUtils]: 91: Hoare triple {4989#false} assume !(1 == ~T4_E~0); {4989#false} is VALID [2022-02-21 04:22:07,041 INFO L290 TraceCheckUtils]: 92: Hoare triple {4989#false} assume !(1 == ~T5_E~0); {4989#false} is VALID [2022-02-21 04:22:07,041 INFO L290 TraceCheckUtils]: 93: Hoare triple {4989#false} assume !(1 == ~T6_E~0); {4989#false} is VALID [2022-02-21 04:22:07,041 INFO L290 TraceCheckUtils]: 94: Hoare triple {4989#false} assume !(1 == ~T7_E~0); {4989#false} is VALID [2022-02-21 04:22:07,043 INFO L290 TraceCheckUtils]: 95: Hoare triple {4989#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,044 INFO L290 TraceCheckUtils]: 96: Hoare triple {4989#false} assume !(1 == ~E_M~0); {4989#false} is VALID [2022-02-21 04:22:07,044 INFO L290 TraceCheckUtils]: 97: Hoare triple {4989#false} assume !(1 == ~E_1~0); {4989#false} is VALID [2022-02-21 04:22:07,044 INFO L290 TraceCheckUtils]: 98: Hoare triple {4989#false} assume !(1 == ~E_2~0); {4989#false} is VALID [2022-02-21 04:22:07,044 INFO L290 TraceCheckUtils]: 99: Hoare triple {4989#false} assume !(1 == ~E_3~0); {4989#false} is VALID [2022-02-21 04:22:07,044 INFO L290 TraceCheckUtils]: 100: Hoare triple {4989#false} assume !(1 == ~E_4~0); {4989#false} is VALID [2022-02-21 04:22:07,044 INFO L290 TraceCheckUtils]: 101: Hoare triple {4989#false} assume !(1 == ~E_5~0); {4989#false} is VALID [2022-02-21 04:22:07,044 INFO L290 TraceCheckUtils]: 102: Hoare triple {4989#false} assume !(1 == ~E_6~0); {4989#false} is VALID [2022-02-21 04:22:07,045 INFO L290 TraceCheckUtils]: 103: Hoare triple {4989#false} assume 1 == ~E_7~0;~E_7~0 := 2; {4989#false} is VALID [2022-02-21 04:22:07,045 INFO L290 TraceCheckUtils]: 104: Hoare triple {4989#false} assume !(1 == ~E_8~0); {4989#false} is VALID [2022-02-21 04:22:07,045 INFO L290 TraceCheckUtils]: 105: Hoare triple {4989#false} assume { :end_inline_reset_delta_events } true; {4989#false} is VALID [2022-02-21 04:22:07,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:07,047 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:07,047 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004080367] [2022-02-21 04:22:07,047 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2004080367] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:07,047 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:07,047 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:07,048 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110496335] [2022-02-21 04:22:07,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:07,048 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:07,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:07,050 INFO L85 PathProgramCache]: Analyzing trace with hash -500294447, now seen corresponding path program 1 times [2022-02-21 04:22:07,050 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:07,050 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774306214] [2022-02-21 04:22:07,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:07,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:07,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:07,139 INFO L290 TraceCheckUtils]: 0: Hoare triple {4991#true} assume !false; {4991#true} is VALID [2022-02-21 04:22:07,139 INFO L290 TraceCheckUtils]: 1: Hoare triple {4991#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {4991#true} is VALID [2022-02-21 04:22:07,139 INFO L290 TraceCheckUtils]: 2: Hoare triple {4991#true} assume !false; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 3: Hoare triple {4991#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 4: Hoare triple {4991#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 5: Hoare triple {4991#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 6: Hoare triple {4991#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 7: Hoare triple {4991#true} assume !(0 != eval_~tmp~0#1); {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 8: Hoare triple {4991#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 9: Hoare triple {4991#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 10: Hoare triple {4991#true} assume 0 == ~M_E~0;~M_E~0 := 1; {4991#true} is VALID [2022-02-21 04:22:07,140 INFO L290 TraceCheckUtils]: 11: Hoare triple {4991#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {4991#true} is VALID [2022-02-21 04:22:07,142 INFO L290 TraceCheckUtils]: 12: Hoare triple {4991#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,143 INFO L290 TraceCheckUtils]: 13: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,143 INFO L290 TraceCheckUtils]: 14: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,143 INFO L290 TraceCheckUtils]: 15: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,144 INFO L290 TraceCheckUtils]: 16: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,144 INFO L290 TraceCheckUtils]: 17: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,144 INFO L290 TraceCheckUtils]: 18: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,144 INFO L290 TraceCheckUtils]: 19: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,145 INFO L290 TraceCheckUtils]: 20: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,145 INFO L290 TraceCheckUtils]: 21: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,145 INFO L290 TraceCheckUtils]: 22: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,146 INFO L290 TraceCheckUtils]: 23: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,146 INFO L290 TraceCheckUtils]: 24: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,146 INFO L290 TraceCheckUtils]: 25: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,146 INFO L290 TraceCheckUtils]: 26: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,147 INFO L290 TraceCheckUtils]: 27: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,147 INFO L290 TraceCheckUtils]: 28: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,150 INFO L290 TraceCheckUtils]: 29: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,150 INFO L290 TraceCheckUtils]: 30: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,150 INFO L290 TraceCheckUtils]: 31: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,151 INFO L290 TraceCheckUtils]: 32: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,151 INFO L290 TraceCheckUtils]: 33: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,151 INFO L290 TraceCheckUtils]: 34: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,152 INFO L290 TraceCheckUtils]: 35: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,152 INFO L290 TraceCheckUtils]: 36: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,152 INFO L290 TraceCheckUtils]: 37: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,152 INFO L290 TraceCheckUtils]: 38: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,154 INFO L290 TraceCheckUtils]: 39: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,154 INFO L290 TraceCheckUtils]: 40: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,154 INFO L290 TraceCheckUtils]: 41: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,154 INFO L290 TraceCheckUtils]: 42: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,155 INFO L290 TraceCheckUtils]: 43: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,155 INFO L290 TraceCheckUtils]: 44: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,156 INFO L290 TraceCheckUtils]: 45: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,156 INFO L290 TraceCheckUtils]: 46: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,157 INFO L290 TraceCheckUtils]: 47: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,158 INFO L290 TraceCheckUtils]: 48: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,158 INFO L290 TraceCheckUtils]: 49: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,159 INFO L290 TraceCheckUtils]: 50: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,160 INFO L290 TraceCheckUtils]: 51: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,160 INFO L290 TraceCheckUtils]: 52: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,160 INFO L290 TraceCheckUtils]: 53: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,161 INFO L290 TraceCheckUtils]: 54: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,161 INFO L290 TraceCheckUtils]: 55: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,162 INFO L290 TraceCheckUtils]: 56: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,162 INFO L290 TraceCheckUtils]: 57: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,162 INFO L290 TraceCheckUtils]: 58: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,163 INFO L290 TraceCheckUtils]: 59: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,165 INFO L290 TraceCheckUtils]: 60: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,166 INFO L290 TraceCheckUtils]: 61: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,168 INFO L290 TraceCheckUtils]: 62: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,171 INFO L290 TraceCheckUtils]: 63: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,171 INFO L290 TraceCheckUtils]: 64: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,172 INFO L290 TraceCheckUtils]: 65: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,172 INFO L290 TraceCheckUtils]: 66: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,172 INFO L290 TraceCheckUtils]: 67: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,172 INFO L290 TraceCheckUtils]: 68: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,173 INFO L290 TraceCheckUtils]: 69: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,173 INFO L290 TraceCheckUtils]: 70: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,173 INFO L290 TraceCheckUtils]: 71: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,174 INFO L290 TraceCheckUtils]: 72: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,174 INFO L290 TraceCheckUtils]: 73: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,174 INFO L290 TraceCheckUtils]: 74: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,175 INFO L290 TraceCheckUtils]: 75: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,175 INFO L290 TraceCheckUtils]: 76: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,175 INFO L290 TraceCheckUtils]: 77: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,176 INFO L290 TraceCheckUtils]: 78: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,176 INFO L290 TraceCheckUtils]: 79: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,176 INFO L290 TraceCheckUtils]: 80: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,177 INFO L290 TraceCheckUtils]: 81: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,177 INFO L290 TraceCheckUtils]: 82: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,177 INFO L290 TraceCheckUtils]: 83: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,177 INFO L290 TraceCheckUtils]: 84: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {4993#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 85: Hoare triple {4993#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 86: Hoare triple {4992#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 87: Hoare triple {4992#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 88: Hoare triple {4992#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 89: Hoare triple {4992#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 90: Hoare triple {4992#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 91: Hoare triple {4992#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 92: Hoare triple {4992#false} assume 1 == ~E_M~0;~E_M~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 93: Hoare triple {4992#false} assume !(1 == ~E_1~0); {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 94: Hoare triple {4992#false} assume 1 == ~E_2~0;~E_2~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 95: Hoare triple {4992#false} assume 1 == ~E_3~0;~E_3~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,178 INFO L290 TraceCheckUtils]: 96: Hoare triple {4992#false} assume 1 == ~E_4~0;~E_4~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 97: Hoare triple {4992#false} assume 1 == ~E_5~0;~E_5~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 98: Hoare triple {4992#false} assume 1 == ~E_6~0;~E_6~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 99: Hoare triple {4992#false} assume 1 == ~E_7~0;~E_7~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 100: Hoare triple {4992#false} assume 1 == ~E_8~0;~E_8~0 := 2; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 101: Hoare triple {4992#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 102: Hoare triple {4992#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 103: Hoare triple {4992#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 104: Hoare triple {4992#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 105: Hoare triple {4992#false} assume !(0 == start_simulation_~tmp~3#1); {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 106: Hoare triple {4992#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 107: Hoare triple {4992#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 108: Hoare triple {4992#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 109: Hoare triple {4992#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {4992#false} is VALID [2022-02-21 04:22:07,179 INFO L290 TraceCheckUtils]: 110: Hoare triple {4992#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {4992#false} is VALID [2022-02-21 04:22:07,180 INFO L290 TraceCheckUtils]: 111: Hoare triple {4992#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {4992#false} is VALID [2022-02-21 04:22:07,180 INFO L290 TraceCheckUtils]: 112: Hoare triple {4992#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {4992#false} is VALID [2022-02-21 04:22:07,180 INFO L290 TraceCheckUtils]: 113: Hoare triple {4992#false} assume !(0 != start_simulation_~tmp___0~1#1); {4992#false} is VALID [2022-02-21 04:22:07,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:07,182 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:07,182 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774306214] [2022-02-21 04:22:07,182 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774306214] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:07,183 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:07,183 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:07,183 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062692381] [2022-02-21 04:22:07,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:07,183 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:07,184 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:07,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:07,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:07,184 INFO L87 Difference]: Start difference. First operand 993 states and 1481 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:07,895 INFO L93 Difference]: Finished difference Result 993 states and 1480 transitions. [2022-02-21 04:22:07,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:07,896 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,960 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:07,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1480 transitions. [2022-02-21 04:22:07,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:08,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1480 transitions. [2022-02-21 04:22:08,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:08,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:08,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1480 transitions. [2022-02-21 04:22:08,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:08,014 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-02-21 04:22:08,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1480 transitions. [2022-02-21 04:22:08,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:08,025 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:08,027 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1480 transitions. Second operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,028 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1480 transitions. Second operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,030 INFO L87 Difference]: Start difference. First operand 993 states and 1480 transitions. Second operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:08,054 INFO L93 Difference]: Finished difference Result 993 states and 1480 transitions. [2022-02-21 04:22:08,054 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1480 transitions. [2022-02-21 04:22:08,055 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:08,056 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:08,057 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1480 transitions. [2022-02-21 04:22:08,059 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1480 transitions. [2022-02-21 04:22:08,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:08,084 INFO L93 Difference]: Finished difference Result 993 states and 1480 transitions. [2022-02-21 04:22:08,084 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1480 transitions. [2022-02-21 04:22:08,085 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:08,085 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:08,085 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:08,085 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:08,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4904330312185297) internal successors, (1480), 992 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1480 transitions. [2022-02-21 04:22:08,111 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-02-21 04:22:08,111 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1480 transitions. [2022-02-21 04:22:08,111 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:22:08,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1480 transitions. [2022-02-21 04:22:08,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:08,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:08,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:08,116 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:08,116 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:08,116 INFO L791 eck$LassoCheckResult]: Stem: 6747#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6034#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6035#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6072#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 6698#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6699#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6320#L607-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6321#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6261#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6262#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6505#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6478#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6479#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6751#L854 assume !(0 == ~M_E~0); 6565#L854-2 assume !(0 == ~T1_E~0); 6566#L859-1 assume !(0 == ~T2_E~0); 6136#L864-1 assume !(0 == ~T3_E~0); 6137#L869-1 assume !(0 == ~T4_E~0); 6250#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6950#L879-1 assume !(0 == ~T6_E~0); 6553#L884-1 assume !(0 == ~T7_E~0); 6004#L889-1 assume !(0 == ~T8_E~0); 6005#L894-1 assume !(0 == ~E_M~0); 6335#L899-1 assume !(0 == ~E_1~0); 6758#L904-1 assume !(0 == ~E_2~0); 6494#L909-1 assume !(0 == ~E_3~0); 6495#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6689#L919-1 assume !(0 == ~E_5~0); 6415#L924-1 assume !(0 == ~E_6~0); 6233#L929-1 assume !(0 == ~E_7~0); 6234#L934-1 assume !(0 == ~E_8~0); 6475#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6022#L418 assume !(1 == ~m_pc~0); 5994#L418-2 is_master_triggered_~__retres1~0#1 := 0; 5993#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6909#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6858#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6783#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6784#L437 assume 1 == ~t1_pc~0; 6967#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6866#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6819#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6370#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 6371#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6849#L456 assume !(1 == ~t2_pc~0); 6286#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6285#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6624#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6625#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 6600#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6130#L475 assume 1 == ~t3_pc~0; 6131#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6191#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6192#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6945#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 6374#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6375#L494 assume !(1 == ~t4_pc~0); 6410#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6411#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6615#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6616#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 6712#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6186#L513 assume 1 == ~t5_pc~0; 6187#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6412#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6449#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6147#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 6148#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6099#L532 assume !(1 == ~t6_pc~0); 6100#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6251#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6530#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6609#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 6340#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6341#L551 assume 1 == ~t7_pc~0; 6887#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6716#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6717#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6898#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 6976#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6514#L570 assume 1 == ~t8_pc~0; 6515#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6626#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6760#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6620#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 6124#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6125#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 6073#L952-2 assume !(1 == ~T1_E~0); 6074#L957-1 assume !(1 == ~T2_E~0); 6831#L962-1 assume !(1 == ~T3_E~0); 6636#L967-1 assume !(1 == ~T4_E~0); 6637#L972-1 assume !(1 == ~T5_E~0); 6888#L977-1 assume !(1 == ~T6_E~0); 6889#L982-1 assume !(1 == ~T7_E~0); 6253#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6254#L992-1 assume !(1 == ~E_M~0); 6263#L997-1 assume !(1 == ~E_1~0); 6598#L1002-1 assume !(1 == ~E_2~0); 6586#L1007-1 assume !(1 == ~E_3~0); 6006#L1012-1 assume !(1 == ~E_4~0); 6007#L1017-1 assume !(1 == ~E_5~0); 6587#L1022-1 assume !(1 == ~E_6~0); 6588#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6610#L1032-1 assume !(1 == ~E_8~0); 6735#L1037-1 assume { :end_inline_reset_delta_events } true; 6736#L1303-2 [2022-02-21 04:22:08,116 INFO L793 eck$LassoCheckResult]: Loop: 6736#L1303-2 assume !false; 6826#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6017#L829 assume !false; 6780#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6395#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6323#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6726#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6704#L712 assume !(0 != eval_~tmp~0#1); 6705#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6041#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6042#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6707#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6708#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6974#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6948#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6531#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6532#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6599#L884-3 assume !(0 == ~T7_E~0); 6580#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6224#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6225#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6257#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6258#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6198#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6199#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6246#L924-3 assume !(0 == ~E_6~0); 6788#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6690#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6691#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6817#L418-30 assume 1 == ~m_pc~0; 6088#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6089#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6543#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6544#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6287#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6288#L437-30 assume !(1 == ~t1_pc~0); 6413#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 6618#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6619#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6806#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6965#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6379#L456-30 assume 1 == ~t2_pc~0; 6380#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6777#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6778#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6172#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6173#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6506#L475-30 assume 1 == ~t3_pc~0; 6881#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6055#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6706#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6951#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6397#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6398#L494-30 assume 1 == ~t4_pc~0; 6391#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5990#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5991#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6922#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 6901#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6902#L513-30 assume 1 == ~t5_pc~0; 6978#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6512#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6576#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6802#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6803#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6522#L532-30 assume !(1 == ~t6_pc~0); 6523#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 6128#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6129#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6150#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6212#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6213#L551-30 assume 1 == ~t7_pc~0; 6265#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6325#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6197#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6008#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6009#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6376#L570-30 assume 1 == ~t8_pc~0; 6867#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6264#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6216#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6070#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6071#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6437#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6472#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6929#L957-3 assume !(1 == ~T2_E~0); 6930#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6847#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6848#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6756#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6757#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6979#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6425#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6426#L997-3 assume !(1 == ~E_1~0); 6421#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6422#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6237#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6238#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6334#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6552#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6039#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6040#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6277#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6278#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6182#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6183#L1322 assume !(0 == start_simulation_~tmp~3#1); 6451#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6118#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6119#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6931#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 6023#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6024#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6759#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6891#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 6736#L1303-2 [2022-02-21 04:22:08,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:08,117 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2022-02-21 04:22:08,117 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:08,117 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146130054] [2022-02-21 04:22:08,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:08,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:08,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:08,147 INFO L290 TraceCheckUtils]: 0: Hoare triple {8969#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {8969#true} is VALID [2022-02-21 04:22:08,148 INFO L290 TraceCheckUtils]: 1: Hoare triple {8969#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {8971#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:08,148 INFO L290 TraceCheckUtils]: 2: Hoare triple {8971#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8971#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:08,149 INFO L290 TraceCheckUtils]: 3: Hoare triple {8971#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8971#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:08,149 INFO L290 TraceCheckUtils]: 4: Hoare triple {8971#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {8971#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:08,149 INFO L290 TraceCheckUtils]: 5: Hoare triple {8971#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8971#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 6: Hoare triple {8971#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8971#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 7: Hoare triple {8971#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 8: Hoare triple {8970#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 9: Hoare triple {8970#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 10: Hoare triple {8970#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 11: Hoare triple {8970#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 12: Hoare triple {8970#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,150 INFO L290 TraceCheckUtils]: 13: Hoare triple {8970#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 14: Hoare triple {8970#false} assume !(0 == ~M_E~0); {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 15: Hoare triple {8970#false} assume !(0 == ~T1_E~0); {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 16: Hoare triple {8970#false} assume !(0 == ~T2_E~0); {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 17: Hoare triple {8970#false} assume !(0 == ~T3_E~0); {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 18: Hoare triple {8970#false} assume !(0 == ~T4_E~0); {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 19: Hoare triple {8970#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 20: Hoare triple {8970#false} assume !(0 == ~T6_E~0); {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 21: Hoare triple {8970#false} assume !(0 == ~T7_E~0); {8970#false} is VALID [2022-02-21 04:22:08,151 INFO L290 TraceCheckUtils]: 22: Hoare triple {8970#false} assume !(0 == ~T8_E~0); {8970#false} is VALID [2022-02-21 04:22:08,152 INFO L290 TraceCheckUtils]: 23: Hoare triple {8970#false} assume !(0 == ~E_M~0); {8970#false} is VALID [2022-02-21 04:22:08,152 INFO L290 TraceCheckUtils]: 24: Hoare triple {8970#false} assume !(0 == ~E_1~0); {8970#false} is VALID [2022-02-21 04:22:08,152 INFO L290 TraceCheckUtils]: 25: Hoare triple {8970#false} assume !(0 == ~E_2~0); {8970#false} is VALID [2022-02-21 04:22:08,152 INFO L290 TraceCheckUtils]: 26: Hoare triple {8970#false} assume !(0 == ~E_3~0); {8970#false} is VALID [2022-02-21 04:22:08,152 INFO L290 TraceCheckUtils]: 27: Hoare triple {8970#false} assume 0 == ~E_4~0;~E_4~0 := 1; {8970#false} is VALID [2022-02-21 04:22:08,152 INFO L290 TraceCheckUtils]: 28: Hoare triple {8970#false} assume !(0 == ~E_5~0); {8970#false} is VALID [2022-02-21 04:22:08,152 INFO L290 TraceCheckUtils]: 29: Hoare triple {8970#false} assume !(0 == ~E_6~0); {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 30: Hoare triple {8970#false} assume !(0 == ~E_7~0); {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 31: Hoare triple {8970#false} assume !(0 == ~E_8~0); {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 32: Hoare triple {8970#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 33: Hoare triple {8970#false} assume !(1 == ~m_pc~0); {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 34: Hoare triple {8970#false} is_master_triggered_~__retres1~0#1 := 0; {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 35: Hoare triple {8970#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 36: Hoare triple {8970#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 37: Hoare triple {8970#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8970#false} is VALID [2022-02-21 04:22:08,153 INFO L290 TraceCheckUtils]: 38: Hoare triple {8970#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 39: Hoare triple {8970#false} assume 1 == ~t1_pc~0; {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 40: Hoare triple {8970#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 41: Hoare triple {8970#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 42: Hoare triple {8970#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 43: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___0~0#1); {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 44: Hoare triple {8970#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 45: Hoare triple {8970#false} assume !(1 == ~t2_pc~0); {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 46: Hoare triple {8970#false} is_transmit2_triggered_~__retres1~2#1 := 0; {8970#false} is VALID [2022-02-21 04:22:08,154 INFO L290 TraceCheckUtils]: 47: Hoare triple {8970#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 48: Hoare triple {8970#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 49: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___1~0#1); {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 50: Hoare triple {8970#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 51: Hoare triple {8970#false} assume 1 == ~t3_pc~0; {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 52: Hoare triple {8970#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 53: Hoare triple {8970#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 54: Hoare triple {8970#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 55: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___2~0#1); {8970#false} is VALID [2022-02-21 04:22:08,155 INFO L290 TraceCheckUtils]: 56: Hoare triple {8970#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8970#false} is VALID [2022-02-21 04:22:08,156 INFO L290 TraceCheckUtils]: 57: Hoare triple {8970#false} assume !(1 == ~t4_pc~0); {8970#false} is VALID [2022-02-21 04:22:08,156 INFO L290 TraceCheckUtils]: 58: Hoare triple {8970#false} is_transmit4_triggered_~__retres1~4#1 := 0; {8970#false} is VALID [2022-02-21 04:22:08,156 INFO L290 TraceCheckUtils]: 59: Hoare triple {8970#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8970#false} is VALID [2022-02-21 04:22:08,156 INFO L290 TraceCheckUtils]: 60: Hoare triple {8970#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8970#false} is VALID [2022-02-21 04:22:08,156 INFO L290 TraceCheckUtils]: 61: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___3~0#1); {8970#false} is VALID [2022-02-21 04:22:08,156 INFO L290 TraceCheckUtils]: 62: Hoare triple {8970#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8970#false} is VALID [2022-02-21 04:22:08,157 INFO L290 TraceCheckUtils]: 63: Hoare triple {8970#false} assume 1 == ~t5_pc~0; {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 64: Hoare triple {8970#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 65: Hoare triple {8970#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 66: Hoare triple {8970#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 67: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___4~0#1); {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 68: Hoare triple {8970#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 69: Hoare triple {8970#false} assume !(1 == ~t6_pc~0); {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 70: Hoare triple {8970#false} is_transmit6_triggered_~__retres1~6#1 := 0; {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 71: Hoare triple {8970#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8970#false} is VALID [2022-02-21 04:22:08,158 INFO L290 TraceCheckUtils]: 72: Hoare triple {8970#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 73: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___5~0#1); {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 74: Hoare triple {8970#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 75: Hoare triple {8970#false} assume 1 == ~t7_pc~0; {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 76: Hoare triple {8970#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 77: Hoare triple {8970#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 78: Hoare triple {8970#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 79: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___6~0#1); {8970#false} is VALID [2022-02-21 04:22:08,159 INFO L290 TraceCheckUtils]: 80: Hoare triple {8970#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 81: Hoare triple {8970#false} assume 1 == ~t8_pc~0; {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 82: Hoare triple {8970#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 83: Hoare triple {8970#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 84: Hoare triple {8970#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 85: Hoare triple {8970#false} assume !(0 != activate_threads_~tmp___7~0#1); {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 86: Hoare triple {8970#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 87: Hoare triple {8970#false} assume 1 == ~M_E~0;~M_E~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,160 INFO L290 TraceCheckUtils]: 88: Hoare triple {8970#false} assume !(1 == ~T1_E~0); {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 89: Hoare triple {8970#false} assume !(1 == ~T2_E~0); {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 90: Hoare triple {8970#false} assume !(1 == ~T3_E~0); {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 91: Hoare triple {8970#false} assume !(1 == ~T4_E~0); {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 92: Hoare triple {8970#false} assume !(1 == ~T5_E~0); {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 93: Hoare triple {8970#false} assume !(1 == ~T6_E~0); {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 94: Hoare triple {8970#false} assume !(1 == ~T7_E~0); {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 95: Hoare triple {8970#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,161 INFO L290 TraceCheckUtils]: 96: Hoare triple {8970#false} assume !(1 == ~E_M~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 97: Hoare triple {8970#false} assume !(1 == ~E_1~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 98: Hoare triple {8970#false} assume !(1 == ~E_2~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 99: Hoare triple {8970#false} assume !(1 == ~E_3~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 100: Hoare triple {8970#false} assume !(1 == ~E_4~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 101: Hoare triple {8970#false} assume !(1 == ~E_5~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 102: Hoare triple {8970#false} assume !(1 == ~E_6~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 103: Hoare triple {8970#false} assume 1 == ~E_7~0;~E_7~0 := 2; {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 104: Hoare triple {8970#false} assume !(1 == ~E_8~0); {8970#false} is VALID [2022-02-21 04:22:08,162 INFO L290 TraceCheckUtils]: 105: Hoare triple {8970#false} assume { :end_inline_reset_delta_events } true; {8970#false} is VALID [2022-02-21 04:22:08,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:08,163 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:08,164 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146130054] [2022-02-21 04:22:08,164 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146130054] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:08,164 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:08,164 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:08,164 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140517468] [2022-02-21 04:22:08,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:08,164 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:08,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:08,165 INFO L85 PathProgramCache]: Analyzing trace with hash -1524153841, now seen corresponding path program 1 times [2022-02-21 04:22:08,165 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:08,166 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173155233] [2022-02-21 04:22:08,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:08,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:08,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:08,214 INFO L290 TraceCheckUtils]: 0: Hoare triple {8972#true} assume !false; {8972#true} is VALID [2022-02-21 04:22:08,214 INFO L290 TraceCheckUtils]: 1: Hoare triple {8972#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8972#true} is VALID [2022-02-21 04:22:08,214 INFO L290 TraceCheckUtils]: 2: Hoare triple {8972#true} assume !false; {8972#true} is VALID [2022-02-21 04:22:08,214 INFO L290 TraceCheckUtils]: 3: Hoare triple {8972#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {8972#true} is VALID [2022-02-21 04:22:08,214 INFO L290 TraceCheckUtils]: 4: Hoare triple {8972#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {8972#true} is VALID [2022-02-21 04:22:08,214 INFO L290 TraceCheckUtils]: 5: Hoare triple {8972#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {8972#true} is VALID [2022-02-21 04:22:08,214 INFO L290 TraceCheckUtils]: 6: Hoare triple {8972#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {8972#true} is VALID [2022-02-21 04:22:08,215 INFO L290 TraceCheckUtils]: 7: Hoare triple {8972#true} assume !(0 != eval_~tmp~0#1); {8972#true} is VALID [2022-02-21 04:22:08,215 INFO L290 TraceCheckUtils]: 8: Hoare triple {8972#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8972#true} is VALID [2022-02-21 04:22:08,215 INFO L290 TraceCheckUtils]: 9: Hoare triple {8972#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8972#true} is VALID [2022-02-21 04:22:08,215 INFO L290 TraceCheckUtils]: 10: Hoare triple {8972#true} assume 0 == ~M_E~0;~M_E~0 := 1; {8972#true} is VALID [2022-02-21 04:22:08,215 INFO L290 TraceCheckUtils]: 11: Hoare triple {8972#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8972#true} is VALID [2022-02-21 04:22:08,215 INFO L290 TraceCheckUtils]: 12: Hoare triple {8972#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,216 INFO L290 TraceCheckUtils]: 13: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,216 INFO L290 TraceCheckUtils]: 14: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,216 INFO L290 TraceCheckUtils]: 15: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,216 INFO L290 TraceCheckUtils]: 16: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,217 INFO L290 TraceCheckUtils]: 17: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,217 INFO L290 TraceCheckUtils]: 18: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,217 INFO L290 TraceCheckUtils]: 19: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,218 INFO L290 TraceCheckUtils]: 20: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,218 INFO L290 TraceCheckUtils]: 21: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,218 INFO L290 TraceCheckUtils]: 22: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,218 INFO L290 TraceCheckUtils]: 23: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,219 INFO L290 TraceCheckUtils]: 24: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,219 INFO L290 TraceCheckUtils]: 25: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,219 INFO L290 TraceCheckUtils]: 26: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,219 INFO L290 TraceCheckUtils]: 27: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,220 INFO L290 TraceCheckUtils]: 28: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,220 INFO L290 TraceCheckUtils]: 29: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,220 INFO L290 TraceCheckUtils]: 30: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,221 INFO L290 TraceCheckUtils]: 31: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,221 INFO L290 TraceCheckUtils]: 32: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,221 INFO L290 TraceCheckUtils]: 33: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,221 INFO L290 TraceCheckUtils]: 34: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,222 INFO L290 TraceCheckUtils]: 35: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,222 INFO L290 TraceCheckUtils]: 36: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,222 INFO L290 TraceCheckUtils]: 37: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,222 INFO L290 TraceCheckUtils]: 38: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,223 INFO L290 TraceCheckUtils]: 39: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,223 INFO L290 TraceCheckUtils]: 40: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,223 INFO L290 TraceCheckUtils]: 41: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,224 INFO L290 TraceCheckUtils]: 42: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,224 INFO L290 TraceCheckUtils]: 43: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,224 INFO L290 TraceCheckUtils]: 44: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,225 INFO L290 TraceCheckUtils]: 45: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,225 INFO L290 TraceCheckUtils]: 46: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,225 INFO L290 TraceCheckUtils]: 47: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,226 INFO L290 TraceCheckUtils]: 48: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,226 INFO L290 TraceCheckUtils]: 49: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,226 INFO L290 TraceCheckUtils]: 50: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,226 INFO L290 TraceCheckUtils]: 51: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,227 INFO L290 TraceCheckUtils]: 52: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,227 INFO L290 TraceCheckUtils]: 53: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,227 INFO L290 TraceCheckUtils]: 54: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,228 INFO L290 TraceCheckUtils]: 55: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,228 INFO L290 TraceCheckUtils]: 56: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,228 INFO L290 TraceCheckUtils]: 57: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,228 INFO L290 TraceCheckUtils]: 58: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,229 INFO L290 TraceCheckUtils]: 59: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,229 INFO L290 TraceCheckUtils]: 60: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,229 INFO L290 TraceCheckUtils]: 61: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,229 INFO L290 TraceCheckUtils]: 62: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,230 INFO L290 TraceCheckUtils]: 63: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,230 INFO L290 TraceCheckUtils]: 64: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,230 INFO L290 TraceCheckUtils]: 65: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,231 INFO L290 TraceCheckUtils]: 66: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,231 INFO L290 TraceCheckUtils]: 67: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,231 INFO L290 TraceCheckUtils]: 68: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,231 INFO L290 TraceCheckUtils]: 69: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,232 INFO L290 TraceCheckUtils]: 70: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,232 INFO L290 TraceCheckUtils]: 71: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,232 INFO L290 TraceCheckUtils]: 72: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,232 INFO L290 TraceCheckUtils]: 73: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,233 INFO L290 TraceCheckUtils]: 74: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,233 INFO L290 TraceCheckUtils]: 75: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,233 INFO L290 TraceCheckUtils]: 76: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,234 INFO L290 TraceCheckUtils]: 77: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,234 INFO L290 TraceCheckUtils]: 78: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,234 INFO L290 TraceCheckUtils]: 79: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,234 INFO L290 TraceCheckUtils]: 80: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,235 INFO L290 TraceCheckUtils]: 81: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,235 INFO L290 TraceCheckUtils]: 82: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,235 INFO L290 TraceCheckUtils]: 83: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,236 INFO L290 TraceCheckUtils]: 84: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8974#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,236 INFO L290 TraceCheckUtils]: 85: Hoare triple {8974#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {8973#false} is VALID [2022-02-21 04:22:08,236 INFO L290 TraceCheckUtils]: 86: Hoare triple {8973#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,236 INFO L290 TraceCheckUtils]: 87: Hoare triple {8973#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,236 INFO L290 TraceCheckUtils]: 88: Hoare triple {8973#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,236 INFO L290 TraceCheckUtils]: 89: Hoare triple {8973#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,236 INFO L290 TraceCheckUtils]: 90: Hoare triple {8973#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 91: Hoare triple {8973#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 92: Hoare triple {8973#false} assume 1 == ~E_M~0;~E_M~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 93: Hoare triple {8973#false} assume !(1 == ~E_1~0); {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 94: Hoare triple {8973#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 95: Hoare triple {8973#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 96: Hoare triple {8973#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 97: Hoare triple {8973#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 98: Hoare triple {8973#false} assume 1 == ~E_6~0;~E_6~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,237 INFO L290 TraceCheckUtils]: 99: Hoare triple {8973#false} assume 1 == ~E_7~0;~E_7~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 100: Hoare triple {8973#false} assume 1 == ~E_8~0;~E_8~0 := 2; {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 101: Hoare triple {8973#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 102: Hoare triple {8973#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 103: Hoare triple {8973#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 104: Hoare triple {8973#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 105: Hoare triple {8973#false} assume !(0 == start_simulation_~tmp~3#1); {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 106: Hoare triple {8973#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {8973#false} is VALID [2022-02-21 04:22:08,238 INFO L290 TraceCheckUtils]: 107: Hoare triple {8973#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {8973#false} is VALID [2022-02-21 04:22:08,239 INFO L290 TraceCheckUtils]: 108: Hoare triple {8973#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {8973#false} is VALID [2022-02-21 04:22:08,239 INFO L290 TraceCheckUtils]: 109: Hoare triple {8973#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {8973#false} is VALID [2022-02-21 04:22:08,239 INFO L290 TraceCheckUtils]: 110: Hoare triple {8973#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8973#false} is VALID [2022-02-21 04:22:08,239 INFO L290 TraceCheckUtils]: 111: Hoare triple {8973#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8973#false} is VALID [2022-02-21 04:22:08,239 INFO L290 TraceCheckUtils]: 112: Hoare triple {8973#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {8973#false} is VALID [2022-02-21 04:22:08,239 INFO L290 TraceCheckUtils]: 113: Hoare triple {8973#false} assume !(0 != start_simulation_~tmp___0~1#1); {8973#false} is VALID [2022-02-21 04:22:08,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:08,240 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:08,240 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173155233] [2022-02-21 04:22:08,240 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173155233] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:08,240 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:08,240 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:08,240 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320594495] [2022-02-21 04:22:08,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:08,241 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:08,241 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:08,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:08,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:08,242 INFO L87 Difference]: Start difference. First operand 993 states and 1480 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:08,955 INFO L93 Difference]: Finished difference Result 993 states and 1479 transitions. [2022-02-21 04:22:08,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:08,955 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,020 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:09,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1479 transitions. [2022-02-21 04:22:09,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:09,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1479 transitions. [2022-02-21 04:22:09,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:09,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:09,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1479 transitions. [2022-02-21 04:22:09,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:09,074 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-02-21 04:22:09,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1479 transitions. [2022-02-21 04:22:09,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:09,083 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:09,084 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1479 transitions. Second operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,086 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1479 transitions. Second operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,087 INFO L87 Difference]: Start difference. First operand 993 states and 1479 transitions. Second operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,112 INFO L93 Difference]: Finished difference Result 993 states and 1479 transitions. [2022-02-21 04:22:09,112 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1479 transitions. [2022-02-21 04:22:09,113 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:09,113 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:09,115 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1479 transitions. [2022-02-21 04:22:09,116 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1479 transitions. [2022-02-21 04:22:09,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,142 INFO L93 Difference]: Finished difference Result 993 states and 1479 transitions. [2022-02-21 04:22:09,142 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1479 transitions. [2022-02-21 04:22:09,143 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:09,143 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:09,143 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:09,143 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:09,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4894259818731117) internal successors, (1479), 992 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1479 transitions. [2022-02-21 04:22:09,169 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-02-21 04:22:09,169 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1479 transitions. [2022-02-21 04:22:09,169 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:22:09,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1479 transitions. [2022-02-21 04:22:09,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:09,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:09,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:09,174 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:09,174 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:09,174 INFO L791 eck$LassoCheckResult]: Stem: 10728#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10729#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10015#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10016#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10053#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 10679#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10680#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10301#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10302#L612-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10242#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10243#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10486#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10459#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10460#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10732#L854 assume !(0 == ~M_E~0); 10546#L854-2 assume !(0 == ~T1_E~0); 10547#L859-1 assume !(0 == ~T2_E~0); 10117#L864-1 assume !(0 == ~T3_E~0); 10118#L869-1 assume !(0 == ~T4_E~0); 10231#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10931#L879-1 assume !(0 == ~T6_E~0); 10534#L884-1 assume !(0 == ~T7_E~0); 9985#L889-1 assume !(0 == ~T8_E~0); 9986#L894-1 assume !(0 == ~E_M~0); 10316#L899-1 assume !(0 == ~E_1~0); 10739#L904-1 assume !(0 == ~E_2~0); 10475#L909-1 assume !(0 == ~E_3~0); 10476#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10670#L919-1 assume !(0 == ~E_5~0); 10396#L924-1 assume !(0 == ~E_6~0); 10214#L929-1 assume !(0 == ~E_7~0); 10215#L934-1 assume !(0 == ~E_8~0); 10456#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10003#L418 assume !(1 == ~m_pc~0); 9975#L418-2 is_master_triggered_~__retres1~0#1 := 0; 9974#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10890#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10839#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10764#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10765#L437 assume 1 == ~t1_pc~0; 10948#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10847#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10800#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10351#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 10352#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10830#L456 assume !(1 == ~t2_pc~0); 10267#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10266#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10605#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10606#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 10581#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10111#L475 assume 1 == ~t3_pc~0; 10112#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10172#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10173#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10926#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 10355#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10356#L494 assume !(1 == ~t4_pc~0); 10391#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10392#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10596#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10597#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 10693#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10167#L513 assume 1 == ~t5_pc~0; 10168#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10393#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10430#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10128#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 10129#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10080#L532 assume !(1 == ~t6_pc~0); 10081#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10232#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10511#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10590#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 10321#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10322#L551 assume 1 == ~t7_pc~0; 10868#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10697#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10698#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10879#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 10957#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10495#L570 assume 1 == ~t8_pc~0; 10496#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10607#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10741#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10601#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 10105#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10106#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 10054#L952-2 assume !(1 == ~T1_E~0); 10055#L957-1 assume !(1 == ~T2_E~0); 10812#L962-1 assume !(1 == ~T3_E~0); 10617#L967-1 assume !(1 == ~T4_E~0); 10618#L972-1 assume !(1 == ~T5_E~0); 10869#L977-1 assume !(1 == ~T6_E~0); 10870#L982-1 assume !(1 == ~T7_E~0); 10234#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10235#L992-1 assume !(1 == ~E_M~0); 10244#L997-1 assume !(1 == ~E_1~0); 10579#L1002-1 assume !(1 == ~E_2~0); 10567#L1007-1 assume !(1 == ~E_3~0); 9987#L1012-1 assume !(1 == ~E_4~0); 9988#L1017-1 assume !(1 == ~E_5~0); 10568#L1022-1 assume !(1 == ~E_6~0); 10569#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10591#L1032-1 assume !(1 == ~E_8~0); 10716#L1037-1 assume { :end_inline_reset_delta_events } true; 10717#L1303-2 [2022-02-21 04:22:09,174 INFO L793 eck$LassoCheckResult]: Loop: 10717#L1303-2 assume !false; 10807#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9998#L829 assume !false; 10761#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10376#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10304#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10707#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10685#L712 assume !(0 != eval_~tmp~0#1); 10686#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10022#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10023#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10688#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10689#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10955#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10929#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10512#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10513#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10580#L884-3 assume !(0 == ~T7_E~0); 10561#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10205#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10206#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10238#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10239#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10179#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10180#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10227#L924-3 assume !(0 == ~E_6~0); 10769#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10671#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10672#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10798#L418-30 assume 1 == ~m_pc~0; 10069#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10070#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10524#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10525#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10268#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10269#L437-30 assume !(1 == ~t1_pc~0); 10394#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 10599#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10600#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10787#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10946#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10360#L456-30 assume 1 == ~t2_pc~0; 10361#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10758#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10759#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10153#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10154#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10487#L475-30 assume !(1 == ~t3_pc~0); 10035#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 10036#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10687#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10932#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10378#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10379#L494-30 assume 1 == ~t4_pc~0; 10372#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9971#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9972#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10903#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 10882#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10883#L513-30 assume !(1 == ~t5_pc~0); 10492#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10493#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10557#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10783#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10784#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10503#L532-30 assume !(1 == ~t6_pc~0); 10504#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10109#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10110#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10131#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10193#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10194#L551-30 assume 1 == ~t7_pc~0; 10246#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10306#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10178#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9989#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9990#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10357#L570-30 assume 1 == ~t8_pc~0; 10848#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10245#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10197#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10051#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10052#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10418#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10453#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10910#L957-3 assume !(1 == ~T2_E~0); 10911#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10828#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10829#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10737#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10738#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10960#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10406#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10407#L997-3 assume !(1 == ~E_1~0); 10402#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10403#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10218#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10219#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10315#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10533#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10020#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10021#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10258#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10259#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10163#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10164#L1322 assume !(0 == start_simulation_~tmp~3#1); 10432#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10099#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10100#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10912#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 10004#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10005#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10740#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10872#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 10717#L1303-2 [2022-02-21 04:22:09,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:09,175 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2022-02-21 04:22:09,175 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:09,175 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4179175] [2022-02-21 04:22:09,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:09,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:09,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:09,195 INFO L290 TraceCheckUtils]: 0: Hoare triple {12950#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {12950#true} is VALID [2022-02-21 04:22:09,195 INFO L290 TraceCheckUtils]: 1: Hoare triple {12950#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {12952#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:09,196 INFO L290 TraceCheckUtils]: 2: Hoare triple {12952#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {12952#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:09,196 INFO L290 TraceCheckUtils]: 3: Hoare triple {12952#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {12952#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:09,196 INFO L290 TraceCheckUtils]: 4: Hoare triple {12952#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {12952#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:09,196 INFO L290 TraceCheckUtils]: 5: Hoare triple {12952#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {12952#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:09,197 INFO L290 TraceCheckUtils]: 6: Hoare triple {12952#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {12952#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:09,197 INFO L290 TraceCheckUtils]: 7: Hoare triple {12952#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {12952#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:09,197 INFO L290 TraceCheckUtils]: 8: Hoare triple {12952#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,197 INFO L290 TraceCheckUtils]: 9: Hoare triple {12951#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,197 INFO L290 TraceCheckUtils]: 10: Hoare triple {12951#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,197 INFO L290 TraceCheckUtils]: 11: Hoare triple {12951#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 12: Hoare triple {12951#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 13: Hoare triple {12951#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 14: Hoare triple {12951#false} assume !(0 == ~M_E~0); {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 15: Hoare triple {12951#false} assume !(0 == ~T1_E~0); {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 16: Hoare triple {12951#false} assume !(0 == ~T2_E~0); {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 17: Hoare triple {12951#false} assume !(0 == ~T3_E~0); {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 18: Hoare triple {12951#false} assume !(0 == ~T4_E~0); {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 19: Hoare triple {12951#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {12951#false} is VALID [2022-02-21 04:22:09,198 INFO L290 TraceCheckUtils]: 20: Hoare triple {12951#false} assume !(0 == ~T6_E~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 21: Hoare triple {12951#false} assume !(0 == ~T7_E~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 22: Hoare triple {12951#false} assume !(0 == ~T8_E~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 23: Hoare triple {12951#false} assume !(0 == ~E_M~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 24: Hoare triple {12951#false} assume !(0 == ~E_1~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 25: Hoare triple {12951#false} assume !(0 == ~E_2~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 26: Hoare triple {12951#false} assume !(0 == ~E_3~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 27: Hoare triple {12951#false} assume 0 == ~E_4~0;~E_4~0 := 1; {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 28: Hoare triple {12951#false} assume !(0 == ~E_5~0); {12951#false} is VALID [2022-02-21 04:22:09,199 INFO L290 TraceCheckUtils]: 29: Hoare triple {12951#false} assume !(0 == ~E_6~0); {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 30: Hoare triple {12951#false} assume !(0 == ~E_7~0); {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 31: Hoare triple {12951#false} assume !(0 == ~E_8~0); {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 32: Hoare triple {12951#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 33: Hoare triple {12951#false} assume !(1 == ~m_pc~0); {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 34: Hoare triple {12951#false} is_master_triggered_~__retres1~0#1 := 0; {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 35: Hoare triple {12951#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 36: Hoare triple {12951#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {12951#false} is VALID [2022-02-21 04:22:09,200 INFO L290 TraceCheckUtils]: 37: Hoare triple {12951#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 38: Hoare triple {12951#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 39: Hoare triple {12951#false} assume 1 == ~t1_pc~0; {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 40: Hoare triple {12951#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 41: Hoare triple {12951#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 42: Hoare triple {12951#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 43: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___0~0#1); {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 44: Hoare triple {12951#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 45: Hoare triple {12951#false} assume !(1 == ~t2_pc~0); {12951#false} is VALID [2022-02-21 04:22:09,201 INFO L290 TraceCheckUtils]: 46: Hoare triple {12951#false} is_transmit2_triggered_~__retres1~2#1 := 0; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 47: Hoare triple {12951#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 48: Hoare triple {12951#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 49: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___1~0#1); {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 50: Hoare triple {12951#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 51: Hoare triple {12951#false} assume 1 == ~t3_pc~0; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 52: Hoare triple {12951#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 53: Hoare triple {12951#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 54: Hoare triple {12951#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12951#false} is VALID [2022-02-21 04:22:09,202 INFO L290 TraceCheckUtils]: 55: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___2~0#1); {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 56: Hoare triple {12951#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 57: Hoare triple {12951#false} assume !(1 == ~t4_pc~0); {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 58: Hoare triple {12951#false} is_transmit4_triggered_~__retres1~4#1 := 0; {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 59: Hoare triple {12951#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 60: Hoare triple {12951#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 61: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___3~0#1); {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 62: Hoare triple {12951#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 63: Hoare triple {12951#false} assume 1 == ~t5_pc~0; {12951#false} is VALID [2022-02-21 04:22:09,203 INFO L290 TraceCheckUtils]: 64: Hoare triple {12951#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 65: Hoare triple {12951#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 66: Hoare triple {12951#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 67: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___4~0#1); {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 68: Hoare triple {12951#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 69: Hoare triple {12951#false} assume !(1 == ~t6_pc~0); {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 70: Hoare triple {12951#false} is_transmit6_triggered_~__retres1~6#1 := 0; {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 71: Hoare triple {12951#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 72: Hoare triple {12951#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12951#false} is VALID [2022-02-21 04:22:09,204 INFO L290 TraceCheckUtils]: 73: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___5~0#1); {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 74: Hoare triple {12951#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 75: Hoare triple {12951#false} assume 1 == ~t7_pc~0; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 76: Hoare triple {12951#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 77: Hoare triple {12951#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 78: Hoare triple {12951#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 79: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___6~0#1); {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 80: Hoare triple {12951#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 81: Hoare triple {12951#false} assume 1 == ~t8_pc~0; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 82: Hoare triple {12951#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {12951#false} is VALID [2022-02-21 04:22:09,205 INFO L290 TraceCheckUtils]: 83: Hoare triple {12951#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 84: Hoare triple {12951#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 85: Hoare triple {12951#false} assume !(0 != activate_threads_~tmp___7~0#1); {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 86: Hoare triple {12951#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 87: Hoare triple {12951#false} assume 1 == ~M_E~0;~M_E~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 88: Hoare triple {12951#false} assume !(1 == ~T1_E~0); {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 89: Hoare triple {12951#false} assume !(1 == ~T2_E~0); {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 90: Hoare triple {12951#false} assume !(1 == ~T3_E~0); {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 91: Hoare triple {12951#false} assume !(1 == ~T4_E~0); {12951#false} is VALID [2022-02-21 04:22:09,206 INFO L290 TraceCheckUtils]: 92: Hoare triple {12951#false} assume !(1 == ~T5_E~0); {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 93: Hoare triple {12951#false} assume !(1 == ~T6_E~0); {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 94: Hoare triple {12951#false} assume !(1 == ~T7_E~0); {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 95: Hoare triple {12951#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 96: Hoare triple {12951#false} assume !(1 == ~E_M~0); {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 97: Hoare triple {12951#false} assume !(1 == ~E_1~0); {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 98: Hoare triple {12951#false} assume !(1 == ~E_2~0); {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 99: Hoare triple {12951#false} assume !(1 == ~E_3~0); {12951#false} is VALID [2022-02-21 04:22:09,207 INFO L290 TraceCheckUtils]: 100: Hoare triple {12951#false} assume !(1 == ~E_4~0); {12951#false} is VALID [2022-02-21 04:22:09,208 INFO L290 TraceCheckUtils]: 101: Hoare triple {12951#false} assume !(1 == ~E_5~0); {12951#false} is VALID [2022-02-21 04:22:09,208 INFO L290 TraceCheckUtils]: 102: Hoare triple {12951#false} assume !(1 == ~E_6~0); {12951#false} is VALID [2022-02-21 04:22:09,208 INFO L290 TraceCheckUtils]: 103: Hoare triple {12951#false} assume 1 == ~E_7~0;~E_7~0 := 2; {12951#false} is VALID [2022-02-21 04:22:09,208 INFO L290 TraceCheckUtils]: 104: Hoare triple {12951#false} assume !(1 == ~E_8~0); {12951#false} is VALID [2022-02-21 04:22:09,208 INFO L290 TraceCheckUtils]: 105: Hoare triple {12951#false} assume { :end_inline_reset_delta_events } true; {12951#false} is VALID [2022-02-21 04:22:09,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:09,208 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:09,209 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4179175] [2022-02-21 04:22:09,209 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [4179175] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:09,209 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:09,209 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:09,209 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833120693] [2022-02-21 04:22:09,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:09,209 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:09,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:09,210 INFO L85 PathProgramCache]: Analyzing trace with hash -494788207, now seen corresponding path program 1 times [2022-02-21 04:22:09,210 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:09,210 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766535097] [2022-02-21 04:22:09,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:09,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:09,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:09,236 INFO L290 TraceCheckUtils]: 0: Hoare triple {12953#true} assume !false; {12953#true} is VALID [2022-02-21 04:22:09,236 INFO L290 TraceCheckUtils]: 1: Hoare triple {12953#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {12953#true} is VALID [2022-02-21 04:22:09,236 INFO L290 TraceCheckUtils]: 2: Hoare triple {12953#true} assume !false; {12953#true} is VALID [2022-02-21 04:22:09,236 INFO L290 TraceCheckUtils]: 3: Hoare triple {12953#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {12953#true} is VALID [2022-02-21 04:22:09,236 INFO L290 TraceCheckUtils]: 4: Hoare triple {12953#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {12953#true} is VALID [2022-02-21 04:22:09,237 INFO L290 TraceCheckUtils]: 5: Hoare triple {12953#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {12953#true} is VALID [2022-02-21 04:22:09,237 INFO L290 TraceCheckUtils]: 6: Hoare triple {12953#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {12953#true} is VALID [2022-02-21 04:22:09,237 INFO L290 TraceCheckUtils]: 7: Hoare triple {12953#true} assume !(0 != eval_~tmp~0#1); {12953#true} is VALID [2022-02-21 04:22:09,237 INFO L290 TraceCheckUtils]: 8: Hoare triple {12953#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {12953#true} is VALID [2022-02-21 04:22:09,237 INFO L290 TraceCheckUtils]: 9: Hoare triple {12953#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {12953#true} is VALID [2022-02-21 04:22:09,237 INFO L290 TraceCheckUtils]: 10: Hoare triple {12953#true} assume 0 == ~M_E~0;~M_E~0 := 1; {12953#true} is VALID [2022-02-21 04:22:09,237 INFO L290 TraceCheckUtils]: 11: Hoare triple {12953#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {12953#true} is VALID [2022-02-21 04:22:09,238 INFO L290 TraceCheckUtils]: 12: Hoare triple {12953#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,238 INFO L290 TraceCheckUtils]: 13: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,238 INFO L290 TraceCheckUtils]: 14: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,238 INFO L290 TraceCheckUtils]: 15: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,239 INFO L290 TraceCheckUtils]: 16: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,239 INFO L290 TraceCheckUtils]: 17: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,239 INFO L290 TraceCheckUtils]: 18: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,239 INFO L290 TraceCheckUtils]: 19: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,240 INFO L290 TraceCheckUtils]: 20: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,240 INFO L290 TraceCheckUtils]: 21: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,240 INFO L290 TraceCheckUtils]: 22: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,240 INFO L290 TraceCheckUtils]: 23: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,241 INFO L290 TraceCheckUtils]: 24: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,241 INFO L290 TraceCheckUtils]: 25: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,241 INFO L290 TraceCheckUtils]: 26: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,241 INFO L290 TraceCheckUtils]: 27: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,242 INFO L290 TraceCheckUtils]: 28: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,242 INFO L290 TraceCheckUtils]: 29: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,242 INFO L290 TraceCheckUtils]: 30: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,242 INFO L290 TraceCheckUtils]: 31: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,243 INFO L290 TraceCheckUtils]: 32: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,243 INFO L290 TraceCheckUtils]: 33: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,243 INFO L290 TraceCheckUtils]: 34: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,243 INFO L290 TraceCheckUtils]: 35: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,244 INFO L290 TraceCheckUtils]: 36: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,244 INFO L290 TraceCheckUtils]: 37: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,244 INFO L290 TraceCheckUtils]: 38: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,244 INFO L290 TraceCheckUtils]: 39: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,245 INFO L290 TraceCheckUtils]: 40: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,245 INFO L290 TraceCheckUtils]: 41: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,245 INFO L290 TraceCheckUtils]: 42: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,245 INFO L290 TraceCheckUtils]: 43: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,246 INFO L290 TraceCheckUtils]: 44: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,246 INFO L290 TraceCheckUtils]: 45: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,246 INFO L290 TraceCheckUtils]: 46: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,246 INFO L290 TraceCheckUtils]: 47: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,247 INFO L290 TraceCheckUtils]: 48: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,247 INFO L290 TraceCheckUtils]: 49: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,247 INFO L290 TraceCheckUtils]: 50: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,247 INFO L290 TraceCheckUtils]: 51: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,248 INFO L290 TraceCheckUtils]: 52: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,248 INFO L290 TraceCheckUtils]: 53: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,248 INFO L290 TraceCheckUtils]: 54: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,248 INFO L290 TraceCheckUtils]: 55: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,249 INFO L290 TraceCheckUtils]: 56: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,249 INFO L290 TraceCheckUtils]: 57: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,249 INFO L290 TraceCheckUtils]: 58: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,249 INFO L290 TraceCheckUtils]: 59: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,250 INFO L290 TraceCheckUtils]: 60: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,250 INFO L290 TraceCheckUtils]: 61: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,250 INFO L290 TraceCheckUtils]: 62: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,250 INFO L290 TraceCheckUtils]: 63: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,251 INFO L290 TraceCheckUtils]: 64: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,251 INFO L290 TraceCheckUtils]: 65: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,251 INFO L290 TraceCheckUtils]: 66: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,251 INFO L290 TraceCheckUtils]: 67: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,252 INFO L290 TraceCheckUtils]: 68: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,252 INFO L290 TraceCheckUtils]: 69: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,252 INFO L290 TraceCheckUtils]: 70: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,252 INFO L290 TraceCheckUtils]: 71: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,253 INFO L290 TraceCheckUtils]: 72: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,253 INFO L290 TraceCheckUtils]: 73: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,253 INFO L290 TraceCheckUtils]: 74: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,253 INFO L290 TraceCheckUtils]: 75: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,254 INFO L290 TraceCheckUtils]: 76: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,254 INFO L290 TraceCheckUtils]: 77: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,254 INFO L290 TraceCheckUtils]: 78: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,254 INFO L290 TraceCheckUtils]: 79: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,255 INFO L290 TraceCheckUtils]: 80: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,255 INFO L290 TraceCheckUtils]: 81: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,255 INFO L290 TraceCheckUtils]: 82: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,255 INFO L290 TraceCheckUtils]: 83: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,256 INFO L290 TraceCheckUtils]: 84: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {12955#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:09,256 INFO L290 TraceCheckUtils]: 85: Hoare triple {12955#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {12954#false} is VALID [2022-02-21 04:22:09,256 INFO L290 TraceCheckUtils]: 86: Hoare triple {12954#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,256 INFO L290 TraceCheckUtils]: 87: Hoare triple {12954#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,256 INFO L290 TraceCheckUtils]: 88: Hoare triple {12954#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,256 INFO L290 TraceCheckUtils]: 89: Hoare triple {12954#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 90: Hoare triple {12954#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 91: Hoare triple {12954#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 92: Hoare triple {12954#false} assume 1 == ~E_M~0;~E_M~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 93: Hoare triple {12954#false} assume !(1 == ~E_1~0); {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 94: Hoare triple {12954#false} assume 1 == ~E_2~0;~E_2~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 95: Hoare triple {12954#false} assume 1 == ~E_3~0;~E_3~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 96: Hoare triple {12954#false} assume 1 == ~E_4~0;~E_4~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 97: Hoare triple {12954#false} assume 1 == ~E_5~0;~E_5~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,257 INFO L290 TraceCheckUtils]: 98: Hoare triple {12954#false} assume 1 == ~E_6~0;~E_6~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 99: Hoare triple {12954#false} assume 1 == ~E_7~0;~E_7~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 100: Hoare triple {12954#false} assume 1 == ~E_8~0;~E_8~0 := 2; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 101: Hoare triple {12954#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 102: Hoare triple {12954#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 103: Hoare triple {12954#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 104: Hoare triple {12954#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 105: Hoare triple {12954#false} assume !(0 == start_simulation_~tmp~3#1); {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 106: Hoare triple {12954#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {12954#false} is VALID [2022-02-21 04:22:09,258 INFO L290 TraceCheckUtils]: 107: Hoare triple {12954#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {12954#false} is VALID [2022-02-21 04:22:09,259 INFO L290 TraceCheckUtils]: 108: Hoare triple {12954#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {12954#false} is VALID [2022-02-21 04:22:09,259 INFO L290 TraceCheckUtils]: 109: Hoare triple {12954#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {12954#false} is VALID [2022-02-21 04:22:09,259 INFO L290 TraceCheckUtils]: 110: Hoare triple {12954#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {12954#false} is VALID [2022-02-21 04:22:09,259 INFO L290 TraceCheckUtils]: 111: Hoare triple {12954#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {12954#false} is VALID [2022-02-21 04:22:09,259 INFO L290 TraceCheckUtils]: 112: Hoare triple {12954#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {12954#false} is VALID [2022-02-21 04:22:09,259 INFO L290 TraceCheckUtils]: 113: Hoare triple {12954#false} assume !(0 != start_simulation_~tmp___0~1#1); {12954#false} is VALID [2022-02-21 04:22:09,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:09,260 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:09,260 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766535097] [2022-02-21 04:22:09,260 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766535097] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:09,260 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:09,260 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:09,260 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890412669] [2022-02-21 04:22:09,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:09,261 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:09,261 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:09,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:09,261 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:09,262 INFO L87 Difference]: Start difference. First operand 993 states and 1479 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,955 INFO L93 Difference]: Finished difference Result 993 states and 1478 transitions. [2022-02-21 04:22:09,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:09,956 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,019 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:10,020 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1478 transitions. [2022-02-21 04:22:10,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:10,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1478 transitions. [2022-02-21 04:22:10,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:10,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:10,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1478 transitions. [2022-02-21 04:22:10,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:10,072 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-02-21 04:22:10,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1478 transitions. [2022-02-21 04:22:10,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:10,080 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:10,082 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1478 transitions. Second operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,083 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1478 transitions. Second operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,085 INFO L87 Difference]: Start difference. First operand 993 states and 1478 transitions. Second operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,110 INFO L93 Difference]: Finished difference Result 993 states and 1478 transitions. [2022-02-21 04:22:10,110 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1478 transitions. [2022-02-21 04:22:10,111 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:10,112 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:10,124 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1478 transitions. [2022-02-21 04:22:10,126 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1478 transitions. [2022-02-21 04:22:10,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,151 INFO L93 Difference]: Finished difference Result 993 states and 1478 transitions. [2022-02-21 04:22:10,151 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1478 transitions. [2022-02-21 04:22:10,152 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:10,152 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:10,152 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:10,153 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:10,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4884189325276937) internal successors, (1478), 992 states have internal predecessors, (1478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1478 transitions. [2022-02-21 04:22:10,178 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-02-21 04:22:10,178 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1478 transitions. [2022-02-21 04:22:10,178 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:22:10,178 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1478 transitions. [2022-02-21 04:22:10,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:10,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:10,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:10,182 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:10,182 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:10,183 INFO L791 eck$LassoCheckResult]: Stem: 14709#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14710#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13996#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13997#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14034#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 14660#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14661#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14282#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14283#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14223#L617-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14224#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14467#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14440#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14441#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14713#L854 assume !(0 == ~M_E~0); 14527#L854-2 assume !(0 == ~T1_E~0); 14528#L859-1 assume !(0 == ~T2_E~0); 14098#L864-1 assume !(0 == ~T3_E~0); 14099#L869-1 assume !(0 == ~T4_E~0); 14212#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14912#L879-1 assume !(0 == ~T6_E~0); 14515#L884-1 assume !(0 == ~T7_E~0); 13966#L889-1 assume !(0 == ~T8_E~0); 13967#L894-1 assume !(0 == ~E_M~0); 14297#L899-1 assume !(0 == ~E_1~0); 14720#L904-1 assume !(0 == ~E_2~0); 14456#L909-1 assume !(0 == ~E_3~0); 14457#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14651#L919-1 assume !(0 == ~E_5~0); 14377#L924-1 assume !(0 == ~E_6~0); 14195#L929-1 assume !(0 == ~E_7~0); 14196#L934-1 assume !(0 == ~E_8~0); 14437#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13984#L418 assume !(1 == ~m_pc~0); 13956#L418-2 is_master_triggered_~__retres1~0#1 := 0; 13955#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14871#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14820#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14745#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14746#L437 assume 1 == ~t1_pc~0; 14929#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14828#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14781#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14332#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 14333#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14811#L456 assume !(1 == ~t2_pc~0); 14248#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14247#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14586#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14587#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 14562#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14092#L475 assume 1 == ~t3_pc~0; 14093#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14153#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14154#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14907#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 14336#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14337#L494 assume !(1 == ~t4_pc~0); 14372#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14373#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14577#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14578#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 14674#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14148#L513 assume 1 == ~t5_pc~0; 14149#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14374#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14411#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14109#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 14110#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14061#L532 assume !(1 == ~t6_pc~0); 14062#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14213#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14492#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14571#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 14302#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14303#L551 assume 1 == ~t7_pc~0; 14849#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14678#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14679#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14860#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 14938#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14476#L570 assume 1 == ~t8_pc~0; 14477#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14588#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14722#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14582#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 14086#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14087#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 14035#L952-2 assume !(1 == ~T1_E~0); 14036#L957-1 assume !(1 == ~T2_E~0); 14793#L962-1 assume !(1 == ~T3_E~0); 14598#L967-1 assume !(1 == ~T4_E~0); 14599#L972-1 assume !(1 == ~T5_E~0); 14850#L977-1 assume !(1 == ~T6_E~0); 14851#L982-1 assume !(1 == ~T7_E~0); 14215#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14216#L992-1 assume !(1 == ~E_M~0); 14225#L997-1 assume !(1 == ~E_1~0); 14560#L1002-1 assume !(1 == ~E_2~0); 14548#L1007-1 assume !(1 == ~E_3~0); 13968#L1012-1 assume !(1 == ~E_4~0); 13969#L1017-1 assume !(1 == ~E_5~0); 14549#L1022-1 assume !(1 == ~E_6~0); 14550#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14572#L1032-1 assume !(1 == ~E_8~0); 14697#L1037-1 assume { :end_inline_reset_delta_events } true; 14698#L1303-2 [2022-02-21 04:22:10,183 INFO L793 eck$LassoCheckResult]: Loop: 14698#L1303-2 assume !false; 14788#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13979#L829 assume !false; 14742#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14357#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14285#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14688#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14666#L712 assume !(0 != eval_~tmp~0#1); 14667#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14003#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14004#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14669#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14670#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14936#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14910#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14493#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14494#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14561#L884-3 assume !(0 == ~T7_E~0); 14542#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14186#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14187#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14219#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14220#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14160#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14161#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14208#L924-3 assume !(0 == ~E_6~0); 14750#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14652#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14653#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14779#L418-30 assume 1 == ~m_pc~0; 14050#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14051#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14505#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14506#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14249#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14250#L437-30 assume !(1 == ~t1_pc~0); 14375#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 14580#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14581#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14768#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14927#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14341#L456-30 assume 1 == ~t2_pc~0; 14342#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14739#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14740#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14134#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14135#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14468#L475-30 assume !(1 == ~t3_pc~0); 14016#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 14017#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14668#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14913#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14359#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14360#L494-30 assume 1 == ~t4_pc~0; 14353#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13952#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13953#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14884#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 14863#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14864#L513-30 assume !(1 == ~t5_pc~0); 14473#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 14474#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14538#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14764#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14765#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14484#L532-30 assume !(1 == ~t6_pc~0); 14485#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 14090#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14091#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14112#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14174#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14175#L551-30 assume 1 == ~t7_pc~0; 14227#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14287#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14159#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13970#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13971#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14338#L570-30 assume !(1 == ~t8_pc~0); 14659#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 14226#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14178#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14032#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14033#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14399#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14434#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14891#L957-3 assume !(1 == ~T2_E~0); 14892#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14809#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14810#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14718#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14719#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14941#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14387#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14388#L997-3 assume !(1 == ~E_1~0); 14383#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14384#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14199#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14200#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14296#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14514#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14001#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14002#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14239#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14240#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14144#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 14145#L1322 assume !(0 == start_simulation_~tmp~3#1); 14413#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14080#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14081#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14893#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 13985#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13986#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14721#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14853#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 14698#L1303-2 [2022-02-21 04:22:10,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:10,184 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2022-02-21 04:22:10,184 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:10,184 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969018552] [2022-02-21 04:22:10,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:10,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:10,210 INFO L290 TraceCheckUtils]: 0: Hoare triple {16931#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {16931#true} is VALID [2022-02-21 04:22:10,210 INFO L290 TraceCheckUtils]: 1: Hoare triple {16931#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,210 INFO L290 TraceCheckUtils]: 2: Hoare triple {16933#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,211 INFO L290 TraceCheckUtils]: 3: Hoare triple {16933#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,211 INFO L290 TraceCheckUtils]: 4: Hoare triple {16933#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,211 INFO L290 TraceCheckUtils]: 5: Hoare triple {16933#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,211 INFO L290 TraceCheckUtils]: 6: Hoare triple {16933#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,212 INFO L290 TraceCheckUtils]: 7: Hoare triple {16933#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,212 INFO L290 TraceCheckUtils]: 8: Hoare triple {16933#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {16933#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:10,212 INFO L290 TraceCheckUtils]: 9: Hoare triple {16933#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {16932#false} is VALID [2022-02-21 04:22:10,212 INFO L290 TraceCheckUtils]: 10: Hoare triple {16932#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {16932#false} is VALID [2022-02-21 04:22:10,212 INFO L290 TraceCheckUtils]: 11: Hoare triple {16932#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 12: Hoare triple {16932#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 13: Hoare triple {16932#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 14: Hoare triple {16932#false} assume !(0 == ~M_E~0); {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 15: Hoare triple {16932#false} assume !(0 == ~T1_E~0); {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 16: Hoare triple {16932#false} assume !(0 == ~T2_E~0); {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 17: Hoare triple {16932#false} assume !(0 == ~T3_E~0); {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 18: Hoare triple {16932#false} assume !(0 == ~T4_E~0); {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 19: Hoare triple {16932#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {16932#false} is VALID [2022-02-21 04:22:10,213 INFO L290 TraceCheckUtils]: 20: Hoare triple {16932#false} assume !(0 == ~T6_E~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 21: Hoare triple {16932#false} assume !(0 == ~T7_E~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 22: Hoare triple {16932#false} assume !(0 == ~T8_E~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 23: Hoare triple {16932#false} assume !(0 == ~E_M~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 24: Hoare triple {16932#false} assume !(0 == ~E_1~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 25: Hoare triple {16932#false} assume !(0 == ~E_2~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 26: Hoare triple {16932#false} assume !(0 == ~E_3~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 27: Hoare triple {16932#false} assume 0 == ~E_4~0;~E_4~0 := 1; {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 28: Hoare triple {16932#false} assume !(0 == ~E_5~0); {16932#false} is VALID [2022-02-21 04:22:10,214 INFO L290 TraceCheckUtils]: 29: Hoare triple {16932#false} assume !(0 == ~E_6~0); {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 30: Hoare triple {16932#false} assume !(0 == ~E_7~0); {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 31: Hoare triple {16932#false} assume !(0 == ~E_8~0); {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 32: Hoare triple {16932#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 33: Hoare triple {16932#false} assume !(1 == ~m_pc~0); {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 34: Hoare triple {16932#false} is_master_triggered_~__retres1~0#1 := 0; {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 35: Hoare triple {16932#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 36: Hoare triple {16932#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 37: Hoare triple {16932#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {16932#false} is VALID [2022-02-21 04:22:10,215 INFO L290 TraceCheckUtils]: 38: Hoare triple {16932#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 39: Hoare triple {16932#false} assume 1 == ~t1_pc~0; {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 40: Hoare triple {16932#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 41: Hoare triple {16932#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 42: Hoare triple {16932#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 43: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___0~0#1); {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 44: Hoare triple {16932#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 45: Hoare triple {16932#false} assume !(1 == ~t2_pc~0); {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 46: Hoare triple {16932#false} is_transmit2_triggered_~__retres1~2#1 := 0; {16932#false} is VALID [2022-02-21 04:22:10,216 INFO L290 TraceCheckUtils]: 47: Hoare triple {16932#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 48: Hoare triple {16932#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 49: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___1~0#1); {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 50: Hoare triple {16932#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 51: Hoare triple {16932#false} assume 1 == ~t3_pc~0; {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 52: Hoare triple {16932#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 53: Hoare triple {16932#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 54: Hoare triple {16932#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 55: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___2~0#1); {16932#false} is VALID [2022-02-21 04:22:10,217 INFO L290 TraceCheckUtils]: 56: Hoare triple {16932#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 57: Hoare triple {16932#false} assume !(1 == ~t4_pc~0); {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 58: Hoare triple {16932#false} is_transmit4_triggered_~__retres1~4#1 := 0; {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 59: Hoare triple {16932#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 60: Hoare triple {16932#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 61: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___3~0#1); {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 62: Hoare triple {16932#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 63: Hoare triple {16932#false} assume 1 == ~t5_pc~0; {16932#false} is VALID [2022-02-21 04:22:10,218 INFO L290 TraceCheckUtils]: 64: Hoare triple {16932#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 65: Hoare triple {16932#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 66: Hoare triple {16932#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 67: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___4~0#1); {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 68: Hoare triple {16932#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 69: Hoare triple {16932#false} assume !(1 == ~t6_pc~0); {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 70: Hoare triple {16932#false} is_transmit6_triggered_~__retres1~6#1 := 0; {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 71: Hoare triple {16932#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 72: Hoare triple {16932#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16932#false} is VALID [2022-02-21 04:22:10,219 INFO L290 TraceCheckUtils]: 73: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___5~0#1); {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 74: Hoare triple {16932#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 75: Hoare triple {16932#false} assume 1 == ~t7_pc~0; {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 76: Hoare triple {16932#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 77: Hoare triple {16932#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 78: Hoare triple {16932#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 79: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___6~0#1); {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 80: Hoare triple {16932#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 81: Hoare triple {16932#false} assume 1 == ~t8_pc~0; {16932#false} is VALID [2022-02-21 04:22:10,220 INFO L290 TraceCheckUtils]: 82: Hoare triple {16932#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 83: Hoare triple {16932#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 84: Hoare triple {16932#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 85: Hoare triple {16932#false} assume !(0 != activate_threads_~tmp___7~0#1); {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 86: Hoare triple {16932#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 87: Hoare triple {16932#false} assume 1 == ~M_E~0;~M_E~0 := 2; {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 88: Hoare triple {16932#false} assume !(1 == ~T1_E~0); {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 89: Hoare triple {16932#false} assume !(1 == ~T2_E~0); {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 90: Hoare triple {16932#false} assume !(1 == ~T3_E~0); {16932#false} is VALID [2022-02-21 04:22:10,221 INFO L290 TraceCheckUtils]: 91: Hoare triple {16932#false} assume !(1 == ~T4_E~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 92: Hoare triple {16932#false} assume !(1 == ~T5_E~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 93: Hoare triple {16932#false} assume !(1 == ~T6_E~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 94: Hoare triple {16932#false} assume !(1 == ~T7_E~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 95: Hoare triple {16932#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 96: Hoare triple {16932#false} assume !(1 == ~E_M~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 97: Hoare triple {16932#false} assume !(1 == ~E_1~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 98: Hoare triple {16932#false} assume !(1 == ~E_2~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 99: Hoare triple {16932#false} assume !(1 == ~E_3~0); {16932#false} is VALID [2022-02-21 04:22:10,222 INFO L290 TraceCheckUtils]: 100: Hoare triple {16932#false} assume !(1 == ~E_4~0); {16932#false} is VALID [2022-02-21 04:22:10,223 INFO L290 TraceCheckUtils]: 101: Hoare triple {16932#false} assume !(1 == ~E_5~0); {16932#false} is VALID [2022-02-21 04:22:10,223 INFO L290 TraceCheckUtils]: 102: Hoare triple {16932#false} assume !(1 == ~E_6~0); {16932#false} is VALID [2022-02-21 04:22:10,223 INFO L290 TraceCheckUtils]: 103: Hoare triple {16932#false} assume 1 == ~E_7~0;~E_7~0 := 2; {16932#false} is VALID [2022-02-21 04:22:10,223 INFO L290 TraceCheckUtils]: 104: Hoare triple {16932#false} assume !(1 == ~E_8~0); {16932#false} is VALID [2022-02-21 04:22:10,223 INFO L290 TraceCheckUtils]: 105: Hoare triple {16932#false} assume { :end_inline_reset_delta_events } true; {16932#false} is VALID [2022-02-21 04:22:10,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:10,223 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:10,224 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [969018552] [2022-02-21 04:22:10,224 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [969018552] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:10,224 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:10,224 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:10,224 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076397038] [2022-02-21 04:22:10,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:10,225 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:10,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:10,225 INFO L85 PathProgramCache]: Analyzing trace with hash 630471762, now seen corresponding path program 1 times [2022-02-21 04:22:10,225 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:10,225 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425858200] [2022-02-21 04:22:10,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:10,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:10,250 INFO L290 TraceCheckUtils]: 0: Hoare triple {16934#true} assume !false; {16934#true} is VALID [2022-02-21 04:22:10,250 INFO L290 TraceCheckUtils]: 1: Hoare triple {16934#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {16934#true} is VALID [2022-02-21 04:22:10,250 INFO L290 TraceCheckUtils]: 2: Hoare triple {16934#true} assume !false; {16934#true} is VALID [2022-02-21 04:22:10,250 INFO L290 TraceCheckUtils]: 3: Hoare triple {16934#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 4: Hoare triple {16934#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 5: Hoare triple {16934#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 6: Hoare triple {16934#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 7: Hoare triple {16934#true} assume !(0 != eval_~tmp~0#1); {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 8: Hoare triple {16934#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 9: Hoare triple {16934#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 10: Hoare triple {16934#true} assume 0 == ~M_E~0;~M_E~0 := 1; {16934#true} is VALID [2022-02-21 04:22:10,251 INFO L290 TraceCheckUtils]: 11: Hoare triple {16934#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {16934#true} is VALID [2022-02-21 04:22:10,252 INFO L290 TraceCheckUtils]: 12: Hoare triple {16934#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,252 INFO L290 TraceCheckUtils]: 13: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,252 INFO L290 TraceCheckUtils]: 14: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,252 INFO L290 TraceCheckUtils]: 15: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,253 INFO L290 TraceCheckUtils]: 16: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,253 INFO L290 TraceCheckUtils]: 17: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,253 INFO L290 TraceCheckUtils]: 18: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,254 INFO L290 TraceCheckUtils]: 19: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,254 INFO L290 TraceCheckUtils]: 20: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,254 INFO L290 TraceCheckUtils]: 21: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,254 INFO L290 TraceCheckUtils]: 22: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,255 INFO L290 TraceCheckUtils]: 23: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,255 INFO L290 TraceCheckUtils]: 24: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,255 INFO L290 TraceCheckUtils]: 25: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,255 INFO L290 TraceCheckUtils]: 26: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,256 INFO L290 TraceCheckUtils]: 27: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,256 INFO L290 TraceCheckUtils]: 28: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,256 INFO L290 TraceCheckUtils]: 29: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,256 INFO L290 TraceCheckUtils]: 30: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,257 INFO L290 TraceCheckUtils]: 31: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,257 INFO L290 TraceCheckUtils]: 32: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,257 INFO L290 TraceCheckUtils]: 33: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,257 INFO L290 TraceCheckUtils]: 34: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,258 INFO L290 TraceCheckUtils]: 35: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,258 INFO L290 TraceCheckUtils]: 36: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,258 INFO L290 TraceCheckUtils]: 37: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,258 INFO L290 TraceCheckUtils]: 38: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,259 INFO L290 TraceCheckUtils]: 39: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,259 INFO L290 TraceCheckUtils]: 40: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,259 INFO L290 TraceCheckUtils]: 41: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,260 INFO L290 TraceCheckUtils]: 42: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,260 INFO L290 TraceCheckUtils]: 43: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,260 INFO L290 TraceCheckUtils]: 44: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,260 INFO L290 TraceCheckUtils]: 45: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,261 INFO L290 TraceCheckUtils]: 46: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,261 INFO L290 TraceCheckUtils]: 47: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,261 INFO L290 TraceCheckUtils]: 48: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,261 INFO L290 TraceCheckUtils]: 49: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,262 INFO L290 TraceCheckUtils]: 50: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,262 INFO L290 TraceCheckUtils]: 51: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,262 INFO L290 TraceCheckUtils]: 52: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,262 INFO L290 TraceCheckUtils]: 53: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,263 INFO L290 TraceCheckUtils]: 54: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,263 INFO L290 TraceCheckUtils]: 55: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,263 INFO L290 TraceCheckUtils]: 56: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,263 INFO L290 TraceCheckUtils]: 57: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,264 INFO L290 TraceCheckUtils]: 58: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,264 INFO L290 TraceCheckUtils]: 59: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,264 INFO L290 TraceCheckUtils]: 60: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,264 INFO L290 TraceCheckUtils]: 61: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,265 INFO L290 TraceCheckUtils]: 62: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,265 INFO L290 TraceCheckUtils]: 63: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,265 INFO L290 TraceCheckUtils]: 64: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,266 INFO L290 TraceCheckUtils]: 65: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,266 INFO L290 TraceCheckUtils]: 66: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,266 INFO L290 TraceCheckUtils]: 67: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,266 INFO L290 TraceCheckUtils]: 68: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,267 INFO L290 TraceCheckUtils]: 69: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,267 INFO L290 TraceCheckUtils]: 70: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,267 INFO L290 TraceCheckUtils]: 71: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,267 INFO L290 TraceCheckUtils]: 72: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,268 INFO L290 TraceCheckUtils]: 73: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,268 INFO L290 TraceCheckUtils]: 74: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,268 INFO L290 TraceCheckUtils]: 75: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,268 INFO L290 TraceCheckUtils]: 76: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,269 INFO L290 TraceCheckUtils]: 77: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,269 INFO L290 TraceCheckUtils]: 78: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,269 INFO L290 TraceCheckUtils]: 79: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,269 INFO L290 TraceCheckUtils]: 80: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,270 INFO L290 TraceCheckUtils]: 81: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,270 INFO L290 TraceCheckUtils]: 82: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,270 INFO L290 TraceCheckUtils]: 83: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,270 INFO L290 TraceCheckUtils]: 84: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {16936#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,271 INFO L290 TraceCheckUtils]: 85: Hoare triple {16936#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {16935#false} is VALID [2022-02-21 04:22:10,271 INFO L290 TraceCheckUtils]: 86: Hoare triple {16935#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,271 INFO L290 TraceCheckUtils]: 87: Hoare triple {16935#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,271 INFO L290 TraceCheckUtils]: 88: Hoare triple {16935#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,271 INFO L290 TraceCheckUtils]: 89: Hoare triple {16935#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,271 INFO L290 TraceCheckUtils]: 90: Hoare triple {16935#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,271 INFO L290 TraceCheckUtils]: 91: Hoare triple {16935#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 92: Hoare triple {16935#false} assume 1 == ~E_M~0;~E_M~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 93: Hoare triple {16935#false} assume !(1 == ~E_1~0); {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 94: Hoare triple {16935#false} assume 1 == ~E_2~0;~E_2~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 95: Hoare triple {16935#false} assume 1 == ~E_3~0;~E_3~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 96: Hoare triple {16935#false} assume 1 == ~E_4~0;~E_4~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 97: Hoare triple {16935#false} assume 1 == ~E_5~0;~E_5~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 98: Hoare triple {16935#false} assume 1 == ~E_6~0;~E_6~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 99: Hoare triple {16935#false} assume 1 == ~E_7~0;~E_7~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,272 INFO L290 TraceCheckUtils]: 100: Hoare triple {16935#false} assume 1 == ~E_8~0;~E_8~0 := 2; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 101: Hoare triple {16935#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 102: Hoare triple {16935#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 103: Hoare triple {16935#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 104: Hoare triple {16935#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 105: Hoare triple {16935#false} assume !(0 == start_simulation_~tmp~3#1); {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 106: Hoare triple {16935#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 107: Hoare triple {16935#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 108: Hoare triple {16935#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {16935#false} is VALID [2022-02-21 04:22:10,273 INFO L290 TraceCheckUtils]: 109: Hoare triple {16935#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {16935#false} is VALID [2022-02-21 04:22:10,274 INFO L290 TraceCheckUtils]: 110: Hoare triple {16935#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {16935#false} is VALID [2022-02-21 04:22:10,274 INFO L290 TraceCheckUtils]: 111: Hoare triple {16935#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {16935#false} is VALID [2022-02-21 04:22:10,274 INFO L290 TraceCheckUtils]: 112: Hoare triple {16935#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {16935#false} is VALID [2022-02-21 04:22:10,274 INFO L290 TraceCheckUtils]: 113: Hoare triple {16935#false} assume !(0 != start_simulation_~tmp___0~1#1); {16935#false} is VALID [2022-02-21 04:22:10,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:10,274 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:10,275 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425858200] [2022-02-21 04:22:10,275 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425858200] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:10,275 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:10,275 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:10,275 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529554189] [2022-02-21 04:22:10,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:10,275 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:10,276 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:10,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:10,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:10,276 INFO L87 Difference]: Start difference. First operand 993 states and 1478 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,972 INFO L93 Difference]: Finished difference Result 993 states and 1477 transitions. [2022-02-21 04:22:10,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:10,972 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,026 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:11,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1477 transitions. [2022-02-21 04:22:11,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:11,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1477 transitions. [2022-02-21 04:22:11,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:11,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:11,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1477 transitions. [2022-02-21 04:22:11,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:11,080 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-02-21 04:22:11,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1477 transitions. [2022-02-21 04:22:11,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:11,088 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:11,089 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1477 transitions. Second operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,091 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1477 transitions. Second operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,092 INFO L87 Difference]: Start difference. First operand 993 states and 1477 transitions. Second operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:11,117 INFO L93 Difference]: Finished difference Result 993 states and 1477 transitions. [2022-02-21 04:22:11,117 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1477 transitions. [2022-02-21 04:22:11,118 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:11,119 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:11,120 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1477 transitions. [2022-02-21 04:22:11,121 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1477 transitions. [2022-02-21 04:22:11,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:11,146 INFO L93 Difference]: Finished difference Result 993 states and 1477 transitions. [2022-02-21 04:22:11,146 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1477 transitions. [2022-02-21 04:22:11,147 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:11,148 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:11,148 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:11,148 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:11,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.487411883182276) internal successors, (1477), 992 states have internal predecessors, (1477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1477 transitions. [2022-02-21 04:22:11,173 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-02-21 04:22:11,173 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1477 transitions. [2022-02-21 04:22:11,173 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:22:11,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1477 transitions. [2022-02-21 04:22:11,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:11,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:11,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:11,177 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:11,177 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:11,177 INFO L791 eck$LassoCheckResult]: Stem: 18690#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 18691#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17977#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17978#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18015#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 18641#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18642#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18263#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18264#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18204#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18205#L622-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18448#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18421#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18422#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18694#L854 assume !(0 == ~M_E~0); 18508#L854-2 assume !(0 == ~T1_E~0); 18509#L859-1 assume !(0 == ~T2_E~0); 18079#L864-1 assume !(0 == ~T3_E~0); 18080#L869-1 assume !(0 == ~T4_E~0); 18193#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18893#L879-1 assume !(0 == ~T6_E~0); 18496#L884-1 assume !(0 == ~T7_E~0); 17947#L889-1 assume !(0 == ~T8_E~0); 17948#L894-1 assume !(0 == ~E_M~0); 18278#L899-1 assume !(0 == ~E_1~0); 18701#L904-1 assume !(0 == ~E_2~0); 18437#L909-1 assume !(0 == ~E_3~0); 18438#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18632#L919-1 assume !(0 == ~E_5~0); 18358#L924-1 assume !(0 == ~E_6~0); 18176#L929-1 assume !(0 == ~E_7~0); 18177#L934-1 assume !(0 == ~E_8~0); 18418#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17965#L418 assume !(1 == ~m_pc~0); 17937#L418-2 is_master_triggered_~__retres1~0#1 := 0; 17936#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18852#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18801#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18726#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18727#L437 assume 1 == ~t1_pc~0; 18910#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18809#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18762#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18313#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 18314#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18792#L456 assume !(1 == ~t2_pc~0); 18229#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18228#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18567#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18568#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 18543#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18073#L475 assume 1 == ~t3_pc~0; 18074#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18134#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18135#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18888#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 18317#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18318#L494 assume !(1 == ~t4_pc~0); 18353#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18354#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18558#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18559#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 18655#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18129#L513 assume 1 == ~t5_pc~0; 18130#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18355#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18392#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18090#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 18091#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18042#L532 assume !(1 == ~t6_pc~0); 18043#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18194#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18473#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18552#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 18283#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18284#L551 assume 1 == ~t7_pc~0; 18830#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18659#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18660#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18841#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 18919#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18457#L570 assume 1 == ~t8_pc~0; 18458#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18569#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18703#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18563#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 18067#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18068#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 18016#L952-2 assume !(1 == ~T1_E~0); 18017#L957-1 assume !(1 == ~T2_E~0); 18774#L962-1 assume !(1 == ~T3_E~0); 18579#L967-1 assume !(1 == ~T4_E~0); 18580#L972-1 assume !(1 == ~T5_E~0); 18831#L977-1 assume !(1 == ~T6_E~0); 18832#L982-1 assume !(1 == ~T7_E~0); 18196#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18197#L992-1 assume !(1 == ~E_M~0); 18206#L997-1 assume !(1 == ~E_1~0); 18541#L1002-1 assume !(1 == ~E_2~0); 18529#L1007-1 assume !(1 == ~E_3~0); 17949#L1012-1 assume !(1 == ~E_4~0); 17950#L1017-1 assume !(1 == ~E_5~0); 18530#L1022-1 assume !(1 == ~E_6~0); 18531#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 18553#L1032-1 assume !(1 == ~E_8~0); 18678#L1037-1 assume { :end_inline_reset_delta_events } true; 18679#L1303-2 [2022-02-21 04:22:11,177 INFO L793 eck$LassoCheckResult]: Loop: 18679#L1303-2 assume !false; 18769#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17960#L829 assume !false; 18723#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18338#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18266#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18669#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18647#L712 assume !(0 != eval_~tmp~0#1); 18648#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17984#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17985#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18650#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18651#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18917#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18891#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18474#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18475#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18542#L884-3 assume !(0 == ~T7_E~0); 18523#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18167#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18168#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18200#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18201#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18141#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18142#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18189#L924-3 assume !(0 == ~E_6~0); 18731#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18633#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18634#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18760#L418-30 assume !(1 == ~m_pc~0); 18033#L418-32 is_master_triggered_~__retres1~0#1 := 0; 18032#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18486#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18487#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18230#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18231#L437-30 assume !(1 == ~t1_pc~0); 18356#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 18561#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18562#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18749#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18908#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18322#L456-30 assume 1 == ~t2_pc~0; 18323#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18720#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18721#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18115#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18116#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18449#L475-30 assume 1 == ~t3_pc~0; 18824#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17998#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18649#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18894#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18340#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18341#L494-30 assume !(1 == ~t4_pc~0); 18146#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 17933#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17934#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18865#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 18844#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18845#L513-30 assume !(1 == ~t5_pc~0); 18454#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 18455#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18519#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18745#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18746#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18465#L532-30 assume !(1 == ~t6_pc~0); 18466#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 18071#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18072#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18093#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18155#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18156#L551-30 assume 1 == ~t7_pc~0; 18208#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18268#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18140#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17951#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17952#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18319#L570-30 assume !(1 == ~t8_pc~0); 18640#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 18207#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18159#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18013#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18014#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18380#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18415#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18872#L957-3 assume !(1 == ~T2_E~0); 18873#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18790#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18791#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18699#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18700#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18922#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18368#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18369#L997-3 assume !(1 == ~E_1~0); 18364#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18365#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18180#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18181#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18277#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18495#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17982#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17983#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18220#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18221#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18125#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 18126#L1322 assume !(0 == start_simulation_~tmp~3#1); 18394#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18061#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18062#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18874#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 17966#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17967#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18702#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 18834#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 18679#L1303-2 [2022-02-21 04:22:11,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:11,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2022-02-21 04:22:11,178 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:11,178 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223547627] [2022-02-21 04:22:11,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:11,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:11,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:11,196 INFO L290 TraceCheckUtils]: 0: Hoare triple {20912#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {20912#true} is VALID [2022-02-21 04:22:11,196 INFO L290 TraceCheckUtils]: 1: Hoare triple {20912#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,197 INFO L290 TraceCheckUtils]: 2: Hoare triple {20914#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,197 INFO L290 TraceCheckUtils]: 3: Hoare triple {20914#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,197 INFO L290 TraceCheckUtils]: 4: Hoare triple {20914#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,197 INFO L290 TraceCheckUtils]: 5: Hoare triple {20914#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,197 INFO L290 TraceCheckUtils]: 6: Hoare triple {20914#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,198 INFO L290 TraceCheckUtils]: 7: Hoare triple {20914#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,198 INFO L290 TraceCheckUtils]: 8: Hoare triple {20914#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,198 INFO L290 TraceCheckUtils]: 9: Hoare triple {20914#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {20914#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:11,198 INFO L290 TraceCheckUtils]: 10: Hoare triple {20914#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 11: Hoare triple {20913#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 12: Hoare triple {20913#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 13: Hoare triple {20913#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 14: Hoare triple {20913#false} assume !(0 == ~M_E~0); {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 15: Hoare triple {20913#false} assume !(0 == ~T1_E~0); {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 16: Hoare triple {20913#false} assume !(0 == ~T2_E~0); {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 17: Hoare triple {20913#false} assume !(0 == ~T3_E~0); {20913#false} is VALID [2022-02-21 04:22:11,199 INFO L290 TraceCheckUtils]: 18: Hoare triple {20913#false} assume !(0 == ~T4_E~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 19: Hoare triple {20913#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 20: Hoare triple {20913#false} assume !(0 == ~T6_E~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 21: Hoare triple {20913#false} assume !(0 == ~T7_E~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 22: Hoare triple {20913#false} assume !(0 == ~T8_E~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 23: Hoare triple {20913#false} assume !(0 == ~E_M~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 24: Hoare triple {20913#false} assume !(0 == ~E_1~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 25: Hoare triple {20913#false} assume !(0 == ~E_2~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 26: Hoare triple {20913#false} assume !(0 == ~E_3~0); {20913#false} is VALID [2022-02-21 04:22:11,200 INFO L290 TraceCheckUtils]: 27: Hoare triple {20913#false} assume 0 == ~E_4~0;~E_4~0 := 1; {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 28: Hoare triple {20913#false} assume !(0 == ~E_5~0); {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 29: Hoare triple {20913#false} assume !(0 == ~E_6~0); {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 30: Hoare triple {20913#false} assume !(0 == ~E_7~0); {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 31: Hoare triple {20913#false} assume !(0 == ~E_8~0); {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 32: Hoare triple {20913#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 33: Hoare triple {20913#false} assume !(1 == ~m_pc~0); {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 34: Hoare triple {20913#false} is_master_triggered_~__retres1~0#1 := 0; {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 35: Hoare triple {20913#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20913#false} is VALID [2022-02-21 04:22:11,201 INFO L290 TraceCheckUtils]: 36: Hoare triple {20913#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 37: Hoare triple {20913#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 38: Hoare triple {20913#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 39: Hoare triple {20913#false} assume 1 == ~t1_pc~0; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 40: Hoare triple {20913#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 41: Hoare triple {20913#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 42: Hoare triple {20913#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 43: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___0~0#1); {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 44: Hoare triple {20913#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20913#false} is VALID [2022-02-21 04:22:11,202 INFO L290 TraceCheckUtils]: 45: Hoare triple {20913#false} assume !(1 == ~t2_pc~0); {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 46: Hoare triple {20913#false} is_transmit2_triggered_~__retres1~2#1 := 0; {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 47: Hoare triple {20913#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 48: Hoare triple {20913#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 49: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___1~0#1); {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 50: Hoare triple {20913#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 51: Hoare triple {20913#false} assume 1 == ~t3_pc~0; {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 52: Hoare triple {20913#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 53: Hoare triple {20913#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20913#false} is VALID [2022-02-21 04:22:11,203 INFO L290 TraceCheckUtils]: 54: Hoare triple {20913#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 55: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___2~0#1); {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 56: Hoare triple {20913#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 57: Hoare triple {20913#false} assume !(1 == ~t4_pc~0); {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 58: Hoare triple {20913#false} is_transmit4_triggered_~__retres1~4#1 := 0; {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 59: Hoare triple {20913#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 60: Hoare triple {20913#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 61: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___3~0#1); {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 62: Hoare triple {20913#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20913#false} is VALID [2022-02-21 04:22:11,204 INFO L290 TraceCheckUtils]: 63: Hoare triple {20913#false} assume 1 == ~t5_pc~0; {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 64: Hoare triple {20913#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 65: Hoare triple {20913#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 66: Hoare triple {20913#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 67: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___4~0#1); {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 68: Hoare triple {20913#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 69: Hoare triple {20913#false} assume !(1 == ~t6_pc~0); {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 70: Hoare triple {20913#false} is_transmit6_triggered_~__retres1~6#1 := 0; {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 71: Hoare triple {20913#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20913#false} is VALID [2022-02-21 04:22:11,205 INFO L290 TraceCheckUtils]: 72: Hoare triple {20913#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 73: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___5~0#1); {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 74: Hoare triple {20913#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 75: Hoare triple {20913#false} assume 1 == ~t7_pc~0; {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 76: Hoare triple {20913#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 77: Hoare triple {20913#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 78: Hoare triple {20913#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 79: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___6~0#1); {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 80: Hoare triple {20913#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {20913#false} is VALID [2022-02-21 04:22:11,206 INFO L290 TraceCheckUtils]: 81: Hoare triple {20913#false} assume 1 == ~t8_pc~0; {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 82: Hoare triple {20913#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 83: Hoare triple {20913#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 84: Hoare triple {20913#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 85: Hoare triple {20913#false} assume !(0 != activate_threads_~tmp___7~0#1); {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 86: Hoare triple {20913#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 87: Hoare triple {20913#false} assume 1 == ~M_E~0;~M_E~0 := 2; {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 88: Hoare triple {20913#false} assume !(1 == ~T1_E~0); {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 89: Hoare triple {20913#false} assume !(1 == ~T2_E~0); {20913#false} is VALID [2022-02-21 04:22:11,207 INFO L290 TraceCheckUtils]: 90: Hoare triple {20913#false} assume !(1 == ~T3_E~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 91: Hoare triple {20913#false} assume !(1 == ~T4_E~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 92: Hoare triple {20913#false} assume !(1 == ~T5_E~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 93: Hoare triple {20913#false} assume !(1 == ~T6_E~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 94: Hoare triple {20913#false} assume !(1 == ~T7_E~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 95: Hoare triple {20913#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 96: Hoare triple {20913#false} assume !(1 == ~E_M~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 97: Hoare triple {20913#false} assume !(1 == ~E_1~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 98: Hoare triple {20913#false} assume !(1 == ~E_2~0); {20913#false} is VALID [2022-02-21 04:22:11,208 INFO L290 TraceCheckUtils]: 99: Hoare triple {20913#false} assume !(1 == ~E_3~0); {20913#false} is VALID [2022-02-21 04:22:11,209 INFO L290 TraceCheckUtils]: 100: Hoare triple {20913#false} assume !(1 == ~E_4~0); {20913#false} is VALID [2022-02-21 04:22:11,209 INFO L290 TraceCheckUtils]: 101: Hoare triple {20913#false} assume !(1 == ~E_5~0); {20913#false} is VALID [2022-02-21 04:22:11,209 INFO L290 TraceCheckUtils]: 102: Hoare triple {20913#false} assume !(1 == ~E_6~0); {20913#false} is VALID [2022-02-21 04:22:11,209 INFO L290 TraceCheckUtils]: 103: Hoare triple {20913#false} assume 1 == ~E_7~0;~E_7~0 := 2; {20913#false} is VALID [2022-02-21 04:22:11,209 INFO L290 TraceCheckUtils]: 104: Hoare triple {20913#false} assume !(1 == ~E_8~0); {20913#false} is VALID [2022-02-21 04:22:11,209 INFO L290 TraceCheckUtils]: 105: Hoare triple {20913#false} assume { :end_inline_reset_delta_events } true; {20913#false} is VALID [2022-02-21 04:22:11,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:11,210 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:11,210 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223547627] [2022-02-21 04:22:11,210 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223547627] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:11,210 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:11,210 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:11,210 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807073957] [2022-02-21 04:22:11,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:11,211 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:11,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:11,211 INFO L85 PathProgramCache]: Analyzing trace with hash -1695676973, now seen corresponding path program 1 times [2022-02-21 04:22:11,211 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:11,211 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677891566] [2022-02-21 04:22:11,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:11,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:11,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 0: Hoare triple {20915#true} assume !false; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 1: Hoare triple {20915#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 2: Hoare triple {20915#true} assume !false; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 3: Hoare triple {20915#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 4: Hoare triple {20915#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 5: Hoare triple {20915#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 6: Hoare triple {20915#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 7: Hoare triple {20915#true} assume !(0 != eval_~tmp~0#1); {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 8: Hoare triple {20915#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 9: Hoare triple {20915#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {20915#true} is VALID [2022-02-21 04:22:11,252 INFO L290 TraceCheckUtils]: 10: Hoare triple {20915#true} assume 0 == ~M_E~0;~M_E~0 := 1; {20915#true} is VALID [2022-02-21 04:22:11,253 INFO L290 TraceCheckUtils]: 11: Hoare triple {20915#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {20915#true} is VALID [2022-02-21 04:22:11,253 INFO L290 TraceCheckUtils]: 12: Hoare triple {20915#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,253 INFO L290 TraceCheckUtils]: 13: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,254 INFO L290 TraceCheckUtils]: 14: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,254 INFO L290 TraceCheckUtils]: 15: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,254 INFO L290 TraceCheckUtils]: 16: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,254 INFO L290 TraceCheckUtils]: 17: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,255 INFO L290 TraceCheckUtils]: 18: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,255 INFO L290 TraceCheckUtils]: 19: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,255 INFO L290 TraceCheckUtils]: 20: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,256 INFO L290 TraceCheckUtils]: 21: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,256 INFO L290 TraceCheckUtils]: 22: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,256 INFO L290 TraceCheckUtils]: 23: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,256 INFO L290 TraceCheckUtils]: 24: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,257 INFO L290 TraceCheckUtils]: 25: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,257 INFO L290 TraceCheckUtils]: 26: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,257 INFO L290 TraceCheckUtils]: 27: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,258 INFO L290 TraceCheckUtils]: 28: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,258 INFO L290 TraceCheckUtils]: 29: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,258 INFO L290 TraceCheckUtils]: 30: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,258 INFO L290 TraceCheckUtils]: 31: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,259 INFO L290 TraceCheckUtils]: 32: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,259 INFO L290 TraceCheckUtils]: 33: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,259 INFO L290 TraceCheckUtils]: 34: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,260 INFO L290 TraceCheckUtils]: 35: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,260 INFO L290 TraceCheckUtils]: 36: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,260 INFO L290 TraceCheckUtils]: 37: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,260 INFO L290 TraceCheckUtils]: 38: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,261 INFO L290 TraceCheckUtils]: 39: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,261 INFO L290 TraceCheckUtils]: 40: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,261 INFO L290 TraceCheckUtils]: 41: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,261 INFO L290 TraceCheckUtils]: 42: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,262 INFO L290 TraceCheckUtils]: 43: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,262 INFO L290 TraceCheckUtils]: 44: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,262 INFO L290 TraceCheckUtils]: 45: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,262 INFO L290 TraceCheckUtils]: 46: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,263 INFO L290 TraceCheckUtils]: 47: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,263 INFO L290 TraceCheckUtils]: 48: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,263 INFO L290 TraceCheckUtils]: 49: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,264 INFO L290 TraceCheckUtils]: 50: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,264 INFO L290 TraceCheckUtils]: 51: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,264 INFO L290 TraceCheckUtils]: 52: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,264 INFO L290 TraceCheckUtils]: 53: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,265 INFO L290 TraceCheckUtils]: 54: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,265 INFO L290 TraceCheckUtils]: 55: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,265 INFO L290 TraceCheckUtils]: 56: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,265 INFO L290 TraceCheckUtils]: 57: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,266 INFO L290 TraceCheckUtils]: 58: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,266 INFO L290 TraceCheckUtils]: 59: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,266 INFO L290 TraceCheckUtils]: 60: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,266 INFO L290 TraceCheckUtils]: 61: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,267 INFO L290 TraceCheckUtils]: 62: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,267 INFO L290 TraceCheckUtils]: 63: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,267 INFO L290 TraceCheckUtils]: 64: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,267 INFO L290 TraceCheckUtils]: 65: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,268 INFO L290 TraceCheckUtils]: 66: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,268 INFO L290 TraceCheckUtils]: 67: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,268 INFO L290 TraceCheckUtils]: 68: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,268 INFO L290 TraceCheckUtils]: 69: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,269 INFO L290 TraceCheckUtils]: 70: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,269 INFO L290 TraceCheckUtils]: 71: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,269 INFO L290 TraceCheckUtils]: 72: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,269 INFO L290 TraceCheckUtils]: 73: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,270 INFO L290 TraceCheckUtils]: 74: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,270 INFO L290 TraceCheckUtils]: 75: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,270 INFO L290 TraceCheckUtils]: 76: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,270 INFO L290 TraceCheckUtils]: 77: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,271 INFO L290 TraceCheckUtils]: 78: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,271 INFO L290 TraceCheckUtils]: 79: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,271 INFO L290 TraceCheckUtils]: 80: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,272 INFO L290 TraceCheckUtils]: 81: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,272 INFO L290 TraceCheckUtils]: 82: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,272 INFO L290 TraceCheckUtils]: 83: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,272 INFO L290 TraceCheckUtils]: 84: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {20917#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 85: Hoare triple {20917#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 86: Hoare triple {20916#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 87: Hoare triple {20916#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 88: Hoare triple {20916#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 89: Hoare triple {20916#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 90: Hoare triple {20916#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 91: Hoare triple {20916#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 92: Hoare triple {20916#false} assume 1 == ~E_M~0;~E_M~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,273 INFO L290 TraceCheckUtils]: 93: Hoare triple {20916#false} assume !(1 == ~E_1~0); {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 94: Hoare triple {20916#false} assume 1 == ~E_2~0;~E_2~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 95: Hoare triple {20916#false} assume 1 == ~E_3~0;~E_3~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 96: Hoare triple {20916#false} assume 1 == ~E_4~0;~E_4~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 97: Hoare triple {20916#false} assume 1 == ~E_5~0;~E_5~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 98: Hoare triple {20916#false} assume 1 == ~E_6~0;~E_6~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 99: Hoare triple {20916#false} assume 1 == ~E_7~0;~E_7~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 100: Hoare triple {20916#false} assume 1 == ~E_8~0;~E_8~0 := 2; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 101: Hoare triple {20916#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {20916#false} is VALID [2022-02-21 04:22:11,274 INFO L290 TraceCheckUtils]: 102: Hoare triple {20916#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 103: Hoare triple {20916#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 104: Hoare triple {20916#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 105: Hoare triple {20916#false} assume !(0 == start_simulation_~tmp~3#1); {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 106: Hoare triple {20916#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 107: Hoare triple {20916#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 108: Hoare triple {20916#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 109: Hoare triple {20916#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 110: Hoare triple {20916#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {20916#false} is VALID [2022-02-21 04:22:11,275 INFO L290 TraceCheckUtils]: 111: Hoare triple {20916#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {20916#false} is VALID [2022-02-21 04:22:11,276 INFO L290 TraceCheckUtils]: 112: Hoare triple {20916#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {20916#false} is VALID [2022-02-21 04:22:11,276 INFO L290 TraceCheckUtils]: 113: Hoare triple {20916#false} assume !(0 != start_simulation_~tmp___0~1#1); {20916#false} is VALID [2022-02-21 04:22:11,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:11,276 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:11,276 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677891566] [2022-02-21 04:22:11,277 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677891566] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:11,277 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:11,277 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:11,277 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360901211] [2022-02-21 04:22:11,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:11,278 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:11,278 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:11,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:11,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:11,278 INFO L87 Difference]: Start difference. First operand 993 states and 1477 transitions. cyclomatic complexity: 485 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:11,910 INFO L93 Difference]: Finished difference Result 993 states and 1476 transitions. [2022-02-21 04:22:11,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:11,910 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,973 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:11,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1476 transitions. [2022-02-21 04:22:12,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:12,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1476 transitions. [2022-02-21 04:22:12,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:12,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:12,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1476 transitions. [2022-02-21 04:22:12,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:12,045 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-02-21 04:22:12,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1476 transitions. [2022-02-21 04:22:12,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:12,053 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:12,054 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1476 transitions. Second operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,055 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1476 transitions. Second operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,056 INFO L87 Difference]: Start difference. First operand 993 states and 1476 transitions. Second operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,081 INFO L93 Difference]: Finished difference Result 993 states and 1476 transitions. [2022-02-21 04:22:12,081 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1476 transitions. [2022-02-21 04:22:12,082 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:12,082 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:12,084 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1476 transitions. [2022-02-21 04:22:12,085 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1476 transitions. [2022-02-21 04:22:12,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,109 INFO L93 Difference]: Finished difference Result 993 states and 1476 transitions. [2022-02-21 04:22:12,110 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1476 transitions. [2022-02-21 04:22:12,111 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:12,111 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:12,111 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:12,111 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:12,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.486404833836858) internal successors, (1476), 992 states have internal predecessors, (1476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1476 transitions. [2022-02-21 04:22:12,137 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-02-21 04:22:12,137 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1476 transitions. [2022-02-21 04:22:12,137 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:22:12,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1476 transitions. [2022-02-21 04:22:12,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:12,140 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:12,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:12,141 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:12,141 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:12,141 INFO L791 eck$LassoCheckResult]: Stem: 22671#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 22672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 21958#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21959#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21996#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 22622#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22623#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22244#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22245#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22185#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22186#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22429#L627-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22402#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22403#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22675#L854 assume !(0 == ~M_E~0); 22489#L854-2 assume !(0 == ~T1_E~0); 22490#L859-1 assume !(0 == ~T2_E~0); 22060#L864-1 assume !(0 == ~T3_E~0); 22061#L869-1 assume !(0 == ~T4_E~0); 22174#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22874#L879-1 assume !(0 == ~T6_E~0); 22477#L884-1 assume !(0 == ~T7_E~0); 21928#L889-1 assume !(0 == ~T8_E~0); 21929#L894-1 assume !(0 == ~E_M~0); 22259#L899-1 assume !(0 == ~E_1~0); 22682#L904-1 assume !(0 == ~E_2~0); 22418#L909-1 assume !(0 == ~E_3~0); 22419#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22613#L919-1 assume !(0 == ~E_5~0); 22339#L924-1 assume !(0 == ~E_6~0); 22157#L929-1 assume !(0 == ~E_7~0); 22158#L934-1 assume !(0 == ~E_8~0); 22399#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21946#L418 assume !(1 == ~m_pc~0); 21918#L418-2 is_master_triggered_~__retres1~0#1 := 0; 21917#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22833#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22782#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22707#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22708#L437 assume 1 == ~t1_pc~0; 22891#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22790#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22743#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22294#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 22295#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22773#L456 assume !(1 == ~t2_pc~0); 22210#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22209#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22548#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22549#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 22524#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22054#L475 assume 1 == ~t3_pc~0; 22055#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22115#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22116#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22869#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 22298#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22299#L494 assume !(1 == ~t4_pc~0); 22334#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22335#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22539#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22540#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 22636#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22110#L513 assume 1 == ~t5_pc~0; 22111#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22336#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22373#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22071#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 22072#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22023#L532 assume !(1 == ~t6_pc~0); 22024#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22175#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22454#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22533#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 22264#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22265#L551 assume 1 == ~t7_pc~0; 22811#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22640#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22641#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22822#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 22900#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22438#L570 assume 1 == ~t8_pc~0; 22439#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22550#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22684#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22544#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 22048#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22049#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 21997#L952-2 assume !(1 == ~T1_E~0); 21998#L957-1 assume !(1 == ~T2_E~0); 22755#L962-1 assume !(1 == ~T3_E~0); 22560#L967-1 assume !(1 == ~T4_E~0); 22561#L972-1 assume !(1 == ~T5_E~0); 22812#L977-1 assume !(1 == ~T6_E~0); 22813#L982-1 assume !(1 == ~T7_E~0); 22177#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22178#L992-1 assume !(1 == ~E_M~0); 22187#L997-1 assume !(1 == ~E_1~0); 22522#L1002-1 assume !(1 == ~E_2~0); 22510#L1007-1 assume !(1 == ~E_3~0); 21930#L1012-1 assume !(1 == ~E_4~0); 21931#L1017-1 assume !(1 == ~E_5~0); 22511#L1022-1 assume !(1 == ~E_6~0); 22512#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22534#L1032-1 assume !(1 == ~E_8~0); 22659#L1037-1 assume { :end_inline_reset_delta_events } true; 22660#L1303-2 [2022-02-21 04:22:12,141 INFO L793 eck$LassoCheckResult]: Loop: 22660#L1303-2 assume !false; 22750#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21941#L829 assume !false; 22704#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 22319#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 22247#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 22650#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22628#L712 assume !(0 != eval_~tmp~0#1); 22629#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21965#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21966#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22631#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22632#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22898#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22872#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22455#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22456#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22523#L884-3 assume !(0 == ~T7_E~0); 22504#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22148#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22149#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22181#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22182#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22122#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22123#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22170#L924-3 assume !(0 == ~E_6~0); 22712#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22614#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22615#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22741#L418-30 assume 1 == ~m_pc~0; 22012#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22013#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22467#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22468#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22211#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22212#L437-30 assume !(1 == ~t1_pc~0); 22337#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 22542#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22543#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22730#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22889#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22303#L456-30 assume 1 == ~t2_pc~0; 22304#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22701#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22702#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22096#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22097#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22430#L475-30 assume 1 == ~t3_pc~0; 22805#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21979#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22630#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22875#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22321#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22322#L494-30 assume 1 == ~t4_pc~0; 22315#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21914#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21915#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22846#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 22825#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22826#L513-30 assume !(1 == ~t5_pc~0); 22435#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 22436#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22500#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22726#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22727#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22446#L532-30 assume 1 == ~t6_pc~0; 22448#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22052#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22053#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22074#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22136#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22137#L551-30 assume 1 == ~t7_pc~0; 22189#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22249#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22121#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21932#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21933#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22300#L570-30 assume 1 == ~t8_pc~0; 22791#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22188#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22140#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21994#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21995#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22361#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22396#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22853#L957-3 assume !(1 == ~T2_E~0); 22854#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22771#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22772#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22680#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22681#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22903#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22349#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22350#L997-3 assume !(1 == ~E_1~0); 22345#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22346#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22161#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22162#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22258#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22476#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21963#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21964#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 22201#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 22202#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 22106#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 22107#L1322 assume !(0 == start_simulation_~tmp~3#1); 22375#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 22042#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 22043#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 22855#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 21947#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21948#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22683#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 22815#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 22660#L1303-2 [2022-02-21 04:22:12,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:12,142 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2022-02-21 04:22:12,142 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:12,142 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220334515] [2022-02-21 04:22:12,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:12,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:12,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:12,159 INFO L290 TraceCheckUtils]: 0: Hoare triple {24893#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {24893#true} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 1: Hoare triple {24893#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 2: Hoare triple {24895#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 3: Hoare triple {24895#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 4: Hoare triple {24895#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 5: Hoare triple {24895#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 6: Hoare triple {24895#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 7: Hoare triple {24895#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 8: Hoare triple {24895#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 9: Hoare triple {24895#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 10: Hoare triple {24895#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {24895#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 11: Hoare triple {24895#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {24894#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 12: Hoare triple {24894#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 13: Hoare triple {24894#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 14: Hoare triple {24894#false} assume !(0 == ~M_E~0); {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 15: Hoare triple {24894#false} assume !(0 == ~T1_E~0); {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 16: Hoare triple {24894#false} assume !(0 == ~T2_E~0); {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 17: Hoare triple {24894#false} assume !(0 == ~T3_E~0); {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 18: Hoare triple {24894#false} assume !(0 == ~T4_E~0); {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 19: Hoare triple {24894#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {24894#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 20: Hoare triple {24894#false} assume !(0 == ~T6_E~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 21: Hoare triple {24894#false} assume !(0 == ~T7_E~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 22: Hoare triple {24894#false} assume !(0 == ~T8_E~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 23: Hoare triple {24894#false} assume !(0 == ~E_M~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 24: Hoare triple {24894#false} assume !(0 == ~E_1~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 25: Hoare triple {24894#false} assume !(0 == ~E_2~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 26: Hoare triple {24894#false} assume !(0 == ~E_3~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 27: Hoare triple {24894#false} assume 0 == ~E_4~0;~E_4~0 := 1; {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 28: Hoare triple {24894#false} assume !(0 == ~E_5~0); {24894#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 29: Hoare triple {24894#false} assume !(0 == ~E_6~0); {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 30: Hoare triple {24894#false} assume !(0 == ~E_7~0); {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 31: Hoare triple {24894#false} assume !(0 == ~E_8~0); {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 32: Hoare triple {24894#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 33: Hoare triple {24894#false} assume !(1 == ~m_pc~0); {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 34: Hoare triple {24894#false} is_master_triggered_~__retres1~0#1 := 0; {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 35: Hoare triple {24894#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 36: Hoare triple {24894#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 37: Hoare triple {24894#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {24894#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 38: Hoare triple {24894#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 39: Hoare triple {24894#false} assume 1 == ~t1_pc~0; {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 40: Hoare triple {24894#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 41: Hoare triple {24894#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 42: Hoare triple {24894#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 43: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___0~0#1); {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 44: Hoare triple {24894#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 45: Hoare triple {24894#false} assume !(1 == ~t2_pc~0); {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 46: Hoare triple {24894#false} is_transmit2_triggered_~__retres1~2#1 := 0; {24894#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 47: Hoare triple {24894#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 48: Hoare triple {24894#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 49: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___1~0#1); {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 50: Hoare triple {24894#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 51: Hoare triple {24894#false} assume 1 == ~t3_pc~0; {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 52: Hoare triple {24894#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 53: Hoare triple {24894#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 54: Hoare triple {24894#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 55: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___2~0#1); {24894#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 56: Hoare triple {24894#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 57: Hoare triple {24894#false} assume !(1 == ~t4_pc~0); {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 58: Hoare triple {24894#false} is_transmit4_triggered_~__retres1~4#1 := 0; {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 59: Hoare triple {24894#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 60: Hoare triple {24894#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 61: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___3~0#1); {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 62: Hoare triple {24894#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 63: Hoare triple {24894#false} assume 1 == ~t5_pc~0; {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 64: Hoare triple {24894#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24894#false} is VALID [2022-02-21 04:22:12,168 INFO L290 TraceCheckUtils]: 65: Hoare triple {24894#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 66: Hoare triple {24894#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 67: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___4~0#1); {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 68: Hoare triple {24894#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 69: Hoare triple {24894#false} assume !(1 == ~t6_pc~0); {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 70: Hoare triple {24894#false} is_transmit6_triggered_~__retres1~6#1 := 0; {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 71: Hoare triple {24894#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 72: Hoare triple {24894#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 73: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___5~0#1); {24894#false} is VALID [2022-02-21 04:22:12,169 INFO L290 TraceCheckUtils]: 74: Hoare triple {24894#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 75: Hoare triple {24894#false} assume 1 == ~t7_pc~0; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 76: Hoare triple {24894#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 77: Hoare triple {24894#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 78: Hoare triple {24894#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 79: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___6~0#1); {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 80: Hoare triple {24894#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 81: Hoare triple {24894#false} assume 1 == ~t8_pc~0; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 82: Hoare triple {24894#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {24894#false} is VALID [2022-02-21 04:22:12,170 INFO L290 TraceCheckUtils]: 83: Hoare triple {24894#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 84: Hoare triple {24894#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 85: Hoare triple {24894#false} assume !(0 != activate_threads_~tmp___7~0#1); {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 86: Hoare triple {24894#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 87: Hoare triple {24894#false} assume 1 == ~M_E~0;~M_E~0 := 2; {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 88: Hoare triple {24894#false} assume !(1 == ~T1_E~0); {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 89: Hoare triple {24894#false} assume !(1 == ~T2_E~0); {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 90: Hoare triple {24894#false} assume !(1 == ~T3_E~0); {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 91: Hoare triple {24894#false} assume !(1 == ~T4_E~0); {24894#false} is VALID [2022-02-21 04:22:12,171 INFO L290 TraceCheckUtils]: 92: Hoare triple {24894#false} assume !(1 == ~T5_E~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 93: Hoare triple {24894#false} assume !(1 == ~T6_E~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 94: Hoare triple {24894#false} assume !(1 == ~T7_E~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 95: Hoare triple {24894#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 96: Hoare triple {24894#false} assume !(1 == ~E_M~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 97: Hoare triple {24894#false} assume !(1 == ~E_1~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 98: Hoare triple {24894#false} assume !(1 == ~E_2~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 99: Hoare triple {24894#false} assume !(1 == ~E_3~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 100: Hoare triple {24894#false} assume !(1 == ~E_4~0); {24894#false} is VALID [2022-02-21 04:22:12,172 INFO L290 TraceCheckUtils]: 101: Hoare triple {24894#false} assume !(1 == ~E_5~0); {24894#false} is VALID [2022-02-21 04:22:12,173 INFO L290 TraceCheckUtils]: 102: Hoare triple {24894#false} assume !(1 == ~E_6~0); {24894#false} is VALID [2022-02-21 04:22:12,173 INFO L290 TraceCheckUtils]: 103: Hoare triple {24894#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24894#false} is VALID [2022-02-21 04:22:12,173 INFO L290 TraceCheckUtils]: 104: Hoare triple {24894#false} assume !(1 == ~E_8~0); {24894#false} is VALID [2022-02-21 04:22:12,173 INFO L290 TraceCheckUtils]: 105: Hoare triple {24894#false} assume { :end_inline_reset_delta_events } true; {24894#false} is VALID [2022-02-21 04:22:12,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:12,173 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:12,174 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220334515] [2022-02-21 04:22:12,174 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220334515] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:12,174 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:12,174 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:12,174 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450682966] [2022-02-21 04:22:12,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:12,174 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:12,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:12,175 INFO L85 PathProgramCache]: Analyzing trace with hash 194481487, now seen corresponding path program 1 times [2022-02-21 04:22:12,175 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:12,175 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082292735] [2022-02-21 04:22:12,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:12,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:12,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:12,196 INFO L290 TraceCheckUtils]: 0: Hoare triple {24896#true} assume !false; {24896#true} is VALID [2022-02-21 04:22:12,196 INFO L290 TraceCheckUtils]: 1: Hoare triple {24896#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {24896#true} is VALID [2022-02-21 04:22:12,196 INFO L290 TraceCheckUtils]: 2: Hoare triple {24896#true} assume !false; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 3: Hoare triple {24896#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 4: Hoare triple {24896#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 5: Hoare triple {24896#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 6: Hoare triple {24896#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 7: Hoare triple {24896#true} assume !(0 != eval_~tmp~0#1); {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 8: Hoare triple {24896#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 9: Hoare triple {24896#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 10: Hoare triple {24896#true} assume 0 == ~M_E~0;~M_E~0 := 1; {24896#true} is VALID [2022-02-21 04:22:12,197 INFO L290 TraceCheckUtils]: 11: Hoare triple {24896#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {24896#true} is VALID [2022-02-21 04:22:12,198 INFO L290 TraceCheckUtils]: 12: Hoare triple {24896#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,198 INFO L290 TraceCheckUtils]: 13: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,198 INFO L290 TraceCheckUtils]: 14: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,199 INFO L290 TraceCheckUtils]: 15: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,199 INFO L290 TraceCheckUtils]: 16: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,199 INFO L290 TraceCheckUtils]: 17: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,199 INFO L290 TraceCheckUtils]: 18: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,200 INFO L290 TraceCheckUtils]: 19: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,200 INFO L290 TraceCheckUtils]: 20: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,200 INFO L290 TraceCheckUtils]: 21: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,200 INFO L290 TraceCheckUtils]: 22: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,201 INFO L290 TraceCheckUtils]: 23: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,201 INFO L290 TraceCheckUtils]: 24: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,201 INFO L290 TraceCheckUtils]: 25: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,201 INFO L290 TraceCheckUtils]: 26: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,202 INFO L290 TraceCheckUtils]: 27: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,202 INFO L290 TraceCheckUtils]: 28: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,202 INFO L290 TraceCheckUtils]: 29: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,202 INFO L290 TraceCheckUtils]: 30: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,203 INFO L290 TraceCheckUtils]: 31: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,203 INFO L290 TraceCheckUtils]: 32: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,203 INFO L290 TraceCheckUtils]: 33: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,203 INFO L290 TraceCheckUtils]: 34: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,204 INFO L290 TraceCheckUtils]: 35: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,204 INFO L290 TraceCheckUtils]: 36: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,204 INFO L290 TraceCheckUtils]: 37: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,204 INFO L290 TraceCheckUtils]: 38: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,205 INFO L290 TraceCheckUtils]: 39: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,205 INFO L290 TraceCheckUtils]: 40: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,205 INFO L290 TraceCheckUtils]: 41: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,205 INFO L290 TraceCheckUtils]: 42: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,206 INFO L290 TraceCheckUtils]: 43: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,206 INFO L290 TraceCheckUtils]: 44: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,206 INFO L290 TraceCheckUtils]: 45: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,206 INFO L290 TraceCheckUtils]: 46: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,207 INFO L290 TraceCheckUtils]: 47: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,207 INFO L290 TraceCheckUtils]: 48: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,207 INFO L290 TraceCheckUtils]: 49: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,207 INFO L290 TraceCheckUtils]: 50: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,208 INFO L290 TraceCheckUtils]: 51: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,208 INFO L290 TraceCheckUtils]: 52: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,208 INFO L290 TraceCheckUtils]: 53: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,208 INFO L290 TraceCheckUtils]: 54: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,209 INFO L290 TraceCheckUtils]: 55: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,209 INFO L290 TraceCheckUtils]: 56: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,209 INFO L290 TraceCheckUtils]: 57: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,209 INFO L290 TraceCheckUtils]: 58: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,210 INFO L290 TraceCheckUtils]: 59: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,210 INFO L290 TraceCheckUtils]: 60: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,210 INFO L290 TraceCheckUtils]: 61: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,210 INFO L290 TraceCheckUtils]: 62: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,211 INFO L290 TraceCheckUtils]: 63: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,211 INFO L290 TraceCheckUtils]: 64: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,211 INFO L290 TraceCheckUtils]: 65: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,211 INFO L290 TraceCheckUtils]: 66: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,212 INFO L290 TraceCheckUtils]: 67: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,212 INFO L290 TraceCheckUtils]: 68: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,212 INFO L290 TraceCheckUtils]: 69: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,212 INFO L290 TraceCheckUtils]: 70: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,213 INFO L290 TraceCheckUtils]: 71: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,213 INFO L290 TraceCheckUtils]: 72: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,213 INFO L290 TraceCheckUtils]: 73: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,213 INFO L290 TraceCheckUtils]: 74: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,214 INFO L290 TraceCheckUtils]: 75: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,214 INFO L290 TraceCheckUtils]: 76: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,214 INFO L290 TraceCheckUtils]: 77: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,214 INFO L290 TraceCheckUtils]: 78: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,215 INFO L290 TraceCheckUtils]: 79: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,215 INFO L290 TraceCheckUtils]: 80: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,222 INFO L290 TraceCheckUtils]: 81: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,222 INFO L290 TraceCheckUtils]: 82: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,222 INFO L290 TraceCheckUtils]: 83: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,222 INFO L290 TraceCheckUtils]: 84: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {24898#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,223 INFO L290 TraceCheckUtils]: 85: Hoare triple {24898#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {24897#false} is VALID [2022-02-21 04:22:12,223 INFO L290 TraceCheckUtils]: 86: Hoare triple {24897#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,223 INFO L290 TraceCheckUtils]: 87: Hoare triple {24897#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,223 INFO L290 TraceCheckUtils]: 88: Hoare triple {24897#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,223 INFO L290 TraceCheckUtils]: 89: Hoare triple {24897#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,223 INFO L290 TraceCheckUtils]: 90: Hoare triple {24897#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,223 INFO L290 TraceCheckUtils]: 91: Hoare triple {24897#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 92: Hoare triple {24897#false} assume 1 == ~E_M~0;~E_M~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 93: Hoare triple {24897#false} assume !(1 == ~E_1~0); {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 94: Hoare triple {24897#false} assume 1 == ~E_2~0;~E_2~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 95: Hoare triple {24897#false} assume 1 == ~E_3~0;~E_3~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 96: Hoare triple {24897#false} assume 1 == ~E_4~0;~E_4~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 97: Hoare triple {24897#false} assume 1 == ~E_5~0;~E_5~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 98: Hoare triple {24897#false} assume 1 == ~E_6~0;~E_6~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 99: Hoare triple {24897#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,224 INFO L290 TraceCheckUtils]: 100: Hoare triple {24897#false} assume 1 == ~E_8~0;~E_8~0 := 2; {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 101: Hoare triple {24897#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 102: Hoare triple {24897#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 103: Hoare triple {24897#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 104: Hoare triple {24897#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 105: Hoare triple {24897#false} assume !(0 == start_simulation_~tmp~3#1); {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 106: Hoare triple {24897#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 107: Hoare triple {24897#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {24897#false} is VALID [2022-02-21 04:22:12,225 INFO L290 TraceCheckUtils]: 108: Hoare triple {24897#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {24897#false} is VALID [2022-02-21 04:22:12,226 INFO L290 TraceCheckUtils]: 109: Hoare triple {24897#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {24897#false} is VALID [2022-02-21 04:22:12,226 INFO L290 TraceCheckUtils]: 110: Hoare triple {24897#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {24897#false} is VALID [2022-02-21 04:22:12,226 INFO L290 TraceCheckUtils]: 111: Hoare triple {24897#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24897#false} is VALID [2022-02-21 04:22:12,226 INFO L290 TraceCheckUtils]: 112: Hoare triple {24897#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {24897#false} is VALID [2022-02-21 04:22:12,226 INFO L290 TraceCheckUtils]: 113: Hoare triple {24897#false} assume !(0 != start_simulation_~tmp___0~1#1); {24897#false} is VALID [2022-02-21 04:22:12,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:12,226 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:12,227 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082292735] [2022-02-21 04:22:12,227 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082292735] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:12,227 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:12,227 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:12,227 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999535852] [2022-02-21 04:22:12,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:12,228 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:12,228 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:12,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:12,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:12,228 INFO L87 Difference]: Start difference. First operand 993 states and 1476 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,883 INFO L93 Difference]: Finished difference Result 993 states and 1475 transitions. [2022-02-21 04:22:12,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:12,884 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,937 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:12,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1475 transitions. [2022-02-21 04:22:12,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:12,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1475 transitions. [2022-02-21 04:22:12,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:12,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:12,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1475 transitions. [2022-02-21 04:22:12,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:12,987 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-02-21 04:22:12,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1475 transitions. [2022-02-21 04:22:12,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:12,994 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:12,996 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1475 transitions. Second operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,997 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1475 transitions. Second operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,997 INFO L87 Difference]: Start difference. First operand 993 states and 1475 transitions. Second operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,020 INFO L93 Difference]: Finished difference Result 993 states and 1475 transitions. [2022-02-21 04:22:13,020 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1475 transitions. [2022-02-21 04:22:13,021 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:13,021 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:13,022 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1475 transitions. [2022-02-21 04:22:13,023 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1475 transitions. [2022-02-21 04:22:13,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,045 INFO L93 Difference]: Finished difference Result 993 states and 1475 transitions. [2022-02-21 04:22:13,046 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1475 transitions. [2022-02-21 04:22:13,047 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:13,047 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:13,047 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:13,047 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:13,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.48539778449144) internal successors, (1475), 992 states have internal predecessors, (1475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1475 transitions. [2022-02-21 04:22:13,070 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-02-21 04:22:13,070 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1475 transitions. [2022-02-21 04:22:13,070 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:22:13,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1475 transitions. [2022-02-21 04:22:13,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:13,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:13,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:13,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:13,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:13,084 INFO L791 eck$LassoCheckResult]: Stem: 26652#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 26653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25939#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25940#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25977#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 26603#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26604#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26225#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26226#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26166#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26167#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26410#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26383#L632-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26384#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26656#L854 assume !(0 == ~M_E~0); 26470#L854-2 assume !(0 == ~T1_E~0); 26471#L859-1 assume !(0 == ~T2_E~0); 26041#L864-1 assume !(0 == ~T3_E~0); 26042#L869-1 assume !(0 == ~T4_E~0); 26155#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26855#L879-1 assume !(0 == ~T6_E~0); 26458#L884-1 assume !(0 == ~T7_E~0); 25909#L889-1 assume !(0 == ~T8_E~0); 25910#L894-1 assume !(0 == ~E_M~0); 26240#L899-1 assume !(0 == ~E_1~0); 26663#L904-1 assume !(0 == ~E_2~0); 26399#L909-1 assume !(0 == ~E_3~0); 26400#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26594#L919-1 assume !(0 == ~E_5~0); 26320#L924-1 assume !(0 == ~E_6~0); 26138#L929-1 assume !(0 == ~E_7~0); 26139#L934-1 assume !(0 == ~E_8~0); 26380#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25927#L418 assume !(1 == ~m_pc~0); 25899#L418-2 is_master_triggered_~__retres1~0#1 := 0; 25898#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26814#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26763#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26688#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26689#L437 assume 1 == ~t1_pc~0; 26872#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26771#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26724#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26275#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 26276#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26754#L456 assume !(1 == ~t2_pc~0); 26191#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26190#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26529#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26530#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 26505#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26035#L475 assume 1 == ~t3_pc~0; 26036#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26096#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26097#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26850#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 26279#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26280#L494 assume !(1 == ~t4_pc~0); 26315#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26316#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26520#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26521#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 26617#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26091#L513 assume 1 == ~t5_pc~0; 26092#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26317#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26354#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26052#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 26053#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26004#L532 assume !(1 == ~t6_pc~0); 26005#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26156#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26435#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26514#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 26245#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26246#L551 assume 1 == ~t7_pc~0; 26792#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26621#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26622#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26803#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 26881#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26419#L570 assume 1 == ~t8_pc~0; 26420#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26531#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26665#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26525#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 26029#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26030#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 25978#L952-2 assume !(1 == ~T1_E~0); 25979#L957-1 assume !(1 == ~T2_E~0); 26736#L962-1 assume !(1 == ~T3_E~0); 26541#L967-1 assume !(1 == ~T4_E~0); 26542#L972-1 assume !(1 == ~T5_E~0); 26793#L977-1 assume !(1 == ~T6_E~0); 26794#L982-1 assume !(1 == ~T7_E~0); 26158#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26159#L992-1 assume !(1 == ~E_M~0); 26168#L997-1 assume !(1 == ~E_1~0); 26503#L1002-1 assume !(1 == ~E_2~0); 26491#L1007-1 assume !(1 == ~E_3~0); 25911#L1012-1 assume !(1 == ~E_4~0); 25912#L1017-1 assume !(1 == ~E_5~0); 26492#L1022-1 assume !(1 == ~E_6~0); 26493#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26515#L1032-1 assume !(1 == ~E_8~0); 26640#L1037-1 assume { :end_inline_reset_delta_events } true; 26641#L1303-2 [2022-02-21 04:22:13,085 INFO L793 eck$LassoCheckResult]: Loop: 26641#L1303-2 assume !false; 26731#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25922#L829 assume !false; 26685#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26300#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26228#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26631#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26609#L712 assume !(0 != eval_~tmp~0#1); 26610#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25946#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25947#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26612#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26613#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26879#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26853#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26436#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26437#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26504#L884-3 assume !(0 == ~T7_E~0); 26485#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26129#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26130#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26162#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26163#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26103#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26104#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26151#L924-3 assume !(0 == ~E_6~0); 26693#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26595#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26596#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26722#L418-30 assume 1 == ~m_pc~0; 25993#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25994#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26448#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26449#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26192#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26193#L437-30 assume !(1 == ~t1_pc~0); 26318#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 26523#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26524#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26711#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26870#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26284#L456-30 assume 1 == ~t2_pc~0; 26285#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26682#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26683#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26077#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26078#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26411#L475-30 assume 1 == ~t3_pc~0; 26786#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25960#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26611#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26856#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26302#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26303#L494-30 assume 1 == ~t4_pc~0; 26296#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25895#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25896#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26827#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 26806#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26807#L513-30 assume !(1 == ~t5_pc~0); 26416#L513-32 is_transmit5_triggered_~__retres1~5#1 := 0; 26417#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26481#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26707#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26708#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26427#L532-30 assume !(1 == ~t6_pc~0); 26428#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 26033#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26034#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26055#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26117#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26118#L551-30 assume 1 == ~t7_pc~0; 26170#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26230#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26102#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25913#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25914#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26281#L570-30 assume 1 == ~t8_pc~0; 26772#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26169#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26121#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25975#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25976#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26342#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26377#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26834#L957-3 assume !(1 == ~T2_E~0); 26835#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26752#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26753#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26661#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26662#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26884#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26330#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26331#L997-3 assume !(1 == ~E_1~0); 26326#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26327#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26142#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26143#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26239#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26457#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25944#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25945#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26182#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26183#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26087#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 26088#L1322 assume !(0 == start_simulation_~tmp~3#1); 26356#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26023#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26024#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26836#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 25928#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25929#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26664#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 26796#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 26641#L1303-2 [2022-02-21 04:22:13,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:13,085 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2022-02-21 04:22:13,085 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:13,085 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616967144] [2022-02-21 04:22:13,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:13,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:13,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:13,102 INFO L290 TraceCheckUtils]: 0: Hoare triple {28874#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {28874#true} is VALID [2022-02-21 04:22:13,102 INFO L290 TraceCheckUtils]: 1: Hoare triple {28874#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,102 INFO L290 TraceCheckUtils]: 2: Hoare triple {28876#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,103 INFO L290 TraceCheckUtils]: 3: Hoare triple {28876#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,103 INFO L290 TraceCheckUtils]: 4: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,103 INFO L290 TraceCheckUtils]: 5: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,103 INFO L290 TraceCheckUtils]: 6: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,104 INFO L290 TraceCheckUtils]: 7: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,104 INFO L290 TraceCheckUtils]: 8: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,104 INFO L290 TraceCheckUtils]: 9: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,104 INFO L290 TraceCheckUtils]: 10: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,105 INFO L290 TraceCheckUtils]: 11: Hoare triple {28876#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {28876#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:13,105 INFO L290 TraceCheckUtils]: 12: Hoare triple {28876#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {28875#false} is VALID [2022-02-21 04:22:13,105 INFO L290 TraceCheckUtils]: 13: Hoare triple {28875#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {28875#false} is VALID [2022-02-21 04:22:13,105 INFO L290 TraceCheckUtils]: 14: Hoare triple {28875#false} assume !(0 == ~M_E~0); {28875#false} is VALID [2022-02-21 04:22:13,105 INFO L290 TraceCheckUtils]: 15: Hoare triple {28875#false} assume !(0 == ~T1_E~0); {28875#false} is VALID [2022-02-21 04:22:13,105 INFO L290 TraceCheckUtils]: 16: Hoare triple {28875#false} assume !(0 == ~T2_E~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 17: Hoare triple {28875#false} assume !(0 == ~T3_E~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 18: Hoare triple {28875#false} assume !(0 == ~T4_E~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 19: Hoare triple {28875#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 20: Hoare triple {28875#false} assume !(0 == ~T6_E~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 21: Hoare triple {28875#false} assume !(0 == ~T7_E~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 22: Hoare triple {28875#false} assume !(0 == ~T8_E~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 23: Hoare triple {28875#false} assume !(0 == ~E_M~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 24: Hoare triple {28875#false} assume !(0 == ~E_1~0); {28875#false} is VALID [2022-02-21 04:22:13,106 INFO L290 TraceCheckUtils]: 25: Hoare triple {28875#false} assume !(0 == ~E_2~0); {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 26: Hoare triple {28875#false} assume !(0 == ~E_3~0); {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 27: Hoare triple {28875#false} assume 0 == ~E_4~0;~E_4~0 := 1; {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 28: Hoare triple {28875#false} assume !(0 == ~E_5~0); {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 29: Hoare triple {28875#false} assume !(0 == ~E_6~0); {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 30: Hoare triple {28875#false} assume !(0 == ~E_7~0); {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 31: Hoare triple {28875#false} assume !(0 == ~E_8~0); {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 32: Hoare triple {28875#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 33: Hoare triple {28875#false} assume !(1 == ~m_pc~0); {28875#false} is VALID [2022-02-21 04:22:13,107 INFO L290 TraceCheckUtils]: 34: Hoare triple {28875#false} is_master_triggered_~__retres1~0#1 := 0; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 35: Hoare triple {28875#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 36: Hoare triple {28875#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 37: Hoare triple {28875#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 38: Hoare triple {28875#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 39: Hoare triple {28875#false} assume 1 == ~t1_pc~0; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 40: Hoare triple {28875#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 41: Hoare triple {28875#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 42: Hoare triple {28875#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {28875#false} is VALID [2022-02-21 04:22:13,108 INFO L290 TraceCheckUtils]: 43: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___0~0#1); {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 44: Hoare triple {28875#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 45: Hoare triple {28875#false} assume !(1 == ~t2_pc~0); {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 46: Hoare triple {28875#false} is_transmit2_triggered_~__retres1~2#1 := 0; {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 47: Hoare triple {28875#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 48: Hoare triple {28875#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 49: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___1~0#1); {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 50: Hoare triple {28875#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 51: Hoare triple {28875#false} assume 1 == ~t3_pc~0; {28875#false} is VALID [2022-02-21 04:22:13,109 INFO L290 TraceCheckUtils]: 52: Hoare triple {28875#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 53: Hoare triple {28875#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 54: Hoare triple {28875#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 55: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___2~0#1); {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 56: Hoare triple {28875#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 57: Hoare triple {28875#false} assume !(1 == ~t4_pc~0); {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 58: Hoare triple {28875#false} is_transmit4_triggered_~__retres1~4#1 := 0; {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 59: Hoare triple {28875#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 60: Hoare triple {28875#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28875#false} is VALID [2022-02-21 04:22:13,110 INFO L290 TraceCheckUtils]: 61: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___3~0#1); {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 62: Hoare triple {28875#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 63: Hoare triple {28875#false} assume 1 == ~t5_pc~0; {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 64: Hoare triple {28875#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 65: Hoare triple {28875#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 66: Hoare triple {28875#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 67: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___4~0#1); {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 68: Hoare triple {28875#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 69: Hoare triple {28875#false} assume !(1 == ~t6_pc~0); {28875#false} is VALID [2022-02-21 04:22:13,111 INFO L290 TraceCheckUtils]: 70: Hoare triple {28875#false} is_transmit6_triggered_~__retres1~6#1 := 0; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 71: Hoare triple {28875#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 72: Hoare triple {28875#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 73: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___5~0#1); {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 74: Hoare triple {28875#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 75: Hoare triple {28875#false} assume 1 == ~t7_pc~0; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 76: Hoare triple {28875#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 77: Hoare triple {28875#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 78: Hoare triple {28875#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28875#false} is VALID [2022-02-21 04:22:13,112 INFO L290 TraceCheckUtils]: 79: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___6~0#1); {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 80: Hoare triple {28875#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 81: Hoare triple {28875#false} assume 1 == ~t8_pc~0; {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 82: Hoare triple {28875#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 83: Hoare triple {28875#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 84: Hoare triple {28875#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 85: Hoare triple {28875#false} assume !(0 != activate_threads_~tmp___7~0#1); {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 86: Hoare triple {28875#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 87: Hoare triple {28875#false} assume 1 == ~M_E~0;~M_E~0 := 2; {28875#false} is VALID [2022-02-21 04:22:13,113 INFO L290 TraceCheckUtils]: 88: Hoare triple {28875#false} assume !(1 == ~T1_E~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 89: Hoare triple {28875#false} assume !(1 == ~T2_E~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 90: Hoare triple {28875#false} assume !(1 == ~T3_E~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 91: Hoare triple {28875#false} assume !(1 == ~T4_E~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 92: Hoare triple {28875#false} assume !(1 == ~T5_E~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 93: Hoare triple {28875#false} assume !(1 == ~T6_E~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 94: Hoare triple {28875#false} assume !(1 == ~T7_E~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 95: Hoare triple {28875#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 96: Hoare triple {28875#false} assume !(1 == ~E_M~0); {28875#false} is VALID [2022-02-21 04:22:13,114 INFO L290 TraceCheckUtils]: 97: Hoare triple {28875#false} assume !(1 == ~E_1~0); {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 98: Hoare triple {28875#false} assume !(1 == ~E_2~0); {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 99: Hoare triple {28875#false} assume !(1 == ~E_3~0); {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 100: Hoare triple {28875#false} assume !(1 == ~E_4~0); {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 101: Hoare triple {28875#false} assume !(1 == ~E_5~0); {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 102: Hoare triple {28875#false} assume !(1 == ~E_6~0); {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 103: Hoare triple {28875#false} assume 1 == ~E_7~0;~E_7~0 := 2; {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 104: Hoare triple {28875#false} assume !(1 == ~E_8~0); {28875#false} is VALID [2022-02-21 04:22:13,115 INFO L290 TraceCheckUtils]: 105: Hoare triple {28875#false} assume { :end_inline_reset_delta_events } true; {28875#false} is VALID [2022-02-21 04:22:13,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:13,116 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:13,116 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616967144] [2022-02-21 04:22:13,116 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616967144] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:13,116 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:13,116 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:13,116 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747083170] [2022-02-21 04:22:13,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:13,117 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:13,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:13,117 INFO L85 PathProgramCache]: Analyzing trace with hash 1662684816, now seen corresponding path program 1 times [2022-02-21 04:22:13,117 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:13,118 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215904459] [2022-02-21 04:22:13,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:13,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:13,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:13,158 INFO L290 TraceCheckUtils]: 0: Hoare triple {28877#true} assume !false; {28877#true} is VALID [2022-02-21 04:22:13,158 INFO L290 TraceCheckUtils]: 1: Hoare triple {28877#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 2: Hoare triple {28877#true} assume !false; {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 3: Hoare triple {28877#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 4: Hoare triple {28877#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 5: Hoare triple {28877#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 6: Hoare triple {28877#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 7: Hoare triple {28877#true} assume !(0 != eval_~tmp~0#1); {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 8: Hoare triple {28877#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {28877#true} is VALID [2022-02-21 04:22:13,159 INFO L290 TraceCheckUtils]: 9: Hoare triple {28877#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {28877#true} is VALID [2022-02-21 04:22:13,160 INFO L290 TraceCheckUtils]: 10: Hoare triple {28877#true} assume 0 == ~M_E~0;~M_E~0 := 1; {28877#true} is VALID [2022-02-21 04:22:13,160 INFO L290 TraceCheckUtils]: 11: Hoare triple {28877#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {28877#true} is VALID [2022-02-21 04:22:13,160 INFO L290 TraceCheckUtils]: 12: Hoare triple {28877#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,160 INFO L290 TraceCheckUtils]: 13: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,160 INFO L290 TraceCheckUtils]: 14: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,161 INFO L290 TraceCheckUtils]: 15: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,161 INFO L290 TraceCheckUtils]: 16: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,161 INFO L290 TraceCheckUtils]: 17: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,161 INFO L290 TraceCheckUtils]: 18: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,162 INFO L290 TraceCheckUtils]: 19: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,162 INFO L290 TraceCheckUtils]: 20: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,162 INFO L290 TraceCheckUtils]: 21: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,162 INFO L290 TraceCheckUtils]: 22: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,163 INFO L290 TraceCheckUtils]: 23: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,163 INFO L290 TraceCheckUtils]: 24: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,163 INFO L290 TraceCheckUtils]: 25: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,163 INFO L290 TraceCheckUtils]: 26: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,164 INFO L290 TraceCheckUtils]: 27: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,164 INFO L290 TraceCheckUtils]: 28: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,164 INFO L290 TraceCheckUtils]: 29: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,164 INFO L290 TraceCheckUtils]: 30: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 31: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 32: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 33: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 34: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 35: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 36: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 37: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 38: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 39: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 40: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 41: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 42: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 43: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 44: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 45: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 46: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 47: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 48: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 49: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 50: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 51: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 52: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 53: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 54: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 55: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 56: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 57: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 58: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 59: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 60: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 61: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 62: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 63: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 64: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 65: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 66: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 67: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 68: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 69: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 70: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 71: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 72: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 73: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 74: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 75: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 76: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 77: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 78: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,177 INFO L290 TraceCheckUtils]: 79: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,177 INFO L290 TraceCheckUtils]: 80: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,177 INFO L290 TraceCheckUtils]: 81: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,178 INFO L290 TraceCheckUtils]: 82: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,178 INFO L290 TraceCheckUtils]: 83: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,178 INFO L290 TraceCheckUtils]: 84: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {28879#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,178 INFO L290 TraceCheckUtils]: 85: Hoare triple {28879#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {28878#false} is VALID [2022-02-21 04:22:13,178 INFO L290 TraceCheckUtils]: 86: Hoare triple {28878#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 87: Hoare triple {28878#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 88: Hoare triple {28878#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 89: Hoare triple {28878#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 90: Hoare triple {28878#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 91: Hoare triple {28878#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 92: Hoare triple {28878#false} assume 1 == ~E_M~0;~E_M~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 93: Hoare triple {28878#false} assume !(1 == ~E_1~0); {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 94: Hoare triple {28878#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,179 INFO L290 TraceCheckUtils]: 95: Hoare triple {28878#false} assume 1 == ~E_3~0;~E_3~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 96: Hoare triple {28878#false} assume 1 == ~E_4~0;~E_4~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 97: Hoare triple {28878#false} assume 1 == ~E_5~0;~E_5~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 98: Hoare triple {28878#false} assume 1 == ~E_6~0;~E_6~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 99: Hoare triple {28878#false} assume 1 == ~E_7~0;~E_7~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 100: Hoare triple {28878#false} assume 1 == ~E_8~0;~E_8~0 := 2; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 101: Hoare triple {28878#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 102: Hoare triple {28878#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 103: Hoare triple {28878#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {28878#false} is VALID [2022-02-21 04:22:13,180 INFO L290 TraceCheckUtils]: 104: Hoare triple {28878#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 105: Hoare triple {28878#false} assume !(0 == start_simulation_~tmp~3#1); {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 106: Hoare triple {28878#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 107: Hoare triple {28878#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 108: Hoare triple {28878#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 109: Hoare triple {28878#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 110: Hoare triple {28878#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 111: Hoare triple {28878#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 112: Hoare triple {28878#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {28878#false} is VALID [2022-02-21 04:22:13,181 INFO L290 TraceCheckUtils]: 113: Hoare triple {28878#false} assume !(0 != start_simulation_~tmp___0~1#1); {28878#false} is VALID [2022-02-21 04:22:13,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:13,182 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:13,184 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215904459] [2022-02-21 04:22:13,185 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215904459] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:13,185 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:13,185 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:13,185 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147827299] [2022-02-21 04:22:13,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:13,186 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:13,186 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:13,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:13,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:13,187 INFO L87 Difference]: Start difference. First operand 993 states and 1475 transitions. cyclomatic complexity: 483 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,831 INFO L93 Difference]: Finished difference Result 993 states and 1474 transitions. [2022-02-21 04:22:13,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:13,832 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,894 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:13,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 993 states and 1474 transitions. [2022-02-21 04:22:13,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:13,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 993 states to 993 states and 1474 transitions. [2022-02-21 04:22:13,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 993 [2022-02-21 04:22:13,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 993 [2022-02-21 04:22:13,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 993 states and 1474 transitions. [2022-02-21 04:22:13,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:13,943 INFO L681 BuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-02-21 04:22:13,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 993 states and 1474 transitions. [2022-02-21 04:22:13,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 993 to 993. [2022-02-21 04:22:13,951 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:13,952 INFO L82 GeneralOperation]: Start isEquivalent. First operand 993 states and 1474 transitions. Second operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,952 INFO L74 IsIncluded]: Start isIncluded. First operand 993 states and 1474 transitions. Second operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,953 INFO L87 Difference]: Start difference. First operand 993 states and 1474 transitions. Second operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,975 INFO L93 Difference]: Finished difference Result 993 states and 1474 transitions. [2022-02-21 04:22:13,975 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1474 transitions. [2022-02-21 04:22:13,976 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:13,977 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:13,978 INFO L74 IsIncluded]: Start isIncluded. First operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1474 transitions. [2022-02-21 04:22:13,978 INFO L87 Difference]: Start difference. First operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 993 states and 1474 transitions. [2022-02-21 04:22:14,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:14,001 INFO L93 Difference]: Finished difference Result 993 states and 1474 transitions. [2022-02-21 04:22:14,001 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1474 transitions. [2022-02-21 04:22:14,002 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:14,002 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:14,002 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:14,002 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:14,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 993 states, 993 states have (on average 1.4843907351460222) internal successors, (1474), 992 states have internal predecessors, (1474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 993 states and 1474 transitions. [2022-02-21 04:22:14,025 INFO L704 BuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-02-21 04:22:14,025 INFO L587 BuchiCegarLoop]: Abstraction has 993 states and 1474 transitions. [2022-02-21 04:22:14,025 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:22:14,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 993 states and 1474 transitions. [2022-02-21 04:22:14,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 878 [2022-02-21 04:22:14,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:14,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:14,029 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,030 INFO L791 eck$LassoCheckResult]: Stem: 30633#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 30634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 29920#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29921#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29958#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 30584#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30585#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30206#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30207#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30147#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30148#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30391#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30364#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30365#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30637#L854 assume !(0 == ~M_E~0); 30451#L854-2 assume !(0 == ~T1_E~0); 30452#L859-1 assume !(0 == ~T2_E~0); 30022#L864-1 assume !(0 == ~T3_E~0); 30023#L869-1 assume !(0 == ~T4_E~0); 30136#L874-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30836#L879-1 assume !(0 == ~T6_E~0); 30439#L884-1 assume !(0 == ~T7_E~0); 29890#L889-1 assume !(0 == ~T8_E~0); 29891#L894-1 assume !(0 == ~E_M~0); 30221#L899-1 assume !(0 == ~E_1~0); 30644#L904-1 assume !(0 == ~E_2~0); 30380#L909-1 assume !(0 == ~E_3~0); 30381#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30575#L919-1 assume !(0 == ~E_5~0); 30301#L924-1 assume !(0 == ~E_6~0); 30119#L929-1 assume !(0 == ~E_7~0); 30120#L934-1 assume !(0 == ~E_8~0); 30361#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29908#L418 assume !(1 == ~m_pc~0); 29880#L418-2 is_master_triggered_~__retres1~0#1 := 0; 29879#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30795#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30744#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30669#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30670#L437 assume 1 == ~t1_pc~0; 30853#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30752#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30705#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30256#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 30257#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30735#L456 assume !(1 == ~t2_pc~0); 30172#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30171#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30510#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30511#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 30486#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30016#L475 assume 1 == ~t3_pc~0; 30017#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30077#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30078#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30831#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 30260#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30261#L494 assume !(1 == ~t4_pc~0); 30296#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30297#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30501#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30502#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 30598#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30072#L513 assume 1 == ~t5_pc~0; 30073#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30298#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30335#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30033#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 30034#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29985#L532 assume !(1 == ~t6_pc~0); 29986#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30137#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30416#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30495#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 30226#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30227#L551 assume 1 == ~t7_pc~0; 30773#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30602#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30603#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30784#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 30862#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30400#L570 assume 1 == ~t8_pc~0; 30401#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30512#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30646#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30506#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 30010#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30011#L952 assume 1 == ~M_E~0;~M_E~0 := 2; 29959#L952-2 assume !(1 == ~T1_E~0); 29960#L957-1 assume !(1 == ~T2_E~0); 30717#L962-1 assume !(1 == ~T3_E~0); 30522#L967-1 assume !(1 == ~T4_E~0); 30523#L972-1 assume !(1 == ~T5_E~0); 30774#L977-1 assume !(1 == ~T6_E~0); 30775#L982-1 assume !(1 == ~T7_E~0); 30139#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30140#L992-1 assume !(1 == ~E_M~0); 30149#L997-1 assume !(1 == ~E_1~0); 30484#L1002-1 assume !(1 == ~E_2~0); 30472#L1007-1 assume !(1 == ~E_3~0); 29892#L1012-1 assume !(1 == ~E_4~0); 29893#L1017-1 assume !(1 == ~E_5~0); 30473#L1022-1 assume !(1 == ~E_6~0); 30474#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30496#L1032-1 assume !(1 == ~E_8~0); 30621#L1037-1 assume { :end_inline_reset_delta_events } true; 30622#L1303-2 [2022-02-21 04:22:14,030 INFO L793 eck$LassoCheckResult]: Loop: 30622#L1303-2 assume !false; 30712#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29903#L829 assume !false; 30666#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 30281#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 30209#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 30612#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30590#L712 assume !(0 != eval_~tmp~0#1); 30591#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29927#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29928#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30593#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30594#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30860#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30834#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30417#L874-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30418#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30485#L884-3 assume !(0 == ~T7_E~0); 30466#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30110#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30111#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30143#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30144#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30084#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30085#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30132#L924-3 assume !(0 == ~E_6~0); 30674#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30576#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30577#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30703#L418-30 assume 1 == ~m_pc~0; 29974#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29975#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30429#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30430#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30173#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30174#L437-30 assume !(1 == ~t1_pc~0); 30299#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 30504#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30505#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30692#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30851#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30265#L456-30 assume 1 == ~t2_pc~0; 30266#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30663#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30664#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30058#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30059#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30392#L475-30 assume !(1 == ~t3_pc~0); 29940#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 29941#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30592#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30837#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30283#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30284#L494-30 assume 1 == ~t4_pc~0; 30277#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29876#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29877#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30808#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 30787#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30788#L513-30 assume 1 == ~t5_pc~0; 30864#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30398#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30462#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30688#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30689#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30408#L532-30 assume !(1 == ~t6_pc~0); 30409#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 30014#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30015#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30036#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30098#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30099#L551-30 assume 1 == ~t7_pc~0; 30151#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30211#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30083#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29894#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29895#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30262#L570-30 assume 1 == ~t8_pc~0; 30753#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30150#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30102#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29956#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29957#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30323#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30358#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30815#L957-3 assume !(1 == ~T2_E~0); 30816#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30733#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30734#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30642#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30643#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30865#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30311#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30312#L997-3 assume !(1 == ~E_1~0); 30307#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30308#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30123#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30124#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30220#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30438#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29925#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29926#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 30163#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 30164#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 30068#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 30069#L1322 assume !(0 == start_simulation_~tmp~3#1); 30337#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 30004#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 30005#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 30817#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 29909#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29910#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30645#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 30777#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 30622#L1303-2 [2022-02-21 04:22:14,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,031 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2022-02-21 04:22:14,031 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,031 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218749451] [2022-02-21 04:22:14,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,056 INFO L290 TraceCheckUtils]: 0: Hoare triple {32855#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,056 INFO L290 TraceCheckUtils]: 1: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,056 INFO L290 TraceCheckUtils]: 2: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,057 INFO L290 TraceCheckUtils]: 3: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,057 INFO L290 TraceCheckUtils]: 4: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,057 INFO L290 TraceCheckUtils]: 5: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,057 INFO L290 TraceCheckUtils]: 6: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,058 INFO L290 TraceCheckUtils]: 7: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,058 INFO L290 TraceCheckUtils]: 8: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,058 INFO L290 TraceCheckUtils]: 9: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,058 INFO L290 TraceCheckUtils]: 10: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,059 INFO L290 TraceCheckUtils]: 11: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,059 INFO L290 TraceCheckUtils]: 12: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,059 INFO L290 TraceCheckUtils]: 13: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {32857#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,059 INFO L290 TraceCheckUtils]: 14: Hoare triple {32857#(= ~T5_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {32858#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:14,060 INFO L290 TraceCheckUtils]: 15: Hoare triple {32858#(not (= ~T5_E~0 0))} assume !(0 == ~T1_E~0); {32858#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:14,060 INFO L290 TraceCheckUtils]: 16: Hoare triple {32858#(not (= ~T5_E~0 0))} assume !(0 == ~T2_E~0); {32858#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:14,060 INFO L290 TraceCheckUtils]: 17: Hoare triple {32858#(not (= ~T5_E~0 0))} assume !(0 == ~T3_E~0); {32858#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 18: Hoare triple {32858#(not (= ~T5_E~0 0))} assume !(0 == ~T4_E~0); {32858#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 19: Hoare triple {32858#(not (= ~T5_E~0 0))} assume 0 == ~T5_E~0;~T5_E~0 := 1; {32856#false} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 20: Hoare triple {32856#false} assume !(0 == ~T6_E~0); {32856#false} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 21: Hoare triple {32856#false} assume !(0 == ~T7_E~0); {32856#false} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 22: Hoare triple {32856#false} assume !(0 == ~T8_E~0); {32856#false} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 23: Hoare triple {32856#false} assume !(0 == ~E_M~0); {32856#false} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 24: Hoare triple {32856#false} assume !(0 == ~E_1~0); {32856#false} is VALID [2022-02-21 04:22:14,061 INFO L290 TraceCheckUtils]: 25: Hoare triple {32856#false} assume !(0 == ~E_2~0); {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 26: Hoare triple {32856#false} assume !(0 == ~E_3~0); {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 27: Hoare triple {32856#false} assume 0 == ~E_4~0;~E_4~0 := 1; {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 28: Hoare triple {32856#false} assume !(0 == ~E_5~0); {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 29: Hoare triple {32856#false} assume !(0 == ~E_6~0); {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 30: Hoare triple {32856#false} assume !(0 == ~E_7~0); {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 31: Hoare triple {32856#false} assume !(0 == ~E_8~0); {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 32: Hoare triple {32856#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 33: Hoare triple {32856#false} assume !(1 == ~m_pc~0); {32856#false} is VALID [2022-02-21 04:22:14,062 INFO L290 TraceCheckUtils]: 34: Hoare triple {32856#false} is_master_triggered_~__retres1~0#1 := 0; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 35: Hoare triple {32856#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 36: Hoare triple {32856#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 37: Hoare triple {32856#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 38: Hoare triple {32856#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 39: Hoare triple {32856#false} assume 1 == ~t1_pc~0; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 40: Hoare triple {32856#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 41: Hoare triple {32856#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32856#false} is VALID [2022-02-21 04:22:14,063 INFO L290 TraceCheckUtils]: 42: Hoare triple {32856#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 43: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___0~0#1); {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 44: Hoare triple {32856#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 45: Hoare triple {32856#false} assume !(1 == ~t2_pc~0); {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 46: Hoare triple {32856#false} is_transmit2_triggered_~__retres1~2#1 := 0; {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 47: Hoare triple {32856#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 48: Hoare triple {32856#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 49: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___1~0#1); {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 50: Hoare triple {32856#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32856#false} is VALID [2022-02-21 04:22:14,064 INFO L290 TraceCheckUtils]: 51: Hoare triple {32856#false} assume 1 == ~t3_pc~0; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 52: Hoare triple {32856#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 53: Hoare triple {32856#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 54: Hoare triple {32856#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 55: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___2~0#1); {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 56: Hoare triple {32856#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 57: Hoare triple {32856#false} assume !(1 == ~t4_pc~0); {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 58: Hoare triple {32856#false} is_transmit4_triggered_~__retres1~4#1 := 0; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 59: Hoare triple {32856#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 60: Hoare triple {32856#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32856#false} is VALID [2022-02-21 04:22:14,065 INFO L290 TraceCheckUtils]: 61: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___3~0#1); {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 62: Hoare triple {32856#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 63: Hoare triple {32856#false} assume 1 == ~t5_pc~0; {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 64: Hoare triple {32856#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 65: Hoare triple {32856#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 66: Hoare triple {32856#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 67: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___4~0#1); {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 68: Hoare triple {32856#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32856#false} is VALID [2022-02-21 04:22:14,066 INFO L290 TraceCheckUtils]: 69: Hoare triple {32856#false} assume !(1 == ~t6_pc~0); {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 70: Hoare triple {32856#false} is_transmit6_triggered_~__retres1~6#1 := 0; {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 71: Hoare triple {32856#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 72: Hoare triple {32856#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 73: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___5~0#1); {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 74: Hoare triple {32856#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 75: Hoare triple {32856#false} assume 1 == ~t7_pc~0; {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 76: Hoare triple {32856#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 77: Hoare triple {32856#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32856#false} is VALID [2022-02-21 04:22:14,067 INFO L290 TraceCheckUtils]: 78: Hoare triple {32856#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 79: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___6~0#1); {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 80: Hoare triple {32856#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 81: Hoare triple {32856#false} assume 1 == ~t8_pc~0; {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 82: Hoare triple {32856#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 83: Hoare triple {32856#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 84: Hoare triple {32856#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 85: Hoare triple {32856#false} assume !(0 != activate_threads_~tmp___7~0#1); {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 86: Hoare triple {32856#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32856#false} is VALID [2022-02-21 04:22:14,068 INFO L290 TraceCheckUtils]: 87: Hoare triple {32856#false} assume 1 == ~M_E~0;~M_E~0 := 2; {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 88: Hoare triple {32856#false} assume !(1 == ~T1_E~0); {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 89: Hoare triple {32856#false} assume !(1 == ~T2_E~0); {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 90: Hoare triple {32856#false} assume !(1 == ~T3_E~0); {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 91: Hoare triple {32856#false} assume !(1 == ~T4_E~0); {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 92: Hoare triple {32856#false} assume !(1 == ~T5_E~0); {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 93: Hoare triple {32856#false} assume !(1 == ~T6_E~0); {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 94: Hoare triple {32856#false} assume !(1 == ~T7_E~0); {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 95: Hoare triple {32856#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {32856#false} is VALID [2022-02-21 04:22:14,069 INFO L290 TraceCheckUtils]: 96: Hoare triple {32856#false} assume !(1 == ~E_M~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 97: Hoare triple {32856#false} assume !(1 == ~E_1~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 98: Hoare triple {32856#false} assume !(1 == ~E_2~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 99: Hoare triple {32856#false} assume !(1 == ~E_3~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 100: Hoare triple {32856#false} assume !(1 == ~E_4~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 101: Hoare triple {32856#false} assume !(1 == ~E_5~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 102: Hoare triple {32856#false} assume !(1 == ~E_6~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 103: Hoare triple {32856#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 104: Hoare triple {32856#false} assume !(1 == ~E_8~0); {32856#false} is VALID [2022-02-21 04:22:14,070 INFO L290 TraceCheckUtils]: 105: Hoare triple {32856#false} assume { :end_inline_reset_delta_events } true; {32856#false} is VALID [2022-02-21 04:22:14,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,071 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,071 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218749451] [2022-02-21 04:22:14,071 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218749451] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,071 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,071 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,071 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345630288] [2022-02-21 04:22:14,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,072 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:14,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,072 INFO L85 PathProgramCache]: Analyzing trace with hash 613340432, now seen corresponding path program 1 times [2022-02-21 04:22:14,072 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,073 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247897821] [2022-02-21 04:22:14,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,093 INFO L290 TraceCheckUtils]: 0: Hoare triple {32859#true} assume !false; {32859#true} is VALID [2022-02-21 04:22:14,093 INFO L290 TraceCheckUtils]: 1: Hoare triple {32859#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 2: Hoare triple {32859#true} assume !false; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 3: Hoare triple {32859#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 4: Hoare triple {32859#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 5: Hoare triple {32859#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 6: Hoare triple {32859#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 7: Hoare triple {32859#true} assume !(0 != eval_~tmp~0#1); {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 8: Hoare triple {32859#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 9: Hoare triple {32859#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {32859#true} is VALID [2022-02-21 04:22:14,094 INFO L290 TraceCheckUtils]: 10: Hoare triple {32859#true} assume 0 == ~M_E~0;~M_E~0 := 1; {32859#true} is VALID [2022-02-21 04:22:14,095 INFO L290 TraceCheckUtils]: 11: Hoare triple {32859#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {32859#true} is VALID [2022-02-21 04:22:14,095 INFO L290 TraceCheckUtils]: 12: Hoare triple {32859#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,095 INFO L290 TraceCheckUtils]: 13: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,096 INFO L290 TraceCheckUtils]: 14: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,096 INFO L290 TraceCheckUtils]: 15: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,096 INFO L290 TraceCheckUtils]: 16: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,096 INFO L290 TraceCheckUtils]: 17: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,097 INFO L290 TraceCheckUtils]: 18: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,097 INFO L290 TraceCheckUtils]: 19: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,097 INFO L290 TraceCheckUtils]: 20: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,097 INFO L290 TraceCheckUtils]: 21: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,098 INFO L290 TraceCheckUtils]: 22: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,098 INFO L290 TraceCheckUtils]: 23: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,098 INFO L290 TraceCheckUtils]: 24: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,098 INFO L290 TraceCheckUtils]: 25: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,099 INFO L290 TraceCheckUtils]: 26: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,099 INFO L290 TraceCheckUtils]: 27: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,099 INFO L290 TraceCheckUtils]: 28: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,100 INFO L290 TraceCheckUtils]: 29: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,100 INFO L290 TraceCheckUtils]: 30: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,100 INFO L290 TraceCheckUtils]: 31: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,100 INFO L290 TraceCheckUtils]: 32: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,101 INFO L290 TraceCheckUtils]: 33: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,101 INFO L290 TraceCheckUtils]: 34: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,101 INFO L290 TraceCheckUtils]: 35: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,101 INFO L290 TraceCheckUtils]: 36: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,102 INFO L290 TraceCheckUtils]: 37: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,102 INFO L290 TraceCheckUtils]: 38: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,102 INFO L290 TraceCheckUtils]: 39: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,102 INFO L290 TraceCheckUtils]: 40: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,103 INFO L290 TraceCheckUtils]: 41: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,103 INFO L290 TraceCheckUtils]: 42: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,103 INFO L290 TraceCheckUtils]: 43: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,103 INFO L290 TraceCheckUtils]: 44: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,104 INFO L290 TraceCheckUtils]: 45: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,104 INFO L290 TraceCheckUtils]: 46: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,104 INFO L290 TraceCheckUtils]: 47: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,105 INFO L290 TraceCheckUtils]: 48: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,105 INFO L290 TraceCheckUtils]: 49: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,105 INFO L290 TraceCheckUtils]: 50: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,105 INFO L290 TraceCheckUtils]: 51: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,106 INFO L290 TraceCheckUtils]: 52: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,106 INFO L290 TraceCheckUtils]: 53: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,106 INFO L290 TraceCheckUtils]: 54: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,106 INFO L290 TraceCheckUtils]: 55: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,107 INFO L290 TraceCheckUtils]: 56: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,107 INFO L290 TraceCheckUtils]: 57: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,107 INFO L290 TraceCheckUtils]: 58: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,107 INFO L290 TraceCheckUtils]: 59: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,108 INFO L290 TraceCheckUtils]: 60: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,108 INFO L290 TraceCheckUtils]: 61: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,108 INFO L290 TraceCheckUtils]: 62: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,108 INFO L290 TraceCheckUtils]: 63: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,109 INFO L290 TraceCheckUtils]: 64: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,109 INFO L290 TraceCheckUtils]: 65: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,109 INFO L290 TraceCheckUtils]: 66: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,110 INFO L290 TraceCheckUtils]: 67: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,110 INFO L290 TraceCheckUtils]: 68: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,110 INFO L290 TraceCheckUtils]: 69: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,110 INFO L290 TraceCheckUtils]: 70: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,111 INFO L290 TraceCheckUtils]: 71: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,111 INFO L290 TraceCheckUtils]: 72: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,111 INFO L290 TraceCheckUtils]: 73: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,111 INFO L290 TraceCheckUtils]: 74: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,112 INFO L290 TraceCheckUtils]: 75: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,112 INFO L290 TraceCheckUtils]: 76: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,112 INFO L290 TraceCheckUtils]: 77: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,112 INFO L290 TraceCheckUtils]: 78: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,113 INFO L290 TraceCheckUtils]: 79: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,113 INFO L290 TraceCheckUtils]: 80: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,113 INFO L290 TraceCheckUtils]: 81: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,114 INFO L290 TraceCheckUtils]: 82: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,138 INFO L290 TraceCheckUtils]: 83: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,139 INFO L290 TraceCheckUtils]: 84: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {32861#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,139 INFO L290 TraceCheckUtils]: 85: Hoare triple {32861#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {32860#false} is VALID [2022-02-21 04:22:14,139 INFO L290 TraceCheckUtils]: 86: Hoare triple {32860#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,139 INFO L290 TraceCheckUtils]: 87: Hoare triple {32860#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,139 INFO L290 TraceCheckUtils]: 88: Hoare triple {32860#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,139 INFO L290 TraceCheckUtils]: 89: Hoare triple {32860#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,139 INFO L290 TraceCheckUtils]: 90: Hoare triple {32860#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 91: Hoare triple {32860#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 92: Hoare triple {32860#false} assume 1 == ~E_M~0;~E_M~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 93: Hoare triple {32860#false} assume !(1 == ~E_1~0); {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 94: Hoare triple {32860#false} assume 1 == ~E_2~0;~E_2~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 95: Hoare triple {32860#false} assume 1 == ~E_3~0;~E_3~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 96: Hoare triple {32860#false} assume 1 == ~E_4~0;~E_4~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 97: Hoare triple {32860#false} assume 1 == ~E_5~0;~E_5~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 98: Hoare triple {32860#false} assume 1 == ~E_6~0;~E_6~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,140 INFO L290 TraceCheckUtils]: 99: Hoare triple {32860#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 100: Hoare triple {32860#false} assume 1 == ~E_8~0;~E_8~0 := 2; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 101: Hoare triple {32860#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 102: Hoare triple {32860#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 103: Hoare triple {32860#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 104: Hoare triple {32860#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 105: Hoare triple {32860#false} assume !(0 == start_simulation_~tmp~3#1); {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 106: Hoare triple {32860#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 107: Hoare triple {32860#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {32860#false} is VALID [2022-02-21 04:22:14,141 INFO L290 TraceCheckUtils]: 108: Hoare triple {32860#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {32860#false} is VALID [2022-02-21 04:22:14,142 INFO L290 TraceCheckUtils]: 109: Hoare triple {32860#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {32860#false} is VALID [2022-02-21 04:22:14,142 INFO L290 TraceCheckUtils]: 110: Hoare triple {32860#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {32860#false} is VALID [2022-02-21 04:22:14,142 INFO L290 TraceCheckUtils]: 111: Hoare triple {32860#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {32860#false} is VALID [2022-02-21 04:22:14,142 INFO L290 TraceCheckUtils]: 112: Hoare triple {32860#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {32860#false} is VALID [2022-02-21 04:22:14,142 INFO L290 TraceCheckUtils]: 113: Hoare triple {32860#false} assume !(0 != start_simulation_~tmp___0~1#1); {32860#false} is VALID [2022-02-21 04:22:14,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,143 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,143 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247897821] [2022-02-21 04:22:14,143 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247897821] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,143 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,143 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,143 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976273627] [2022-02-21 04:22:14,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,144 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:14,144 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:14,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:14,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:14,144 INFO L87 Difference]: Start difference. First operand 993 states and 1474 transitions. cyclomatic complexity: 482 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:15,832 INFO L93 Difference]: Finished difference Result 1806 states and 2671 transitions. [2022-02-21 04:22:15,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:15,832 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,888 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:15,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1806 states and 2671 transitions. [2022-02-21 04:22:15,960 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2022-02-21 04:22:16,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1806 states to 1806 states and 2671 transitions. [2022-02-21 04:22:16,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1806 [2022-02-21 04:22:16,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1806 [2022-02-21 04:22:16,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1806 states and 2671 transitions. [2022-02-21 04:22:16,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:16,034 INFO L681 BuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-02-21 04:22:16,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1806 states and 2671 transitions. [2022-02-21 04:22:16,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1806 to 1806. [2022-02-21 04:22:16,051 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:16,052 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1806 states and 2671 transitions. Second operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,054 INFO L74 IsIncluded]: Start isIncluded. First operand 1806 states and 2671 transitions. Second operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,055 INFO L87 Difference]: Start difference. First operand 1806 states and 2671 transitions. Second operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:16,128 INFO L93 Difference]: Finished difference Result 1806 states and 2671 transitions. [2022-02-21 04:22:16,128 INFO L276 IsEmpty]: Start isEmpty. Operand 1806 states and 2671 transitions. [2022-02-21 04:22:16,130 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:16,131 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:16,133 INFO L74 IsIncluded]: Start isIncluded. First operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1806 states and 2671 transitions. [2022-02-21 04:22:16,134 INFO L87 Difference]: Start difference. First operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1806 states and 2671 transitions. [2022-02-21 04:22:16,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:16,205 INFO L93 Difference]: Finished difference Result 1806 states and 2671 transitions. [2022-02-21 04:22:16,205 INFO L276 IsEmpty]: Start isEmpty. Operand 1806 states and 2671 transitions. [2022-02-21 04:22:16,208 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:16,208 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:16,208 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:16,208 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:16,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1806 states, 1806 states have (on average 1.4789590254706533) internal successors, (2671), 1805 states have internal predecessors, (2671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1806 states to 1806 states and 2671 transitions. [2022-02-21 04:22:16,279 INFO L704 BuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-02-21 04:22:16,279 INFO L587 BuchiCegarLoop]: Abstraction has 1806 states and 2671 transitions. [2022-02-21 04:22:16,279 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:22:16,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1806 states and 2671 transitions. [2022-02-21 04:22:16,282 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1673 [2022-02-21 04:22:16,283 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:16,283 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:16,284 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:16,284 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:16,284 INFO L791 eck$LassoCheckResult]: Stem: 35444#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 35445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 34717#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34718#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34755#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 35392#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35393#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35005#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35006#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34945#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34946#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35195#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35168#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35169#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35449#L854 assume !(0 == ~M_E~0); 35256#L854-2 assume !(0 == ~T1_E~0); 35257#L859-1 assume !(0 == ~T2_E~0); 34819#L864-1 assume !(0 == ~T3_E~0); 34820#L869-1 assume !(0 == ~T4_E~0); 34934#L874-1 assume !(0 == ~T5_E~0); 35680#L879-1 assume !(0 == ~T6_E~0); 35244#L884-1 assume !(0 == ~T7_E~0); 34687#L889-1 assume !(0 == ~T8_E~0); 34688#L894-1 assume !(0 == ~E_M~0); 35020#L899-1 assume !(0 == ~E_1~0); 35456#L904-1 assume !(0 == ~E_2~0); 35184#L909-1 assume !(0 == ~E_3~0); 35185#L914-1 assume 0 == ~E_4~0;~E_4~0 := 1; 35383#L919-1 assume !(0 == ~E_5~0); 35102#L924-1 assume !(0 == ~E_6~0); 34917#L929-1 assume !(0 == ~E_7~0); 34918#L934-1 assume !(0 == ~E_8~0); 35165#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34705#L418 assume !(1 == ~m_pc~0); 34677#L418-2 is_master_triggered_~__retres1~0#1 := 0; 34676#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35627#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35566#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35482#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35483#L437 assume 1 == ~t1_pc~0; 35703#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35576#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35523#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35055#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 35056#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35557#L456 assume !(1 == ~t2_pc~0); 34971#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34970#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35317#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35318#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 35293#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34813#L475 assume 1 == ~t3_pc~0; 34814#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34875#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34876#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35672#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 35059#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35060#L494 assume !(1 == ~t4_pc~0); 35097#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35098#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35308#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35309#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 35406#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34870#L513 assume 1 == ~t5_pc~0; 34871#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35099#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35138#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34830#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 34831#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34782#L532 assume !(1 == ~t6_pc~0); 34783#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34935#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35220#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35302#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 35025#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35026#L551 assume 1 == ~t7_pc~0; 35600#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35411#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35412#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35615#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 35715#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35204#L570 assume 1 == ~t8_pc~0; 35205#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35319#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35458#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35313#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 34807#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34808#L952 assume !(1 == ~M_E~0); 35580#L952-2 assume !(1 == ~T1_E~0); 35848#L957-1 assume !(1 == ~T2_E~0); 35846#L962-1 assume !(1 == ~T3_E~0); 35844#L967-1 assume !(1 == ~T4_E~0); 35843#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35601#L977-1 assume !(1 == ~T6_E~0); 35602#L982-1 assume !(1 == ~T7_E~0); 34937#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34938#L992-1 assume !(1 == ~E_M~0); 34947#L997-1 assume !(1 == ~E_1~0); 35291#L1002-1 assume !(1 == ~E_2~0); 35279#L1007-1 assume !(1 == ~E_3~0); 34689#L1012-1 assume !(1 == ~E_4~0); 34690#L1017-1 assume !(1 == ~E_5~0); 35755#L1022-1 assume !(1 == ~E_6~0); 35753#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 35751#L1032-1 assume !(1 == ~E_8~0); 35750#L1037-1 assume { :end_inline_reset_delta_events } true; 35532#L1303-2 [2022-02-21 04:22:16,284 INFO L793 eck$LassoCheckResult]: Loop: 35532#L1303-2 assume !false; 35533#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35741#L829 assume !false; 35479#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 35082#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 35008#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 35731#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 35729#L712 assume !(0 != eval_~tmp~0#1); 35530#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34724#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34725#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35727#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36140#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36139#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36138#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36137#L874-3 assume !(0 == ~T5_E~0); 36136#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36135#L884-3 assume !(0 == ~T7_E~0); 36134#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36133#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36132#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36131#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36130#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36129#L914-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36128#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36127#L924-3 assume !(0 == ~E_6~0); 36126#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36125#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36124#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36123#L418-30 assume 1 == ~m_pc~0; 36121#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36120#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36119#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36118#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36117#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36116#L437-30 assume !(1 == ~t1_pc~0); 36114#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 36113#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36112#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36111#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36110#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36109#L456-30 assume 1 == ~t2_pc~0; 36107#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36106#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36105#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36104#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36103#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36102#L475-30 assume !(1 == ~t3_pc~0); 36100#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 36099#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36098#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36097#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36096#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36095#L494-30 assume 1 == ~t4_pc~0; 36093#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36092#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36091#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36090#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 36089#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36088#L513-30 assume 1 == ~t5_pc~0; 36086#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36085#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36084#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36083#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36082#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36081#L532-30 assume 1 == ~t6_pc~0; 36080#L533-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36078#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36077#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36076#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36075#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36074#L551-30 assume 1 == ~t7_pc~0; 36072#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36071#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36070#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36069#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36068#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36067#L570-30 assume !(1 == ~t8_pc~0); 36064#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 36061#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36059#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36057#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36055#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36053#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35161#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36049#L957-3 assume !(1 == ~T2_E~0); 36047#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36045#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36043#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35673#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36040#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36037#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36035#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36033#L997-3 assume !(1 == ~E_1~0); 36031#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36029#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36027#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36024#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36022#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36020#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36018#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36017#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 36008#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 36007#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 36006#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 36005#L1322 assume !(0 == start_simulation_~tmp~3#1); 35470#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 36003#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 35653#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 35654#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 35993#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35992#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35677#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 35678#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 35532#L1303-2 [2022-02-21 04:22:16,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:16,285 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2022-02-21 04:22:16,285 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:16,285 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015852345] [2022-02-21 04:22:16,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:16,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:16,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:16,306 INFO L290 TraceCheckUtils]: 0: Hoare triple {40091#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,306 INFO L290 TraceCheckUtils]: 1: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,307 INFO L290 TraceCheckUtils]: 2: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,307 INFO L290 TraceCheckUtils]: 3: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,307 INFO L290 TraceCheckUtils]: 4: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,307 INFO L290 TraceCheckUtils]: 5: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,308 INFO L290 TraceCheckUtils]: 6: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,308 INFO L290 TraceCheckUtils]: 7: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,308 INFO L290 TraceCheckUtils]: 8: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,308 INFO L290 TraceCheckUtils]: 9: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,309 INFO L290 TraceCheckUtils]: 10: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,309 INFO L290 TraceCheckUtils]: 11: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,309 INFO L290 TraceCheckUtils]: 12: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,309 INFO L290 TraceCheckUtils]: 13: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {40093#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,310 INFO L290 TraceCheckUtils]: 14: Hoare triple {40093#(= ~E_4~0 ~M_E~0)} assume !(0 == ~M_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,310 INFO L290 TraceCheckUtils]: 15: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T1_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,310 INFO L290 TraceCheckUtils]: 16: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T2_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,310 INFO L290 TraceCheckUtils]: 17: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T3_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,311 INFO L290 TraceCheckUtils]: 18: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T4_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,311 INFO L290 TraceCheckUtils]: 19: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T5_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,311 INFO L290 TraceCheckUtils]: 20: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T6_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,311 INFO L290 TraceCheckUtils]: 21: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T7_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,312 INFO L290 TraceCheckUtils]: 22: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~T8_E~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,312 INFO L290 TraceCheckUtils]: 23: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~E_M~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,312 INFO L290 TraceCheckUtils]: 24: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~E_1~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,312 INFO L290 TraceCheckUtils]: 25: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~E_2~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,313 INFO L290 TraceCheckUtils]: 26: Hoare triple {40094#(not (= ~E_4~0 0))} assume !(0 == ~E_3~0); {40094#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:16,313 INFO L290 TraceCheckUtils]: 27: Hoare triple {40094#(not (= ~E_4~0 0))} assume 0 == ~E_4~0;~E_4~0 := 1; {40092#false} is VALID [2022-02-21 04:22:16,313 INFO L290 TraceCheckUtils]: 28: Hoare triple {40092#false} assume !(0 == ~E_5~0); {40092#false} is VALID [2022-02-21 04:22:16,313 INFO L290 TraceCheckUtils]: 29: Hoare triple {40092#false} assume !(0 == ~E_6~0); {40092#false} is VALID [2022-02-21 04:22:16,313 INFO L290 TraceCheckUtils]: 30: Hoare triple {40092#false} assume !(0 == ~E_7~0); {40092#false} is VALID [2022-02-21 04:22:16,313 INFO L290 TraceCheckUtils]: 31: Hoare triple {40092#false} assume !(0 == ~E_8~0); {40092#false} is VALID [2022-02-21 04:22:16,313 INFO L290 TraceCheckUtils]: 32: Hoare triple {40092#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 33: Hoare triple {40092#false} assume !(1 == ~m_pc~0); {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 34: Hoare triple {40092#false} is_master_triggered_~__retres1~0#1 := 0; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 35: Hoare triple {40092#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 36: Hoare triple {40092#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 37: Hoare triple {40092#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 38: Hoare triple {40092#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 39: Hoare triple {40092#false} assume 1 == ~t1_pc~0; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 40: Hoare triple {40092#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {40092#false} is VALID [2022-02-21 04:22:16,314 INFO L290 TraceCheckUtils]: 41: Hoare triple {40092#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 42: Hoare triple {40092#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 43: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___0~0#1); {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 44: Hoare triple {40092#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 45: Hoare triple {40092#false} assume !(1 == ~t2_pc~0); {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 46: Hoare triple {40092#false} is_transmit2_triggered_~__retres1~2#1 := 0; {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 47: Hoare triple {40092#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 48: Hoare triple {40092#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {40092#false} is VALID [2022-02-21 04:22:16,315 INFO L290 TraceCheckUtils]: 49: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___1~0#1); {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 50: Hoare triple {40092#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 51: Hoare triple {40092#false} assume 1 == ~t3_pc~0; {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 52: Hoare triple {40092#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 53: Hoare triple {40092#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 54: Hoare triple {40092#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 55: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___2~0#1); {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 56: Hoare triple {40092#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 57: Hoare triple {40092#false} assume !(1 == ~t4_pc~0); {40092#false} is VALID [2022-02-21 04:22:16,316 INFO L290 TraceCheckUtils]: 58: Hoare triple {40092#false} is_transmit4_triggered_~__retres1~4#1 := 0; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 59: Hoare triple {40092#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 60: Hoare triple {40092#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 61: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___3~0#1); {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 62: Hoare triple {40092#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 63: Hoare triple {40092#false} assume 1 == ~t5_pc~0; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 64: Hoare triple {40092#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 65: Hoare triple {40092#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 66: Hoare triple {40092#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40092#false} is VALID [2022-02-21 04:22:16,317 INFO L290 TraceCheckUtils]: 67: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___4~0#1); {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 68: Hoare triple {40092#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 69: Hoare triple {40092#false} assume !(1 == ~t6_pc~0); {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 70: Hoare triple {40092#false} is_transmit6_triggered_~__retres1~6#1 := 0; {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 71: Hoare triple {40092#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 72: Hoare triple {40092#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 73: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___5~0#1); {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 74: Hoare triple {40092#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 75: Hoare triple {40092#false} assume 1 == ~t7_pc~0; {40092#false} is VALID [2022-02-21 04:22:16,318 INFO L290 TraceCheckUtils]: 76: Hoare triple {40092#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 77: Hoare triple {40092#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 78: Hoare triple {40092#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 79: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___6~0#1); {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 80: Hoare triple {40092#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 81: Hoare triple {40092#false} assume 1 == ~t8_pc~0; {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 82: Hoare triple {40092#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 83: Hoare triple {40092#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40092#false} is VALID [2022-02-21 04:22:16,319 INFO L290 TraceCheckUtils]: 84: Hoare triple {40092#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 85: Hoare triple {40092#false} assume !(0 != activate_threads_~tmp___7~0#1); {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 86: Hoare triple {40092#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 87: Hoare triple {40092#false} assume !(1 == ~M_E~0); {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 88: Hoare triple {40092#false} assume !(1 == ~T1_E~0); {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 89: Hoare triple {40092#false} assume !(1 == ~T2_E~0); {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 90: Hoare triple {40092#false} assume !(1 == ~T3_E~0); {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 91: Hoare triple {40092#false} assume !(1 == ~T4_E~0); {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 92: Hoare triple {40092#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 93: Hoare triple {40092#false} assume !(1 == ~T6_E~0); {40092#false} is VALID [2022-02-21 04:22:16,320 INFO L290 TraceCheckUtils]: 94: Hoare triple {40092#false} assume !(1 == ~T7_E~0); {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 95: Hoare triple {40092#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 96: Hoare triple {40092#false} assume !(1 == ~E_M~0); {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 97: Hoare triple {40092#false} assume !(1 == ~E_1~0); {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 98: Hoare triple {40092#false} assume !(1 == ~E_2~0); {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 99: Hoare triple {40092#false} assume !(1 == ~E_3~0); {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 100: Hoare triple {40092#false} assume !(1 == ~E_4~0); {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 101: Hoare triple {40092#false} assume !(1 == ~E_5~0); {40092#false} is VALID [2022-02-21 04:22:16,321 INFO L290 TraceCheckUtils]: 102: Hoare triple {40092#false} assume !(1 == ~E_6~0); {40092#false} is VALID [2022-02-21 04:22:16,322 INFO L290 TraceCheckUtils]: 103: Hoare triple {40092#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40092#false} is VALID [2022-02-21 04:22:16,322 INFO L290 TraceCheckUtils]: 104: Hoare triple {40092#false} assume !(1 == ~E_8~0); {40092#false} is VALID [2022-02-21 04:22:16,322 INFO L290 TraceCheckUtils]: 105: Hoare triple {40092#false} assume { :end_inline_reset_delta_events } true; {40092#false} is VALID [2022-02-21 04:22:16,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:16,322 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:16,322 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015852345] [2022-02-21 04:22:16,322 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015852345] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:16,323 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:16,323 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:16,323 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753066782] [2022-02-21 04:22:16,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:16,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:16,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:16,324 INFO L85 PathProgramCache]: Analyzing trace with hash 1301437970, now seen corresponding path program 1 times [2022-02-21 04:22:16,324 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:16,325 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600163448] [2022-02-21 04:22:16,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:16,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:16,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:16,355 INFO L290 TraceCheckUtils]: 0: Hoare triple {40095#true} assume !false; {40095#true} is VALID [2022-02-21 04:22:16,355 INFO L290 TraceCheckUtils]: 1: Hoare triple {40095#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {40095#true} is VALID [2022-02-21 04:22:16,355 INFO L290 TraceCheckUtils]: 2: Hoare triple {40095#true} assume !false; {40095#true} is VALID [2022-02-21 04:22:16,355 INFO L290 TraceCheckUtils]: 3: Hoare triple {40095#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 4: Hoare triple {40095#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 5: Hoare triple {40095#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 6: Hoare triple {40095#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 7: Hoare triple {40095#true} assume !(0 != eval_~tmp~0#1); {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 8: Hoare triple {40095#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 9: Hoare triple {40095#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 10: Hoare triple {40095#true} assume 0 == ~M_E~0;~M_E~0 := 1; {40095#true} is VALID [2022-02-21 04:22:16,356 INFO L290 TraceCheckUtils]: 11: Hoare triple {40095#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {40095#true} is VALID [2022-02-21 04:22:16,357 INFO L290 TraceCheckUtils]: 12: Hoare triple {40095#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,357 INFO L290 TraceCheckUtils]: 13: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,357 INFO L290 TraceCheckUtils]: 14: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,357 INFO L290 TraceCheckUtils]: 15: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,358 INFO L290 TraceCheckUtils]: 16: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,358 INFO L290 TraceCheckUtils]: 17: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,358 INFO L290 TraceCheckUtils]: 18: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,358 INFO L290 TraceCheckUtils]: 19: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,359 INFO L290 TraceCheckUtils]: 20: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,359 INFO L290 TraceCheckUtils]: 21: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,359 INFO L290 TraceCheckUtils]: 22: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,359 INFO L290 TraceCheckUtils]: 23: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,360 INFO L290 TraceCheckUtils]: 24: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,360 INFO L290 TraceCheckUtils]: 25: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,360 INFO L290 TraceCheckUtils]: 26: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,360 INFO L290 TraceCheckUtils]: 27: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,361 INFO L290 TraceCheckUtils]: 28: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,361 INFO L290 TraceCheckUtils]: 29: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,361 INFO L290 TraceCheckUtils]: 30: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,361 INFO L290 TraceCheckUtils]: 31: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,362 INFO L290 TraceCheckUtils]: 32: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,362 INFO L290 TraceCheckUtils]: 33: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,362 INFO L290 TraceCheckUtils]: 34: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,362 INFO L290 TraceCheckUtils]: 35: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,363 INFO L290 TraceCheckUtils]: 36: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,363 INFO L290 TraceCheckUtils]: 37: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,363 INFO L290 TraceCheckUtils]: 38: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,363 INFO L290 TraceCheckUtils]: 39: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,364 INFO L290 TraceCheckUtils]: 40: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,364 INFO L290 TraceCheckUtils]: 41: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,364 INFO L290 TraceCheckUtils]: 42: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,364 INFO L290 TraceCheckUtils]: 43: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,365 INFO L290 TraceCheckUtils]: 44: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,365 INFO L290 TraceCheckUtils]: 45: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,365 INFO L290 TraceCheckUtils]: 46: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,365 INFO L290 TraceCheckUtils]: 47: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,366 INFO L290 TraceCheckUtils]: 48: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,366 INFO L290 TraceCheckUtils]: 49: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,366 INFO L290 TraceCheckUtils]: 50: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,366 INFO L290 TraceCheckUtils]: 51: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,367 INFO L290 TraceCheckUtils]: 52: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,367 INFO L290 TraceCheckUtils]: 53: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,367 INFO L290 TraceCheckUtils]: 54: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,367 INFO L290 TraceCheckUtils]: 55: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,368 INFO L290 TraceCheckUtils]: 56: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,368 INFO L290 TraceCheckUtils]: 57: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,368 INFO L290 TraceCheckUtils]: 58: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,368 INFO L290 TraceCheckUtils]: 59: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,369 INFO L290 TraceCheckUtils]: 60: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,369 INFO L290 TraceCheckUtils]: 61: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,369 INFO L290 TraceCheckUtils]: 62: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,369 INFO L290 TraceCheckUtils]: 63: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,370 INFO L290 TraceCheckUtils]: 64: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,370 INFO L290 TraceCheckUtils]: 65: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,370 INFO L290 TraceCheckUtils]: 66: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,370 INFO L290 TraceCheckUtils]: 67: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,371 INFO L290 TraceCheckUtils]: 68: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,371 INFO L290 TraceCheckUtils]: 69: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,371 INFO L290 TraceCheckUtils]: 70: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,371 INFO L290 TraceCheckUtils]: 71: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,372 INFO L290 TraceCheckUtils]: 72: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,372 INFO L290 TraceCheckUtils]: 73: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,372 INFO L290 TraceCheckUtils]: 74: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,372 INFO L290 TraceCheckUtils]: 75: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,373 INFO L290 TraceCheckUtils]: 76: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,373 INFO L290 TraceCheckUtils]: 77: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,373 INFO L290 TraceCheckUtils]: 78: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,373 INFO L290 TraceCheckUtils]: 79: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,374 INFO L290 TraceCheckUtils]: 80: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,374 INFO L290 TraceCheckUtils]: 81: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,374 INFO L290 TraceCheckUtils]: 82: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,374 INFO L290 TraceCheckUtils]: 83: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,375 INFO L290 TraceCheckUtils]: 84: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {40097#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,375 INFO L290 TraceCheckUtils]: 85: Hoare triple {40097#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {40096#false} is VALID [2022-02-21 04:22:16,375 INFO L290 TraceCheckUtils]: 86: Hoare triple {40096#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,375 INFO L290 TraceCheckUtils]: 87: Hoare triple {40096#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,375 INFO L290 TraceCheckUtils]: 88: Hoare triple {40096#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,375 INFO L290 TraceCheckUtils]: 89: Hoare triple {40096#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 90: Hoare triple {40096#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 91: Hoare triple {40096#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 92: Hoare triple {40096#false} assume 1 == ~E_M~0;~E_M~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 93: Hoare triple {40096#false} assume !(1 == ~E_1~0); {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 94: Hoare triple {40096#false} assume 1 == ~E_2~0;~E_2~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 95: Hoare triple {40096#false} assume 1 == ~E_3~0;~E_3~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 96: Hoare triple {40096#false} assume 1 == ~E_4~0;~E_4~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 97: Hoare triple {40096#false} assume 1 == ~E_5~0;~E_5~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,376 INFO L290 TraceCheckUtils]: 98: Hoare triple {40096#false} assume 1 == ~E_6~0;~E_6~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 99: Hoare triple {40096#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 100: Hoare triple {40096#false} assume 1 == ~E_8~0;~E_8~0 := 2; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 101: Hoare triple {40096#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 102: Hoare triple {40096#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 103: Hoare triple {40096#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 104: Hoare triple {40096#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 105: Hoare triple {40096#false} assume !(0 == start_simulation_~tmp~3#1); {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 106: Hoare triple {40096#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {40096#false} is VALID [2022-02-21 04:22:16,377 INFO L290 TraceCheckUtils]: 107: Hoare triple {40096#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {40096#false} is VALID [2022-02-21 04:22:16,378 INFO L290 TraceCheckUtils]: 108: Hoare triple {40096#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {40096#false} is VALID [2022-02-21 04:22:16,378 INFO L290 TraceCheckUtils]: 109: Hoare triple {40096#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {40096#false} is VALID [2022-02-21 04:22:16,378 INFO L290 TraceCheckUtils]: 110: Hoare triple {40096#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {40096#false} is VALID [2022-02-21 04:22:16,378 INFO L290 TraceCheckUtils]: 111: Hoare triple {40096#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {40096#false} is VALID [2022-02-21 04:22:16,378 INFO L290 TraceCheckUtils]: 112: Hoare triple {40096#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {40096#false} is VALID [2022-02-21 04:22:16,378 INFO L290 TraceCheckUtils]: 113: Hoare triple {40096#false} assume !(0 != start_simulation_~tmp___0~1#1); {40096#false} is VALID [2022-02-21 04:22:16,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:16,379 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:16,379 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600163448] [2022-02-21 04:22:16,379 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600163448] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:16,379 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:16,379 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:16,379 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902091694] [2022-02-21 04:22:16,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:16,380 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:16,380 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:16,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:16,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:16,380 INFO L87 Difference]: Start difference. First operand 1806 states and 2671 transitions. cyclomatic complexity: 867 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:18,150 INFO L93 Difference]: Finished difference Result 3286 states and 4848 transitions. [2022-02-21 04:22:18,150 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:18,150 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,219 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:18,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3286 states and 4848 transitions. [2022-02-21 04:22:18,461 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2022-02-21 04:22:18,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3286 states to 3286 states and 4848 transitions. [2022-02-21 04:22:18,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3286 [2022-02-21 04:22:18,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3286 [2022-02-21 04:22:18,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3286 states and 4848 transitions. [2022-02-21 04:22:18,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:18,708 INFO L681 BuchiCegarLoop]: Abstraction has 3286 states and 4848 transitions. [2022-02-21 04:22:18,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3286 states and 4848 transitions. [2022-02-21 04:22:18,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3286 to 3284. [2022-02-21 04:22:18,744 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:18,748 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3286 states and 4848 transitions. Second operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,750 INFO L74 IsIncluded]: Start isIncluded. First operand 3286 states and 4848 transitions. Second operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,753 INFO L87 Difference]: Start difference. First operand 3286 states and 4848 transitions. Second operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:18,974 INFO L93 Difference]: Finished difference Result 3286 states and 4848 transitions. [2022-02-21 04:22:18,974 INFO L276 IsEmpty]: Start isEmpty. Operand 3286 states and 4848 transitions. [2022-02-21 04:22:18,978 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:18,978 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:18,982 INFO L74 IsIncluded]: Start isIncluded. First operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3286 states and 4848 transitions. [2022-02-21 04:22:18,984 INFO L87 Difference]: Start difference. First operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3286 states and 4848 transitions. [2022-02-21 04:22:19,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:19,221 INFO L93 Difference]: Finished difference Result 3286 states and 4848 transitions. [2022-02-21 04:22:19,221 INFO L276 IsEmpty]: Start isEmpty. Operand 3286 states and 4848 transitions. [2022-02-21 04:22:19,224 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:19,224 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:19,224 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:19,224 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:19,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3284 states, 3284 states have (on average 1.4756394640682096) internal successors, (4846), 3283 states have internal predecessors, (4846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:19,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3284 states to 3284 states and 4846 transitions. [2022-02-21 04:22:19,456 INFO L704 BuchiCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2022-02-21 04:22:19,456 INFO L587 BuchiCegarLoop]: Abstraction has 3284 states and 4846 transitions. [2022-02-21 04:22:19,456 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:22:19,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3284 states and 4846 transitions. [2022-02-21 04:22:19,462 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3133 [2022-02-21 04:22:19,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:19,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:19,463 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:19,463 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:19,463 INFO L791 eck$LassoCheckResult]: Stem: 44160#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 44161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 43437#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43438#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43472#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 44109#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44110#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43723#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43724#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43663#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43664#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43913#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43885#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43886#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44164#L854 assume !(0 == ~M_E~0); 43974#L854-2 assume !(0 == ~T1_E~0); 43975#L859-1 assume !(0 == ~T2_E~0); 43536#L864-1 assume !(0 == ~T3_E~0); 43537#L869-1 assume !(0 == ~T4_E~0); 43651#L874-1 assume !(0 == ~T5_E~0); 44373#L879-1 assume !(0 == ~T6_E~0); 43960#L884-1 assume !(0 == ~T7_E~0); 43403#L889-1 assume !(0 == ~T8_E~0); 43404#L894-1 assume !(0 == ~E_M~0); 43739#L899-1 assume !(0 == ~E_1~0); 44172#L904-1 assume !(0 == ~E_2~0); 43905#L909-1 assume !(0 == ~E_3~0); 43906#L914-1 assume !(0 == ~E_4~0); 44099#L919-1 assume !(0 == ~E_5~0); 43818#L924-1 assume !(0 == ~E_6~0); 43638#L929-1 assume !(0 == ~E_7~0); 43639#L934-1 assume !(0 == ~E_8~0); 43884#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43422#L418 assume !(1 == ~m_pc~0); 43395#L418-2 is_master_triggered_~__retres1~0#1 := 0; 43394#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44331#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44275#L1061 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44199#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44200#L437 assume 1 == ~t1_pc~0; 44395#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44283#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44233#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43772#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 43773#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44269#L456 assume !(1 == ~t2_pc~0); 43690#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43689#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44033#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44034#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 44009#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43530#L475 assume 1 == ~t3_pc~0; 43531#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43593#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43594#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44367#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 43776#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43777#L494 assume !(1 == ~t4_pc~0); 43813#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43814#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44025#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44026#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 44123#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43586#L513 assume 1 == ~t5_pc~0; 43587#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43817#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43856#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43547#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 43548#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43501#L532 assume !(1 == ~t6_pc~0); 43502#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43652#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43937#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44018#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 43742#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43743#L551 assume 1 == ~t7_pc~0; 44307#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44127#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44128#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44318#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 44407#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43923#L570 assume 1 == ~t8_pc~0; 43924#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44036#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44173#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44031#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 43528#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43529#L952 assume !(1 == ~M_E~0); 44288#L952-2 assume !(1 == ~T1_E~0); 44509#L957-1 assume !(1 == ~T2_E~0); 44508#L962-1 assume !(1 == ~T3_E~0); 44507#L967-1 assume !(1 == ~T4_E~0); 44389#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44308#L977-1 assume !(1 == ~T6_E~0); 44309#L982-1 assume !(1 == ~T7_E~0); 43654#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43655#L992-1 assume !(1 == ~E_M~0); 44006#L997-1 assume !(1 == ~E_1~0); 44007#L1002-1 assume !(1 == ~E_2~0); 44476#L1007-1 assume !(1 == ~E_3~0); 44464#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 44462#L1017-1 assume !(1 == ~E_5~0); 44460#L1022-1 assume !(1 == ~E_6~0); 44458#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44456#L1032-1 assume !(1 == ~E_8~0); 44446#L1037-1 assume { :end_inline_reset_delta_events } true; 44439#L1303-2 [2022-02-21 04:22:19,463 INFO L793 eck$LassoCheckResult]: Loop: 44439#L1303-2 assume !false; 44434#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44432#L829 assume !false; 44431#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44426#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44421#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44420#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44418#L712 assume !(0 != eval_~tmp~0#1); 44417#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44416#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44414#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44415#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45123#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45121#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45119#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45117#L874-3 assume !(0 == ~T5_E~0); 45114#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45112#L884-3 assume !(0 == ~T7_E~0); 45110#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45108#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45106#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45104#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45101#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45099#L914-3 assume !(0 == ~E_4~0); 45097#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45095#L924-3 assume !(0 == ~E_6~0); 45093#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45092#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45091#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45089#L418-30 assume 1 == ~m_pc~0; 45085#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45083#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45081#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45079#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45077#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45075#L437-30 assume 1 == ~t1_pc~0; 45072#L438-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45069#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45067#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45065#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45063#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45061#L456-30 assume 1 == ~t2_pc~0; 45057#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45055#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45053#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45051#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45049#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45047#L475-30 assume !(1 == ~t3_pc~0); 45043#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 45041#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45039#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45037#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45035#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45033#L494-30 assume 1 == ~t4_pc~0; 45029#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45027#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45025#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45023#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 45021#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45019#L513-30 assume 1 == ~t5_pc~0; 45015#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45014#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45013#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45011#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45008#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45006#L532-30 assume !(1 == ~t6_pc~0); 45003#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 45001#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44999#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44997#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44994#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44992#L551-30 assume 1 == ~t7_pc~0; 44989#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44987#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44985#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44983#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44980#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44978#L570-30 assume 1 == ~t8_pc~0; 44976#L571-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44973#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44880#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44878#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44863#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44843#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43878#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44828#L957-3 assume !(1 == ~T2_E~0); 44810#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44803#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44780#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44747#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44744#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44742#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44715#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44713#L997-3 assume !(1 == ~E_1~0); 44688#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44686#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44683#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44642#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44610#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44584#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44552#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44550#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44525#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44506#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44484#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 44482#L1322 assume !(0 == start_simulation_~tmp~3#1); 44185#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44473#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44463#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44461#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 44459#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44457#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44455#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 44445#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 44439#L1303-2 [2022-02-21 04:22:19,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:19,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2022-02-21 04:22:19,464 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:19,464 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608685176] [2022-02-21 04:22:19,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:19,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:19,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:19,491 INFO L290 TraceCheckUtils]: 0: Hoare triple {53245#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 1: Hoare triple {53245#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 2: Hoare triple {53245#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 3: Hoare triple {53245#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 4: Hoare triple {53245#true} assume 1 == ~m_i~0;~m_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 5: Hoare triple {53245#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 6: Hoare triple {53245#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 7: Hoare triple {53245#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,492 INFO L290 TraceCheckUtils]: 8: Hoare triple {53245#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 9: Hoare triple {53245#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 10: Hoare triple {53245#true} assume 1 == ~t6_i~0;~t6_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 11: Hoare triple {53245#true} assume 1 == ~t7_i~0;~t7_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 12: Hoare triple {53245#true} assume 1 == ~t8_i~0;~t8_st~0 := 0; {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 13: Hoare triple {53245#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 14: Hoare triple {53245#true} assume !(0 == ~M_E~0); {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 15: Hoare triple {53245#true} assume !(0 == ~T1_E~0); {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 16: Hoare triple {53245#true} assume !(0 == ~T2_E~0); {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 17: Hoare triple {53245#true} assume !(0 == ~T3_E~0); {53245#true} is VALID [2022-02-21 04:22:19,493 INFO L290 TraceCheckUtils]: 18: Hoare triple {53245#true} assume !(0 == ~T4_E~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 19: Hoare triple {53245#true} assume !(0 == ~T5_E~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 20: Hoare triple {53245#true} assume !(0 == ~T6_E~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 21: Hoare triple {53245#true} assume !(0 == ~T7_E~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 22: Hoare triple {53245#true} assume !(0 == ~T8_E~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 23: Hoare triple {53245#true} assume !(0 == ~E_M~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 24: Hoare triple {53245#true} assume !(0 == ~E_1~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 25: Hoare triple {53245#true} assume !(0 == ~E_2~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 26: Hoare triple {53245#true} assume !(0 == ~E_3~0); {53245#true} is VALID [2022-02-21 04:22:19,494 INFO L290 TraceCheckUtils]: 27: Hoare triple {53245#true} assume !(0 == ~E_4~0); {53245#true} is VALID [2022-02-21 04:22:19,495 INFO L290 TraceCheckUtils]: 28: Hoare triple {53245#true} assume !(0 == ~E_5~0); {53245#true} is VALID [2022-02-21 04:22:19,495 INFO L290 TraceCheckUtils]: 29: Hoare triple {53245#true} assume !(0 == ~E_6~0); {53245#true} is VALID [2022-02-21 04:22:19,495 INFO L290 TraceCheckUtils]: 30: Hoare triple {53245#true} assume !(0 == ~E_7~0); {53245#true} is VALID [2022-02-21 04:22:19,495 INFO L290 TraceCheckUtils]: 31: Hoare triple {53245#true} assume !(0 == ~E_8~0); {53245#true} is VALID [2022-02-21 04:22:19,496 INFO L290 TraceCheckUtils]: 32: Hoare triple {53245#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {53245#true} is VALID [2022-02-21 04:22:19,496 INFO L290 TraceCheckUtils]: 33: Hoare triple {53245#true} assume !(1 == ~m_pc~0); {53245#true} is VALID [2022-02-21 04:22:19,497 INFO L290 TraceCheckUtils]: 34: Hoare triple {53245#true} is_master_triggered_~__retres1~0#1 := 0; {53247#(= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0)} is VALID [2022-02-21 04:22:19,497 INFO L290 TraceCheckUtils]: 35: Hoare triple {53247#(= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {53248#(= |ULTIMATE.start_is_master_triggered_#res#1| 0)} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 36: Hoare triple {53248#(= |ULTIMATE.start_is_master_triggered_#res#1| 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {53249#(= |ULTIMATE.start_activate_threads_~tmp~1#1| 0)} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 37: Hoare triple {53249#(= |ULTIMATE.start_activate_threads_~tmp~1#1| 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {53246#false} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 38: Hoare triple {53246#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {53246#false} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 39: Hoare triple {53246#false} assume 1 == ~t1_pc~0; {53246#false} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 40: Hoare triple {53246#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {53246#false} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 41: Hoare triple {53246#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {53246#false} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 42: Hoare triple {53246#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {53246#false} is VALID [2022-02-21 04:22:19,498 INFO L290 TraceCheckUtils]: 43: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___0~0#1); {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 44: Hoare triple {53246#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 45: Hoare triple {53246#false} assume !(1 == ~t2_pc~0); {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 46: Hoare triple {53246#false} is_transmit2_triggered_~__retres1~2#1 := 0; {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 47: Hoare triple {53246#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 48: Hoare triple {53246#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 49: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___1~0#1); {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 50: Hoare triple {53246#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 51: Hoare triple {53246#false} assume 1 == ~t3_pc~0; {53246#false} is VALID [2022-02-21 04:22:19,499 INFO L290 TraceCheckUtils]: 52: Hoare triple {53246#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {53246#false} is VALID [2022-02-21 04:22:19,500 INFO L290 TraceCheckUtils]: 53: Hoare triple {53246#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {53246#false} is VALID [2022-02-21 04:22:19,500 INFO L290 TraceCheckUtils]: 54: Hoare triple {53246#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {53246#false} is VALID [2022-02-21 04:22:19,500 INFO L290 TraceCheckUtils]: 55: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___2~0#1); {53246#false} is VALID [2022-02-21 04:22:19,500 INFO L290 TraceCheckUtils]: 56: Hoare triple {53246#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {53246#false} is VALID [2022-02-21 04:22:19,500 INFO L290 TraceCheckUtils]: 57: Hoare triple {53246#false} assume !(1 == ~t4_pc~0); {53246#false} is VALID [2022-02-21 04:22:19,500 INFO L290 TraceCheckUtils]: 58: Hoare triple {53246#false} is_transmit4_triggered_~__retres1~4#1 := 0; {53246#false} is VALID [2022-02-21 04:22:19,513 INFO L290 TraceCheckUtils]: 59: Hoare triple {53246#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {53246#false} is VALID [2022-02-21 04:22:19,513 INFO L290 TraceCheckUtils]: 60: Hoare triple {53246#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {53246#false} is VALID [2022-02-21 04:22:19,513 INFO L290 TraceCheckUtils]: 61: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___3~0#1); {53246#false} is VALID [2022-02-21 04:22:19,513 INFO L290 TraceCheckUtils]: 62: Hoare triple {53246#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 63: Hoare triple {53246#false} assume 1 == ~t5_pc~0; {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 64: Hoare triple {53246#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 65: Hoare triple {53246#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 66: Hoare triple {53246#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 67: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___4~0#1); {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 68: Hoare triple {53246#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 69: Hoare triple {53246#false} assume !(1 == ~t6_pc~0); {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 70: Hoare triple {53246#false} is_transmit6_triggered_~__retres1~6#1 := 0; {53246#false} is VALID [2022-02-21 04:22:19,514 INFO L290 TraceCheckUtils]: 71: Hoare triple {53246#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 72: Hoare triple {53246#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 73: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___5~0#1); {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 74: Hoare triple {53246#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 75: Hoare triple {53246#false} assume 1 == ~t7_pc~0; {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 76: Hoare triple {53246#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 77: Hoare triple {53246#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 78: Hoare triple {53246#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 79: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___6~0#1); {53246#false} is VALID [2022-02-21 04:22:19,515 INFO L290 TraceCheckUtils]: 80: Hoare triple {53246#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 81: Hoare triple {53246#false} assume 1 == ~t8_pc~0; {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 82: Hoare triple {53246#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 83: Hoare triple {53246#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 84: Hoare triple {53246#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 85: Hoare triple {53246#false} assume !(0 != activate_threads_~tmp___7~0#1); {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 86: Hoare triple {53246#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 87: Hoare triple {53246#false} assume !(1 == ~M_E~0); {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 88: Hoare triple {53246#false} assume !(1 == ~T1_E~0); {53246#false} is VALID [2022-02-21 04:22:19,516 INFO L290 TraceCheckUtils]: 89: Hoare triple {53246#false} assume !(1 == ~T2_E~0); {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 90: Hoare triple {53246#false} assume !(1 == ~T3_E~0); {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 91: Hoare triple {53246#false} assume !(1 == ~T4_E~0); {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 92: Hoare triple {53246#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 93: Hoare triple {53246#false} assume !(1 == ~T6_E~0); {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 94: Hoare triple {53246#false} assume !(1 == ~T7_E~0); {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 95: Hoare triple {53246#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 96: Hoare triple {53246#false} assume !(1 == ~E_M~0); {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 97: Hoare triple {53246#false} assume !(1 == ~E_1~0); {53246#false} is VALID [2022-02-21 04:22:19,517 INFO L290 TraceCheckUtils]: 98: Hoare triple {53246#false} assume !(1 == ~E_2~0); {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L290 TraceCheckUtils]: 99: Hoare triple {53246#false} assume !(1 == ~E_3~0); {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L290 TraceCheckUtils]: 100: Hoare triple {53246#false} assume 1 == ~E_4~0;~E_4~0 := 2; {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L290 TraceCheckUtils]: 101: Hoare triple {53246#false} assume !(1 == ~E_5~0); {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L290 TraceCheckUtils]: 102: Hoare triple {53246#false} assume !(1 == ~E_6~0); {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L290 TraceCheckUtils]: 103: Hoare triple {53246#false} assume 1 == ~E_7~0;~E_7~0 := 2; {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L290 TraceCheckUtils]: 104: Hoare triple {53246#false} assume !(1 == ~E_8~0); {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L290 TraceCheckUtils]: 105: Hoare triple {53246#false} assume { :end_inline_reset_delta_events } true; {53246#false} is VALID [2022-02-21 04:22:19,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:19,519 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:19,519 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608685176] [2022-02-21 04:22:19,519 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1608685176] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:19,519 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:19,519 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:22:19,519 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869772112] [2022-02-21 04:22:19,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:19,520 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:19,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:19,520 INFO L85 PathProgramCache]: Analyzing trace with hash 640826515, now seen corresponding path program 1 times [2022-02-21 04:22:19,520 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:19,520 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665855964] [2022-02-21 04:22:19,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:19,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:19,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:19,544 INFO L290 TraceCheckUtils]: 0: Hoare triple {53250#true} assume !false; {53250#true} is VALID [2022-02-21 04:22:19,544 INFO L290 TraceCheckUtils]: 1: Hoare triple {53250#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {53250#true} is VALID [2022-02-21 04:22:19,544 INFO L290 TraceCheckUtils]: 2: Hoare triple {53250#true} assume !false; {53250#true} is VALID [2022-02-21 04:22:19,546 INFO L290 TraceCheckUtils]: 3: Hoare triple {53250#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {53250#true} is VALID [2022-02-21 04:22:19,546 INFO L290 TraceCheckUtils]: 4: Hoare triple {53250#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {53250#true} is VALID [2022-02-21 04:22:19,546 INFO L290 TraceCheckUtils]: 5: Hoare triple {53250#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {53250#true} is VALID [2022-02-21 04:22:19,546 INFO L290 TraceCheckUtils]: 6: Hoare triple {53250#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {53250#true} is VALID [2022-02-21 04:22:19,547 INFO L290 TraceCheckUtils]: 7: Hoare triple {53250#true} assume !(0 != eval_~tmp~0#1); {53250#true} is VALID [2022-02-21 04:22:19,547 INFO L290 TraceCheckUtils]: 8: Hoare triple {53250#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {53250#true} is VALID [2022-02-21 04:22:19,547 INFO L290 TraceCheckUtils]: 9: Hoare triple {53250#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {53250#true} is VALID [2022-02-21 04:22:19,547 INFO L290 TraceCheckUtils]: 10: Hoare triple {53250#true} assume 0 == ~M_E~0;~M_E~0 := 1; {53250#true} is VALID [2022-02-21 04:22:19,547 INFO L290 TraceCheckUtils]: 11: Hoare triple {53250#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {53250#true} is VALID [2022-02-21 04:22:19,547 INFO L290 TraceCheckUtils]: 12: Hoare triple {53250#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,548 INFO L290 TraceCheckUtils]: 13: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,548 INFO L290 TraceCheckUtils]: 14: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,548 INFO L290 TraceCheckUtils]: 15: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,548 INFO L290 TraceCheckUtils]: 16: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,549 INFO L290 TraceCheckUtils]: 17: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,549 INFO L290 TraceCheckUtils]: 18: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,549 INFO L290 TraceCheckUtils]: 19: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,549 INFO L290 TraceCheckUtils]: 20: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,550 INFO L290 TraceCheckUtils]: 21: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,550 INFO L290 TraceCheckUtils]: 22: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,550 INFO L290 TraceCheckUtils]: 23: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,551 INFO L290 TraceCheckUtils]: 24: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,551 INFO L290 TraceCheckUtils]: 25: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,551 INFO L290 TraceCheckUtils]: 26: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,551 INFO L290 TraceCheckUtils]: 27: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,552 INFO L290 TraceCheckUtils]: 28: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,552 INFO L290 TraceCheckUtils]: 29: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,552 INFO L290 TraceCheckUtils]: 30: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,552 INFO L290 TraceCheckUtils]: 31: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,553 INFO L290 TraceCheckUtils]: 32: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,553 INFO L290 TraceCheckUtils]: 33: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,553 INFO L290 TraceCheckUtils]: 34: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,553 INFO L290 TraceCheckUtils]: 35: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,554 INFO L290 TraceCheckUtils]: 36: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,554 INFO L290 TraceCheckUtils]: 37: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,554 INFO L290 TraceCheckUtils]: 38: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,554 INFO L290 TraceCheckUtils]: 39: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,555 INFO L290 TraceCheckUtils]: 40: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,555 INFO L290 TraceCheckUtils]: 41: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,555 INFO L290 TraceCheckUtils]: 42: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,555 INFO L290 TraceCheckUtils]: 43: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,556 INFO L290 TraceCheckUtils]: 44: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,556 INFO L290 TraceCheckUtils]: 45: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,556 INFO L290 TraceCheckUtils]: 46: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,556 INFO L290 TraceCheckUtils]: 47: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,557 INFO L290 TraceCheckUtils]: 48: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,557 INFO L290 TraceCheckUtils]: 49: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,557 INFO L290 TraceCheckUtils]: 50: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,558 INFO L290 TraceCheckUtils]: 51: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,558 INFO L290 TraceCheckUtils]: 52: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,558 INFO L290 TraceCheckUtils]: 53: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,558 INFO L290 TraceCheckUtils]: 54: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,559 INFO L290 TraceCheckUtils]: 55: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,559 INFO L290 TraceCheckUtils]: 56: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,559 INFO L290 TraceCheckUtils]: 57: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,559 INFO L290 TraceCheckUtils]: 58: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,560 INFO L290 TraceCheckUtils]: 59: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,560 INFO L290 TraceCheckUtils]: 60: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,560 INFO L290 TraceCheckUtils]: 61: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,560 INFO L290 TraceCheckUtils]: 62: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,561 INFO L290 TraceCheckUtils]: 63: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,561 INFO L290 TraceCheckUtils]: 64: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,561 INFO L290 TraceCheckUtils]: 65: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,561 INFO L290 TraceCheckUtils]: 66: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,562 INFO L290 TraceCheckUtils]: 67: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,562 INFO L290 TraceCheckUtils]: 68: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,562 INFO L290 TraceCheckUtils]: 69: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,562 INFO L290 TraceCheckUtils]: 70: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,563 INFO L290 TraceCheckUtils]: 71: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,563 INFO L290 TraceCheckUtils]: 72: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,563 INFO L290 TraceCheckUtils]: 73: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,563 INFO L290 TraceCheckUtils]: 74: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,564 INFO L290 TraceCheckUtils]: 75: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,564 INFO L290 TraceCheckUtils]: 76: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,564 INFO L290 TraceCheckUtils]: 77: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,564 INFO L290 TraceCheckUtils]: 78: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,565 INFO L290 TraceCheckUtils]: 79: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,565 INFO L290 TraceCheckUtils]: 80: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,565 INFO L290 TraceCheckUtils]: 81: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,565 INFO L290 TraceCheckUtils]: 82: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,566 INFO L290 TraceCheckUtils]: 83: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,566 INFO L290 TraceCheckUtils]: 84: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {53252#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:19,566 INFO L290 TraceCheckUtils]: 85: Hoare triple {53252#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {53251#false} is VALID [2022-02-21 04:22:19,566 INFO L290 TraceCheckUtils]: 86: Hoare triple {53251#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 87: Hoare triple {53251#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 88: Hoare triple {53251#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 89: Hoare triple {53251#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 90: Hoare triple {53251#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 91: Hoare triple {53251#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 92: Hoare triple {53251#false} assume 1 == ~E_M~0;~E_M~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 93: Hoare triple {53251#false} assume !(1 == ~E_1~0); {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 94: Hoare triple {53251#false} assume 1 == ~E_2~0;~E_2~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 95: Hoare triple {53251#false} assume 1 == ~E_3~0;~E_3~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,567 INFO L290 TraceCheckUtils]: 96: Hoare triple {53251#false} assume 1 == ~E_4~0;~E_4~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 97: Hoare triple {53251#false} assume 1 == ~E_5~0;~E_5~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 98: Hoare triple {53251#false} assume 1 == ~E_6~0;~E_6~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 99: Hoare triple {53251#false} assume 1 == ~E_7~0;~E_7~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 100: Hoare triple {53251#false} assume 1 == ~E_8~0;~E_8~0 := 2; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 101: Hoare triple {53251#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 102: Hoare triple {53251#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 103: Hoare triple {53251#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 104: Hoare triple {53251#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {53251#false} is VALID [2022-02-21 04:22:19,568 INFO L290 TraceCheckUtils]: 105: Hoare triple {53251#false} assume !(0 == start_simulation_~tmp~3#1); {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 106: Hoare triple {53251#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 107: Hoare triple {53251#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 108: Hoare triple {53251#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 109: Hoare triple {53251#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 110: Hoare triple {53251#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 111: Hoare triple {53251#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 112: Hoare triple {53251#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {53251#false} is VALID [2022-02-21 04:22:19,569 INFO L290 TraceCheckUtils]: 113: Hoare triple {53251#false} assume !(0 != start_simulation_~tmp___0~1#1); {53251#false} is VALID [2022-02-21 04:22:19,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:19,570 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:19,570 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665855964] [2022-02-21 04:22:19,570 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665855964] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:19,570 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:19,570 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:19,570 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078415822] [2022-02-21 04:22:19,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:19,571 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:19,571 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:19,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:22:19,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:22:19,571 INFO L87 Difference]: Start difference. First operand 3284 states and 4846 transitions. cyclomatic complexity: 1566 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:24,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:24,504 INFO L93 Difference]: Finished difference Result 9426 states and 13840 transitions. [2022-02-21 04:22:24,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:22:24,504 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:24,558 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:24,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9426 states and 13840 transitions. [2022-02-21 04:22:26,302 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9048 [2022-02-21 04:22:28,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9426 states to 9426 states and 13840 transitions. [2022-02-21 04:22:28,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9426 [2022-02-21 04:22:28,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9426 [2022-02-21 04:22:28,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9426 states and 13840 transitions. [2022-02-21 04:22:28,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:28,118 INFO L681 BuchiCegarLoop]: Abstraction has 9426 states and 13840 transitions. [2022-02-21 04:22:28,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9426 states and 13840 transitions. [2022-02-21 04:22:28,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9426 to 3404. [2022-02-21 04:22:28,169 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:28,172 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9426 states and 13840 transitions. Second operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:28,174 INFO L74 IsIncluded]: Start isIncluded. First operand 9426 states and 13840 transitions. Second operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:28,176 INFO L87 Difference]: Start difference. First operand 9426 states and 13840 transitions. Second operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:29,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:29,934 INFO L93 Difference]: Finished difference Result 9426 states and 13840 transitions. [2022-02-21 04:22:29,934 INFO L276 IsEmpty]: Start isEmpty. Operand 9426 states and 13840 transitions. [2022-02-21 04:22:29,943 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:29,943 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:29,946 INFO L74 IsIncluded]: Start isIncluded. First operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9426 states and 13840 transitions. [2022-02-21 04:22:29,947 INFO L87 Difference]: Start difference. First operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9426 states and 13840 transitions. [2022-02-21 04:22:31,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:31,816 INFO L93 Difference]: Finished difference Result 9426 states and 13840 transitions. [2022-02-21 04:22:31,816 INFO L276 IsEmpty]: Start isEmpty. Operand 9426 states and 13840 transitions. [2022-02-21 04:22:31,823 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:31,823 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:31,823 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:31,823 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:31,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3404 states, 3404 states have (on average 1.4588719153936545) internal successors, (4966), 3403 states have internal predecessors, (4966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:32,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3404 states to 3404 states and 4966 transitions. [2022-02-21 04:22:32,070 INFO L704 BuchiCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2022-02-21 04:22:32,070 INFO L587 BuchiCegarLoop]: Abstraction has 3404 states and 4966 transitions. [2022-02-21 04:22:32,070 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:22:32,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3404 states and 4966 transitions. [2022-02-21 04:22:32,077 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3250 [2022-02-21 04:22:32,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:32,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:32,079 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:32,079 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:32,079 INFO L791 eck$LassoCheckResult]: Stem: 63466#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 63467#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 62731#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62732#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62769#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 63411#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63412#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63018#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63019#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62959#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62960#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63207#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63179#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63180#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63470#L854 assume !(0 == ~M_E~0); 63270#L854-2 assume !(0 == ~T1_E~0); 63271#L859-1 assume !(0 == ~T2_E~0); 62833#L864-1 assume !(0 == ~T3_E~0); 62834#L869-1 assume !(0 == ~T4_E~0); 62948#L874-1 assume !(0 == ~T5_E~0); 63723#L879-1 assume !(0 == ~T6_E~0); 63257#L884-1 assume !(0 == ~T7_E~0); 62700#L889-1 assume !(0 == ~T8_E~0); 62701#L894-1 assume !(0 == ~E_M~0); 63033#L899-1 assume !(0 == ~E_1~0); 63478#L904-1 assume !(0 == ~E_2~0); 63196#L909-1 assume !(0 == ~E_3~0); 63197#L914-1 assume !(0 == ~E_4~0); 63402#L919-1 assume !(0 == ~E_5~0); 63113#L924-1 assume !(0 == ~E_6~0); 62931#L929-1 assume !(0 == ~E_7~0); 62932#L934-1 assume !(0 == ~E_8~0); 63176#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62719#L418 assume !(1 == ~m_pc~0); 62690#L418-2 is_master_triggered_~__retres1~0#1 := 0; 63670#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63671#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 63599#L1061 assume !(0 != activate_threads_~tmp~1#1); 63507#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63508#L437 assume 1 == ~t1_pc~0; 63746#L438 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 63607#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63555#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63068#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 63069#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63590#L456 assume !(1 == ~t2_pc~0); 62984#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62983#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63330#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63331#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 63306#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62827#L475 assume 1 == ~t3_pc~0; 62828#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62888#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62889#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63713#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 63072#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63073#L494 assume !(1 == ~t4_pc~0); 63108#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63109#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63321#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63322#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 63426#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62883#L513 assume 1 == ~t5_pc~0; 62884#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63110#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63148#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62844#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 62845#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62796#L532 assume !(1 == ~t6_pc~0); 62797#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 62949#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63233#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63315#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 63038#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63039#L551 assume 1 == ~t7_pc~0; 63636#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63430#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63431#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63656#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 63767#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63217#L570 assume 1 == ~t8_pc~0; 63218#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63332#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63480#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63326#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 62821#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62822#L952 assume !(1 == ~M_E~0); 63611#L952-2 assume !(1 == ~T1_E~0); 65532#L957-1 assume !(1 == ~T2_E~0); 65531#L962-1 assume !(1 == ~T3_E~0); 65530#L967-1 assume !(1 == ~T4_E~0); 65529#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63956#L977-1 assume !(1 == ~T6_E~0); 63954#L982-1 assume !(1 == ~T7_E~0); 63952#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63950#L992-1 assume !(1 == ~E_M~0); 63948#L997-1 assume !(1 == ~E_1~0); 63946#L1002-1 assume !(1 == ~E_2~0); 63291#L1007-1 assume !(1 == ~E_3~0); 63292#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 63883#L1017-1 assume !(1 == ~E_5~0); 63873#L1022-1 assume !(1 == ~E_6~0); 63860#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 63850#L1032-1 assume !(1 == ~E_8~0); 63837#L1037-1 assume { :end_inline_reset_delta_events } true; 63830#L1303-2 [2022-02-21 04:22:32,080 INFO L793 eck$LassoCheckResult]: Loop: 63830#L1303-2 assume !false; 63825#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63823#L829 assume !false; 63822#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63817#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 63812#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63811#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63810#L712 assume !(0 != eval_~tmp~0#1); 63809#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63808#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63807#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63421#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63422#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 63759#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 63721#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63234#L874-3 assume !(0 == ~T5_E~0); 63235#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63305#L884-3 assume !(0 == ~T7_E~0); 63285#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62922#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62923#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62955#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62956#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62895#L914-3 assume !(0 == ~E_4~0); 62896#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62944#L924-3 assume !(0 == ~E_6~0); 63513#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 63403#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63404#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63551#L418-30 assume 1 == ~m_pc~0; 63552#L419-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 66070#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66069#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66011#L1061-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62985#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62986#L437-30 assume !(1 == ~t1_pc~0); 63111#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 63324#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63325#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63533#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63742#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63077#L456-30 assume 1 == ~t2_pc~0; 63078#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 63501#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63502#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62869#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62870#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63208#L475-30 assume 1 == ~t3_pc~0; 63628#L476-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62752#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63420#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63724#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63095#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63096#L494-30 assume 1 == ~t4_pc~0; 63089#L495-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62686#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62687#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63684#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 63659#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63660#L513-30 assume 1 == ~t5_pc~0; 63772#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63214#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63281#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63529#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63530#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63225#L532-30 assume !(1 == ~t6_pc~0); 63226#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 62825#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62826#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62847#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62909#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62910#L551-30 assume 1 == ~t7_pc~0; 62963#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63023#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66022#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66021#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66020#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66019#L570-30 assume !(1 == ~t8_pc~0); 66017#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 66016#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66015#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62767#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62768#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63135#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63172#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66010#L957-3 assume !(1 == ~T2_E~0); 66009#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66008#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66007#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63476#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63477#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63777#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63778#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66004#L997-3 assume !(1 == ~E_1~0); 66003#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66002#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63945#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63941#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63939#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63938#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63937#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63935#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63913#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 63910#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63909#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 63908#L1322 assume !(0 == start_simulation_~tmp~3#1); 63495#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 63881#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 63872#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 63859#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 63849#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63847#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63845#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 63836#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 63830#L1303-2 [2022-02-21 04:22:32,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:32,080 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2022-02-21 04:22:32,080 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:32,080 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086309184] [2022-02-21 04:22:32,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:32,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:32,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:32,103 INFO L290 TraceCheckUtils]: 0: Hoare triple {84942#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,103 INFO L290 TraceCheckUtils]: 1: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,104 INFO L290 TraceCheckUtils]: 2: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,104 INFO L290 TraceCheckUtils]: 3: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,104 INFO L290 TraceCheckUtils]: 4: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,105 INFO L290 TraceCheckUtils]: 5: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,105 INFO L290 TraceCheckUtils]: 6: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,105 INFO L290 TraceCheckUtils]: 7: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,105 INFO L290 TraceCheckUtils]: 8: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,106 INFO L290 TraceCheckUtils]: 9: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,106 INFO L290 TraceCheckUtils]: 10: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,106 INFO L290 TraceCheckUtils]: 11: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,107 INFO L290 TraceCheckUtils]: 12: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,107 INFO L290 TraceCheckUtils]: 13: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,107 INFO L290 TraceCheckUtils]: 14: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,107 INFO L290 TraceCheckUtils]: 15: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,108 INFO L290 TraceCheckUtils]: 16: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,108 INFO L290 TraceCheckUtils]: 17: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,108 INFO L290 TraceCheckUtils]: 18: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,108 INFO L290 TraceCheckUtils]: 19: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,109 INFO L290 TraceCheckUtils]: 20: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,109 INFO L290 TraceCheckUtils]: 21: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,109 INFO L290 TraceCheckUtils]: 22: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,110 INFO L290 TraceCheckUtils]: 23: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,110 INFO L290 TraceCheckUtils]: 24: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,110 INFO L290 TraceCheckUtils]: 25: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,110 INFO L290 TraceCheckUtils]: 26: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,111 INFO L290 TraceCheckUtils]: 27: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,111 INFO L290 TraceCheckUtils]: 28: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,111 INFO L290 TraceCheckUtils]: 29: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,111 INFO L290 TraceCheckUtils]: 30: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,112 INFO L290 TraceCheckUtils]: 31: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,112 INFO L290 TraceCheckUtils]: 32: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {84944#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:32,112 INFO L290 TraceCheckUtils]: 33: Hoare triple {84944#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {84945#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:32,113 INFO L290 TraceCheckUtils]: 34: Hoare triple {84945#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {84945#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:32,113 INFO L290 TraceCheckUtils]: 35: Hoare triple {84945#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {84945#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:32,113 INFO L290 TraceCheckUtils]: 36: Hoare triple {84945#(not (= ~t1_pc~0 1))} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {84945#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:32,113 INFO L290 TraceCheckUtils]: 37: Hoare triple {84945#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {84945#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:32,113 INFO L290 TraceCheckUtils]: 38: Hoare triple {84945#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {84945#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 39: Hoare triple {84945#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {84943#false} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 40: Hoare triple {84943#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {84943#false} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 41: Hoare triple {84943#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {84943#false} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 42: Hoare triple {84943#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {84943#false} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 43: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___0~0#1); {84943#false} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 44: Hoare triple {84943#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {84943#false} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 45: Hoare triple {84943#false} assume !(1 == ~t2_pc~0); {84943#false} is VALID [2022-02-21 04:22:32,114 INFO L290 TraceCheckUtils]: 46: Hoare triple {84943#false} is_transmit2_triggered_~__retres1~2#1 := 0; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 47: Hoare triple {84943#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 48: Hoare triple {84943#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 49: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___1~0#1); {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 50: Hoare triple {84943#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 51: Hoare triple {84943#false} assume 1 == ~t3_pc~0; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 52: Hoare triple {84943#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 53: Hoare triple {84943#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 54: Hoare triple {84943#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {84943#false} is VALID [2022-02-21 04:22:32,115 INFO L290 TraceCheckUtils]: 55: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___2~0#1); {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 56: Hoare triple {84943#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 57: Hoare triple {84943#false} assume !(1 == ~t4_pc~0); {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 58: Hoare triple {84943#false} is_transmit4_triggered_~__retres1~4#1 := 0; {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 59: Hoare triple {84943#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 60: Hoare triple {84943#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 61: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___3~0#1); {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 62: Hoare triple {84943#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 63: Hoare triple {84943#false} assume 1 == ~t5_pc~0; {84943#false} is VALID [2022-02-21 04:22:32,116 INFO L290 TraceCheckUtils]: 64: Hoare triple {84943#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {84943#false} is VALID [2022-02-21 04:22:32,117 INFO L290 TraceCheckUtils]: 65: Hoare triple {84943#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {84943#false} is VALID [2022-02-21 04:22:32,117 INFO L290 TraceCheckUtils]: 66: Hoare triple {84943#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {84943#false} is VALID [2022-02-21 04:22:32,117 INFO L290 TraceCheckUtils]: 67: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___4~0#1); {84943#false} is VALID [2022-02-21 04:22:32,117 INFO L290 TraceCheckUtils]: 68: Hoare triple {84943#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 69: Hoare triple {84943#false} assume !(1 == ~t6_pc~0); {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 70: Hoare triple {84943#false} is_transmit6_triggered_~__retres1~6#1 := 0; {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 71: Hoare triple {84943#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 72: Hoare triple {84943#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 73: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___5~0#1); {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 74: Hoare triple {84943#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 75: Hoare triple {84943#false} assume 1 == ~t7_pc~0; {84943#false} is VALID [2022-02-21 04:22:32,118 INFO L290 TraceCheckUtils]: 76: Hoare triple {84943#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 77: Hoare triple {84943#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 78: Hoare triple {84943#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 79: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___6~0#1); {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 80: Hoare triple {84943#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 81: Hoare triple {84943#false} assume 1 == ~t8_pc~0; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 82: Hoare triple {84943#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 83: Hoare triple {84943#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 84: Hoare triple {84943#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {84943#false} is VALID [2022-02-21 04:22:32,119 INFO L290 TraceCheckUtils]: 85: Hoare triple {84943#false} assume !(0 != activate_threads_~tmp___7~0#1); {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 86: Hoare triple {84943#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 87: Hoare triple {84943#false} assume !(1 == ~M_E~0); {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 88: Hoare triple {84943#false} assume !(1 == ~T1_E~0); {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 89: Hoare triple {84943#false} assume !(1 == ~T2_E~0); {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 90: Hoare triple {84943#false} assume !(1 == ~T3_E~0); {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 91: Hoare triple {84943#false} assume !(1 == ~T4_E~0); {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 92: Hoare triple {84943#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 93: Hoare triple {84943#false} assume !(1 == ~T6_E~0); {84943#false} is VALID [2022-02-21 04:22:32,120 INFO L290 TraceCheckUtils]: 94: Hoare triple {84943#false} assume !(1 == ~T7_E~0); {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 95: Hoare triple {84943#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 96: Hoare triple {84943#false} assume !(1 == ~E_M~0); {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 97: Hoare triple {84943#false} assume !(1 == ~E_1~0); {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 98: Hoare triple {84943#false} assume !(1 == ~E_2~0); {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 99: Hoare triple {84943#false} assume !(1 == ~E_3~0); {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 100: Hoare triple {84943#false} assume 1 == ~E_4~0;~E_4~0 := 2; {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 101: Hoare triple {84943#false} assume !(1 == ~E_5~0); {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 102: Hoare triple {84943#false} assume !(1 == ~E_6~0); {84943#false} is VALID [2022-02-21 04:22:32,121 INFO L290 TraceCheckUtils]: 103: Hoare triple {84943#false} assume 1 == ~E_7~0;~E_7~0 := 2; {84943#false} is VALID [2022-02-21 04:22:32,122 INFO L290 TraceCheckUtils]: 104: Hoare triple {84943#false} assume !(1 == ~E_8~0); {84943#false} is VALID [2022-02-21 04:22:32,122 INFO L290 TraceCheckUtils]: 105: Hoare triple {84943#false} assume { :end_inline_reset_delta_events } true; {84943#false} is VALID [2022-02-21 04:22:32,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:32,122 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:32,122 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086309184] [2022-02-21 04:22:32,122 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086309184] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:32,124 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:32,124 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:32,124 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514887092] [2022-02-21 04:22:32,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:32,125 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:32,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:32,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1308434988, now seen corresponding path program 1 times [2022-02-21 04:22:32,125 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:32,125 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106797316] [2022-02-21 04:22:32,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:32,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:32,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:32,146 INFO L290 TraceCheckUtils]: 0: Hoare triple {84946#true} assume !false; {84946#true} is VALID [2022-02-21 04:22:32,146 INFO L290 TraceCheckUtils]: 1: Hoare triple {84946#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 2: Hoare triple {84946#true} assume !false; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 3: Hoare triple {84946#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 4: Hoare triple {84946#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 5: Hoare triple {84946#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 6: Hoare triple {84946#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 7: Hoare triple {84946#true} assume !(0 != eval_~tmp~0#1); {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 8: Hoare triple {84946#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 9: Hoare triple {84946#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {84946#true} is VALID [2022-02-21 04:22:32,147 INFO L290 TraceCheckUtils]: 10: Hoare triple {84946#true} assume 0 == ~M_E~0;~M_E~0 := 1; {84946#true} is VALID [2022-02-21 04:22:32,148 INFO L290 TraceCheckUtils]: 11: Hoare triple {84946#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {84946#true} is VALID [2022-02-21 04:22:32,148 INFO L290 TraceCheckUtils]: 12: Hoare triple {84946#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,148 INFO L290 TraceCheckUtils]: 13: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,148 INFO L290 TraceCheckUtils]: 14: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,149 INFO L290 TraceCheckUtils]: 15: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,149 INFO L290 TraceCheckUtils]: 16: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,149 INFO L290 TraceCheckUtils]: 17: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,149 INFO L290 TraceCheckUtils]: 18: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,150 INFO L290 TraceCheckUtils]: 19: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,150 INFO L290 TraceCheckUtils]: 20: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,150 INFO L290 TraceCheckUtils]: 21: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,150 INFO L290 TraceCheckUtils]: 22: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,151 INFO L290 TraceCheckUtils]: 23: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,151 INFO L290 TraceCheckUtils]: 24: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,151 INFO L290 TraceCheckUtils]: 25: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,151 INFO L290 TraceCheckUtils]: 26: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,151 INFO L290 TraceCheckUtils]: 27: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,152 INFO L290 TraceCheckUtils]: 28: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,152 INFO L290 TraceCheckUtils]: 29: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,152 INFO L290 TraceCheckUtils]: 30: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,152 INFO L290 TraceCheckUtils]: 31: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,153 INFO L290 TraceCheckUtils]: 32: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,153 INFO L290 TraceCheckUtils]: 33: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,153 INFO L290 TraceCheckUtils]: 34: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,153 INFO L290 TraceCheckUtils]: 35: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,154 INFO L290 TraceCheckUtils]: 36: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,154 INFO L290 TraceCheckUtils]: 37: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,154 INFO L290 TraceCheckUtils]: 38: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,154 INFO L290 TraceCheckUtils]: 39: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,155 INFO L290 TraceCheckUtils]: 40: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,155 INFO L290 TraceCheckUtils]: 41: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,155 INFO L290 TraceCheckUtils]: 42: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,155 INFO L290 TraceCheckUtils]: 43: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,156 INFO L290 TraceCheckUtils]: 44: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,156 INFO L290 TraceCheckUtils]: 45: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,156 INFO L290 TraceCheckUtils]: 46: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,156 INFO L290 TraceCheckUtils]: 47: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,157 INFO L290 TraceCheckUtils]: 48: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,157 INFO L290 TraceCheckUtils]: 49: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,157 INFO L290 TraceCheckUtils]: 50: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,157 INFO L290 TraceCheckUtils]: 51: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,158 INFO L290 TraceCheckUtils]: 52: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,158 INFO L290 TraceCheckUtils]: 53: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,158 INFO L290 TraceCheckUtils]: 54: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,158 INFO L290 TraceCheckUtils]: 55: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,158 INFO L290 TraceCheckUtils]: 56: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,159 INFO L290 TraceCheckUtils]: 57: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,159 INFO L290 TraceCheckUtils]: 58: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,159 INFO L290 TraceCheckUtils]: 59: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,159 INFO L290 TraceCheckUtils]: 60: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,160 INFO L290 TraceCheckUtils]: 61: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,160 INFO L290 TraceCheckUtils]: 62: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,160 INFO L290 TraceCheckUtils]: 63: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,160 INFO L290 TraceCheckUtils]: 64: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,161 INFO L290 TraceCheckUtils]: 65: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,161 INFO L290 TraceCheckUtils]: 66: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,161 INFO L290 TraceCheckUtils]: 67: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,161 INFO L290 TraceCheckUtils]: 68: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,162 INFO L290 TraceCheckUtils]: 69: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,162 INFO L290 TraceCheckUtils]: 70: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,162 INFO L290 TraceCheckUtils]: 71: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,162 INFO L290 TraceCheckUtils]: 72: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,163 INFO L290 TraceCheckUtils]: 73: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,163 INFO L290 TraceCheckUtils]: 74: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,163 INFO L290 TraceCheckUtils]: 75: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,163 INFO L290 TraceCheckUtils]: 76: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,164 INFO L290 TraceCheckUtils]: 77: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,164 INFO L290 TraceCheckUtils]: 78: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,164 INFO L290 TraceCheckUtils]: 79: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,164 INFO L290 TraceCheckUtils]: 80: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,164 INFO L290 TraceCheckUtils]: 81: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,165 INFO L290 TraceCheckUtils]: 82: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,165 INFO L290 TraceCheckUtils]: 83: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,165 INFO L290 TraceCheckUtils]: 84: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {84948#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 85: Hoare triple {84948#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 86: Hoare triple {84947#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 87: Hoare triple {84947#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 88: Hoare triple {84947#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 89: Hoare triple {84947#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 90: Hoare triple {84947#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 91: Hoare triple {84947#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 92: Hoare triple {84947#false} assume 1 == ~E_M~0;~E_M~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 93: Hoare triple {84947#false} assume !(1 == ~E_1~0); {84947#false} is VALID [2022-02-21 04:22:32,166 INFO L290 TraceCheckUtils]: 94: Hoare triple {84947#false} assume 1 == ~E_2~0;~E_2~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 95: Hoare triple {84947#false} assume 1 == ~E_3~0;~E_3~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 96: Hoare triple {84947#false} assume 1 == ~E_4~0;~E_4~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 97: Hoare triple {84947#false} assume 1 == ~E_5~0;~E_5~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 98: Hoare triple {84947#false} assume 1 == ~E_6~0;~E_6~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 99: Hoare triple {84947#false} assume 1 == ~E_7~0;~E_7~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 100: Hoare triple {84947#false} assume 1 == ~E_8~0;~E_8~0 := 2; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 101: Hoare triple {84947#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 102: Hoare triple {84947#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {84947#false} is VALID [2022-02-21 04:22:32,167 INFO L290 TraceCheckUtils]: 103: Hoare triple {84947#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 104: Hoare triple {84947#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 105: Hoare triple {84947#false} assume !(0 == start_simulation_~tmp~3#1); {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 106: Hoare triple {84947#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 107: Hoare triple {84947#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 108: Hoare triple {84947#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 109: Hoare triple {84947#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 110: Hoare triple {84947#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 111: Hoare triple {84947#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {84947#false} is VALID [2022-02-21 04:22:32,168 INFO L290 TraceCheckUtils]: 112: Hoare triple {84947#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {84947#false} is VALID [2022-02-21 04:22:32,169 INFO L290 TraceCheckUtils]: 113: Hoare triple {84947#false} assume !(0 != start_simulation_~tmp___0~1#1); {84947#false} is VALID [2022-02-21 04:22:32,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:32,169 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:32,169 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106797316] [2022-02-21 04:22:32,169 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106797316] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:32,169 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:32,169 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:32,170 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264068749] [2022-02-21 04:22:32,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:32,170 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:32,170 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:32,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:32,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:32,171 INFO L87 Difference]: Start difference. First operand 3404 states and 4966 transitions. cyclomatic complexity: 1566 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:35,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:35,931 INFO L93 Difference]: Finished difference Result 9349 states and 13457 transitions. [2022-02-21 04:22:35,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:35,931 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:35,986 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:35,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9349 states and 13457 transitions. [2022-02-21 04:22:37,870 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8920 [2022-02-21 04:22:39,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9349 states to 9349 states and 13457 transitions. [2022-02-21 04:22:39,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9349 [2022-02-21 04:22:39,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9349 [2022-02-21 04:22:39,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9349 states and 13457 transitions. [2022-02-21 04:22:39,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:39,784 INFO L681 BuchiCegarLoop]: Abstraction has 9349 states and 13457 transitions. [2022-02-21 04:22:39,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9349 states and 13457 transitions. [2022-02-21 04:22:39,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9349 to 8861. [2022-02-21 04:22:39,888 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:39,898 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9349 states and 13457 transitions. Second operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:39,907 INFO L74 IsIncluded]: Start isIncluded. First operand 9349 states and 13457 transitions. Second operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:39,917 INFO L87 Difference]: Start difference. First operand 9349 states and 13457 transitions. Second operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:41,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:41,713 INFO L93 Difference]: Finished difference Result 9349 states and 13457 transitions. [2022-02-21 04:22:41,713 INFO L276 IsEmpty]: Start isEmpty. Operand 9349 states and 13457 transitions. [2022-02-21 04:22:41,721 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:41,721 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:41,730 INFO L74 IsIncluded]: Start isIncluded. First operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9349 states and 13457 transitions. [2022-02-21 04:22:41,738 INFO L87 Difference]: Start difference. First operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9349 states and 13457 transitions. [2022-02-21 04:22:43,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:43,609 INFO L93 Difference]: Finished difference Result 9349 states and 13457 transitions. [2022-02-21 04:22:43,609 INFO L276 IsEmpty]: Start isEmpty. Operand 9349 states and 13457 transitions. [2022-02-21 04:22:43,617 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:43,617 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:43,617 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:43,617 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:43,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8861 states, 8861 states have (on average 1.4432908249633225) internal successors, (12789), 8860 states have internal predecessors, (12789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:45,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8861 states to 8861 states and 12789 transitions. [2022-02-21 04:22:45,474 INFO L704 BuchiCegarLoop]: Abstraction has 8861 states and 12789 transitions. [2022-02-21 04:22:45,474 INFO L587 BuchiCegarLoop]: Abstraction has 8861 states and 12789 transitions. [2022-02-21 04:22:45,474 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:22:45,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8861 states and 12789 transitions. [2022-02-21 04:22:45,491 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8692 [2022-02-21 04:22:45,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:45,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:45,492 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:45,492 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:45,493 INFO L791 eck$LassoCheckResult]: Stem: 95095#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 95096#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 94346#L1266 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94347#L590 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94384#L597 assume 1 == ~m_i~0;~m_st~0 := 0; 95035#L597-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95036#L602-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94638#L607-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94639#L612-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94576#L617-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94577#L622-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 94823#L627-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 94796#L632-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 94797#L637-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95099#L854 assume !(0 == ~M_E~0); 94888#L854-2 assume !(0 == ~T1_E~0); 94889#L859-1 assume !(0 == ~T2_E~0); 94448#L864-1 assume !(0 == ~T3_E~0); 94449#L869-1 assume !(0 == ~T4_E~0); 94565#L874-1 assume !(0 == ~T5_E~0); 95361#L879-1 assume !(0 == ~T6_E~0); 94876#L884-1 assume !(0 == ~T7_E~0); 94314#L889-1 assume !(0 == ~T8_E~0); 94315#L894-1 assume !(0 == ~E_M~0); 94653#L899-1 assume !(0 == ~E_1~0); 95106#L904-1 assume !(0 == ~E_2~0); 94812#L909-1 assume !(0 == ~E_3~0); 94813#L914-1 assume !(0 == ~E_4~0); 95025#L919-1 assume !(0 == ~E_5~0); 94731#L924-1 assume !(0 == ~E_6~0); 94547#L929-1 assume !(0 == ~E_7~0); 94548#L934-1 assume !(0 == ~E_8~0); 94793#L939-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94333#L418 assume !(1 == ~m_pc~0); 94334#L418-2 is_master_triggered_~__retres1~0#1 := 0; 95294#L429 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95295#L430 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95221#L1061 assume !(0 != activate_threads_~tmp~1#1); 95133#L1061-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95134#L437 assume !(1 == ~t1_pc~0); 95349#L437-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95229#L448 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95177#L449 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94687#L1069 assume !(0 != activate_threads_~tmp___0~0#1); 94688#L1069-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95212#L456 assume !(1 == ~t2_pc~0); 94601#L456-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94600#L467 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94952#L468 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94953#L1077 assume !(0 != activate_threads_~tmp___1~0#1); 94925#L1077-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94442#L475 assume 1 == ~t3_pc~0; 94443#L476 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94505#L486 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94506#L487 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95351#L1085 assume !(0 != activate_threads_~tmp___2~0#1); 94691#L1085-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94692#L494 assume !(1 == ~t4_pc~0); 94727#L494-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94728#L505 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94941#L506 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 94942#L1093 assume !(0 != activate_threads_~tmp___3~0#1); 95051#L1093-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94499#L513 assume 1 == ~t5_pc~0; 94500#L514 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94729#L524 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94767#L525 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94459#L1101 assume !(0 != activate_threads_~tmp___4~0#1); 94460#L1101-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94411#L532 assume !(1 == ~t6_pc~0); 94412#L532-2 is_transmit6_triggered_~__retres1~6#1 := 0; 94566#L543 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94850#L544 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94934#L1109 assume !(0 != activate_threads_~tmp___5~0#1); 94658#L1109-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94659#L551 assume 1 == ~t7_pc~0; 95256#L552 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95056#L562 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95057#L563 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95276#L1117 assume !(0 != activate_threads_~tmp___6~0#1); 95419#L1117-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94834#L570 assume 1 == ~t8_pc~0; 94835#L571 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94954#L581 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 95108#L582 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94947#L1125 assume !(0 != activate_threads_~tmp___7~0#1); 94436#L1125-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94437#L952 assume !(1 == ~M_E~0); 94385#L952-2 assume !(1 == ~T1_E~0); 94386#L957-1 assume !(1 == ~T2_E~0); 95192#L962-1 assume !(1 == ~T3_E~0); 95399#L967-1 assume !(1 == ~T4_E~0); 95380#L972-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95257#L977-1 assume !(1 == ~T6_E~0); 95258#L982-1 assume !(1 == ~T7_E~0); 94568#L987-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94569#L992-1 assume !(1 == ~E_M~0); 94578#L997-1 assume !(1 == ~E_1~0); 96858#L1002-1 assume !(1 == ~E_2~0); 96857#L1007-1 assume !(1 == ~E_3~0); 96779#L1012-1 assume 1 == ~E_4~0;~E_4~0 := 2; 96745#L1017-1 assume !(1 == ~E_5~0); 96721#L1022-1 assume !(1 == ~E_6~0); 96704#L1027-1 assume 1 == ~E_7~0;~E_7~0 := 2; 96691#L1032-1 assume !(1 == ~E_8~0); 96681#L1037-1 assume { :end_inline_reset_delta_events } true; 96674#L1303-2 [2022-02-21 04:22:45,493 INFO L793 eck$LassoCheckResult]: Loop: 96674#L1303-2 assume !false; 96669#L1304 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96667#L829 assume !false; 96666#L708 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 96661#L650 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 96656#L697 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 96655#L698 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 96653#L712 assume !(0 != eval_~tmp~0#1); 96652#L844 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96651#L590-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96647#L854-3 assume 0 == ~M_E~0;~M_E~0 := 1; 96648#L854-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98296#L859-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 97477#L864-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 97478#L869-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98236#L874-3 assume !(0 == ~T5_E~0); 96630#L879-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96631#L884-3 assume !(0 == ~T7_E~0); 96625#L889-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 96623#L894-3 assume 0 == ~E_M~0;~E_M~0 := 1; 96621#L899-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96618#L904-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96616#L909-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96614#L914-3 assume !(0 == ~E_4~0); 96612#L919-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96610#L924-3 assume !(0 == ~E_6~0); 96609#L929-3 assume 0 == ~E_7~0;~E_7~0 := 1; 96608#L934-3 assume 0 == ~E_8~0;~E_8~0 := 1; 96607#L939-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96606#L418-30 assume !(1 == ~m_pc~0); 96604#L418-32 is_master_triggered_~__retres1~0#1 := 0; 96601#L429-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96599#L430-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96596#L1061-30 assume !(0 != activate_threads_~tmp~1#1); 96592#L1061-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96589#L437-30 assume !(1 == ~t1_pc~0); 96585#L437-32 is_transmit1_triggered_~__retres1~1#1 := 0; 96582#L448-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96578#L449-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96579#L1069-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 97568#L1069-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97567#L456-30 assume 1 == ~t2_pc~0; 97561#L457-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 97555#L467-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97553#L468-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 97551#L1077-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 97550#L1077-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97549#L475-30 assume !(1 == ~t3_pc~0); 97547#L475-32 is_transmit3_triggered_~__retres1~3#1 := 0; 97546#L486-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95908#L487-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95909#L1085-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97545#L1085-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97544#L494-30 assume !(1 == ~t4_pc~0); 97543#L494-32 is_transmit4_triggered_~__retres1~4#1 := 0; 97541#L505-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97540#L506-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 97539#L1093-30 assume !(0 != activate_threads_~tmp___3~0#1); 97529#L1093-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97519#L513-30 assume 1 == ~t5_pc~0; 97515#L514-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 97512#L524-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97509#L525-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97489#L1101-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 97487#L1101-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95872#L532-30 assume !(1 == ~t6_pc~0); 95702#L532-32 is_transmit6_triggered_~__retres1~6#1 := 0; 95703#L543-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95694#L544-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95695#L1109-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97307#L1109-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95686#L551-30 assume 1 == ~t7_pc~0; 95680#L552-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95681#L562-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97283#L563-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95673#L1117-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 95669#L1117-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95670#L570-30 assume !(1 == ~t8_pc~0); 97239#L570-32 is_transmit8_triggered_~__retres1~8#1 := 0; 97232#L581-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97225#L582-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97219#L1125-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 97218#L1125-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97206#L952-3 assume 1 == ~M_E~0;~M_E~0 := 2; 95633#L952-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97193#L957-3 assume !(1 == ~T2_E~0); 97184#L962-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97177#L967-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97175#L972-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95616#L977-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 97161#L982-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 97152#L987-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 97144#L992-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97136#L997-3 assume !(1 == ~E_1~0); 97129#L1002-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97122#L1007-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97114#L1012-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97104#L1017-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97096#L1022-3 assume 1 == ~E_6~0;~E_6~0 := 2; 97088#L1027-3 assume 1 == ~E_7~0;~E_7~0 := 2; 97082#L1032-3 assume 1 == ~E_8~0;~E_8~0 := 2; 97011#L1037-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 96990#L650-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 96984#L697-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 96920#L698-1 start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 96815#L1322 assume !(0 == start_simulation_~tmp~3#1); 96813#L1322-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 96770#L650-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 96732#L697-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 96709#L698-2 stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; 96705#L1277 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 96703#L1284 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96690#L1285 start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 96680#L1335 assume !(0 != start_simulation_~tmp___0~1#1); 96674#L1303-2 [2022-02-21 04:22:45,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:45,494 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2022-02-21 04:22:45,494 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:45,494 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041807415] [2022-02-21 04:22:45,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:45,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:45,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:45,514 INFO L290 TraceCheckUtils]: 0: Hoare triple {121862#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,515 INFO L290 TraceCheckUtils]: 1: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,515 INFO L290 TraceCheckUtils]: 2: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret25#1, start_simulation_#t~ret26#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,515 INFO L290 TraceCheckUtils]: 3: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,516 INFO L290 TraceCheckUtils]: 4: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,516 INFO L290 TraceCheckUtils]: 5: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,516 INFO L290 TraceCheckUtils]: 6: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,516 INFO L290 TraceCheckUtils]: 7: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,517 INFO L290 TraceCheckUtils]: 8: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,517 INFO L290 TraceCheckUtils]: 9: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,517 INFO L290 TraceCheckUtils]: 10: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,518 INFO L290 TraceCheckUtils]: 11: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,518 INFO L290 TraceCheckUtils]: 12: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,518 INFO L290 TraceCheckUtils]: 13: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,518 INFO L290 TraceCheckUtils]: 14: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,519 INFO L290 TraceCheckUtils]: 15: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,519 INFO L290 TraceCheckUtils]: 16: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,519 INFO L290 TraceCheckUtils]: 17: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,519 INFO L290 TraceCheckUtils]: 18: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,520 INFO L290 TraceCheckUtils]: 19: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,520 INFO L290 TraceCheckUtils]: 20: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T6_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,520 INFO L290 TraceCheckUtils]: 21: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T7_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,521 INFO L290 TraceCheckUtils]: 22: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T8_E~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,521 INFO L290 TraceCheckUtils]: 23: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_M~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,521 INFO L290 TraceCheckUtils]: 24: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,521 INFO L290 TraceCheckUtils]: 25: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,522 INFO L290 TraceCheckUtils]: 26: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,522 INFO L290 TraceCheckUtils]: 27: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,522 INFO L290 TraceCheckUtils]: 28: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,522 INFO L290 TraceCheckUtils]: 29: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_6~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,523 INFO L290 TraceCheckUtils]: 30: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_7~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,523 INFO L290 TraceCheckUtils]: 31: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_8~0); {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,523 INFO L290 TraceCheckUtils]: 32: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {121864#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:45,523 INFO L290 TraceCheckUtils]: 33: Hoare triple {121864#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,524 INFO L290 TraceCheckUtils]: 34: Hoare triple {121865#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,524 INFO L290 TraceCheckUtils]: 35: Hoare triple {121865#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,524 INFO L290 TraceCheckUtils]: 36: Hoare triple {121865#(not (= ~t3_pc~0 1))} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,524 INFO L290 TraceCheckUtils]: 37: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,525 INFO L290 TraceCheckUtils]: 38: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,525 INFO L290 TraceCheckUtils]: 39: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,525 INFO L290 TraceCheckUtils]: 40: Hoare triple {121865#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,525 INFO L290 TraceCheckUtils]: 41: Hoare triple {121865#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,526 INFO L290 TraceCheckUtils]: 42: Hoare triple {121865#(not (= ~t3_pc~0 1))} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,526 INFO L290 TraceCheckUtils]: 43: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,526 INFO L290 TraceCheckUtils]: 44: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,526 INFO L290 TraceCheckUtils]: 45: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,527 INFO L290 TraceCheckUtils]: 46: Hoare triple {121865#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,527 INFO L290 TraceCheckUtils]: 47: Hoare triple {121865#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,527 INFO L290 TraceCheckUtils]: 48: Hoare triple {121865#(not (= ~t3_pc~0 1))} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,527 INFO L290 TraceCheckUtils]: 49: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 50: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {121865#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 51: Hoare triple {121865#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {121863#false} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 52: Hoare triple {121863#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {121863#false} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 53: Hoare triple {121863#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {121863#false} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 54: Hoare triple {121863#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {121863#false} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 55: Hoare triple {121863#false} assume !(0 != activate_threads_~tmp___2~0#1); {121863#false} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 56: Hoare triple {121863#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {121863#false} is VALID [2022-02-21 04:22:45,528 INFO L290 TraceCheckUtils]: 57: Hoare triple {121863#false} assume !(1 == ~t4_pc~0); {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 58: Hoare triple {121863#false} is_transmit4_triggered_~__retres1~4#1 := 0; {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 59: Hoare triple {121863#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 60: Hoare triple {121863#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 61: Hoare triple {121863#false} assume !(0 != activate_threads_~tmp___3~0#1); {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 62: Hoare triple {121863#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 63: Hoare triple {121863#false} assume 1 == ~t5_pc~0; {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 64: Hoare triple {121863#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 65: Hoare triple {121863#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {121863#false} is VALID [2022-02-21 04:22:45,529 INFO L290 TraceCheckUtils]: 66: Hoare triple {121863#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 67: Hoare triple {121863#false} assume !(0 != activate_threads_~tmp___4~0#1); {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 68: Hoare triple {121863#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 69: Hoare triple {121863#false} assume !(1 == ~t6_pc~0); {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 70: Hoare triple {121863#false} is_transmit6_triggered_~__retres1~6#1 := 0; {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 71: Hoare triple {121863#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 72: Hoare triple {121863#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 73: Hoare triple {121863#false} assume !(0 != activate_threads_~tmp___5~0#1); {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 74: Hoare triple {121863#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 75: Hoare triple {121863#false} assume 1 == ~t7_pc~0; {121863#false} is VALID [2022-02-21 04:22:45,530 INFO L290 TraceCheckUtils]: 76: Hoare triple {121863#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 77: Hoare triple {121863#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 78: Hoare triple {121863#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 79: Hoare triple {121863#false} assume !(0 != activate_threads_~tmp___6~0#1); {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 80: Hoare triple {121863#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 81: Hoare triple {121863#false} assume 1 == ~t8_pc~0; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 82: Hoare triple {121863#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 83: Hoare triple {121863#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 84: Hoare triple {121863#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {121863#false} is VALID [2022-02-21 04:22:45,531 INFO L290 TraceCheckUtils]: 85: Hoare triple {121863#false} assume !(0 != activate_threads_~tmp___7~0#1); {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 86: Hoare triple {121863#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 87: Hoare triple {121863#false} assume !(1 == ~M_E~0); {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 88: Hoare triple {121863#false} assume !(1 == ~T1_E~0); {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 89: Hoare triple {121863#false} assume !(1 == ~T2_E~0); {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 90: Hoare triple {121863#false} assume !(1 == ~T3_E~0); {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 91: Hoare triple {121863#false} assume !(1 == ~T4_E~0); {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 92: Hoare triple {121863#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 93: Hoare triple {121863#false} assume !(1 == ~T6_E~0); {121863#false} is VALID [2022-02-21 04:22:45,532 INFO L290 TraceCheckUtils]: 94: Hoare triple {121863#false} assume !(1 == ~T7_E~0); {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 95: Hoare triple {121863#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 96: Hoare triple {121863#false} assume !(1 == ~E_M~0); {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 97: Hoare triple {121863#false} assume !(1 == ~E_1~0); {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 98: Hoare triple {121863#false} assume !(1 == ~E_2~0); {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 99: Hoare triple {121863#false} assume !(1 == ~E_3~0); {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 100: Hoare triple {121863#false} assume 1 == ~E_4~0;~E_4~0 := 2; {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 101: Hoare triple {121863#false} assume !(1 == ~E_5~0); {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 102: Hoare triple {121863#false} assume !(1 == ~E_6~0); {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 103: Hoare triple {121863#false} assume 1 == ~E_7~0;~E_7~0 := 2; {121863#false} is VALID [2022-02-21 04:22:45,533 INFO L290 TraceCheckUtils]: 104: Hoare triple {121863#false} assume !(1 == ~E_8~0); {121863#false} is VALID [2022-02-21 04:22:45,534 INFO L290 TraceCheckUtils]: 105: Hoare triple {121863#false} assume { :end_inline_reset_delta_events } true; {121863#false} is VALID [2022-02-21 04:22:45,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:45,534 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:45,534 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041807415] [2022-02-21 04:22:45,534 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041807415] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:45,534 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:45,534 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:45,535 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43855568] [2022-02-21 04:22:45,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:45,535 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:45,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:45,535 INFO L85 PathProgramCache]: Analyzing trace with hash -417433255, now seen corresponding path program 1 times [2022-02-21 04:22:45,536 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:45,536 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373236224] [2022-02-21 04:22:45,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:45,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:45,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:45,553 INFO L290 TraceCheckUtils]: 0: Hoare triple {121866#true} assume !false; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 1: Hoare triple {121866#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 2: Hoare triple {121866#true} assume !false; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 3: Hoare triple {121866#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 4: Hoare triple {121866#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 5: Hoare triple {121866#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 6: Hoare triple {121866#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 7: Hoare triple {121866#true} assume !(0 != eval_~tmp~0#1); {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 8: Hoare triple {121866#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {121866#true} is VALID [2022-02-21 04:22:45,554 INFO L290 TraceCheckUtils]: 9: Hoare triple {121866#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {121866#true} is VALID [2022-02-21 04:22:45,555 INFO L290 TraceCheckUtils]: 10: Hoare triple {121866#true} assume 0 == ~M_E~0;~M_E~0 := 1; {121866#true} is VALID [2022-02-21 04:22:45,555 INFO L290 TraceCheckUtils]: 11: Hoare triple {121866#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {121866#true} is VALID [2022-02-21 04:22:45,555 INFO L290 TraceCheckUtils]: 12: Hoare triple {121866#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,555 INFO L290 TraceCheckUtils]: 13: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,555 INFO L290 TraceCheckUtils]: 14: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,556 INFO L290 TraceCheckUtils]: 15: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,556 INFO L290 TraceCheckUtils]: 16: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,556 INFO L290 TraceCheckUtils]: 17: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,556 INFO L290 TraceCheckUtils]: 18: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,557 INFO L290 TraceCheckUtils]: 19: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,557 INFO L290 TraceCheckUtils]: 20: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,557 INFO L290 TraceCheckUtils]: 21: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,557 INFO L290 TraceCheckUtils]: 22: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,558 INFO L290 TraceCheckUtils]: 23: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,558 INFO L290 TraceCheckUtils]: 24: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,558 INFO L290 TraceCheckUtils]: 25: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,558 INFO L290 TraceCheckUtils]: 26: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,559 INFO L290 TraceCheckUtils]: 27: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,559 INFO L290 TraceCheckUtils]: 28: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,559 INFO L290 TraceCheckUtils]: 29: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,559 INFO L290 TraceCheckUtils]: 30: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,559 INFO L290 TraceCheckUtils]: 31: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,560 INFO L290 TraceCheckUtils]: 32: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,560 INFO L290 TraceCheckUtils]: 33: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,560 INFO L290 TraceCheckUtils]: 34: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,560 INFO L290 TraceCheckUtils]: 35: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,561 INFO L290 TraceCheckUtils]: 36: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,561 INFO L290 TraceCheckUtils]: 37: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,561 INFO L290 TraceCheckUtils]: 38: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,561 INFO L290 TraceCheckUtils]: 39: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,562 INFO L290 TraceCheckUtils]: 40: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,562 INFO L290 TraceCheckUtils]: 41: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,562 INFO L290 TraceCheckUtils]: 42: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,562 INFO L290 TraceCheckUtils]: 43: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,563 INFO L290 TraceCheckUtils]: 44: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,563 INFO L290 TraceCheckUtils]: 45: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,563 INFO L290 TraceCheckUtils]: 46: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,593 INFO L290 TraceCheckUtils]: 47: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,593 INFO L290 TraceCheckUtils]: 48: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,593 INFO L290 TraceCheckUtils]: 49: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,594 INFO L290 TraceCheckUtils]: 50: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,594 INFO L290 TraceCheckUtils]: 51: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,594 INFO L290 TraceCheckUtils]: 52: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,594 INFO L290 TraceCheckUtils]: 53: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,594 INFO L290 TraceCheckUtils]: 54: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,595 INFO L290 TraceCheckUtils]: 55: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,595 INFO L290 TraceCheckUtils]: 56: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,595 INFO L290 TraceCheckUtils]: 57: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,595 INFO L290 TraceCheckUtils]: 58: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,596 INFO L290 TraceCheckUtils]: 59: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,596 INFO L290 TraceCheckUtils]: 60: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,596 INFO L290 TraceCheckUtils]: 61: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,596 INFO L290 TraceCheckUtils]: 62: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,597 INFO L290 TraceCheckUtils]: 63: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,597 INFO L290 TraceCheckUtils]: 64: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,597 INFO L290 TraceCheckUtils]: 65: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,597 INFO L290 TraceCheckUtils]: 66: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,597 INFO L290 TraceCheckUtils]: 67: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,598 INFO L290 TraceCheckUtils]: 68: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,598 INFO L290 TraceCheckUtils]: 69: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,598 INFO L290 TraceCheckUtils]: 70: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,598 INFO L290 TraceCheckUtils]: 71: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,599 INFO L290 TraceCheckUtils]: 72: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,599 INFO L290 TraceCheckUtils]: 73: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,599 INFO L290 TraceCheckUtils]: 74: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,599 INFO L290 TraceCheckUtils]: 75: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,600 INFO L290 TraceCheckUtils]: 76: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,600 INFO L290 TraceCheckUtils]: 77: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,600 INFO L290 TraceCheckUtils]: 78: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,600 INFO L290 TraceCheckUtils]: 79: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,600 INFO L290 TraceCheckUtils]: 80: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,601 INFO L290 TraceCheckUtils]: 81: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,601 INFO L290 TraceCheckUtils]: 82: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,601 INFO L290 TraceCheckUtils]: 83: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,601 INFO L290 TraceCheckUtils]: 84: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {121868#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 85: Hoare triple {121868#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 86: Hoare triple {121867#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 87: Hoare triple {121867#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 88: Hoare triple {121867#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 89: Hoare triple {121867#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 90: Hoare triple {121867#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 91: Hoare triple {121867#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 92: Hoare triple {121867#false} assume 1 == ~E_M~0;~E_M~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 93: Hoare triple {121867#false} assume !(1 == ~E_1~0); {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 94: Hoare triple {121867#false} assume 1 == ~E_2~0;~E_2~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 95: Hoare triple {121867#false} assume 1 == ~E_3~0;~E_3~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 96: Hoare triple {121867#false} assume 1 == ~E_4~0;~E_4~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 97: Hoare triple {121867#false} assume 1 == ~E_5~0;~E_5~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 98: Hoare triple {121867#false} assume 1 == ~E_6~0;~E_6~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 99: Hoare triple {121867#false} assume 1 == ~E_7~0;~E_7~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 100: Hoare triple {121867#false} assume 1 == ~E_8~0;~E_8~0 := 2; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 101: Hoare triple {121867#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {121867#false} is VALID [2022-02-21 04:22:45,602 INFO L290 TraceCheckUtils]: 102: Hoare triple {121867#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 103: Hoare triple {121867#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 104: Hoare triple {121867#false} start_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 105: Hoare triple {121867#false} assume !(0 == start_simulation_~tmp~3#1); {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 106: Hoare triple {121867#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret24#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 107: Hoare triple {121867#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 108: Hoare triple {121867#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 109: Hoare triple {121867#false} stop_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret24#1;havoc stop_simulation_#t~ret24#1; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 110: Hoare triple {121867#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {121867#false} is VALID [2022-02-21 04:22:45,603 INFO L290 TraceCheckUtils]: 111: Hoare triple {121867#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {121867#false} is VALID [2022-02-21 04:22:45,604 INFO L290 TraceCheckUtils]: 112: Hoare triple {121867#false} start_simulation_#t~ret26#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {121867#false} is VALID [2022-02-21 04:22:45,604 INFO L290 TraceCheckUtils]: 113: Hoare triple {121867#false} assume !(0 != start_simulation_~tmp___0~1#1); {121867#false} is VALID [2022-02-21 04:22:45,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:45,604 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:45,604 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373236224] [2022-02-21 04:22:45,604 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373236224] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:45,605 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:45,605 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:45,605 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894123694] [2022-02-21 04:22:45,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:45,605 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:45,606 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:45,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:45,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:45,606 INFO L87 Difference]: Start difference. First operand 8861 states and 12789 transitions. cyclomatic complexity: 3936 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:00,993 INFO L93 Difference]: Finished difference Result 25208 states and 35974 transitions. [2022-02-21 04:23:00,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:00,997 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,059 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:01,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25208 states and 35974 transitions.