./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:22:03,916 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:22:03,918 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:22:03,949 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:22:03,949 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:22:03,952 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:22:03,953 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:22:03,955 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:22:03,956 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:22:03,959 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:22:03,959 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:22:03,960 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:22:03,961 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:22:03,962 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:22:03,963 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:22:03,966 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:22:03,966 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:22:03,967 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:22:03,968 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:22:03,972 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:22:03,973 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:22:03,974 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:22:03,975 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:22:03,975 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:22:03,980 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:22:03,980 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:22:03,980 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:22:03,981 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:22:03,982 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:22:03,982 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:22:03,982 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:22:03,983 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:22:03,984 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:22:03,985 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:22:03,986 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:22:03,986 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:22:03,986 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:22:03,987 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:22:03,988 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:22:03,988 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:22:03,989 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:22:03,989 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:22:04,013 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:22:04,013 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:22:04,014 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:22:04,014 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:22:04,015 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:22:04,015 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:22:04,015 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:22:04,015 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:22:04,015 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:22:04,015 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:22:04,016 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:22:04,016 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:22:04,016 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:22:04,017 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:22:04,017 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:22:04,017 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:22:04,017 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:22:04,017 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:22:04,017 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:22:04,017 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:22:04,018 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:22:04,018 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:22:04,018 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:22:04,018 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:22:04,018 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:22:04,018 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:22:04,018 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:22:04,019 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:22:04,019 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:22:04,019 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:22:04,019 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:22:04,020 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:22:04,020 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 [2022-02-21 04:22:04,183 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:22:04,201 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:22:04,204 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:22:04,204 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:22:04,219 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:22:04,220 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2022-02-21 04:22:04,291 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/55234c48c/58cf4d9868d84a55bb8081042cec1794/FLAGd4554b4b0 [2022-02-21 04:22:04,724 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:22:04,724 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2022-02-21 04:22:04,738 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/55234c48c/58cf4d9868d84a55bb8081042cec1794/FLAGd4554b4b0 [2022-02-21 04:22:05,062 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/55234c48c/58cf4d9868d84a55bb8081042cec1794 [2022-02-21 04:22:05,064 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:22:05,065 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:22:05,077 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:05,077 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:22:05,079 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:22:05,080 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,081 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@305297eb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05, skipping insertion in model container [2022-02-21 04:22:05,081 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,086 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:22:05,131 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:22:05,239 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2022-02-21 04:22:05,306 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:05,313 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:22:05,323 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2022-02-21 04:22:05,362 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:05,373 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:22:05,374 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05 WrapperNode [2022-02-21 04:22:05,374 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:05,375 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:05,375 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:22:05,375 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:22:05,388 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,399 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,486 INFO L137 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2370 [2022-02-21 04:22:05,486 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:05,487 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:22:05,487 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:22:05,487 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:22:05,493 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,493 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,500 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,501 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,533 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,550 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,553 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,558 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:22:05,559 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:22:05,559 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:22:05,559 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:22:05,560 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (1/1) ... [2022-02-21 04:22:05,575 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:22:05,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:22:05,590 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:22:05,609 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:22:05,628 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:22:05,628 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:22:05,628 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:22:05,628 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:22:05,715 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:22:05,716 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:22:06,935 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:22:06,960 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:22:06,960 INFO L299 CfgBuilder]: Removed 11 assume(true) statements. [2022-02-21 04:22:06,962 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:06 BoogieIcfgContainer [2022-02-21 04:22:06,963 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:22:06,963 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:22:06,964 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:22:06,966 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:22:06,966 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:06,966 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:22:05" (1/3) ... [2022-02-21 04:22:06,967 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5008117 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:06, skipping insertion in model container [2022-02-21 04:22:06,967 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:06,967 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:05" (2/3) ... [2022-02-21 04:22:06,968 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5008117 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:06, skipping insertion in model container [2022-02-21 04:22:06,968 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:06,968 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:06" (3/3) ... [2022-02-21 04:22:06,969 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2022-02-21 04:22:06,997 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:22:06,997 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:22:06,997 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:22:06,997 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:22:06,998 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:22:06,998 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:22:06,998 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:22:06,998 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:22:07,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2022-02-21 04:22:07,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:07,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:07,180 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:07,182 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:07,182 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:22:07,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2022-02-21 04:22:07,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:07,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:07,256 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:07,256 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:07,267 INFO L791 eck$LassoCheckResult]: Stem: 486#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 925#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 417#L1278true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512#L602true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 305#L609true assume !(1 == ~m_i~0);~m_st~0 := 2; 1006#L609-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 66#L614-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 105#L619-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 711#L624-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 966#L629-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 51#L634-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 281#L639-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 855#L644-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 298#L649-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108#L866true assume !(0 == ~M_E~0); 970#L866-2true assume !(0 == ~T1_E~0); 440#L871-1true assume !(0 == ~T2_E~0); 837#L876-1true assume !(0 == ~T3_E~0); 830#L881-1true assume !(0 == ~T4_E~0); 455#L886-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 276#L891-1true assume !(0 == ~T6_E~0); 443#L896-1true assume !(0 == ~T7_E~0); 575#L901-1true assume !(0 == ~T8_E~0); 466#L906-1true assume !(0 == ~E_M~0); 851#L911-1true assume !(0 == ~E_1~0); 304#L916-1true assume !(0 == ~E_2~0); 577#L921-1true assume !(0 == ~E_3~0); 732#L926-1true assume 0 == ~E_4~0;~E_4~0 := 1; 864#L931-1true assume !(0 == ~E_5~0); 891#L936-1true assume !(0 == ~E_6~0); 978#L941-1true assume !(0 == ~E_7~0); 307#L946-1true assume !(0 == ~E_8~0); 775#L951-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 896#L430true assume !(1 == ~m_pc~0); 679#L430-2true is_master_triggered_~__retres1~0#1 := 0; 20#L441true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 381#L442true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390#L1073true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 817#L1073-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 559#L449true assume 1 == ~t1_pc~0; 580#L450true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 813#L460true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3#L461true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 902#L1081true assume !(0 != activate_threads_~tmp___0~0#1); 477#L1081-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346#L468true assume !(1 == ~t2_pc~0); 226#L468-2true is_transmit2_triggered_~__retres1~2#1 := 0; 428#L479true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280#L480true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 219#L1089true assume !(0 != activate_threads_~tmp___1~0#1); 21#L1089-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 894#L487true assume 1 == ~t3_pc~0; 818#L488true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68#L498true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542#L499true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630#L1097true assume !(0 != activate_threads_~tmp___2~0#1); 262#L1097-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343#L506true assume !(1 == ~t4_pc~0); 848#L506-2true is_transmit4_triggered_~__retres1~4#1 := 0; 971#L517true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 752#L518true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 819#L1105true assume !(0 != activate_threads_~tmp___3~0#1); 337#L1105-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227#L525true assume 1 == ~t5_pc~0; 188#L526true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 700#L536true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 310#L537true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 955#L1113true assume !(0 != activate_threads_~tmp___4~0#1); 140#L1113-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334#L544true assume !(1 == ~t6_pc~0); 228#L544-2true is_transmit6_triggered_~__retres1~6#1 := 0; 495#L555true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998#L556true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32#L1121true assume !(0 != activate_threads_~tmp___5~0#1); 792#L1121-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 696#L563true assume 1 == ~t7_pc~0; 514#L564true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45#L574true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 368#L575true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 277#L1129true assume !(0 != activate_threads_~tmp___6~0#1); 112#L1129-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 496#L582true assume 1 == ~t8_pc~0; 73#L583true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 821#L593true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 981#L594true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 253#L1137true assume !(0 != activate_threads_~tmp___7~0#1); 190#L1137-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 561#L964true assume 1 == ~M_E~0;~M_E~0 := 2; 816#L964-2true assume !(1 == ~T1_E~0); 141#L969-1true assume !(1 == ~T2_E~0); 745#L974-1true assume !(1 == ~T3_E~0); 597#L979-1true assume !(1 == ~T4_E~0); 950#L984-1true assume !(1 == ~T5_E~0); 231#L989-1true assume !(1 == ~T6_E~0); 449#L994-1true assume !(1 == ~T7_E~0); 163#L999-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 566#L1004-1true assume !(1 == ~E_M~0); 33#L1009-1true assume !(1 == ~E_1~0); 157#L1014-1true assume !(1 == ~E_2~0); 549#L1019-1true assume !(1 == ~E_3~0); 791#L1024-1true assume !(1 == ~E_4~0); 120#L1029-1true assume !(1 == ~E_5~0); 172#L1034-1true assume !(1 == ~E_6~0); 982#L1039-1true assume 1 == ~E_7~0;~E_7~0 := 2; 760#L1044-1true assume !(1 == ~E_8~0); 286#L1049-1true assume { :end_inline_reset_delta_events } true; 104#L1315-2true [2022-02-21 04:22:07,268 INFO L793 eck$LassoCheckResult]: Loop: 104#L1315-2true assume !false; 873#L1316true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 173#L841true assume false; 617#L856true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 987#L602-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24#L866-3true assume 0 == ~M_E~0;~M_E~0 := 1; 826#L866-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 176#L871-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 265#L876-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 184#L881-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 666#L886-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 323#L891-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 452#L896-3true assume !(0 == ~T7_E~0); 240#L901-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 325#L906-3true assume 0 == ~E_M~0;~E_M~0 := 1; 587#L911-3true assume 0 == ~E_1~0;~E_1~0 := 1; 505#L916-3true assume 0 == ~E_2~0;~E_2~0 := 1; 200#L921-3true assume 0 == ~E_3~0;~E_3~0 := 1; 488#L926-3true assume 0 == ~E_4~0;~E_4~0 := 1; 583#L931-3true assume 0 == ~E_5~0;~E_5~0 := 1; 245#L936-3true assume !(0 == ~E_6~0); 336#L941-3true assume 0 == ~E_7~0;~E_7~0 := 1; 586#L946-3true assume 0 == ~E_8~0;~E_8~0 := 1; 177#L951-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 865#L430-30true assume !(1 == ~m_pc~0); 625#L430-32true is_master_triggered_~__retres1~0#1 := 0; 250#L441-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75#L442-10true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 531#L1073-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 917#L1073-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 539#L449-30true assume !(1 == ~t1_pc~0); 929#L449-32true is_transmit1_triggered_~__retres1~1#1 := 0; 31#L460-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 447#L461-10true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 230#L1081-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71#L1081-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 382#L468-30true assume !(1 == ~t2_pc~0); 800#L468-32true is_transmit2_triggered_~__retres1~2#1 := 0; 593#L479-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 898#L480-10true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 318#L1089-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 773#L1089-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222#L487-30true assume 1 == ~t3_pc~0; 211#L488-10true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 843#L498-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306#L499-10true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 803#L1097-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 557#L1097-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272#L506-30true assume 1 == ~t4_pc~0; 983#L507-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 288#L517-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 301#L518-10true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 614#L1105-30true assume !(0 != activate_threads_~tmp___3~0#1); 223#L1105-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 972#L525-30true assume 1 == ~t5_pc~0; 690#L526-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 920#L536-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63#L537-10true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 672#L1113-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 225#L1113-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96#L544-30true assume !(1 == ~t6_pc~0); 741#L544-32true is_transmit6_triggered_~__retres1~6#1 := 0; 868#L555-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 992#L556-10true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 702#L1121-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 994#L1121-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 662#L563-30true assume !(1 == ~t7_pc~0); 165#L563-32true is_transmit7_triggered_~__retres1~7#1 := 0; 90#L574-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 939#L575-10true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 282#L1129-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 909#L1129-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 640#L582-30true assume 1 == ~t8_pc~0; 585#L583-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 274#L593-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 693#L594-10true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991#L1137-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 904#L1137-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36#L964-3true assume 1 == ~M_E~0;~M_E~0 := 2; 102#L964-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 209#L969-3true assume !(1 == ~T2_E~0); 98#L974-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 921#L979-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 349#L984-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 986#L989-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 122#L994-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 824#L999-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 474#L1004-3true assume 1 == ~E_M~0;~E_M~0 := 2; 59#L1009-3true assume !(1 == ~E_1~0); 543#L1014-3true assume 1 == ~E_2~0;~E_2~0 := 2; 331#L1019-3true assume 1 == ~E_3~0;~E_3~0 := 2; 968#L1024-3true assume 1 == ~E_4~0;~E_4~0 := 2; 320#L1029-3true assume 1 == ~E_5~0;~E_5~0 := 2; 302#L1034-3true assume 1 == ~E_6~0;~E_6~0 := 2; 548#L1039-3true assume 1 == ~E_7~0;~E_7~0 := 2; 578#L1044-3true assume 1 == ~E_8~0;~E_8~0 := 2; 117#L1049-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 453#L662-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 687#L709-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 425#L710-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 136#L1334true assume !(0 == start_simulation_~tmp~3#1); 812#L1334-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 146#L662-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5#L709-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 335#L710-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 918#L1289true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 735#L1296true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 497#L1297true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 710#L1347true assume !(0 != start_simulation_~tmp___0~1#1); 104#L1315-2true [2022-02-21 04:22:07,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:07,273 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2022-02-21 04:22:07,279 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:07,279 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690627643] [2022-02-21 04:22:07,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:07,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:07,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:07,428 INFO L290 TraceCheckUtils]: 0: Hoare triple {1010#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {1010#true} is VALID [2022-02-21 04:22:07,429 INFO L290 TraceCheckUtils]: 1: Hoare triple {1010#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {1012#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:07,429 INFO L290 TraceCheckUtils]: 2: Hoare triple {1012#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1012#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:07,430 INFO L290 TraceCheckUtils]: 3: Hoare triple {1012#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1012#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:07,431 INFO L290 TraceCheckUtils]: 4: Hoare triple {1012#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,431 INFO L290 TraceCheckUtils]: 5: Hoare triple {1011#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1011#false} is VALID [2022-02-21 04:22:07,431 INFO L290 TraceCheckUtils]: 6: Hoare triple {1011#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,431 INFO L290 TraceCheckUtils]: 7: Hoare triple {1011#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,431 INFO L290 TraceCheckUtils]: 8: Hoare triple {1011#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,432 INFO L290 TraceCheckUtils]: 9: Hoare triple {1011#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,432 INFO L290 TraceCheckUtils]: 10: Hoare triple {1011#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,432 INFO L290 TraceCheckUtils]: 11: Hoare triple {1011#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,432 INFO L290 TraceCheckUtils]: 12: Hoare triple {1011#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,432 INFO L290 TraceCheckUtils]: 13: Hoare triple {1011#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1011#false} is VALID [2022-02-21 04:22:07,439 INFO L290 TraceCheckUtils]: 14: Hoare triple {1011#false} assume !(0 == ~M_E~0); {1011#false} is VALID [2022-02-21 04:22:07,439 INFO L290 TraceCheckUtils]: 15: Hoare triple {1011#false} assume !(0 == ~T1_E~0); {1011#false} is VALID [2022-02-21 04:22:07,439 INFO L290 TraceCheckUtils]: 16: Hoare triple {1011#false} assume !(0 == ~T2_E~0); {1011#false} is VALID [2022-02-21 04:22:07,439 INFO L290 TraceCheckUtils]: 17: Hoare triple {1011#false} assume !(0 == ~T3_E~0); {1011#false} is VALID [2022-02-21 04:22:07,439 INFO L290 TraceCheckUtils]: 18: Hoare triple {1011#false} assume !(0 == ~T4_E~0); {1011#false} is VALID [2022-02-21 04:22:07,439 INFO L290 TraceCheckUtils]: 19: Hoare triple {1011#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1011#false} is VALID [2022-02-21 04:22:07,440 INFO L290 TraceCheckUtils]: 20: Hoare triple {1011#false} assume !(0 == ~T6_E~0); {1011#false} is VALID [2022-02-21 04:22:07,440 INFO L290 TraceCheckUtils]: 21: Hoare triple {1011#false} assume !(0 == ~T7_E~0); {1011#false} is VALID [2022-02-21 04:22:07,440 INFO L290 TraceCheckUtils]: 22: Hoare triple {1011#false} assume !(0 == ~T8_E~0); {1011#false} is VALID [2022-02-21 04:22:07,440 INFO L290 TraceCheckUtils]: 23: Hoare triple {1011#false} assume !(0 == ~E_M~0); {1011#false} is VALID [2022-02-21 04:22:07,440 INFO L290 TraceCheckUtils]: 24: Hoare triple {1011#false} assume !(0 == ~E_1~0); {1011#false} is VALID [2022-02-21 04:22:07,441 INFO L290 TraceCheckUtils]: 25: Hoare triple {1011#false} assume !(0 == ~E_2~0); {1011#false} is VALID [2022-02-21 04:22:07,441 INFO L290 TraceCheckUtils]: 26: Hoare triple {1011#false} assume !(0 == ~E_3~0); {1011#false} is VALID [2022-02-21 04:22:07,441 INFO L290 TraceCheckUtils]: 27: Hoare triple {1011#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1011#false} is VALID [2022-02-21 04:22:07,441 INFO L290 TraceCheckUtils]: 28: Hoare triple {1011#false} assume !(0 == ~E_5~0); {1011#false} is VALID [2022-02-21 04:22:07,441 INFO L290 TraceCheckUtils]: 29: Hoare triple {1011#false} assume !(0 == ~E_6~0); {1011#false} is VALID [2022-02-21 04:22:07,441 INFO L290 TraceCheckUtils]: 30: Hoare triple {1011#false} assume !(0 == ~E_7~0); {1011#false} is VALID [2022-02-21 04:22:07,442 INFO L290 TraceCheckUtils]: 31: Hoare triple {1011#false} assume !(0 == ~E_8~0); {1011#false} is VALID [2022-02-21 04:22:07,442 INFO L290 TraceCheckUtils]: 32: Hoare triple {1011#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1011#false} is VALID [2022-02-21 04:22:07,442 INFO L290 TraceCheckUtils]: 33: Hoare triple {1011#false} assume !(1 == ~m_pc~0); {1011#false} is VALID [2022-02-21 04:22:07,442 INFO L290 TraceCheckUtils]: 34: Hoare triple {1011#false} is_master_triggered_~__retres1~0#1 := 0; {1011#false} is VALID [2022-02-21 04:22:07,442 INFO L290 TraceCheckUtils]: 35: Hoare triple {1011#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1011#false} is VALID [2022-02-21 04:22:07,443 INFO L290 TraceCheckUtils]: 36: Hoare triple {1011#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1011#false} is VALID [2022-02-21 04:22:07,443 INFO L290 TraceCheckUtils]: 37: Hoare triple {1011#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1011#false} is VALID [2022-02-21 04:22:07,443 INFO L290 TraceCheckUtils]: 38: Hoare triple {1011#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1011#false} is VALID [2022-02-21 04:22:07,443 INFO L290 TraceCheckUtils]: 39: Hoare triple {1011#false} assume 1 == ~t1_pc~0; {1011#false} is VALID [2022-02-21 04:22:07,443 INFO L290 TraceCheckUtils]: 40: Hoare triple {1011#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1011#false} is VALID [2022-02-21 04:22:07,444 INFO L290 TraceCheckUtils]: 41: Hoare triple {1011#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1011#false} is VALID [2022-02-21 04:22:07,444 INFO L290 TraceCheckUtils]: 42: Hoare triple {1011#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1011#false} is VALID [2022-02-21 04:22:07,444 INFO L290 TraceCheckUtils]: 43: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___0~0#1); {1011#false} is VALID [2022-02-21 04:22:07,444 INFO L290 TraceCheckUtils]: 44: Hoare triple {1011#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1011#false} is VALID [2022-02-21 04:22:07,444 INFO L290 TraceCheckUtils]: 45: Hoare triple {1011#false} assume !(1 == ~t2_pc~0); {1011#false} is VALID [2022-02-21 04:22:07,444 INFO L290 TraceCheckUtils]: 46: Hoare triple {1011#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1011#false} is VALID [2022-02-21 04:22:07,445 INFO L290 TraceCheckUtils]: 47: Hoare triple {1011#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1011#false} is VALID [2022-02-21 04:22:07,445 INFO L290 TraceCheckUtils]: 48: Hoare triple {1011#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1011#false} is VALID [2022-02-21 04:22:07,445 INFO L290 TraceCheckUtils]: 49: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___1~0#1); {1011#false} is VALID [2022-02-21 04:22:07,445 INFO L290 TraceCheckUtils]: 50: Hoare triple {1011#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1011#false} is VALID [2022-02-21 04:22:07,445 INFO L290 TraceCheckUtils]: 51: Hoare triple {1011#false} assume 1 == ~t3_pc~0; {1011#false} is VALID [2022-02-21 04:22:07,446 INFO L290 TraceCheckUtils]: 52: Hoare triple {1011#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1011#false} is VALID [2022-02-21 04:22:07,446 INFO L290 TraceCheckUtils]: 53: Hoare triple {1011#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1011#false} is VALID [2022-02-21 04:22:07,446 INFO L290 TraceCheckUtils]: 54: Hoare triple {1011#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1011#false} is VALID [2022-02-21 04:22:07,446 INFO L290 TraceCheckUtils]: 55: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___2~0#1); {1011#false} is VALID [2022-02-21 04:22:07,446 INFO L290 TraceCheckUtils]: 56: Hoare triple {1011#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1011#false} is VALID [2022-02-21 04:22:07,446 INFO L290 TraceCheckUtils]: 57: Hoare triple {1011#false} assume !(1 == ~t4_pc~0); {1011#false} is VALID [2022-02-21 04:22:07,447 INFO L290 TraceCheckUtils]: 58: Hoare triple {1011#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1011#false} is VALID [2022-02-21 04:22:07,447 INFO L290 TraceCheckUtils]: 59: Hoare triple {1011#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1011#false} is VALID [2022-02-21 04:22:07,447 INFO L290 TraceCheckUtils]: 60: Hoare triple {1011#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1011#false} is VALID [2022-02-21 04:22:07,447 INFO L290 TraceCheckUtils]: 61: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___3~0#1); {1011#false} is VALID [2022-02-21 04:22:07,447 INFO L290 TraceCheckUtils]: 62: Hoare triple {1011#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1011#false} is VALID [2022-02-21 04:22:07,448 INFO L290 TraceCheckUtils]: 63: Hoare triple {1011#false} assume 1 == ~t5_pc~0; {1011#false} is VALID [2022-02-21 04:22:07,448 INFO L290 TraceCheckUtils]: 64: Hoare triple {1011#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1011#false} is VALID [2022-02-21 04:22:07,448 INFO L290 TraceCheckUtils]: 65: Hoare triple {1011#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1011#false} is VALID [2022-02-21 04:22:07,448 INFO L290 TraceCheckUtils]: 66: Hoare triple {1011#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1011#false} is VALID [2022-02-21 04:22:07,448 INFO L290 TraceCheckUtils]: 67: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___4~0#1); {1011#false} is VALID [2022-02-21 04:22:07,449 INFO L290 TraceCheckUtils]: 68: Hoare triple {1011#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1011#false} is VALID [2022-02-21 04:22:07,449 INFO L290 TraceCheckUtils]: 69: Hoare triple {1011#false} assume !(1 == ~t6_pc~0); {1011#false} is VALID [2022-02-21 04:22:07,449 INFO L290 TraceCheckUtils]: 70: Hoare triple {1011#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1011#false} is VALID [2022-02-21 04:22:07,449 INFO L290 TraceCheckUtils]: 71: Hoare triple {1011#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1011#false} is VALID [2022-02-21 04:22:07,449 INFO L290 TraceCheckUtils]: 72: Hoare triple {1011#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1011#false} is VALID [2022-02-21 04:22:07,449 INFO L290 TraceCheckUtils]: 73: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___5~0#1); {1011#false} is VALID [2022-02-21 04:22:07,450 INFO L290 TraceCheckUtils]: 74: Hoare triple {1011#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1011#false} is VALID [2022-02-21 04:22:07,450 INFO L290 TraceCheckUtils]: 75: Hoare triple {1011#false} assume 1 == ~t7_pc~0; {1011#false} is VALID [2022-02-21 04:22:07,450 INFO L290 TraceCheckUtils]: 76: Hoare triple {1011#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1011#false} is VALID [2022-02-21 04:22:07,450 INFO L290 TraceCheckUtils]: 77: Hoare triple {1011#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1011#false} is VALID [2022-02-21 04:22:07,450 INFO L290 TraceCheckUtils]: 78: Hoare triple {1011#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1011#false} is VALID [2022-02-21 04:22:07,451 INFO L290 TraceCheckUtils]: 79: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___6~0#1); {1011#false} is VALID [2022-02-21 04:22:07,451 INFO L290 TraceCheckUtils]: 80: Hoare triple {1011#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1011#false} is VALID [2022-02-21 04:22:07,451 INFO L290 TraceCheckUtils]: 81: Hoare triple {1011#false} assume 1 == ~t8_pc~0; {1011#false} is VALID [2022-02-21 04:22:07,451 INFO L290 TraceCheckUtils]: 82: Hoare triple {1011#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1011#false} is VALID [2022-02-21 04:22:07,451 INFO L290 TraceCheckUtils]: 83: Hoare triple {1011#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1011#false} is VALID [2022-02-21 04:22:07,451 INFO L290 TraceCheckUtils]: 84: Hoare triple {1011#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1011#false} is VALID [2022-02-21 04:22:07,452 INFO L290 TraceCheckUtils]: 85: Hoare triple {1011#false} assume !(0 != activate_threads_~tmp___7~0#1); {1011#false} is VALID [2022-02-21 04:22:07,452 INFO L290 TraceCheckUtils]: 86: Hoare triple {1011#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1011#false} is VALID [2022-02-21 04:22:07,452 INFO L290 TraceCheckUtils]: 87: Hoare triple {1011#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,452 INFO L290 TraceCheckUtils]: 88: Hoare triple {1011#false} assume !(1 == ~T1_E~0); {1011#false} is VALID [2022-02-21 04:22:07,452 INFO L290 TraceCheckUtils]: 89: Hoare triple {1011#false} assume !(1 == ~T2_E~0); {1011#false} is VALID [2022-02-21 04:22:07,452 INFO L290 TraceCheckUtils]: 90: Hoare triple {1011#false} assume !(1 == ~T3_E~0); {1011#false} is VALID [2022-02-21 04:22:07,453 INFO L290 TraceCheckUtils]: 91: Hoare triple {1011#false} assume !(1 == ~T4_E~0); {1011#false} is VALID [2022-02-21 04:22:07,453 INFO L290 TraceCheckUtils]: 92: Hoare triple {1011#false} assume !(1 == ~T5_E~0); {1011#false} is VALID [2022-02-21 04:22:07,453 INFO L290 TraceCheckUtils]: 93: Hoare triple {1011#false} assume !(1 == ~T6_E~0); {1011#false} is VALID [2022-02-21 04:22:07,453 INFO L290 TraceCheckUtils]: 94: Hoare triple {1011#false} assume !(1 == ~T7_E~0); {1011#false} is VALID [2022-02-21 04:22:07,453 INFO L290 TraceCheckUtils]: 95: Hoare triple {1011#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,454 INFO L290 TraceCheckUtils]: 96: Hoare triple {1011#false} assume !(1 == ~E_M~0); {1011#false} is VALID [2022-02-21 04:22:07,454 INFO L290 TraceCheckUtils]: 97: Hoare triple {1011#false} assume !(1 == ~E_1~0); {1011#false} is VALID [2022-02-21 04:22:07,454 INFO L290 TraceCheckUtils]: 98: Hoare triple {1011#false} assume !(1 == ~E_2~0); {1011#false} is VALID [2022-02-21 04:22:07,454 INFO L290 TraceCheckUtils]: 99: Hoare triple {1011#false} assume !(1 == ~E_3~0); {1011#false} is VALID [2022-02-21 04:22:07,454 INFO L290 TraceCheckUtils]: 100: Hoare triple {1011#false} assume !(1 == ~E_4~0); {1011#false} is VALID [2022-02-21 04:22:07,454 INFO L290 TraceCheckUtils]: 101: Hoare triple {1011#false} assume !(1 == ~E_5~0); {1011#false} is VALID [2022-02-21 04:22:07,455 INFO L290 TraceCheckUtils]: 102: Hoare triple {1011#false} assume !(1 == ~E_6~0); {1011#false} is VALID [2022-02-21 04:22:07,455 INFO L290 TraceCheckUtils]: 103: Hoare triple {1011#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1011#false} is VALID [2022-02-21 04:22:07,455 INFO L290 TraceCheckUtils]: 104: Hoare triple {1011#false} assume !(1 == ~E_8~0); {1011#false} is VALID [2022-02-21 04:22:07,455 INFO L290 TraceCheckUtils]: 105: Hoare triple {1011#false} assume { :end_inline_reset_delta_events } true; {1011#false} is VALID [2022-02-21 04:22:07,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:07,457 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:07,457 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690627643] [2022-02-21 04:22:07,457 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690627643] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:07,457 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:07,458 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:07,459 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287002336] [2022-02-21 04:22:07,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:07,462 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:07,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:07,463 INFO L85 PathProgramCache]: Analyzing trace with hash 1133148117, now seen corresponding path program 1 times [2022-02-21 04:22:07,463 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:07,463 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028641103] [2022-02-21 04:22:07,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:07,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:07,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:07,488 INFO L290 TraceCheckUtils]: 0: Hoare triple {1013#true} assume !false; {1013#true} is VALID [2022-02-21 04:22:07,488 INFO L290 TraceCheckUtils]: 1: Hoare triple {1013#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1013#true} is VALID [2022-02-21 04:22:07,489 INFO L290 TraceCheckUtils]: 2: Hoare triple {1013#true} assume false; {1014#false} is VALID [2022-02-21 04:22:07,489 INFO L290 TraceCheckUtils]: 3: Hoare triple {1014#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1014#false} is VALID [2022-02-21 04:22:07,489 INFO L290 TraceCheckUtils]: 4: Hoare triple {1014#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1014#false} is VALID [2022-02-21 04:22:07,489 INFO L290 TraceCheckUtils]: 5: Hoare triple {1014#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,489 INFO L290 TraceCheckUtils]: 6: Hoare triple {1014#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,490 INFO L290 TraceCheckUtils]: 7: Hoare triple {1014#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,490 INFO L290 TraceCheckUtils]: 8: Hoare triple {1014#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,490 INFO L290 TraceCheckUtils]: 9: Hoare triple {1014#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,490 INFO L290 TraceCheckUtils]: 10: Hoare triple {1014#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,490 INFO L290 TraceCheckUtils]: 11: Hoare triple {1014#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,490 INFO L290 TraceCheckUtils]: 12: Hoare triple {1014#false} assume !(0 == ~T7_E~0); {1014#false} is VALID [2022-02-21 04:22:07,491 INFO L290 TraceCheckUtils]: 13: Hoare triple {1014#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,491 INFO L290 TraceCheckUtils]: 14: Hoare triple {1014#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,491 INFO L290 TraceCheckUtils]: 15: Hoare triple {1014#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,491 INFO L290 TraceCheckUtils]: 16: Hoare triple {1014#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,491 INFO L290 TraceCheckUtils]: 17: Hoare triple {1014#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,492 INFO L290 TraceCheckUtils]: 18: Hoare triple {1014#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,492 INFO L290 TraceCheckUtils]: 19: Hoare triple {1014#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,492 INFO L290 TraceCheckUtils]: 20: Hoare triple {1014#false} assume !(0 == ~E_6~0); {1014#false} is VALID [2022-02-21 04:22:07,492 INFO L290 TraceCheckUtils]: 21: Hoare triple {1014#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,492 INFO L290 TraceCheckUtils]: 22: Hoare triple {1014#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1014#false} is VALID [2022-02-21 04:22:07,492 INFO L290 TraceCheckUtils]: 23: Hoare triple {1014#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1014#false} is VALID [2022-02-21 04:22:07,493 INFO L290 TraceCheckUtils]: 24: Hoare triple {1014#false} assume !(1 == ~m_pc~0); {1014#false} is VALID [2022-02-21 04:22:07,493 INFO L290 TraceCheckUtils]: 25: Hoare triple {1014#false} is_master_triggered_~__retres1~0#1 := 0; {1014#false} is VALID [2022-02-21 04:22:07,493 INFO L290 TraceCheckUtils]: 26: Hoare triple {1014#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1014#false} is VALID [2022-02-21 04:22:07,493 INFO L290 TraceCheckUtils]: 27: Hoare triple {1014#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1014#false} is VALID [2022-02-21 04:22:07,493 INFO L290 TraceCheckUtils]: 28: Hoare triple {1014#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,493 INFO L290 TraceCheckUtils]: 29: Hoare triple {1014#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1014#false} is VALID [2022-02-21 04:22:07,494 INFO L290 TraceCheckUtils]: 30: Hoare triple {1014#false} assume !(1 == ~t1_pc~0); {1014#false} is VALID [2022-02-21 04:22:07,494 INFO L290 TraceCheckUtils]: 31: Hoare triple {1014#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1014#false} is VALID [2022-02-21 04:22:07,494 INFO L290 TraceCheckUtils]: 32: Hoare triple {1014#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1014#false} is VALID [2022-02-21 04:22:07,494 INFO L290 TraceCheckUtils]: 33: Hoare triple {1014#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1014#false} is VALID [2022-02-21 04:22:07,494 INFO L290 TraceCheckUtils]: 34: Hoare triple {1014#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,494 INFO L290 TraceCheckUtils]: 35: Hoare triple {1014#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1014#false} is VALID [2022-02-21 04:22:07,495 INFO L290 TraceCheckUtils]: 36: Hoare triple {1014#false} assume !(1 == ~t2_pc~0); {1014#false} is VALID [2022-02-21 04:22:07,495 INFO L290 TraceCheckUtils]: 37: Hoare triple {1014#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1014#false} is VALID [2022-02-21 04:22:07,495 INFO L290 TraceCheckUtils]: 38: Hoare triple {1014#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1014#false} is VALID [2022-02-21 04:22:07,495 INFO L290 TraceCheckUtils]: 39: Hoare triple {1014#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1014#false} is VALID [2022-02-21 04:22:07,495 INFO L290 TraceCheckUtils]: 40: Hoare triple {1014#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,496 INFO L290 TraceCheckUtils]: 41: Hoare triple {1014#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1014#false} is VALID [2022-02-21 04:22:07,496 INFO L290 TraceCheckUtils]: 42: Hoare triple {1014#false} assume 1 == ~t3_pc~0; {1014#false} is VALID [2022-02-21 04:22:07,496 INFO L290 TraceCheckUtils]: 43: Hoare triple {1014#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1014#false} is VALID [2022-02-21 04:22:07,496 INFO L290 TraceCheckUtils]: 44: Hoare triple {1014#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1014#false} is VALID [2022-02-21 04:22:07,496 INFO L290 TraceCheckUtils]: 45: Hoare triple {1014#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1014#false} is VALID [2022-02-21 04:22:07,496 INFO L290 TraceCheckUtils]: 46: Hoare triple {1014#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,497 INFO L290 TraceCheckUtils]: 47: Hoare triple {1014#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1014#false} is VALID [2022-02-21 04:22:07,497 INFO L290 TraceCheckUtils]: 48: Hoare triple {1014#false} assume 1 == ~t4_pc~0; {1014#false} is VALID [2022-02-21 04:22:07,497 INFO L290 TraceCheckUtils]: 49: Hoare triple {1014#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1014#false} is VALID [2022-02-21 04:22:07,497 INFO L290 TraceCheckUtils]: 50: Hoare triple {1014#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1014#false} is VALID [2022-02-21 04:22:07,497 INFO L290 TraceCheckUtils]: 51: Hoare triple {1014#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1014#false} is VALID [2022-02-21 04:22:07,497 INFO L290 TraceCheckUtils]: 52: Hoare triple {1014#false} assume !(0 != activate_threads_~tmp___3~0#1); {1014#false} is VALID [2022-02-21 04:22:07,498 INFO L290 TraceCheckUtils]: 53: Hoare triple {1014#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1014#false} is VALID [2022-02-21 04:22:07,498 INFO L290 TraceCheckUtils]: 54: Hoare triple {1014#false} assume 1 == ~t5_pc~0; {1014#false} is VALID [2022-02-21 04:22:07,498 INFO L290 TraceCheckUtils]: 55: Hoare triple {1014#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1014#false} is VALID [2022-02-21 04:22:07,498 INFO L290 TraceCheckUtils]: 56: Hoare triple {1014#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1014#false} is VALID [2022-02-21 04:22:07,498 INFO L290 TraceCheckUtils]: 57: Hoare triple {1014#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1014#false} is VALID [2022-02-21 04:22:07,498 INFO L290 TraceCheckUtils]: 58: Hoare triple {1014#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,499 INFO L290 TraceCheckUtils]: 59: Hoare triple {1014#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1014#false} is VALID [2022-02-21 04:22:07,499 INFO L290 TraceCheckUtils]: 60: Hoare triple {1014#false} assume !(1 == ~t6_pc~0); {1014#false} is VALID [2022-02-21 04:22:07,499 INFO L290 TraceCheckUtils]: 61: Hoare triple {1014#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1014#false} is VALID [2022-02-21 04:22:07,499 INFO L290 TraceCheckUtils]: 62: Hoare triple {1014#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1014#false} is VALID [2022-02-21 04:22:07,499 INFO L290 TraceCheckUtils]: 63: Hoare triple {1014#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1014#false} is VALID [2022-02-21 04:22:07,500 INFO L290 TraceCheckUtils]: 64: Hoare triple {1014#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,500 INFO L290 TraceCheckUtils]: 65: Hoare triple {1014#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1014#false} is VALID [2022-02-21 04:22:07,500 INFO L290 TraceCheckUtils]: 66: Hoare triple {1014#false} assume !(1 == ~t7_pc~0); {1014#false} is VALID [2022-02-21 04:22:07,500 INFO L290 TraceCheckUtils]: 67: Hoare triple {1014#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1014#false} is VALID [2022-02-21 04:22:07,500 INFO L290 TraceCheckUtils]: 68: Hoare triple {1014#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1014#false} is VALID [2022-02-21 04:22:07,500 INFO L290 TraceCheckUtils]: 69: Hoare triple {1014#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1014#false} is VALID [2022-02-21 04:22:07,501 INFO L290 TraceCheckUtils]: 70: Hoare triple {1014#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,501 INFO L290 TraceCheckUtils]: 71: Hoare triple {1014#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1014#false} is VALID [2022-02-21 04:22:07,501 INFO L290 TraceCheckUtils]: 72: Hoare triple {1014#false} assume 1 == ~t8_pc~0; {1014#false} is VALID [2022-02-21 04:22:07,501 INFO L290 TraceCheckUtils]: 73: Hoare triple {1014#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1014#false} is VALID [2022-02-21 04:22:07,501 INFO L290 TraceCheckUtils]: 74: Hoare triple {1014#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1014#false} is VALID [2022-02-21 04:22:07,501 INFO L290 TraceCheckUtils]: 75: Hoare triple {1014#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1014#false} is VALID [2022-02-21 04:22:07,502 INFO L290 TraceCheckUtils]: 76: Hoare triple {1014#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1014#false} is VALID [2022-02-21 04:22:07,502 INFO L290 TraceCheckUtils]: 77: Hoare triple {1014#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1014#false} is VALID [2022-02-21 04:22:07,502 INFO L290 TraceCheckUtils]: 78: Hoare triple {1014#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,502 INFO L290 TraceCheckUtils]: 79: Hoare triple {1014#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,502 INFO L290 TraceCheckUtils]: 80: Hoare triple {1014#false} assume !(1 == ~T2_E~0); {1014#false} is VALID [2022-02-21 04:22:07,502 INFO L290 TraceCheckUtils]: 81: Hoare triple {1014#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,503 INFO L290 TraceCheckUtils]: 82: Hoare triple {1014#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,503 INFO L290 TraceCheckUtils]: 83: Hoare triple {1014#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,503 INFO L290 TraceCheckUtils]: 84: Hoare triple {1014#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,503 INFO L290 TraceCheckUtils]: 85: Hoare triple {1014#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,503 INFO L290 TraceCheckUtils]: 86: Hoare triple {1014#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,504 INFO L290 TraceCheckUtils]: 87: Hoare triple {1014#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,504 INFO L290 TraceCheckUtils]: 88: Hoare triple {1014#false} assume !(1 == ~E_1~0); {1014#false} is VALID [2022-02-21 04:22:07,504 INFO L290 TraceCheckUtils]: 89: Hoare triple {1014#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,504 INFO L290 TraceCheckUtils]: 90: Hoare triple {1014#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,504 INFO L290 TraceCheckUtils]: 91: Hoare triple {1014#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,504 INFO L290 TraceCheckUtils]: 92: Hoare triple {1014#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,505 INFO L290 TraceCheckUtils]: 93: Hoare triple {1014#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,505 INFO L290 TraceCheckUtils]: 94: Hoare triple {1014#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,505 INFO L290 TraceCheckUtils]: 95: Hoare triple {1014#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1014#false} is VALID [2022-02-21 04:22:07,505 INFO L290 TraceCheckUtils]: 96: Hoare triple {1014#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {1014#false} is VALID [2022-02-21 04:22:07,505 INFO L290 TraceCheckUtils]: 97: Hoare triple {1014#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {1014#false} is VALID [2022-02-21 04:22:07,505 INFO L290 TraceCheckUtils]: 98: Hoare triple {1014#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {1014#false} is VALID [2022-02-21 04:22:07,506 INFO L290 TraceCheckUtils]: 99: Hoare triple {1014#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {1014#false} is VALID [2022-02-21 04:22:07,506 INFO L290 TraceCheckUtils]: 100: Hoare triple {1014#false} assume !(0 == start_simulation_~tmp~3#1); {1014#false} is VALID [2022-02-21 04:22:07,506 INFO L290 TraceCheckUtils]: 101: Hoare triple {1014#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {1014#false} is VALID [2022-02-21 04:22:07,506 INFO L290 TraceCheckUtils]: 102: Hoare triple {1014#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {1014#false} is VALID [2022-02-21 04:22:07,506 INFO L290 TraceCheckUtils]: 103: Hoare triple {1014#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {1014#false} is VALID [2022-02-21 04:22:07,506 INFO L290 TraceCheckUtils]: 104: Hoare triple {1014#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {1014#false} is VALID [2022-02-21 04:22:07,507 INFO L290 TraceCheckUtils]: 105: Hoare triple {1014#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1014#false} is VALID [2022-02-21 04:22:07,507 INFO L290 TraceCheckUtils]: 106: Hoare triple {1014#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1014#false} is VALID [2022-02-21 04:22:07,507 INFO L290 TraceCheckUtils]: 107: Hoare triple {1014#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {1014#false} is VALID [2022-02-21 04:22:07,507 INFO L290 TraceCheckUtils]: 108: Hoare triple {1014#false} assume !(0 != start_simulation_~tmp___0~1#1); {1014#false} is VALID [2022-02-21 04:22:07,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:07,508 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:07,508 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028641103] [2022-02-21 04:22:07,508 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028641103] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:07,508 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:07,508 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:07,509 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074439684] [2022-02-21 04:22:07,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:07,510 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:07,510 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:07,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:07,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:07,532 INFO L87 Difference]: Start difference. First operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:08,415 INFO L93 Difference]: Finished difference Result 1004 states and 1496 transitions. [2022-02-21 04:22:08,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:08,416 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,484 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:08,488 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1004 states and 1496 transitions. [2022-02-21 04:22:08,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:08,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1004 states to 998 states and 1490 transitions. [2022-02-21 04:22:08,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:08,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:08,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1490 transitions. [2022-02-21 04:22:08,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:08,567 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2022-02-21 04:22:08,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1490 transitions. [2022-02-21 04:22:08,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:08,611 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:08,615 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1490 transitions. Second operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,619 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1490 transitions. Second operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,634 INFO L87 Difference]: Start difference. First operand 998 states and 1490 transitions. Second operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:08,680 INFO L93 Difference]: Finished difference Result 998 states and 1490 transitions. [2022-02-21 04:22:08,681 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1490 transitions. [2022-02-21 04:22:08,689 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:08,689 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:08,694 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1490 transitions. [2022-02-21 04:22:08,696 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1490 transitions. [2022-02-21 04:22:08,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:08,730 INFO L93 Difference]: Finished difference Result 998 states and 1490 transitions. [2022-02-21 04:22:08,730 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1490 transitions. [2022-02-21 04:22:08,733 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:08,733 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:08,733 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:08,733 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:08,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1490 transitions. [2022-02-21 04:22:08,763 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2022-02-21 04:22:08,763 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2022-02-21 04:22:08,763 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:22:08,763 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1490 transitions. [2022-02-21 04:22:08,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:08,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:08,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:08,774 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:08,774 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:08,774 INFO L791 eck$LassoCheckResult]: Stem: 2789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2716#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2717#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2569#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2570#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2155#L614-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2156#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2237#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2948#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2125#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2126#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2533#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2558#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2241#L866 assume !(0 == ~M_E~0); 2242#L866-2 assume !(0 == ~T1_E~0); 2744#L871-1 assume !(0 == ~T2_E~0); 2745#L876-1 assume !(0 == ~T3_E~0); 2995#L881-1 assume !(0 == ~T4_E~0); 2754#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2524#L891-1 assume !(0 == ~T6_E~0); 2525#L896-1 assume !(0 == ~T7_E~0); 2747#L901-1 assume !(0 == ~T8_E~0); 2765#L906-1 assume !(0 == ~E_M~0); 2766#L911-1 assume !(0 == ~E_1~0); 2567#L916-1 assume !(0 == ~E_2~0); 2568#L921-1 assume !(0 == ~E_3~0); 2861#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2960#L931-1 assume !(0 == ~E_5~0); 3000#L936-1 assume !(0 == ~E_6~0); 3007#L941-1 assume !(0 == ~E_7~0); 2573#L946-1 assume !(0 == ~E_8~0); 2574#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2979#L430 assume !(1 == ~m_pc~0); 2432#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2060#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2061#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2674#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2684#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L449 assume 1 == ~t1_pc~0; 2846#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2245#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2019#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2020#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2780#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2629#L468 assume !(1 == ~t2_pc~0); 2044#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2043#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2532#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2439#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2062#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2063#L487 assume 1 == ~t3_pc~0; 2992#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2159#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2160#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2834#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2498#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2499#L506 assume !(1 == ~t4_pc~0); 2625#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2670#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2970#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2971#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2620#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2450#L525 assume 1 == ~t5_pc~0; 2385#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2104#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2577#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2578#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2301#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2302#L544 assume !(1 == ~t6_pc~0); 2451#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2452#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2796#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2086#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2087#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2936#L563 assume 1 == ~t7_pc~0; 2814#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2114#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2115#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2526#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2246#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2247#L582 assume 1 == ~t8_pc~0; 2170#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2171#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2993#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2487#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2389#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2390#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 2848#L964-2 assume !(1 == ~T1_E~0); 2303#L969-1 assume !(1 == ~T2_E~0); 2304#L974-1 assume !(1 == ~T3_E~0); 2873#L979-1 assume !(1 == ~T4_E~0); 2874#L984-1 assume !(1 == ~T5_E~0); 2457#L989-1 assume !(1 == ~T6_E~0); 2458#L994-1 assume !(1 == ~T7_E~0); 2343#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2344#L1004-1 assume !(1 == ~E_M~0); 2088#L1009-1 assume !(1 == ~E_1~0); 2089#L1014-1 assume !(1 == ~E_2~0); 2332#L1019-1 assume !(1 == ~E_3~0); 2837#L1024-1 assume !(1 == ~E_4~0); 2265#L1029-1 assume !(1 == ~E_5~0); 2266#L1034-1 assume !(1 == ~E_6~0); 2360#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2974#L1044-1 assume !(1 == ~E_8~0); 2542#L1049-1 assume { :end_inline_reset_delta_events } true; 2235#L1315-2 [2022-02-21 04:22:08,775 INFO L793 eck$LassoCheckResult]: Loop: 2235#L1315-2 assume !false; 2236#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2022#L841 assume !false; 2361#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2296#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2297#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2137#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2057#L724 assume !(0 != eval_~tmp~0#1); 2059#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2887#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2068#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2069#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2364#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2365#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2378#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2379#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2602#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2603#L896-3 assume !(0 == ~T7_E~0); 2470#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2471#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2604#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2807#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2410#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2411#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2791#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2477#L936-3 assume !(0 == ~E_6~0); 2478#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2619#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2366#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2367#L430-30 assume 1 == ~m_pc~0; 2391#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2392#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2175#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2176#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2825#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2829#L449-30 assume 1 == ~t1_pc~0; 2394#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2084#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2085#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2456#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2168#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2169#L468-30 assume 1 == ~t2_pc~0; 2260#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2261#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2870#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2593#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2594#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2444#L487-30 assume 1 == ~t3_pc~0; 2425#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2240#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2571#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2572#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2844#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2518#L506-30 assume !(1 == ~t4_pc~0); 2519#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2545#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2546#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2563#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2445#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2446#L525-30 assume 1 == ~t5_pc~0; 2931#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2932#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2150#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2151#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2449#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2219#L544-30 assume 1 == ~t6_pc~0; 2027#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2028#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3001#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2941#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2942#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2918#L563-30 assume 1 == ~t7_pc~0; 2189#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2190#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2208#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2534#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2535#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2905#L582-30 assume 1 == ~t8_pc~0; 2867#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2287#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2522#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2935#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3008#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2093#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2094#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2231#L969-3 assume !(1 == ~T2_E~0); 2222#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2634#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2635#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2268#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2269#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2778#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2140#L1009-3 assume !(1 == ~E_1~0); 2141#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2615#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2616#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2597#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2564#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2565#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2836#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2258#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2259#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2388#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2725#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2292#L1334 assume !(0 == start_simulation_~tmp~3#1); 2294#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2312#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2023#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2024#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2618#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2962#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2797#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2798#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2235#L1315-2 [2022-02-21 04:22:08,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:08,777 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2022-02-21 04:22:08,777 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:08,778 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351824510] [2022-02-21 04:22:08,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:08,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:08,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:08,841 INFO L290 TraceCheckUtils]: 0: Hoare triple {5016#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {5016#true} is VALID [2022-02-21 04:22:08,841 INFO L290 TraceCheckUtils]: 1: Hoare triple {5016#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {5018#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:08,842 INFO L290 TraceCheckUtils]: 2: Hoare triple {5018#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {5018#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:08,842 INFO L290 TraceCheckUtils]: 3: Hoare triple {5018#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {5018#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:08,842 INFO L290 TraceCheckUtils]: 4: Hoare triple {5018#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {5018#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:08,843 INFO L290 TraceCheckUtils]: 5: Hoare triple {5018#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5018#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:08,843 INFO L290 TraceCheckUtils]: 6: Hoare triple {5018#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,843 INFO L290 TraceCheckUtils]: 7: Hoare triple {5017#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,843 INFO L290 TraceCheckUtils]: 8: Hoare triple {5017#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,843 INFO L290 TraceCheckUtils]: 9: Hoare triple {5017#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,843 INFO L290 TraceCheckUtils]: 10: Hoare triple {5017#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,844 INFO L290 TraceCheckUtils]: 11: Hoare triple {5017#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,844 INFO L290 TraceCheckUtils]: 12: Hoare triple {5017#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,844 INFO L290 TraceCheckUtils]: 13: Hoare triple {5017#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {5017#false} is VALID [2022-02-21 04:22:08,844 INFO L290 TraceCheckUtils]: 14: Hoare triple {5017#false} assume !(0 == ~M_E~0); {5017#false} is VALID [2022-02-21 04:22:08,844 INFO L290 TraceCheckUtils]: 15: Hoare triple {5017#false} assume !(0 == ~T1_E~0); {5017#false} is VALID [2022-02-21 04:22:08,844 INFO L290 TraceCheckUtils]: 16: Hoare triple {5017#false} assume !(0 == ~T2_E~0); {5017#false} is VALID [2022-02-21 04:22:08,844 INFO L290 TraceCheckUtils]: 17: Hoare triple {5017#false} assume !(0 == ~T3_E~0); {5017#false} is VALID [2022-02-21 04:22:08,845 INFO L290 TraceCheckUtils]: 18: Hoare triple {5017#false} assume !(0 == ~T4_E~0); {5017#false} is VALID [2022-02-21 04:22:08,845 INFO L290 TraceCheckUtils]: 19: Hoare triple {5017#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {5017#false} is VALID [2022-02-21 04:22:08,845 INFO L290 TraceCheckUtils]: 20: Hoare triple {5017#false} assume !(0 == ~T6_E~0); {5017#false} is VALID [2022-02-21 04:22:08,845 INFO L290 TraceCheckUtils]: 21: Hoare triple {5017#false} assume !(0 == ~T7_E~0); {5017#false} is VALID [2022-02-21 04:22:08,845 INFO L290 TraceCheckUtils]: 22: Hoare triple {5017#false} assume !(0 == ~T8_E~0); {5017#false} is VALID [2022-02-21 04:22:08,845 INFO L290 TraceCheckUtils]: 23: Hoare triple {5017#false} assume !(0 == ~E_M~0); {5017#false} is VALID [2022-02-21 04:22:08,845 INFO L290 TraceCheckUtils]: 24: Hoare triple {5017#false} assume !(0 == ~E_1~0); {5017#false} is VALID [2022-02-21 04:22:08,846 INFO L290 TraceCheckUtils]: 25: Hoare triple {5017#false} assume !(0 == ~E_2~0); {5017#false} is VALID [2022-02-21 04:22:08,846 INFO L290 TraceCheckUtils]: 26: Hoare triple {5017#false} assume !(0 == ~E_3~0); {5017#false} is VALID [2022-02-21 04:22:08,846 INFO L290 TraceCheckUtils]: 27: Hoare triple {5017#false} assume 0 == ~E_4~0;~E_4~0 := 1; {5017#false} is VALID [2022-02-21 04:22:08,846 INFO L290 TraceCheckUtils]: 28: Hoare triple {5017#false} assume !(0 == ~E_5~0); {5017#false} is VALID [2022-02-21 04:22:08,846 INFO L290 TraceCheckUtils]: 29: Hoare triple {5017#false} assume !(0 == ~E_6~0); {5017#false} is VALID [2022-02-21 04:22:08,846 INFO L290 TraceCheckUtils]: 30: Hoare triple {5017#false} assume !(0 == ~E_7~0); {5017#false} is VALID [2022-02-21 04:22:08,846 INFO L290 TraceCheckUtils]: 31: Hoare triple {5017#false} assume !(0 == ~E_8~0); {5017#false} is VALID [2022-02-21 04:22:08,847 INFO L290 TraceCheckUtils]: 32: Hoare triple {5017#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5017#false} is VALID [2022-02-21 04:22:08,847 INFO L290 TraceCheckUtils]: 33: Hoare triple {5017#false} assume !(1 == ~m_pc~0); {5017#false} is VALID [2022-02-21 04:22:08,847 INFO L290 TraceCheckUtils]: 34: Hoare triple {5017#false} is_master_triggered_~__retres1~0#1 := 0; {5017#false} is VALID [2022-02-21 04:22:08,847 INFO L290 TraceCheckUtils]: 35: Hoare triple {5017#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5017#false} is VALID [2022-02-21 04:22:08,847 INFO L290 TraceCheckUtils]: 36: Hoare triple {5017#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5017#false} is VALID [2022-02-21 04:22:08,847 INFO L290 TraceCheckUtils]: 37: Hoare triple {5017#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5017#false} is VALID [2022-02-21 04:22:08,848 INFO L290 TraceCheckUtils]: 38: Hoare triple {5017#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5017#false} is VALID [2022-02-21 04:22:08,848 INFO L290 TraceCheckUtils]: 39: Hoare triple {5017#false} assume 1 == ~t1_pc~0; {5017#false} is VALID [2022-02-21 04:22:08,848 INFO L290 TraceCheckUtils]: 40: Hoare triple {5017#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5017#false} is VALID [2022-02-21 04:22:08,848 INFO L290 TraceCheckUtils]: 41: Hoare triple {5017#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5017#false} is VALID [2022-02-21 04:22:08,848 INFO L290 TraceCheckUtils]: 42: Hoare triple {5017#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5017#false} is VALID [2022-02-21 04:22:08,848 INFO L290 TraceCheckUtils]: 43: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___0~0#1); {5017#false} is VALID [2022-02-21 04:22:08,848 INFO L290 TraceCheckUtils]: 44: Hoare triple {5017#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5017#false} is VALID [2022-02-21 04:22:08,849 INFO L290 TraceCheckUtils]: 45: Hoare triple {5017#false} assume !(1 == ~t2_pc~0); {5017#false} is VALID [2022-02-21 04:22:08,849 INFO L290 TraceCheckUtils]: 46: Hoare triple {5017#false} is_transmit2_triggered_~__retres1~2#1 := 0; {5017#false} is VALID [2022-02-21 04:22:08,849 INFO L290 TraceCheckUtils]: 47: Hoare triple {5017#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5017#false} is VALID [2022-02-21 04:22:08,849 INFO L290 TraceCheckUtils]: 48: Hoare triple {5017#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5017#false} is VALID [2022-02-21 04:22:08,849 INFO L290 TraceCheckUtils]: 49: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___1~0#1); {5017#false} is VALID [2022-02-21 04:22:08,849 INFO L290 TraceCheckUtils]: 50: Hoare triple {5017#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5017#false} is VALID [2022-02-21 04:22:08,849 INFO L290 TraceCheckUtils]: 51: Hoare triple {5017#false} assume 1 == ~t3_pc~0; {5017#false} is VALID [2022-02-21 04:22:08,850 INFO L290 TraceCheckUtils]: 52: Hoare triple {5017#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5017#false} is VALID [2022-02-21 04:22:08,850 INFO L290 TraceCheckUtils]: 53: Hoare triple {5017#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5017#false} is VALID [2022-02-21 04:22:08,850 INFO L290 TraceCheckUtils]: 54: Hoare triple {5017#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {5017#false} is VALID [2022-02-21 04:22:08,850 INFO L290 TraceCheckUtils]: 55: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___2~0#1); {5017#false} is VALID [2022-02-21 04:22:08,850 INFO L290 TraceCheckUtils]: 56: Hoare triple {5017#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5017#false} is VALID [2022-02-21 04:22:08,850 INFO L290 TraceCheckUtils]: 57: Hoare triple {5017#false} assume !(1 == ~t4_pc~0); {5017#false} is VALID [2022-02-21 04:22:08,850 INFO L290 TraceCheckUtils]: 58: Hoare triple {5017#false} is_transmit4_triggered_~__retres1~4#1 := 0; {5017#false} is VALID [2022-02-21 04:22:08,851 INFO L290 TraceCheckUtils]: 59: Hoare triple {5017#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5017#false} is VALID [2022-02-21 04:22:08,851 INFO L290 TraceCheckUtils]: 60: Hoare triple {5017#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {5017#false} is VALID [2022-02-21 04:22:08,851 INFO L290 TraceCheckUtils]: 61: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___3~0#1); {5017#false} is VALID [2022-02-21 04:22:08,851 INFO L290 TraceCheckUtils]: 62: Hoare triple {5017#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5017#false} is VALID [2022-02-21 04:22:08,851 INFO L290 TraceCheckUtils]: 63: Hoare triple {5017#false} assume 1 == ~t5_pc~0; {5017#false} is VALID [2022-02-21 04:22:08,851 INFO L290 TraceCheckUtils]: 64: Hoare triple {5017#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {5017#false} is VALID [2022-02-21 04:22:08,851 INFO L290 TraceCheckUtils]: 65: Hoare triple {5017#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5017#false} is VALID [2022-02-21 04:22:08,852 INFO L290 TraceCheckUtils]: 66: Hoare triple {5017#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {5017#false} is VALID [2022-02-21 04:22:08,852 INFO L290 TraceCheckUtils]: 67: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___4~0#1); {5017#false} is VALID [2022-02-21 04:22:08,852 INFO L290 TraceCheckUtils]: 68: Hoare triple {5017#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5017#false} is VALID [2022-02-21 04:22:08,852 INFO L290 TraceCheckUtils]: 69: Hoare triple {5017#false} assume !(1 == ~t6_pc~0); {5017#false} is VALID [2022-02-21 04:22:08,852 INFO L290 TraceCheckUtils]: 70: Hoare triple {5017#false} is_transmit6_triggered_~__retres1~6#1 := 0; {5017#false} is VALID [2022-02-21 04:22:08,852 INFO L290 TraceCheckUtils]: 71: Hoare triple {5017#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5017#false} is VALID [2022-02-21 04:22:08,852 INFO L290 TraceCheckUtils]: 72: Hoare triple {5017#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {5017#false} is VALID [2022-02-21 04:22:08,853 INFO L290 TraceCheckUtils]: 73: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___5~0#1); {5017#false} is VALID [2022-02-21 04:22:08,853 INFO L290 TraceCheckUtils]: 74: Hoare triple {5017#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {5017#false} is VALID [2022-02-21 04:22:08,853 INFO L290 TraceCheckUtils]: 75: Hoare triple {5017#false} assume 1 == ~t7_pc~0; {5017#false} is VALID [2022-02-21 04:22:08,853 INFO L290 TraceCheckUtils]: 76: Hoare triple {5017#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {5017#false} is VALID [2022-02-21 04:22:08,853 INFO L290 TraceCheckUtils]: 77: Hoare triple {5017#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {5017#false} is VALID [2022-02-21 04:22:08,853 INFO L290 TraceCheckUtils]: 78: Hoare triple {5017#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {5017#false} is VALID [2022-02-21 04:22:08,853 INFO L290 TraceCheckUtils]: 79: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___6~0#1); {5017#false} is VALID [2022-02-21 04:22:08,854 INFO L290 TraceCheckUtils]: 80: Hoare triple {5017#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {5017#false} is VALID [2022-02-21 04:22:08,854 INFO L290 TraceCheckUtils]: 81: Hoare triple {5017#false} assume 1 == ~t8_pc~0; {5017#false} is VALID [2022-02-21 04:22:08,854 INFO L290 TraceCheckUtils]: 82: Hoare triple {5017#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {5017#false} is VALID [2022-02-21 04:22:08,854 INFO L290 TraceCheckUtils]: 83: Hoare triple {5017#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {5017#false} is VALID [2022-02-21 04:22:08,854 INFO L290 TraceCheckUtils]: 84: Hoare triple {5017#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {5017#false} is VALID [2022-02-21 04:22:08,854 INFO L290 TraceCheckUtils]: 85: Hoare triple {5017#false} assume !(0 != activate_threads_~tmp___7~0#1); {5017#false} is VALID [2022-02-21 04:22:08,855 INFO L290 TraceCheckUtils]: 86: Hoare triple {5017#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5017#false} is VALID [2022-02-21 04:22:08,855 INFO L290 TraceCheckUtils]: 87: Hoare triple {5017#false} assume 1 == ~M_E~0;~M_E~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,855 INFO L290 TraceCheckUtils]: 88: Hoare triple {5017#false} assume !(1 == ~T1_E~0); {5017#false} is VALID [2022-02-21 04:22:08,855 INFO L290 TraceCheckUtils]: 89: Hoare triple {5017#false} assume !(1 == ~T2_E~0); {5017#false} is VALID [2022-02-21 04:22:08,855 INFO L290 TraceCheckUtils]: 90: Hoare triple {5017#false} assume !(1 == ~T3_E~0); {5017#false} is VALID [2022-02-21 04:22:08,855 INFO L290 TraceCheckUtils]: 91: Hoare triple {5017#false} assume !(1 == ~T4_E~0); {5017#false} is VALID [2022-02-21 04:22:08,855 INFO L290 TraceCheckUtils]: 92: Hoare triple {5017#false} assume !(1 == ~T5_E~0); {5017#false} is VALID [2022-02-21 04:22:08,856 INFO L290 TraceCheckUtils]: 93: Hoare triple {5017#false} assume !(1 == ~T6_E~0); {5017#false} is VALID [2022-02-21 04:22:08,856 INFO L290 TraceCheckUtils]: 94: Hoare triple {5017#false} assume !(1 == ~T7_E~0); {5017#false} is VALID [2022-02-21 04:22:08,856 INFO L290 TraceCheckUtils]: 95: Hoare triple {5017#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,856 INFO L290 TraceCheckUtils]: 96: Hoare triple {5017#false} assume !(1 == ~E_M~0); {5017#false} is VALID [2022-02-21 04:22:08,856 INFO L290 TraceCheckUtils]: 97: Hoare triple {5017#false} assume !(1 == ~E_1~0); {5017#false} is VALID [2022-02-21 04:22:08,856 INFO L290 TraceCheckUtils]: 98: Hoare triple {5017#false} assume !(1 == ~E_2~0); {5017#false} is VALID [2022-02-21 04:22:08,856 INFO L290 TraceCheckUtils]: 99: Hoare triple {5017#false} assume !(1 == ~E_3~0); {5017#false} is VALID [2022-02-21 04:22:08,857 INFO L290 TraceCheckUtils]: 100: Hoare triple {5017#false} assume !(1 == ~E_4~0); {5017#false} is VALID [2022-02-21 04:22:08,857 INFO L290 TraceCheckUtils]: 101: Hoare triple {5017#false} assume !(1 == ~E_5~0); {5017#false} is VALID [2022-02-21 04:22:08,857 INFO L290 TraceCheckUtils]: 102: Hoare triple {5017#false} assume !(1 == ~E_6~0); {5017#false} is VALID [2022-02-21 04:22:08,857 INFO L290 TraceCheckUtils]: 103: Hoare triple {5017#false} assume 1 == ~E_7~0;~E_7~0 := 2; {5017#false} is VALID [2022-02-21 04:22:08,857 INFO L290 TraceCheckUtils]: 104: Hoare triple {5017#false} assume !(1 == ~E_8~0); {5017#false} is VALID [2022-02-21 04:22:08,857 INFO L290 TraceCheckUtils]: 105: Hoare triple {5017#false} assume { :end_inline_reset_delta_events } true; {5017#false} is VALID [2022-02-21 04:22:08,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:08,858 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:08,858 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351824510] [2022-02-21 04:22:08,858 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351824510] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:08,858 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:08,859 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:08,859 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884658723] [2022-02-21 04:22:08,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:08,859 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:08,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:08,860 INFO L85 PathProgramCache]: Analyzing trace with hash 1016404398, now seen corresponding path program 1 times [2022-02-21 04:22:08,860 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:08,860 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839878935] [2022-02-21 04:22:08,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:08,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:08,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:08,922 INFO L290 TraceCheckUtils]: 0: Hoare triple {5019#true} assume !false; {5019#true} is VALID [2022-02-21 04:22:08,922 INFO L290 TraceCheckUtils]: 1: Hoare triple {5019#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5019#true} is VALID [2022-02-21 04:22:08,923 INFO L290 TraceCheckUtils]: 2: Hoare triple {5019#true} assume !false; {5019#true} is VALID [2022-02-21 04:22:08,923 INFO L290 TraceCheckUtils]: 3: Hoare triple {5019#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {5019#true} is VALID [2022-02-21 04:22:08,923 INFO L290 TraceCheckUtils]: 4: Hoare triple {5019#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {5019#true} is VALID [2022-02-21 04:22:08,923 INFO L290 TraceCheckUtils]: 5: Hoare triple {5019#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {5019#true} is VALID [2022-02-21 04:22:08,923 INFO L290 TraceCheckUtils]: 6: Hoare triple {5019#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {5019#true} is VALID [2022-02-21 04:22:08,923 INFO L290 TraceCheckUtils]: 7: Hoare triple {5019#true} assume !(0 != eval_~tmp~0#1); {5019#true} is VALID [2022-02-21 04:22:08,923 INFO L290 TraceCheckUtils]: 8: Hoare triple {5019#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5019#true} is VALID [2022-02-21 04:22:08,924 INFO L290 TraceCheckUtils]: 9: Hoare triple {5019#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5019#true} is VALID [2022-02-21 04:22:08,924 INFO L290 TraceCheckUtils]: 10: Hoare triple {5019#true} assume 0 == ~M_E~0;~M_E~0 := 1; {5019#true} is VALID [2022-02-21 04:22:08,924 INFO L290 TraceCheckUtils]: 11: Hoare triple {5019#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5019#true} is VALID [2022-02-21 04:22:08,924 INFO L290 TraceCheckUtils]: 12: Hoare triple {5019#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,925 INFO L290 TraceCheckUtils]: 13: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,925 INFO L290 TraceCheckUtils]: 14: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,925 INFO L290 TraceCheckUtils]: 15: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,925 INFO L290 TraceCheckUtils]: 16: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,926 INFO L290 TraceCheckUtils]: 17: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,926 INFO L290 TraceCheckUtils]: 18: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,926 INFO L290 TraceCheckUtils]: 19: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,927 INFO L290 TraceCheckUtils]: 20: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,927 INFO L290 TraceCheckUtils]: 21: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,927 INFO L290 TraceCheckUtils]: 22: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,928 INFO L290 TraceCheckUtils]: 23: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,928 INFO L290 TraceCheckUtils]: 24: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,928 INFO L290 TraceCheckUtils]: 25: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,928 INFO L290 TraceCheckUtils]: 26: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,929 INFO L290 TraceCheckUtils]: 27: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,929 INFO L290 TraceCheckUtils]: 28: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,929 INFO L290 TraceCheckUtils]: 29: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,930 INFO L290 TraceCheckUtils]: 30: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,930 INFO L290 TraceCheckUtils]: 31: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,930 INFO L290 TraceCheckUtils]: 32: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,931 INFO L290 TraceCheckUtils]: 33: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,931 INFO L290 TraceCheckUtils]: 34: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,931 INFO L290 TraceCheckUtils]: 35: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,932 INFO L290 TraceCheckUtils]: 36: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,932 INFO L290 TraceCheckUtils]: 37: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,932 INFO L290 TraceCheckUtils]: 38: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,932 INFO L290 TraceCheckUtils]: 39: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,933 INFO L290 TraceCheckUtils]: 40: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,933 INFO L290 TraceCheckUtils]: 41: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,933 INFO L290 TraceCheckUtils]: 42: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,934 INFO L290 TraceCheckUtils]: 43: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,934 INFO L290 TraceCheckUtils]: 44: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,934 INFO L290 TraceCheckUtils]: 45: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,935 INFO L290 TraceCheckUtils]: 46: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,935 INFO L290 TraceCheckUtils]: 47: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,935 INFO L290 TraceCheckUtils]: 48: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,936 INFO L290 TraceCheckUtils]: 49: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,936 INFO L290 TraceCheckUtils]: 50: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,936 INFO L290 TraceCheckUtils]: 51: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,937 INFO L290 TraceCheckUtils]: 52: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,937 INFO L290 TraceCheckUtils]: 53: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,937 INFO L290 TraceCheckUtils]: 54: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,938 INFO L290 TraceCheckUtils]: 55: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,938 INFO L290 TraceCheckUtils]: 56: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,938 INFO L290 TraceCheckUtils]: 57: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,938 INFO L290 TraceCheckUtils]: 58: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,939 INFO L290 TraceCheckUtils]: 59: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,939 INFO L290 TraceCheckUtils]: 60: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,939 INFO L290 TraceCheckUtils]: 61: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,940 INFO L290 TraceCheckUtils]: 62: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,940 INFO L290 TraceCheckUtils]: 63: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,940 INFO L290 TraceCheckUtils]: 64: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,941 INFO L290 TraceCheckUtils]: 65: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,941 INFO L290 TraceCheckUtils]: 66: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,941 INFO L290 TraceCheckUtils]: 67: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,941 INFO L290 TraceCheckUtils]: 68: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,942 INFO L290 TraceCheckUtils]: 69: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,942 INFO L290 TraceCheckUtils]: 70: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,942 INFO L290 TraceCheckUtils]: 71: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,943 INFO L290 TraceCheckUtils]: 72: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,943 INFO L290 TraceCheckUtils]: 73: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,943 INFO L290 TraceCheckUtils]: 74: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,944 INFO L290 TraceCheckUtils]: 75: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,944 INFO L290 TraceCheckUtils]: 76: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,944 INFO L290 TraceCheckUtils]: 77: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,944 INFO L290 TraceCheckUtils]: 78: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,945 INFO L290 TraceCheckUtils]: 79: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,945 INFO L290 TraceCheckUtils]: 80: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,945 INFO L290 TraceCheckUtils]: 81: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,946 INFO L290 TraceCheckUtils]: 82: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,946 INFO L290 TraceCheckUtils]: 83: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,946 INFO L290 TraceCheckUtils]: 84: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5021#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:08,947 INFO L290 TraceCheckUtils]: 85: Hoare triple {5021#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {5020#false} is VALID [2022-02-21 04:22:08,947 INFO L290 TraceCheckUtils]: 86: Hoare triple {5020#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,947 INFO L290 TraceCheckUtils]: 87: Hoare triple {5020#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,947 INFO L290 TraceCheckUtils]: 88: Hoare triple {5020#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,947 INFO L290 TraceCheckUtils]: 89: Hoare triple {5020#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,947 INFO L290 TraceCheckUtils]: 90: Hoare triple {5020#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 91: Hoare triple {5020#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 92: Hoare triple {5020#false} assume 1 == ~E_M~0;~E_M~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 93: Hoare triple {5020#false} assume !(1 == ~E_1~0); {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 94: Hoare triple {5020#false} assume 1 == ~E_2~0;~E_2~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 95: Hoare triple {5020#false} assume 1 == ~E_3~0;~E_3~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 96: Hoare triple {5020#false} assume 1 == ~E_4~0;~E_4~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 97: Hoare triple {5020#false} assume 1 == ~E_5~0;~E_5~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,948 INFO L290 TraceCheckUtils]: 98: Hoare triple {5020#false} assume 1 == ~E_6~0;~E_6~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,949 INFO L290 TraceCheckUtils]: 99: Hoare triple {5020#false} assume 1 == ~E_7~0;~E_7~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,949 INFO L290 TraceCheckUtils]: 100: Hoare triple {5020#false} assume 1 == ~E_8~0;~E_8~0 := 2; {5020#false} is VALID [2022-02-21 04:22:08,949 INFO L290 TraceCheckUtils]: 101: Hoare triple {5020#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {5020#false} is VALID [2022-02-21 04:22:08,949 INFO L290 TraceCheckUtils]: 102: Hoare triple {5020#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {5020#false} is VALID [2022-02-21 04:22:08,949 INFO L290 TraceCheckUtils]: 103: Hoare triple {5020#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {5020#false} is VALID [2022-02-21 04:22:08,949 INFO L290 TraceCheckUtils]: 104: Hoare triple {5020#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {5020#false} is VALID [2022-02-21 04:22:08,949 INFO L290 TraceCheckUtils]: 105: Hoare triple {5020#false} assume !(0 == start_simulation_~tmp~3#1); {5020#false} is VALID [2022-02-21 04:22:08,950 INFO L290 TraceCheckUtils]: 106: Hoare triple {5020#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {5020#false} is VALID [2022-02-21 04:22:08,950 INFO L290 TraceCheckUtils]: 107: Hoare triple {5020#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {5020#false} is VALID [2022-02-21 04:22:08,950 INFO L290 TraceCheckUtils]: 108: Hoare triple {5020#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {5020#false} is VALID [2022-02-21 04:22:08,950 INFO L290 TraceCheckUtils]: 109: Hoare triple {5020#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {5020#false} is VALID [2022-02-21 04:22:08,950 INFO L290 TraceCheckUtils]: 110: Hoare triple {5020#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {5020#false} is VALID [2022-02-21 04:22:08,950 INFO L290 TraceCheckUtils]: 111: Hoare triple {5020#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5020#false} is VALID [2022-02-21 04:22:08,950 INFO L290 TraceCheckUtils]: 112: Hoare triple {5020#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {5020#false} is VALID [2022-02-21 04:22:08,951 INFO L290 TraceCheckUtils]: 113: Hoare triple {5020#false} assume !(0 != start_simulation_~tmp___0~1#1); {5020#false} is VALID [2022-02-21 04:22:08,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:08,952 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:08,952 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839878935] [2022-02-21 04:22:08,952 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839878935] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:08,952 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:08,952 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:08,952 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322434077] [2022-02-21 04:22:08,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:08,953 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:08,953 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:08,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:08,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:08,954 INFO L87 Difference]: Start difference. First operand 998 states and 1490 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,712 INFO L93 Difference]: Finished difference Result 998 states and 1489 transitions. [2022-02-21 04:22:09,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:09,712 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,771 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:09,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1489 transitions. [2022-02-21 04:22:09,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:09,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1489 transitions. [2022-02-21 04:22:09,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:09,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:09,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1489 transitions. [2022-02-21 04:22:09,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:09,830 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2022-02-21 04:22:09,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1489 transitions. [2022-02-21 04:22:09,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:09,842 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:09,844 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1489 transitions. Second operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,845 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1489 transitions. Second operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,847 INFO L87 Difference]: Start difference. First operand 998 states and 1489 transitions. Second operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,871 INFO L93 Difference]: Finished difference Result 998 states and 1489 transitions. [2022-02-21 04:22:09,872 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1489 transitions. [2022-02-21 04:22:09,873 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:09,873 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:09,874 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1489 transitions. [2022-02-21 04:22:09,876 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1489 transitions. [2022-02-21 04:22:09,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,901 INFO L93 Difference]: Finished difference Result 998 states and 1489 transitions. [2022-02-21 04:22:09,901 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1489 transitions. [2022-02-21 04:22:09,902 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:09,902 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:09,902 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:09,902 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:09,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1489 transitions. [2022-02-21 04:22:09,927 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2022-02-21 04:22:09,927 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2022-02-21 04:22:09,927 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:22:09,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1489 transitions. [2022-02-21 04:22:09,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:09,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:09,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:09,932 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:09,932 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:09,932 INFO L791 eck$LassoCheckResult]: Stem: 6790#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6717#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6718#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6570#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6571#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6156#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6157#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6238#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6949#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6126#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6127#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6534#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6559#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6242#L866 assume !(0 == ~M_E~0); 6243#L866-2 assume !(0 == ~T1_E~0); 6745#L871-1 assume !(0 == ~T2_E~0); 6746#L876-1 assume !(0 == ~T3_E~0); 6996#L881-1 assume !(0 == ~T4_E~0); 6755#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6525#L891-1 assume !(0 == ~T6_E~0); 6526#L896-1 assume !(0 == ~T7_E~0); 6748#L901-1 assume !(0 == ~T8_E~0); 6766#L906-1 assume !(0 == ~E_M~0); 6767#L911-1 assume !(0 == ~E_1~0); 6568#L916-1 assume !(0 == ~E_2~0); 6569#L921-1 assume !(0 == ~E_3~0); 6862#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6961#L931-1 assume !(0 == ~E_5~0); 7001#L936-1 assume !(0 == ~E_6~0); 7008#L941-1 assume !(0 == ~E_7~0); 6574#L946-1 assume !(0 == ~E_8~0); 6575#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6980#L430 assume !(1 == ~m_pc~0); 6433#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6061#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6062#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6675#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6685#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6846#L449 assume 1 == ~t1_pc~0; 6847#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6246#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6020#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6021#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6781#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6630#L468 assume !(1 == ~t2_pc~0); 6045#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6044#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6533#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6440#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6063#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6064#L487 assume 1 == ~t3_pc~0; 6993#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6160#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6161#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6835#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6499#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6500#L506 assume !(1 == ~t4_pc~0); 6626#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6671#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6971#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6972#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6621#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6451#L525 assume 1 == ~t5_pc~0; 6386#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6105#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6578#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6579#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6302#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6303#L544 assume !(1 == ~t6_pc~0); 6452#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6453#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6797#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6087#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6088#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6937#L563 assume 1 == ~t7_pc~0; 6815#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6115#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6116#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6527#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6247#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6248#L582 assume 1 == ~t8_pc~0; 6171#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6172#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6994#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6488#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6390#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6391#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 6849#L964-2 assume !(1 == ~T1_E~0); 6304#L969-1 assume !(1 == ~T2_E~0); 6305#L974-1 assume !(1 == ~T3_E~0); 6874#L979-1 assume !(1 == ~T4_E~0); 6875#L984-1 assume !(1 == ~T5_E~0); 6458#L989-1 assume !(1 == ~T6_E~0); 6459#L994-1 assume !(1 == ~T7_E~0); 6344#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6345#L1004-1 assume !(1 == ~E_M~0); 6089#L1009-1 assume !(1 == ~E_1~0); 6090#L1014-1 assume !(1 == ~E_2~0); 6333#L1019-1 assume !(1 == ~E_3~0); 6838#L1024-1 assume !(1 == ~E_4~0); 6266#L1029-1 assume !(1 == ~E_5~0); 6267#L1034-1 assume !(1 == ~E_6~0); 6361#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6975#L1044-1 assume !(1 == ~E_8~0); 6543#L1049-1 assume { :end_inline_reset_delta_events } true; 6236#L1315-2 [2022-02-21 04:22:09,932 INFO L793 eck$LassoCheckResult]: Loop: 6236#L1315-2 assume !false; 6237#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6023#L841 assume !false; 6362#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6297#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6298#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6138#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6058#L724 assume !(0 != eval_~tmp~0#1); 6060#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6888#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6069#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6070#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6365#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6366#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6379#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6380#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6603#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6604#L896-3 assume !(0 == ~T7_E~0); 6471#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6472#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6605#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6808#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6411#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6412#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6792#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6478#L936-3 assume !(0 == ~E_6~0); 6479#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6620#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6367#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6368#L430-30 assume 1 == ~m_pc~0; 6392#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6393#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6176#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6177#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6826#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6830#L449-30 assume 1 == ~t1_pc~0; 6395#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6085#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6086#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6457#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6169#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6170#L468-30 assume 1 == ~t2_pc~0; 6261#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6262#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6871#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6594#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6595#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6445#L487-30 assume !(1 == ~t3_pc~0); 6240#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6241#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6572#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6573#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6845#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6519#L506-30 assume !(1 == ~t4_pc~0); 6520#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 6546#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6547#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6564#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 6446#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6447#L525-30 assume 1 == ~t5_pc~0; 6932#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6933#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6151#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6152#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6450#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6220#L544-30 assume 1 == ~t6_pc~0; 6028#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6029#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7002#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6942#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6943#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6919#L563-30 assume !(1 == ~t7_pc~0); 6192#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 6191#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6209#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6535#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6536#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6906#L582-30 assume 1 == ~t8_pc~0; 6868#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6288#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6523#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6936#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7009#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6094#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6095#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6232#L969-3 assume !(1 == ~T2_E~0); 6223#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6224#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6635#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6636#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6269#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6270#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6779#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6141#L1009-3 assume !(1 == ~E_1~0); 6142#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6616#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6617#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6598#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6565#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6566#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6837#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6259#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6260#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6389#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6726#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6293#L1334 assume !(0 == start_simulation_~tmp~3#1); 6295#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6313#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6024#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6025#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6619#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6963#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6798#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6799#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 6236#L1315-2 [2022-02-21 04:22:09,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:09,933 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2022-02-21 04:22:09,933 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:09,933 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340893543] [2022-02-21 04:22:09,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:09,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:09,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:09,965 INFO L290 TraceCheckUtils]: 0: Hoare triple {9017#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {9017#true} is VALID [2022-02-21 04:22:09,965 INFO L290 TraceCheckUtils]: 1: Hoare triple {9017#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {9019#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:09,965 INFO L290 TraceCheckUtils]: 2: Hoare triple {9019#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {9019#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:09,966 INFO L290 TraceCheckUtils]: 3: Hoare triple {9019#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {9019#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:09,966 INFO L290 TraceCheckUtils]: 4: Hoare triple {9019#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {9019#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:09,966 INFO L290 TraceCheckUtils]: 5: Hoare triple {9019#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {9019#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:09,966 INFO L290 TraceCheckUtils]: 6: Hoare triple {9019#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {9019#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:09,967 INFO L290 TraceCheckUtils]: 7: Hoare triple {9019#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,967 INFO L290 TraceCheckUtils]: 8: Hoare triple {9018#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,967 INFO L290 TraceCheckUtils]: 9: Hoare triple {9018#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,967 INFO L290 TraceCheckUtils]: 10: Hoare triple {9018#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,967 INFO L290 TraceCheckUtils]: 11: Hoare triple {9018#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,967 INFO L290 TraceCheckUtils]: 12: Hoare triple {9018#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,967 INFO L290 TraceCheckUtils]: 13: Hoare triple {9018#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 14: Hoare triple {9018#false} assume !(0 == ~M_E~0); {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 15: Hoare triple {9018#false} assume !(0 == ~T1_E~0); {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 16: Hoare triple {9018#false} assume !(0 == ~T2_E~0); {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 17: Hoare triple {9018#false} assume !(0 == ~T3_E~0); {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 18: Hoare triple {9018#false} assume !(0 == ~T4_E~0); {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 19: Hoare triple {9018#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 20: Hoare triple {9018#false} assume !(0 == ~T6_E~0); {9018#false} is VALID [2022-02-21 04:22:09,968 INFO L290 TraceCheckUtils]: 21: Hoare triple {9018#false} assume !(0 == ~T7_E~0); {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 22: Hoare triple {9018#false} assume !(0 == ~T8_E~0); {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 23: Hoare triple {9018#false} assume !(0 == ~E_M~0); {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 24: Hoare triple {9018#false} assume !(0 == ~E_1~0); {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 25: Hoare triple {9018#false} assume !(0 == ~E_2~0); {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 26: Hoare triple {9018#false} assume !(0 == ~E_3~0); {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 27: Hoare triple {9018#false} assume 0 == ~E_4~0;~E_4~0 := 1; {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 28: Hoare triple {9018#false} assume !(0 == ~E_5~0); {9018#false} is VALID [2022-02-21 04:22:09,969 INFO L290 TraceCheckUtils]: 29: Hoare triple {9018#false} assume !(0 == ~E_6~0); {9018#false} is VALID [2022-02-21 04:22:09,970 INFO L290 TraceCheckUtils]: 30: Hoare triple {9018#false} assume !(0 == ~E_7~0); {9018#false} is VALID [2022-02-21 04:22:09,970 INFO L290 TraceCheckUtils]: 31: Hoare triple {9018#false} assume !(0 == ~E_8~0); {9018#false} is VALID [2022-02-21 04:22:09,970 INFO L290 TraceCheckUtils]: 32: Hoare triple {9018#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9018#false} is VALID [2022-02-21 04:22:09,970 INFO L290 TraceCheckUtils]: 33: Hoare triple {9018#false} assume !(1 == ~m_pc~0); {9018#false} is VALID [2022-02-21 04:22:09,970 INFO L290 TraceCheckUtils]: 34: Hoare triple {9018#false} is_master_triggered_~__retres1~0#1 := 0; {9018#false} is VALID [2022-02-21 04:22:09,970 INFO L290 TraceCheckUtils]: 35: Hoare triple {9018#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9018#false} is VALID [2022-02-21 04:22:09,970 INFO L290 TraceCheckUtils]: 36: Hoare triple {9018#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 37: Hoare triple {9018#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 38: Hoare triple {9018#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 39: Hoare triple {9018#false} assume 1 == ~t1_pc~0; {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 40: Hoare triple {9018#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 41: Hoare triple {9018#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 42: Hoare triple {9018#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 43: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___0~0#1); {9018#false} is VALID [2022-02-21 04:22:09,971 INFO L290 TraceCheckUtils]: 44: Hoare triple {9018#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 45: Hoare triple {9018#false} assume !(1 == ~t2_pc~0); {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 46: Hoare triple {9018#false} is_transmit2_triggered_~__retres1~2#1 := 0; {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 47: Hoare triple {9018#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 48: Hoare triple {9018#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 49: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___1~0#1); {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 50: Hoare triple {9018#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 51: Hoare triple {9018#false} assume 1 == ~t3_pc~0; {9018#false} is VALID [2022-02-21 04:22:09,972 INFO L290 TraceCheckUtils]: 52: Hoare triple {9018#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 53: Hoare triple {9018#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 54: Hoare triple {9018#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 55: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___2~0#1); {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 56: Hoare triple {9018#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 57: Hoare triple {9018#false} assume !(1 == ~t4_pc~0); {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 58: Hoare triple {9018#false} is_transmit4_triggered_~__retres1~4#1 := 0; {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 59: Hoare triple {9018#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9018#false} is VALID [2022-02-21 04:22:09,973 INFO L290 TraceCheckUtils]: 60: Hoare triple {9018#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 61: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___3~0#1); {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 62: Hoare triple {9018#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 63: Hoare triple {9018#false} assume 1 == ~t5_pc~0; {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 64: Hoare triple {9018#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 65: Hoare triple {9018#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 66: Hoare triple {9018#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 67: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___4~0#1); {9018#false} is VALID [2022-02-21 04:22:09,974 INFO L290 TraceCheckUtils]: 68: Hoare triple {9018#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9018#false} is VALID [2022-02-21 04:22:09,975 INFO L290 TraceCheckUtils]: 69: Hoare triple {9018#false} assume !(1 == ~t6_pc~0); {9018#false} is VALID [2022-02-21 04:22:09,975 INFO L290 TraceCheckUtils]: 70: Hoare triple {9018#false} is_transmit6_triggered_~__retres1~6#1 := 0; {9018#false} is VALID [2022-02-21 04:22:09,975 INFO L290 TraceCheckUtils]: 71: Hoare triple {9018#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9018#false} is VALID [2022-02-21 04:22:09,975 INFO L290 TraceCheckUtils]: 72: Hoare triple {9018#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9018#false} is VALID [2022-02-21 04:22:09,980 INFO L290 TraceCheckUtils]: 73: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___5~0#1); {9018#false} is VALID [2022-02-21 04:22:09,980 INFO L290 TraceCheckUtils]: 74: Hoare triple {9018#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9018#false} is VALID [2022-02-21 04:22:09,980 INFO L290 TraceCheckUtils]: 75: Hoare triple {9018#false} assume 1 == ~t7_pc~0; {9018#false} is VALID [2022-02-21 04:22:09,980 INFO L290 TraceCheckUtils]: 76: Hoare triple {9018#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 77: Hoare triple {9018#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 78: Hoare triple {9018#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 79: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___6~0#1); {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 80: Hoare triple {9018#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 81: Hoare triple {9018#false} assume 1 == ~t8_pc~0; {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 82: Hoare triple {9018#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 83: Hoare triple {9018#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9018#false} is VALID [2022-02-21 04:22:09,981 INFO L290 TraceCheckUtils]: 84: Hoare triple {9018#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 85: Hoare triple {9018#false} assume !(0 != activate_threads_~tmp___7~0#1); {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 86: Hoare triple {9018#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 87: Hoare triple {9018#false} assume 1 == ~M_E~0;~M_E~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 88: Hoare triple {9018#false} assume !(1 == ~T1_E~0); {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 89: Hoare triple {9018#false} assume !(1 == ~T2_E~0); {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 90: Hoare triple {9018#false} assume !(1 == ~T3_E~0); {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 91: Hoare triple {9018#false} assume !(1 == ~T4_E~0); {9018#false} is VALID [2022-02-21 04:22:09,982 INFO L290 TraceCheckUtils]: 92: Hoare triple {9018#false} assume !(1 == ~T5_E~0); {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 93: Hoare triple {9018#false} assume !(1 == ~T6_E~0); {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 94: Hoare triple {9018#false} assume !(1 == ~T7_E~0); {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 95: Hoare triple {9018#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 96: Hoare triple {9018#false} assume !(1 == ~E_M~0); {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 97: Hoare triple {9018#false} assume !(1 == ~E_1~0); {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 98: Hoare triple {9018#false} assume !(1 == ~E_2~0); {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 99: Hoare triple {9018#false} assume !(1 == ~E_3~0); {9018#false} is VALID [2022-02-21 04:22:09,983 INFO L290 TraceCheckUtils]: 100: Hoare triple {9018#false} assume !(1 == ~E_4~0); {9018#false} is VALID [2022-02-21 04:22:09,984 INFO L290 TraceCheckUtils]: 101: Hoare triple {9018#false} assume !(1 == ~E_5~0); {9018#false} is VALID [2022-02-21 04:22:09,984 INFO L290 TraceCheckUtils]: 102: Hoare triple {9018#false} assume !(1 == ~E_6~0); {9018#false} is VALID [2022-02-21 04:22:09,984 INFO L290 TraceCheckUtils]: 103: Hoare triple {9018#false} assume 1 == ~E_7~0;~E_7~0 := 2; {9018#false} is VALID [2022-02-21 04:22:09,984 INFO L290 TraceCheckUtils]: 104: Hoare triple {9018#false} assume !(1 == ~E_8~0); {9018#false} is VALID [2022-02-21 04:22:09,984 INFO L290 TraceCheckUtils]: 105: Hoare triple {9018#false} assume { :end_inline_reset_delta_events } true; {9018#false} is VALID [2022-02-21 04:22:09,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:09,985 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:09,985 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340893543] [2022-02-21 04:22:09,985 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340893543] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:09,985 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:09,985 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:09,985 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508731992] [2022-02-21 04:22:09,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:09,986 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:09,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:09,995 INFO L85 PathProgramCache]: Analyzing trace with hash 757461680, now seen corresponding path program 1 times [2022-02-21 04:22:09,996 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:09,996 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957595343] [2022-02-21 04:22:09,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:09,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:10,070 INFO L290 TraceCheckUtils]: 0: Hoare triple {9020#true} assume !false; {9020#true} is VALID [2022-02-21 04:22:10,070 INFO L290 TraceCheckUtils]: 1: Hoare triple {9020#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {9020#true} is VALID [2022-02-21 04:22:10,070 INFO L290 TraceCheckUtils]: 2: Hoare triple {9020#true} assume !false; {9020#true} is VALID [2022-02-21 04:22:10,071 INFO L290 TraceCheckUtils]: 3: Hoare triple {9020#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {9020#true} is VALID [2022-02-21 04:22:10,071 INFO L290 TraceCheckUtils]: 4: Hoare triple {9020#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {9020#true} is VALID [2022-02-21 04:22:10,071 INFO L290 TraceCheckUtils]: 5: Hoare triple {9020#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {9020#true} is VALID [2022-02-21 04:22:10,071 INFO L290 TraceCheckUtils]: 6: Hoare triple {9020#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {9020#true} is VALID [2022-02-21 04:22:10,071 INFO L290 TraceCheckUtils]: 7: Hoare triple {9020#true} assume !(0 != eval_~tmp~0#1); {9020#true} is VALID [2022-02-21 04:22:10,071 INFO L290 TraceCheckUtils]: 8: Hoare triple {9020#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {9020#true} is VALID [2022-02-21 04:22:10,071 INFO L290 TraceCheckUtils]: 9: Hoare triple {9020#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {9020#true} is VALID [2022-02-21 04:22:10,072 INFO L290 TraceCheckUtils]: 10: Hoare triple {9020#true} assume 0 == ~M_E~0;~M_E~0 := 1; {9020#true} is VALID [2022-02-21 04:22:10,072 INFO L290 TraceCheckUtils]: 11: Hoare triple {9020#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {9020#true} is VALID [2022-02-21 04:22:10,072 INFO L290 TraceCheckUtils]: 12: Hoare triple {9020#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,072 INFO L290 TraceCheckUtils]: 13: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,073 INFO L290 TraceCheckUtils]: 14: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,073 INFO L290 TraceCheckUtils]: 15: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,073 INFO L290 TraceCheckUtils]: 16: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,073 INFO L290 TraceCheckUtils]: 17: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,074 INFO L290 TraceCheckUtils]: 18: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,074 INFO L290 TraceCheckUtils]: 19: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,074 INFO L290 TraceCheckUtils]: 20: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,074 INFO L290 TraceCheckUtils]: 21: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,075 INFO L290 TraceCheckUtils]: 22: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,075 INFO L290 TraceCheckUtils]: 23: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,075 INFO L290 TraceCheckUtils]: 24: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,076 INFO L290 TraceCheckUtils]: 25: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,076 INFO L290 TraceCheckUtils]: 26: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,076 INFO L290 TraceCheckUtils]: 27: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,080 INFO L290 TraceCheckUtils]: 28: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,081 INFO L290 TraceCheckUtils]: 29: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,081 INFO L290 TraceCheckUtils]: 30: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,081 INFO L290 TraceCheckUtils]: 31: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,081 INFO L290 TraceCheckUtils]: 32: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,082 INFO L290 TraceCheckUtils]: 33: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,082 INFO L290 TraceCheckUtils]: 34: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,082 INFO L290 TraceCheckUtils]: 35: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,082 INFO L290 TraceCheckUtils]: 36: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,083 INFO L290 TraceCheckUtils]: 37: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,083 INFO L290 TraceCheckUtils]: 38: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,083 INFO L290 TraceCheckUtils]: 39: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,083 INFO L290 TraceCheckUtils]: 40: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,084 INFO L290 TraceCheckUtils]: 41: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,084 INFO L290 TraceCheckUtils]: 42: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,084 INFO L290 TraceCheckUtils]: 43: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,085 INFO L290 TraceCheckUtils]: 44: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,085 INFO L290 TraceCheckUtils]: 45: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,085 INFO L290 TraceCheckUtils]: 46: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,085 INFO L290 TraceCheckUtils]: 47: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,086 INFO L290 TraceCheckUtils]: 48: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,086 INFO L290 TraceCheckUtils]: 49: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,087 INFO L290 TraceCheckUtils]: 50: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,087 INFO L290 TraceCheckUtils]: 51: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,087 INFO L290 TraceCheckUtils]: 52: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,087 INFO L290 TraceCheckUtils]: 53: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,088 INFO L290 TraceCheckUtils]: 54: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,088 INFO L290 TraceCheckUtils]: 55: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,088 INFO L290 TraceCheckUtils]: 56: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,088 INFO L290 TraceCheckUtils]: 57: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,089 INFO L290 TraceCheckUtils]: 58: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,089 INFO L290 TraceCheckUtils]: 59: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,089 INFO L290 TraceCheckUtils]: 60: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,089 INFO L290 TraceCheckUtils]: 61: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,090 INFO L290 TraceCheckUtils]: 62: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,090 INFO L290 TraceCheckUtils]: 63: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,090 INFO L290 TraceCheckUtils]: 64: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,091 INFO L290 TraceCheckUtils]: 65: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,091 INFO L290 TraceCheckUtils]: 66: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,091 INFO L290 TraceCheckUtils]: 67: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,091 INFO L290 TraceCheckUtils]: 68: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,092 INFO L290 TraceCheckUtils]: 69: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,092 INFO L290 TraceCheckUtils]: 70: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,092 INFO L290 TraceCheckUtils]: 71: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,092 INFO L290 TraceCheckUtils]: 72: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,093 INFO L290 TraceCheckUtils]: 73: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,093 INFO L290 TraceCheckUtils]: 74: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,093 INFO L290 TraceCheckUtils]: 75: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,093 INFO L290 TraceCheckUtils]: 76: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,094 INFO L290 TraceCheckUtils]: 77: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,094 INFO L290 TraceCheckUtils]: 78: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,094 INFO L290 TraceCheckUtils]: 79: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,094 INFO L290 TraceCheckUtils]: 80: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,095 INFO L290 TraceCheckUtils]: 81: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,095 INFO L290 TraceCheckUtils]: 82: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,095 INFO L290 TraceCheckUtils]: 83: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,095 INFO L290 TraceCheckUtils]: 84: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {9022#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:10,096 INFO L290 TraceCheckUtils]: 85: Hoare triple {9022#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {9021#false} is VALID [2022-02-21 04:22:10,096 INFO L290 TraceCheckUtils]: 86: Hoare triple {9021#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,096 INFO L290 TraceCheckUtils]: 87: Hoare triple {9021#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,096 INFO L290 TraceCheckUtils]: 88: Hoare triple {9021#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,096 INFO L290 TraceCheckUtils]: 89: Hoare triple {9021#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,096 INFO L290 TraceCheckUtils]: 90: Hoare triple {9021#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,097 INFO L290 TraceCheckUtils]: 91: Hoare triple {9021#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,098 INFO L290 TraceCheckUtils]: 92: Hoare triple {9021#false} assume 1 == ~E_M~0;~E_M~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,098 INFO L290 TraceCheckUtils]: 93: Hoare triple {9021#false} assume !(1 == ~E_1~0); {9021#false} is VALID [2022-02-21 04:22:10,098 INFO L290 TraceCheckUtils]: 94: Hoare triple {9021#false} assume 1 == ~E_2~0;~E_2~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,098 INFO L290 TraceCheckUtils]: 95: Hoare triple {9021#false} assume 1 == ~E_3~0;~E_3~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,098 INFO L290 TraceCheckUtils]: 96: Hoare triple {9021#false} assume 1 == ~E_4~0;~E_4~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,098 INFO L290 TraceCheckUtils]: 97: Hoare triple {9021#false} assume 1 == ~E_5~0;~E_5~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 98: Hoare triple {9021#false} assume 1 == ~E_6~0;~E_6~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 99: Hoare triple {9021#false} assume 1 == ~E_7~0;~E_7~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 100: Hoare triple {9021#false} assume 1 == ~E_8~0;~E_8~0 := 2; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 101: Hoare triple {9021#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 102: Hoare triple {9021#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 103: Hoare triple {9021#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 104: Hoare triple {9021#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 105: Hoare triple {9021#false} assume !(0 == start_simulation_~tmp~3#1); {9021#false} is VALID [2022-02-21 04:22:10,099 INFO L290 TraceCheckUtils]: 106: Hoare triple {9021#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {9021#false} is VALID [2022-02-21 04:22:10,100 INFO L290 TraceCheckUtils]: 107: Hoare triple {9021#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {9021#false} is VALID [2022-02-21 04:22:10,100 INFO L290 TraceCheckUtils]: 108: Hoare triple {9021#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {9021#false} is VALID [2022-02-21 04:22:10,100 INFO L290 TraceCheckUtils]: 109: Hoare triple {9021#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {9021#false} is VALID [2022-02-21 04:22:10,100 INFO L290 TraceCheckUtils]: 110: Hoare triple {9021#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {9021#false} is VALID [2022-02-21 04:22:10,100 INFO L290 TraceCheckUtils]: 111: Hoare triple {9021#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {9021#false} is VALID [2022-02-21 04:22:10,100 INFO L290 TraceCheckUtils]: 112: Hoare triple {9021#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {9021#false} is VALID [2022-02-21 04:22:10,109 INFO L290 TraceCheckUtils]: 113: Hoare triple {9021#false} assume !(0 != start_simulation_~tmp___0~1#1); {9021#false} is VALID [2022-02-21 04:22:10,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:10,112 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:10,112 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957595343] [2022-02-21 04:22:10,113 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957595343] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:10,113 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:10,113 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:10,113 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711831003] [2022-02-21 04:22:10,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:10,114 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:10,114 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:10,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:10,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:10,115 INFO L87 Difference]: Start difference. First operand 998 states and 1489 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,816 INFO L93 Difference]: Finished difference Result 998 states and 1488 transitions. [2022-02-21 04:22:10,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:10,817 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,880 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:10,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1488 transitions. [2022-02-21 04:22:10,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:10,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1488 transitions. [2022-02-21 04:22:10,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:10,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:10,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1488 transitions. [2022-02-21 04:22:10,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:10,943 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2022-02-21 04:22:10,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1488 transitions. [2022-02-21 04:22:10,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:10,951 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:10,953 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1488 transitions. Second operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,955 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1488 transitions. Second operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,956 INFO L87 Difference]: Start difference. First operand 998 states and 1488 transitions. Second operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,988 INFO L93 Difference]: Finished difference Result 998 states and 1488 transitions. [2022-02-21 04:22:10,988 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1488 transitions. [2022-02-21 04:22:10,989 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:10,989 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:10,991 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1488 transitions. [2022-02-21 04:22:10,992 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1488 transitions. [2022-02-21 04:22:11,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:11,020 INFO L93 Difference]: Finished difference Result 998 states and 1488 transitions. [2022-02-21 04:22:11,020 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1488 transitions. [2022-02-21 04:22:11,021 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:11,021 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:11,021 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:11,021 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:11,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1488 transitions. [2022-02-21 04:22:11,049 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2022-02-21 04:22:11,049 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2022-02-21 04:22:11,049 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:22:11,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1488 transitions. [2022-02-21 04:22:11,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:11,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:11,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:11,057 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:11,057 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:11,058 INFO L791 eck$LassoCheckResult]: Stem: 10791#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10718#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10719#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10571#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10572#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10157#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10158#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10239#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10950#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10127#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10128#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10535#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10560#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10243#L866 assume !(0 == ~M_E~0); 10244#L866-2 assume !(0 == ~T1_E~0); 10746#L871-1 assume !(0 == ~T2_E~0); 10747#L876-1 assume !(0 == ~T3_E~0); 10997#L881-1 assume !(0 == ~T4_E~0); 10756#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10526#L891-1 assume !(0 == ~T6_E~0); 10527#L896-1 assume !(0 == ~T7_E~0); 10749#L901-1 assume !(0 == ~T8_E~0); 10767#L906-1 assume !(0 == ~E_M~0); 10768#L911-1 assume !(0 == ~E_1~0); 10569#L916-1 assume !(0 == ~E_2~0); 10570#L921-1 assume !(0 == ~E_3~0); 10863#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10962#L931-1 assume !(0 == ~E_5~0); 11002#L936-1 assume !(0 == ~E_6~0); 11009#L941-1 assume !(0 == ~E_7~0); 10575#L946-1 assume !(0 == ~E_8~0); 10576#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10981#L430 assume !(1 == ~m_pc~0); 10434#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10062#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10063#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10676#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10686#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10847#L449 assume 1 == ~t1_pc~0; 10848#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10247#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10021#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10022#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10782#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10631#L468 assume !(1 == ~t2_pc~0); 10046#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10045#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10534#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10441#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10064#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10065#L487 assume 1 == ~t3_pc~0; 10994#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10161#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10162#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10836#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10500#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10501#L506 assume !(1 == ~t4_pc~0); 10627#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10672#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10972#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10973#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10622#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10452#L525 assume 1 == ~t5_pc~0; 10387#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10106#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10579#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10580#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10303#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10304#L544 assume !(1 == ~t6_pc~0); 10453#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10454#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10798#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10088#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10089#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10938#L563 assume 1 == ~t7_pc~0; 10816#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10116#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10117#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10528#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10248#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10249#L582 assume 1 == ~t8_pc~0; 10172#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10173#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10995#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10489#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10391#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10392#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 10850#L964-2 assume !(1 == ~T1_E~0); 10305#L969-1 assume !(1 == ~T2_E~0); 10306#L974-1 assume !(1 == ~T3_E~0); 10875#L979-1 assume !(1 == ~T4_E~0); 10876#L984-1 assume !(1 == ~T5_E~0); 10459#L989-1 assume !(1 == ~T6_E~0); 10460#L994-1 assume !(1 == ~T7_E~0); 10345#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10346#L1004-1 assume !(1 == ~E_M~0); 10090#L1009-1 assume !(1 == ~E_1~0); 10091#L1014-1 assume !(1 == ~E_2~0); 10334#L1019-1 assume !(1 == ~E_3~0); 10839#L1024-1 assume !(1 == ~E_4~0); 10267#L1029-1 assume !(1 == ~E_5~0); 10268#L1034-1 assume !(1 == ~E_6~0); 10362#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10976#L1044-1 assume !(1 == ~E_8~0); 10544#L1049-1 assume { :end_inline_reset_delta_events } true; 10237#L1315-2 [2022-02-21 04:22:11,059 INFO L793 eck$LassoCheckResult]: Loop: 10237#L1315-2 assume !false; 10238#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10024#L841 assume !false; 10363#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10298#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10299#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10139#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10059#L724 assume !(0 != eval_~tmp~0#1); 10061#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10889#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10070#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10071#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10366#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10367#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10380#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10381#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10604#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10605#L896-3 assume !(0 == ~T7_E~0); 10472#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10473#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10606#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10809#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10412#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10413#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10793#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10479#L936-3 assume !(0 == ~E_6~0); 10480#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10621#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10368#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10369#L430-30 assume 1 == ~m_pc~0; 10393#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10394#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10177#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10178#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10827#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10831#L449-30 assume 1 == ~t1_pc~0; 10396#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10086#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10087#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10458#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10170#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10171#L468-30 assume 1 == ~t2_pc~0; 10262#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10263#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10872#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10595#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10596#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10446#L487-30 assume !(1 == ~t3_pc~0); 10241#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 10242#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10573#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10574#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10846#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10520#L506-30 assume !(1 == ~t4_pc~0); 10521#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10547#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10548#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10565#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 10447#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10448#L525-30 assume 1 == ~t5_pc~0; 10933#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10934#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10152#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10153#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10451#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10221#L544-30 assume 1 == ~t6_pc~0; 10029#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10030#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11003#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10943#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10944#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10920#L563-30 assume !(1 == ~t7_pc~0); 10193#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 10192#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10210#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10536#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10537#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10907#L582-30 assume !(1 == ~t8_pc~0); 10288#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 10289#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10524#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10937#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11010#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10095#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10096#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10233#L969-3 assume !(1 == ~T2_E~0); 10224#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10225#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10636#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10637#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10270#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10271#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10780#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10142#L1009-3 assume !(1 == ~E_1~0); 10143#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10617#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10618#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10599#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10566#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10567#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10838#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10260#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10261#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10390#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10727#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10294#L1334 assume !(0 == start_simulation_~tmp~3#1); 10296#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10314#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10025#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10026#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 10620#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10964#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10799#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10800#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 10237#L1315-2 [2022-02-21 04:22:11,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:11,061 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2022-02-21 04:22:11,062 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:11,062 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1710097271] [2022-02-21 04:22:11,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:11,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:11,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:11,106 INFO L290 TraceCheckUtils]: 0: Hoare triple {13018#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {13018#true} is VALID [2022-02-21 04:22:11,107 INFO L290 TraceCheckUtils]: 1: Hoare triple {13018#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {13020#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:11,107 INFO L290 TraceCheckUtils]: 2: Hoare triple {13020#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {13020#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:11,107 INFO L290 TraceCheckUtils]: 3: Hoare triple {13020#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {13020#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:11,107 INFO L290 TraceCheckUtils]: 4: Hoare triple {13020#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {13020#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 5: Hoare triple {13020#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {13020#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 6: Hoare triple {13020#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {13020#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 7: Hoare triple {13020#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {13020#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 8: Hoare triple {13020#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 9: Hoare triple {13019#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 10: Hoare triple {13019#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 11: Hoare triple {13019#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,108 INFO L290 TraceCheckUtils]: 12: Hoare triple {13019#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 13: Hoare triple {13019#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 14: Hoare triple {13019#false} assume !(0 == ~M_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 15: Hoare triple {13019#false} assume !(0 == ~T1_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 16: Hoare triple {13019#false} assume !(0 == ~T2_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 17: Hoare triple {13019#false} assume !(0 == ~T3_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 18: Hoare triple {13019#false} assume !(0 == ~T4_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 19: Hoare triple {13019#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 20: Hoare triple {13019#false} assume !(0 == ~T6_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 21: Hoare triple {13019#false} assume !(0 == ~T7_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 22: Hoare triple {13019#false} assume !(0 == ~T8_E~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 23: Hoare triple {13019#false} assume !(0 == ~E_M~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 24: Hoare triple {13019#false} assume !(0 == ~E_1~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 25: Hoare triple {13019#false} assume !(0 == ~E_2~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 26: Hoare triple {13019#false} assume !(0 == ~E_3~0); {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 27: Hoare triple {13019#false} assume 0 == ~E_4~0;~E_4~0 := 1; {13019#false} is VALID [2022-02-21 04:22:11,109 INFO L290 TraceCheckUtils]: 28: Hoare triple {13019#false} assume !(0 == ~E_5~0); {13019#false} is VALID [2022-02-21 04:22:11,112 INFO L290 TraceCheckUtils]: 29: Hoare triple {13019#false} assume !(0 == ~E_6~0); {13019#false} is VALID [2022-02-21 04:22:11,112 INFO L290 TraceCheckUtils]: 30: Hoare triple {13019#false} assume !(0 == ~E_7~0); {13019#false} is VALID [2022-02-21 04:22:11,112 INFO L290 TraceCheckUtils]: 31: Hoare triple {13019#false} assume !(0 == ~E_8~0); {13019#false} is VALID [2022-02-21 04:22:11,112 INFO L290 TraceCheckUtils]: 32: Hoare triple {13019#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {13019#false} is VALID [2022-02-21 04:22:11,112 INFO L290 TraceCheckUtils]: 33: Hoare triple {13019#false} assume !(1 == ~m_pc~0); {13019#false} is VALID [2022-02-21 04:22:11,112 INFO L290 TraceCheckUtils]: 34: Hoare triple {13019#false} is_master_triggered_~__retres1~0#1 := 0; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 35: Hoare triple {13019#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 36: Hoare triple {13019#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 37: Hoare triple {13019#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 38: Hoare triple {13019#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 39: Hoare triple {13019#false} assume 1 == ~t1_pc~0; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 40: Hoare triple {13019#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 41: Hoare triple {13019#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 42: Hoare triple {13019#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 43: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___0~0#1); {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 44: Hoare triple {13019#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 45: Hoare triple {13019#false} assume !(1 == ~t2_pc~0); {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 46: Hoare triple {13019#false} is_transmit2_triggered_~__retres1~2#1 := 0; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 47: Hoare triple {13019#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 48: Hoare triple {13019#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 49: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___1~0#1); {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 50: Hoare triple {13019#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 51: Hoare triple {13019#false} assume 1 == ~t3_pc~0; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 52: Hoare triple {13019#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {13019#false} is VALID [2022-02-21 04:22:11,113 INFO L290 TraceCheckUtils]: 53: Hoare triple {13019#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 54: Hoare triple {13019#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 55: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___2~0#1); {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 56: Hoare triple {13019#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 57: Hoare triple {13019#false} assume !(1 == ~t4_pc~0); {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 58: Hoare triple {13019#false} is_transmit4_triggered_~__retres1~4#1 := 0; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 59: Hoare triple {13019#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 60: Hoare triple {13019#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 61: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___3~0#1); {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 62: Hoare triple {13019#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 63: Hoare triple {13019#false} assume 1 == ~t5_pc~0; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 64: Hoare triple {13019#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 65: Hoare triple {13019#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 66: Hoare triple {13019#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 67: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___4~0#1); {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 68: Hoare triple {13019#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 69: Hoare triple {13019#false} assume !(1 == ~t6_pc~0); {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 70: Hoare triple {13019#false} is_transmit6_triggered_~__retres1~6#1 := 0; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 71: Hoare triple {13019#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {13019#false} is VALID [2022-02-21 04:22:11,114 INFO L290 TraceCheckUtils]: 72: Hoare triple {13019#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 73: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___5~0#1); {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 74: Hoare triple {13019#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 75: Hoare triple {13019#false} assume 1 == ~t7_pc~0; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 76: Hoare triple {13019#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 77: Hoare triple {13019#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 78: Hoare triple {13019#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 79: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___6~0#1); {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 80: Hoare triple {13019#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 81: Hoare triple {13019#false} assume 1 == ~t8_pc~0; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 82: Hoare triple {13019#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 83: Hoare triple {13019#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 84: Hoare triple {13019#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 85: Hoare triple {13019#false} assume !(0 != activate_threads_~tmp___7~0#1); {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 86: Hoare triple {13019#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 87: Hoare triple {13019#false} assume 1 == ~M_E~0;~M_E~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 88: Hoare triple {13019#false} assume !(1 == ~T1_E~0); {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 89: Hoare triple {13019#false} assume !(1 == ~T2_E~0); {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 90: Hoare triple {13019#false} assume !(1 == ~T3_E~0); {13019#false} is VALID [2022-02-21 04:22:11,115 INFO L290 TraceCheckUtils]: 91: Hoare triple {13019#false} assume !(1 == ~T4_E~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 92: Hoare triple {13019#false} assume !(1 == ~T5_E~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 93: Hoare triple {13019#false} assume !(1 == ~T6_E~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 94: Hoare triple {13019#false} assume !(1 == ~T7_E~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 95: Hoare triple {13019#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 96: Hoare triple {13019#false} assume !(1 == ~E_M~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 97: Hoare triple {13019#false} assume !(1 == ~E_1~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 98: Hoare triple {13019#false} assume !(1 == ~E_2~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 99: Hoare triple {13019#false} assume !(1 == ~E_3~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 100: Hoare triple {13019#false} assume !(1 == ~E_4~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 101: Hoare triple {13019#false} assume !(1 == ~E_5~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 102: Hoare triple {13019#false} assume !(1 == ~E_6~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 103: Hoare triple {13019#false} assume 1 == ~E_7~0;~E_7~0 := 2; {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 104: Hoare triple {13019#false} assume !(1 == ~E_8~0); {13019#false} is VALID [2022-02-21 04:22:11,116 INFO L290 TraceCheckUtils]: 105: Hoare triple {13019#false} assume { :end_inline_reset_delta_events } true; {13019#false} is VALID [2022-02-21 04:22:11,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:11,132 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:11,132 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1710097271] [2022-02-21 04:22:11,133 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1710097271] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:11,133 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:11,133 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:11,133 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938263253] [2022-02-21 04:22:11,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:11,133 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:11,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:11,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1882721649, now seen corresponding path program 1 times [2022-02-21 04:22:11,134 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:11,134 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803508345] [2022-02-21 04:22:11,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:11,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:11,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 0: Hoare triple {13021#true} assume !false; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 1: Hoare triple {13021#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 2: Hoare triple {13021#true} assume !false; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 3: Hoare triple {13021#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 4: Hoare triple {13021#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 5: Hoare triple {13021#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 6: Hoare triple {13021#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 7: Hoare triple {13021#true} assume !(0 != eval_~tmp~0#1); {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 8: Hoare triple {13021#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 9: Hoare triple {13021#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 10: Hoare triple {13021#true} assume 0 == ~M_E~0;~M_E~0 := 1; {13021#true} is VALID [2022-02-21 04:22:11,163 INFO L290 TraceCheckUtils]: 11: Hoare triple {13021#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {13021#true} is VALID [2022-02-21 04:22:11,164 INFO L290 TraceCheckUtils]: 12: Hoare triple {13021#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,164 INFO L290 TraceCheckUtils]: 13: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,164 INFO L290 TraceCheckUtils]: 14: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,164 INFO L290 TraceCheckUtils]: 15: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,165 INFO L290 TraceCheckUtils]: 16: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,165 INFO L290 TraceCheckUtils]: 17: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,165 INFO L290 TraceCheckUtils]: 18: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,165 INFO L290 TraceCheckUtils]: 19: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,165 INFO L290 TraceCheckUtils]: 20: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,166 INFO L290 TraceCheckUtils]: 21: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,166 INFO L290 TraceCheckUtils]: 22: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,166 INFO L290 TraceCheckUtils]: 23: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,166 INFO L290 TraceCheckUtils]: 24: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,167 INFO L290 TraceCheckUtils]: 25: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,167 INFO L290 TraceCheckUtils]: 26: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,167 INFO L290 TraceCheckUtils]: 27: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,167 INFO L290 TraceCheckUtils]: 28: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,167 INFO L290 TraceCheckUtils]: 29: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,168 INFO L290 TraceCheckUtils]: 30: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,168 INFO L290 TraceCheckUtils]: 31: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,168 INFO L290 TraceCheckUtils]: 32: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,168 INFO L290 TraceCheckUtils]: 33: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,169 INFO L290 TraceCheckUtils]: 34: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,169 INFO L290 TraceCheckUtils]: 35: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,169 INFO L290 TraceCheckUtils]: 36: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,169 INFO L290 TraceCheckUtils]: 37: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,170 INFO L290 TraceCheckUtils]: 38: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,170 INFO L290 TraceCheckUtils]: 39: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,170 INFO L290 TraceCheckUtils]: 40: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,170 INFO L290 TraceCheckUtils]: 41: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,170 INFO L290 TraceCheckUtils]: 42: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,171 INFO L290 TraceCheckUtils]: 43: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,171 INFO L290 TraceCheckUtils]: 44: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,171 INFO L290 TraceCheckUtils]: 45: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,171 INFO L290 TraceCheckUtils]: 46: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,172 INFO L290 TraceCheckUtils]: 47: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,172 INFO L290 TraceCheckUtils]: 48: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,172 INFO L290 TraceCheckUtils]: 49: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,172 INFO L290 TraceCheckUtils]: 50: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,172 INFO L290 TraceCheckUtils]: 51: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,173 INFO L290 TraceCheckUtils]: 52: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,173 INFO L290 TraceCheckUtils]: 53: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,173 INFO L290 TraceCheckUtils]: 54: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,173 INFO L290 TraceCheckUtils]: 55: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,174 INFO L290 TraceCheckUtils]: 56: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,174 INFO L290 TraceCheckUtils]: 57: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,174 INFO L290 TraceCheckUtils]: 58: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,174 INFO L290 TraceCheckUtils]: 59: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,175 INFO L290 TraceCheckUtils]: 60: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,175 INFO L290 TraceCheckUtils]: 61: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,175 INFO L290 TraceCheckUtils]: 62: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,175 INFO L290 TraceCheckUtils]: 63: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,175 INFO L290 TraceCheckUtils]: 64: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,176 INFO L290 TraceCheckUtils]: 65: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,176 INFO L290 TraceCheckUtils]: 66: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,176 INFO L290 TraceCheckUtils]: 67: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,176 INFO L290 TraceCheckUtils]: 68: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,177 INFO L290 TraceCheckUtils]: 69: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,177 INFO L290 TraceCheckUtils]: 70: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,177 INFO L290 TraceCheckUtils]: 71: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,177 INFO L290 TraceCheckUtils]: 72: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,178 INFO L290 TraceCheckUtils]: 73: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,178 INFO L290 TraceCheckUtils]: 74: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,178 INFO L290 TraceCheckUtils]: 75: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,178 INFO L290 TraceCheckUtils]: 76: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,178 INFO L290 TraceCheckUtils]: 77: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,179 INFO L290 TraceCheckUtils]: 78: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,179 INFO L290 TraceCheckUtils]: 79: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,179 INFO L290 TraceCheckUtils]: 80: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,179 INFO L290 TraceCheckUtils]: 81: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 82: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 83: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 84: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {13023#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 85: Hoare triple {13023#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {13022#false} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 86: Hoare triple {13022#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 87: Hoare triple {13022#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 88: Hoare triple {13022#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 89: Hoare triple {13022#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,180 INFO L290 TraceCheckUtils]: 90: Hoare triple {13022#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 91: Hoare triple {13022#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 92: Hoare triple {13022#false} assume 1 == ~E_M~0;~E_M~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 93: Hoare triple {13022#false} assume !(1 == ~E_1~0); {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 94: Hoare triple {13022#false} assume 1 == ~E_2~0;~E_2~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 95: Hoare triple {13022#false} assume 1 == ~E_3~0;~E_3~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 96: Hoare triple {13022#false} assume 1 == ~E_4~0;~E_4~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 97: Hoare triple {13022#false} assume 1 == ~E_5~0;~E_5~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 98: Hoare triple {13022#false} assume 1 == ~E_6~0;~E_6~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 99: Hoare triple {13022#false} assume 1 == ~E_7~0;~E_7~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 100: Hoare triple {13022#false} assume 1 == ~E_8~0;~E_8~0 := 2; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 101: Hoare triple {13022#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 102: Hoare triple {13022#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 103: Hoare triple {13022#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 104: Hoare triple {13022#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 105: Hoare triple {13022#false} assume !(0 == start_simulation_~tmp~3#1); {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 106: Hoare triple {13022#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 107: Hoare triple {13022#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 108: Hoare triple {13022#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 109: Hoare triple {13022#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {13022#false} is VALID [2022-02-21 04:22:11,181 INFO L290 TraceCheckUtils]: 110: Hoare triple {13022#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {13022#false} is VALID [2022-02-21 04:22:11,182 INFO L290 TraceCheckUtils]: 111: Hoare triple {13022#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {13022#false} is VALID [2022-02-21 04:22:11,182 INFO L290 TraceCheckUtils]: 112: Hoare triple {13022#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {13022#false} is VALID [2022-02-21 04:22:11,182 INFO L290 TraceCheckUtils]: 113: Hoare triple {13022#false} assume !(0 != start_simulation_~tmp___0~1#1); {13022#false} is VALID [2022-02-21 04:22:11,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:11,182 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:11,182 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803508345] [2022-02-21 04:22:11,182 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803508345] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:11,182 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:11,182 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:11,183 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570331426] [2022-02-21 04:22:11,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:11,183 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:11,183 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:11,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:11,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:11,183 INFO L87 Difference]: Start difference. First operand 998 states and 1488 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:11,830 INFO L93 Difference]: Finished difference Result 998 states and 1487 transitions. [2022-02-21 04:22:11,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:11,830 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,907 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:11,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1487 transitions. [2022-02-21 04:22:11,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:11,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1487 transitions. [2022-02-21 04:22:11,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:11,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:11,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1487 transitions. [2022-02-21 04:22:11,986 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:11,986 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2022-02-21 04:22:11,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1487 transitions. [2022-02-21 04:22:11,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:11,997 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:11,999 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1487 transitions. Second operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,001 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1487 transitions. Second operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,002 INFO L87 Difference]: Start difference. First operand 998 states and 1487 transitions. Second operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,036 INFO L93 Difference]: Finished difference Result 998 states and 1487 transitions. [2022-02-21 04:22:12,036 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1487 transitions. [2022-02-21 04:22:12,038 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:12,038 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:12,040 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1487 transitions. [2022-02-21 04:22:12,041 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1487 transitions. [2022-02-21 04:22:12,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,066 INFO L93 Difference]: Finished difference Result 998 states and 1487 transitions. [2022-02-21 04:22:12,066 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1487 transitions. [2022-02-21 04:22:12,067 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:12,067 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:12,067 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:12,067 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:12,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1487 transitions. [2022-02-21 04:22:12,115 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2022-02-21 04:22:12,115 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2022-02-21 04:22:12,115 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:22:12,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1487 transitions. [2022-02-21 04:22:12,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:12,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:12,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:12,120 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:12,120 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:12,120 INFO L791 eck$LassoCheckResult]: Stem: 14792#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14719#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14720#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14572#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 14573#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14158#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14159#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14240#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14951#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14128#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14129#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14536#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14561#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14244#L866 assume !(0 == ~M_E~0); 14245#L866-2 assume !(0 == ~T1_E~0); 14747#L871-1 assume !(0 == ~T2_E~0); 14748#L876-1 assume !(0 == ~T3_E~0); 14998#L881-1 assume !(0 == ~T4_E~0); 14757#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14527#L891-1 assume !(0 == ~T6_E~0); 14528#L896-1 assume !(0 == ~T7_E~0); 14750#L901-1 assume !(0 == ~T8_E~0); 14768#L906-1 assume !(0 == ~E_M~0); 14769#L911-1 assume !(0 == ~E_1~0); 14570#L916-1 assume !(0 == ~E_2~0); 14571#L921-1 assume !(0 == ~E_3~0); 14864#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14963#L931-1 assume !(0 == ~E_5~0); 15003#L936-1 assume !(0 == ~E_6~0); 15010#L941-1 assume !(0 == ~E_7~0); 14576#L946-1 assume !(0 == ~E_8~0); 14577#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14982#L430 assume !(1 == ~m_pc~0); 14435#L430-2 is_master_triggered_~__retres1~0#1 := 0; 14063#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14064#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14677#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14687#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14848#L449 assume 1 == ~t1_pc~0; 14849#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14248#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14022#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14023#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 14783#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14632#L468 assume !(1 == ~t2_pc~0); 14047#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14046#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14535#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14442#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 14065#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14066#L487 assume 1 == ~t3_pc~0; 14995#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14162#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14163#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14837#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 14501#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14502#L506 assume !(1 == ~t4_pc~0); 14628#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14673#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14973#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14974#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 14623#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14453#L525 assume 1 == ~t5_pc~0; 14388#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14107#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14580#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14581#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 14304#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14305#L544 assume !(1 == ~t6_pc~0); 14454#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14455#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14799#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14089#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 14090#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14939#L563 assume 1 == ~t7_pc~0; 14817#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14117#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14118#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14529#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 14249#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14250#L582 assume 1 == ~t8_pc~0; 14173#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14174#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14996#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14490#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 14392#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14393#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 14851#L964-2 assume !(1 == ~T1_E~0); 14306#L969-1 assume !(1 == ~T2_E~0); 14307#L974-1 assume !(1 == ~T3_E~0); 14876#L979-1 assume !(1 == ~T4_E~0); 14877#L984-1 assume !(1 == ~T5_E~0); 14460#L989-1 assume !(1 == ~T6_E~0); 14461#L994-1 assume !(1 == ~T7_E~0); 14346#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14347#L1004-1 assume !(1 == ~E_M~0); 14091#L1009-1 assume !(1 == ~E_1~0); 14092#L1014-1 assume !(1 == ~E_2~0); 14335#L1019-1 assume !(1 == ~E_3~0); 14840#L1024-1 assume !(1 == ~E_4~0); 14268#L1029-1 assume !(1 == ~E_5~0); 14269#L1034-1 assume !(1 == ~E_6~0); 14363#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14977#L1044-1 assume !(1 == ~E_8~0); 14545#L1049-1 assume { :end_inline_reset_delta_events } true; 14238#L1315-2 [2022-02-21 04:22:12,135 INFO L793 eck$LassoCheckResult]: Loop: 14238#L1315-2 assume !false; 14239#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14025#L841 assume !false; 14364#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14299#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14300#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14140#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14060#L724 assume !(0 != eval_~tmp~0#1); 14062#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14890#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14071#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14072#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14367#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14368#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14381#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14382#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14605#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14606#L896-3 assume !(0 == ~T7_E~0); 14473#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14474#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14607#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14810#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14413#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14414#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14794#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14480#L936-3 assume !(0 == ~E_6~0); 14481#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14622#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14369#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14370#L430-30 assume 1 == ~m_pc~0; 14394#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14395#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14178#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14179#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14828#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14832#L449-30 assume 1 == ~t1_pc~0; 14397#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14087#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14088#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14459#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14171#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14172#L468-30 assume 1 == ~t2_pc~0; 14263#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14264#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14873#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14596#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14597#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14447#L487-30 assume !(1 == ~t3_pc~0); 14242#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 14243#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14574#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14575#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14847#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14521#L506-30 assume !(1 == ~t4_pc~0); 14522#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14548#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14549#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14566#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 14448#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14449#L525-30 assume 1 == ~t5_pc~0; 14934#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14935#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14153#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14154#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14452#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14222#L544-30 assume !(1 == ~t6_pc~0); 14032#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 14031#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15004#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14944#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14945#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14921#L563-30 assume 1 == ~t7_pc~0; 14192#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14193#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14211#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14537#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14538#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14908#L582-30 assume !(1 == ~t8_pc~0); 14289#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 14290#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14525#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14938#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15011#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14096#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14097#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14234#L969-3 assume !(1 == ~T2_E~0); 14225#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14226#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14637#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14638#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14271#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14272#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14781#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14143#L1009-3 assume !(1 == ~E_1~0); 14144#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14618#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14619#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14600#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14567#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14568#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14839#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14261#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14262#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14391#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14728#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14295#L1334 assume !(0 == start_simulation_~tmp~3#1); 14297#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14315#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14026#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14027#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14621#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14965#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14800#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14801#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 14238#L1315-2 [2022-02-21 04:22:12,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:12,136 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2022-02-21 04:22:12,136 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:12,136 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305067343] [2022-02-21 04:22:12,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:12,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:12,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:12,159 INFO L290 TraceCheckUtils]: 0: Hoare triple {17019#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {17019#true} is VALID [2022-02-21 04:22:12,159 INFO L290 TraceCheckUtils]: 1: Hoare triple {17019#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 2: Hoare triple {17021#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 3: Hoare triple {17021#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 4: Hoare triple {17021#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 5: Hoare triple {17021#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,160 INFO L290 TraceCheckUtils]: 6: Hoare triple {17021#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 7: Hoare triple {17021#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 8: Hoare triple {17021#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {17021#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 9: Hoare triple {17021#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 10: Hoare triple {17020#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 11: Hoare triple {17020#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 12: Hoare triple {17020#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 13: Hoare triple {17020#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 14: Hoare triple {17020#false} assume !(0 == ~M_E~0); {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 15: Hoare triple {17020#false} assume !(0 == ~T1_E~0); {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 16: Hoare triple {17020#false} assume !(0 == ~T2_E~0); {17020#false} is VALID [2022-02-21 04:22:12,161 INFO L290 TraceCheckUtils]: 17: Hoare triple {17020#false} assume !(0 == ~T3_E~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 18: Hoare triple {17020#false} assume !(0 == ~T4_E~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 19: Hoare triple {17020#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 20: Hoare triple {17020#false} assume !(0 == ~T6_E~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 21: Hoare triple {17020#false} assume !(0 == ~T7_E~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 22: Hoare triple {17020#false} assume !(0 == ~T8_E~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 23: Hoare triple {17020#false} assume !(0 == ~E_M~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 24: Hoare triple {17020#false} assume !(0 == ~E_1~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 25: Hoare triple {17020#false} assume !(0 == ~E_2~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 26: Hoare triple {17020#false} assume !(0 == ~E_3~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 27: Hoare triple {17020#false} assume 0 == ~E_4~0;~E_4~0 := 1; {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 28: Hoare triple {17020#false} assume !(0 == ~E_5~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 29: Hoare triple {17020#false} assume !(0 == ~E_6~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 30: Hoare triple {17020#false} assume !(0 == ~E_7~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 31: Hoare triple {17020#false} assume !(0 == ~E_8~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 32: Hoare triple {17020#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 33: Hoare triple {17020#false} assume !(1 == ~m_pc~0); {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 34: Hoare triple {17020#false} is_master_triggered_~__retres1~0#1 := 0; {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 35: Hoare triple {17020#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 36: Hoare triple {17020#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 37: Hoare triple {17020#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17020#false} is VALID [2022-02-21 04:22:12,162 INFO L290 TraceCheckUtils]: 38: Hoare triple {17020#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 39: Hoare triple {17020#false} assume 1 == ~t1_pc~0; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 40: Hoare triple {17020#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 41: Hoare triple {17020#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 42: Hoare triple {17020#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 43: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___0~0#1); {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 44: Hoare triple {17020#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 45: Hoare triple {17020#false} assume !(1 == ~t2_pc~0); {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 46: Hoare triple {17020#false} is_transmit2_triggered_~__retres1~2#1 := 0; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 47: Hoare triple {17020#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 48: Hoare triple {17020#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 49: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___1~0#1); {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 50: Hoare triple {17020#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 51: Hoare triple {17020#false} assume 1 == ~t3_pc~0; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 52: Hoare triple {17020#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17020#false} is VALID [2022-02-21 04:22:12,163 INFO L290 TraceCheckUtils]: 53: Hoare triple {17020#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 54: Hoare triple {17020#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 55: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___2~0#1); {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 56: Hoare triple {17020#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 57: Hoare triple {17020#false} assume !(1 == ~t4_pc~0); {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 58: Hoare triple {17020#false} is_transmit4_triggered_~__retres1~4#1 := 0; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 59: Hoare triple {17020#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 60: Hoare triple {17020#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 61: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___3~0#1); {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 62: Hoare triple {17020#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 63: Hoare triple {17020#false} assume 1 == ~t5_pc~0; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 64: Hoare triple {17020#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 65: Hoare triple {17020#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 66: Hoare triple {17020#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 67: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___4~0#1); {17020#false} is VALID [2022-02-21 04:22:12,164 INFO L290 TraceCheckUtils]: 68: Hoare triple {17020#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 69: Hoare triple {17020#false} assume !(1 == ~t6_pc~0); {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 70: Hoare triple {17020#false} is_transmit6_triggered_~__retres1~6#1 := 0; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 71: Hoare triple {17020#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 72: Hoare triple {17020#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 73: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___5~0#1); {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 74: Hoare triple {17020#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 75: Hoare triple {17020#false} assume 1 == ~t7_pc~0; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 76: Hoare triple {17020#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 77: Hoare triple {17020#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 78: Hoare triple {17020#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 79: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___6~0#1); {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 80: Hoare triple {17020#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 81: Hoare triple {17020#false} assume 1 == ~t8_pc~0; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 82: Hoare triple {17020#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {17020#false} is VALID [2022-02-21 04:22:12,165 INFO L290 TraceCheckUtils]: 83: Hoare triple {17020#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 84: Hoare triple {17020#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 85: Hoare triple {17020#false} assume !(0 != activate_threads_~tmp___7~0#1); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 86: Hoare triple {17020#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 87: Hoare triple {17020#false} assume 1 == ~M_E~0;~M_E~0 := 2; {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 88: Hoare triple {17020#false} assume !(1 == ~T1_E~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 89: Hoare triple {17020#false} assume !(1 == ~T2_E~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 90: Hoare triple {17020#false} assume !(1 == ~T3_E~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 91: Hoare triple {17020#false} assume !(1 == ~T4_E~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 92: Hoare triple {17020#false} assume !(1 == ~T5_E~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 93: Hoare triple {17020#false} assume !(1 == ~T6_E~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 94: Hoare triple {17020#false} assume !(1 == ~T7_E~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 95: Hoare triple {17020#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 96: Hoare triple {17020#false} assume !(1 == ~E_M~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 97: Hoare triple {17020#false} assume !(1 == ~E_1~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 98: Hoare triple {17020#false} assume !(1 == ~E_2~0); {17020#false} is VALID [2022-02-21 04:22:12,166 INFO L290 TraceCheckUtils]: 99: Hoare triple {17020#false} assume !(1 == ~E_3~0); {17020#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 100: Hoare triple {17020#false} assume !(1 == ~E_4~0); {17020#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 101: Hoare triple {17020#false} assume !(1 == ~E_5~0); {17020#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 102: Hoare triple {17020#false} assume !(1 == ~E_6~0); {17020#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 103: Hoare triple {17020#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17020#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 104: Hoare triple {17020#false} assume !(1 == ~E_8~0); {17020#false} is VALID [2022-02-21 04:22:12,167 INFO L290 TraceCheckUtils]: 105: Hoare triple {17020#false} assume { :end_inline_reset_delta_events } true; {17020#false} is VALID [2022-02-21 04:22:12,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:12,167 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:12,167 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305067343] [2022-02-21 04:22:12,167 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305067343] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:12,168 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:12,168 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:12,168 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346214561] [2022-02-21 04:22:12,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:12,168 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:12,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:12,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1452394673, now seen corresponding path program 1 times [2022-02-21 04:22:12,169 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:12,169 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35766119] [2022-02-21 04:22:12,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:12,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:12,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:12,227 INFO L290 TraceCheckUtils]: 0: Hoare triple {17022#true} assume !false; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 1: Hoare triple {17022#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 2: Hoare triple {17022#true} assume !false; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 3: Hoare triple {17022#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 4: Hoare triple {17022#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 5: Hoare triple {17022#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 6: Hoare triple {17022#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 7: Hoare triple {17022#true} assume !(0 != eval_~tmp~0#1); {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 8: Hoare triple {17022#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 9: Hoare triple {17022#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 10: Hoare triple {17022#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 11: Hoare triple {17022#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {17022#true} is VALID [2022-02-21 04:22:12,228 INFO L290 TraceCheckUtils]: 12: Hoare triple {17022#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,229 INFO L290 TraceCheckUtils]: 13: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,229 INFO L290 TraceCheckUtils]: 14: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,229 INFO L290 TraceCheckUtils]: 15: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,229 INFO L290 TraceCheckUtils]: 16: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,229 INFO L290 TraceCheckUtils]: 17: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,230 INFO L290 TraceCheckUtils]: 18: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,230 INFO L290 TraceCheckUtils]: 19: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,230 INFO L290 TraceCheckUtils]: 20: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,230 INFO L290 TraceCheckUtils]: 21: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,231 INFO L290 TraceCheckUtils]: 22: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,231 INFO L290 TraceCheckUtils]: 23: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,231 INFO L290 TraceCheckUtils]: 24: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,231 INFO L290 TraceCheckUtils]: 25: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,231 INFO L290 TraceCheckUtils]: 26: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,232 INFO L290 TraceCheckUtils]: 27: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,232 INFO L290 TraceCheckUtils]: 28: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,232 INFO L290 TraceCheckUtils]: 29: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,232 INFO L290 TraceCheckUtils]: 30: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,233 INFO L290 TraceCheckUtils]: 31: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,233 INFO L290 TraceCheckUtils]: 32: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,233 INFO L290 TraceCheckUtils]: 33: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,233 INFO L290 TraceCheckUtils]: 34: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,233 INFO L290 TraceCheckUtils]: 35: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,234 INFO L290 TraceCheckUtils]: 36: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,234 INFO L290 TraceCheckUtils]: 37: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,234 INFO L290 TraceCheckUtils]: 38: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,234 INFO L290 TraceCheckUtils]: 39: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,235 INFO L290 TraceCheckUtils]: 40: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,235 INFO L290 TraceCheckUtils]: 41: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,235 INFO L290 TraceCheckUtils]: 42: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,235 INFO L290 TraceCheckUtils]: 43: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,235 INFO L290 TraceCheckUtils]: 44: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,236 INFO L290 TraceCheckUtils]: 45: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,236 INFO L290 TraceCheckUtils]: 46: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,236 INFO L290 TraceCheckUtils]: 47: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,236 INFO L290 TraceCheckUtils]: 48: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,237 INFO L290 TraceCheckUtils]: 49: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,237 INFO L290 TraceCheckUtils]: 50: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,237 INFO L290 TraceCheckUtils]: 51: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,237 INFO L290 TraceCheckUtils]: 52: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,237 INFO L290 TraceCheckUtils]: 53: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,238 INFO L290 TraceCheckUtils]: 54: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,238 INFO L290 TraceCheckUtils]: 55: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,238 INFO L290 TraceCheckUtils]: 56: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,238 INFO L290 TraceCheckUtils]: 57: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,238 INFO L290 TraceCheckUtils]: 58: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,239 INFO L290 TraceCheckUtils]: 59: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,239 INFO L290 TraceCheckUtils]: 60: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,239 INFO L290 TraceCheckUtils]: 61: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,239 INFO L290 TraceCheckUtils]: 62: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,240 INFO L290 TraceCheckUtils]: 63: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,240 INFO L290 TraceCheckUtils]: 64: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,240 INFO L290 TraceCheckUtils]: 65: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,240 INFO L290 TraceCheckUtils]: 66: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,240 INFO L290 TraceCheckUtils]: 67: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,241 INFO L290 TraceCheckUtils]: 68: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,241 INFO L290 TraceCheckUtils]: 69: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,241 INFO L290 TraceCheckUtils]: 70: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,241 INFO L290 TraceCheckUtils]: 71: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,242 INFO L290 TraceCheckUtils]: 72: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,242 INFO L290 TraceCheckUtils]: 73: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,242 INFO L290 TraceCheckUtils]: 74: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,242 INFO L290 TraceCheckUtils]: 75: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,242 INFO L290 TraceCheckUtils]: 76: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,243 INFO L290 TraceCheckUtils]: 77: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,243 INFO L290 TraceCheckUtils]: 78: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,243 INFO L290 TraceCheckUtils]: 79: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,243 INFO L290 TraceCheckUtils]: 80: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,244 INFO L290 TraceCheckUtils]: 81: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,244 INFO L290 TraceCheckUtils]: 82: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,244 INFO L290 TraceCheckUtils]: 83: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,244 INFO L290 TraceCheckUtils]: 84: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17024#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,244 INFO L290 TraceCheckUtils]: 85: Hoare triple {17024#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 86: Hoare triple {17023#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 87: Hoare triple {17023#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 88: Hoare triple {17023#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 89: Hoare triple {17023#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 90: Hoare triple {17023#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 91: Hoare triple {17023#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 92: Hoare triple {17023#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 93: Hoare triple {17023#false} assume !(1 == ~E_1~0); {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 94: Hoare triple {17023#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 95: Hoare triple {17023#false} assume 1 == ~E_3~0;~E_3~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 96: Hoare triple {17023#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 97: Hoare triple {17023#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 98: Hoare triple {17023#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 99: Hoare triple {17023#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 100: Hoare triple {17023#false} assume 1 == ~E_8~0;~E_8~0 := 2; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 101: Hoare triple {17023#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 102: Hoare triple {17023#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 103: Hoare triple {17023#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 104: Hoare triple {17023#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 105: Hoare triple {17023#false} assume !(0 == start_simulation_~tmp~3#1); {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 106: Hoare triple {17023#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 107: Hoare triple {17023#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {17023#false} is VALID [2022-02-21 04:22:12,245 INFO L290 TraceCheckUtils]: 108: Hoare triple {17023#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {17023#false} is VALID [2022-02-21 04:22:12,246 INFO L290 TraceCheckUtils]: 109: Hoare triple {17023#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {17023#false} is VALID [2022-02-21 04:22:12,246 INFO L290 TraceCheckUtils]: 110: Hoare triple {17023#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17023#false} is VALID [2022-02-21 04:22:12,246 INFO L290 TraceCheckUtils]: 111: Hoare triple {17023#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17023#false} is VALID [2022-02-21 04:22:12,246 INFO L290 TraceCheckUtils]: 112: Hoare triple {17023#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {17023#false} is VALID [2022-02-21 04:22:12,246 INFO L290 TraceCheckUtils]: 113: Hoare triple {17023#false} assume !(0 != start_simulation_~tmp___0~1#1); {17023#false} is VALID [2022-02-21 04:22:12,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:12,246 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:12,246 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [35766119] [2022-02-21 04:22:12,246 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [35766119] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:12,246 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:12,246 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:12,246 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338837472] [2022-02-21 04:22:12,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:12,247 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:12,247 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:12,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:12,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:12,247 INFO L87 Difference]: Start difference. First operand 998 states and 1487 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,919 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2022-02-21 04:22:12,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:12,919 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,984 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:12,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2022-02-21 04:22:13,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:13,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1486 transitions. [2022-02-21 04:22:13,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:13,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:13,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1486 transitions. [2022-02-21 04:22:13,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:13,054 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2022-02-21 04:22:13,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1486 transitions. [2022-02-21 04:22:13,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:13,063 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:13,064 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1486 transitions. Second operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,065 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1486 transitions. Second operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,065 INFO L87 Difference]: Start difference. First operand 998 states and 1486 transitions. Second operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,088 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2022-02-21 04:22:13,088 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1486 transitions. [2022-02-21 04:22:13,089 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:13,089 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:13,090 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1486 transitions. [2022-02-21 04:22:13,091 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1486 transitions. [2022-02-21 04:22:13,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,114 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2022-02-21 04:22:13,114 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1486 transitions. [2022-02-21 04:22:13,115 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:13,115 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:13,115 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:13,115 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:13,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1486 transitions. [2022-02-21 04:22:13,138 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2022-02-21 04:22:13,138 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2022-02-21 04:22:13,138 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:22:13,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1486 transitions. [2022-02-21 04:22:13,141 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:13,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:13,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:13,142 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:13,142 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:13,142 INFO L791 eck$LassoCheckResult]: Stem: 18793#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 18794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 18720#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18721#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18573#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 18574#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18159#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18160#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18241#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18952#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18129#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18130#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18537#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18562#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18245#L866 assume !(0 == ~M_E~0); 18246#L866-2 assume !(0 == ~T1_E~0); 18748#L871-1 assume !(0 == ~T2_E~0); 18749#L876-1 assume !(0 == ~T3_E~0); 18999#L881-1 assume !(0 == ~T4_E~0); 18758#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18528#L891-1 assume !(0 == ~T6_E~0); 18529#L896-1 assume !(0 == ~T7_E~0); 18751#L901-1 assume !(0 == ~T8_E~0); 18769#L906-1 assume !(0 == ~E_M~0); 18770#L911-1 assume !(0 == ~E_1~0); 18571#L916-1 assume !(0 == ~E_2~0); 18572#L921-1 assume !(0 == ~E_3~0); 18865#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18964#L931-1 assume !(0 == ~E_5~0); 19004#L936-1 assume !(0 == ~E_6~0); 19011#L941-1 assume !(0 == ~E_7~0); 18577#L946-1 assume !(0 == ~E_8~0); 18578#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18983#L430 assume !(1 == ~m_pc~0); 18436#L430-2 is_master_triggered_~__retres1~0#1 := 0; 18064#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18065#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18678#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18688#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18849#L449 assume 1 == ~t1_pc~0; 18850#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18249#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18023#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18024#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 18784#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18633#L468 assume !(1 == ~t2_pc~0); 18048#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18047#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18536#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18443#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 18066#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18067#L487 assume 1 == ~t3_pc~0; 18996#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18163#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18164#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18838#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 18502#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18503#L506 assume !(1 == ~t4_pc~0); 18629#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18674#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18974#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18975#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 18624#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18454#L525 assume 1 == ~t5_pc~0; 18389#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18108#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18581#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18582#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 18305#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18306#L544 assume !(1 == ~t6_pc~0); 18455#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18456#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18800#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18090#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 18091#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18940#L563 assume 1 == ~t7_pc~0; 18818#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18118#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18119#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18530#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 18250#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18251#L582 assume 1 == ~t8_pc~0; 18174#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18175#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18997#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18491#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 18393#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18394#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 18852#L964-2 assume !(1 == ~T1_E~0); 18307#L969-1 assume !(1 == ~T2_E~0); 18308#L974-1 assume !(1 == ~T3_E~0); 18877#L979-1 assume !(1 == ~T4_E~0); 18878#L984-1 assume !(1 == ~T5_E~0); 18461#L989-1 assume !(1 == ~T6_E~0); 18462#L994-1 assume !(1 == ~T7_E~0); 18347#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18348#L1004-1 assume !(1 == ~E_M~0); 18092#L1009-1 assume !(1 == ~E_1~0); 18093#L1014-1 assume !(1 == ~E_2~0); 18336#L1019-1 assume !(1 == ~E_3~0); 18841#L1024-1 assume !(1 == ~E_4~0); 18269#L1029-1 assume !(1 == ~E_5~0); 18270#L1034-1 assume !(1 == ~E_6~0); 18364#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 18978#L1044-1 assume !(1 == ~E_8~0); 18546#L1049-1 assume { :end_inline_reset_delta_events } true; 18239#L1315-2 [2022-02-21 04:22:13,143 INFO L793 eck$LassoCheckResult]: Loop: 18239#L1315-2 assume !false; 18240#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18026#L841 assume !false; 18365#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18300#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18301#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18141#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18061#L724 assume !(0 != eval_~tmp~0#1); 18063#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18891#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18072#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18073#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18368#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18369#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18382#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18383#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18606#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18607#L896-3 assume !(0 == ~T7_E~0); 18474#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18475#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18608#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18811#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18414#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18415#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18795#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18481#L936-3 assume !(0 == ~E_6~0); 18482#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18623#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18370#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18371#L430-30 assume 1 == ~m_pc~0; 18395#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18396#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18179#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18180#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18829#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18833#L449-30 assume 1 == ~t1_pc~0; 18398#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18088#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18089#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18460#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18172#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18173#L468-30 assume 1 == ~t2_pc~0; 18264#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18265#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18874#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18597#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18598#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18448#L487-30 assume !(1 == ~t3_pc~0); 18243#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 18244#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18575#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18576#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18848#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18522#L506-30 assume !(1 == ~t4_pc~0); 18523#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 18549#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18550#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18567#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 18449#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18450#L525-30 assume 1 == ~t5_pc~0; 18935#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18936#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18154#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18155#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18453#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18223#L544-30 assume !(1 == ~t6_pc~0); 18033#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 18032#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19005#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18945#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18946#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18922#L563-30 assume 1 == ~t7_pc~0; 18193#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18194#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18212#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18538#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18539#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18909#L582-30 assume !(1 == ~t8_pc~0); 18290#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 18291#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18526#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18939#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19012#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18097#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18098#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18235#L969-3 assume !(1 == ~T2_E~0); 18226#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18227#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18638#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18639#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18272#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18273#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18782#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18144#L1009-3 assume !(1 == ~E_1~0); 18145#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18619#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18620#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18601#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18568#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18569#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18840#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18262#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18263#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18392#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18729#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 18296#L1334 assume !(0 == start_simulation_~tmp~3#1); 18298#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18316#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18027#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18028#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 18622#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18966#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18801#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 18802#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 18239#L1315-2 [2022-02-21 04:22:13,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:13,143 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2022-02-21 04:22:13,143 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:13,144 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461647939] [2022-02-21 04:22:13,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:13,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:13,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:13,163 INFO L290 TraceCheckUtils]: 0: Hoare triple {21020#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {21020#true} is VALID [2022-02-21 04:22:13,163 INFO L290 TraceCheckUtils]: 1: Hoare triple {21020#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,163 INFO L290 TraceCheckUtils]: 2: Hoare triple {21022#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,164 INFO L290 TraceCheckUtils]: 3: Hoare triple {21022#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,164 INFO L290 TraceCheckUtils]: 4: Hoare triple {21022#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,164 INFO L290 TraceCheckUtils]: 5: Hoare triple {21022#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 6: Hoare triple {21022#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 7: Hoare triple {21022#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 8: Hoare triple {21022#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,165 INFO L290 TraceCheckUtils]: 9: Hoare triple {21022#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {21022#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 10: Hoare triple {21022#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {21021#false} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 11: Hoare triple {21021#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {21021#false} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 12: Hoare triple {21021#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {21021#false} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 13: Hoare triple {21021#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {21021#false} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 14: Hoare triple {21021#false} assume !(0 == ~M_E~0); {21021#false} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 15: Hoare triple {21021#false} assume !(0 == ~T1_E~0); {21021#false} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 16: Hoare triple {21021#false} assume !(0 == ~T2_E~0); {21021#false} is VALID [2022-02-21 04:22:13,166 INFO L290 TraceCheckUtils]: 17: Hoare triple {21021#false} assume !(0 == ~T3_E~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 18: Hoare triple {21021#false} assume !(0 == ~T4_E~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 19: Hoare triple {21021#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 20: Hoare triple {21021#false} assume !(0 == ~T6_E~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 21: Hoare triple {21021#false} assume !(0 == ~T7_E~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 22: Hoare triple {21021#false} assume !(0 == ~T8_E~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 23: Hoare triple {21021#false} assume !(0 == ~E_M~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 24: Hoare triple {21021#false} assume !(0 == ~E_1~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 25: Hoare triple {21021#false} assume !(0 == ~E_2~0); {21021#false} is VALID [2022-02-21 04:22:13,167 INFO L290 TraceCheckUtils]: 26: Hoare triple {21021#false} assume !(0 == ~E_3~0); {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 27: Hoare triple {21021#false} assume 0 == ~E_4~0;~E_4~0 := 1; {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 28: Hoare triple {21021#false} assume !(0 == ~E_5~0); {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 29: Hoare triple {21021#false} assume !(0 == ~E_6~0); {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 30: Hoare triple {21021#false} assume !(0 == ~E_7~0); {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 31: Hoare triple {21021#false} assume !(0 == ~E_8~0); {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 32: Hoare triple {21021#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 33: Hoare triple {21021#false} assume !(1 == ~m_pc~0); {21021#false} is VALID [2022-02-21 04:22:13,168 INFO L290 TraceCheckUtils]: 34: Hoare triple {21021#false} is_master_triggered_~__retres1~0#1 := 0; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 35: Hoare triple {21021#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 36: Hoare triple {21021#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 37: Hoare triple {21021#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 38: Hoare triple {21021#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 39: Hoare triple {21021#false} assume 1 == ~t1_pc~0; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 40: Hoare triple {21021#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 41: Hoare triple {21021#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 42: Hoare triple {21021#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {21021#false} is VALID [2022-02-21 04:22:13,169 INFO L290 TraceCheckUtils]: 43: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___0~0#1); {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 44: Hoare triple {21021#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 45: Hoare triple {21021#false} assume !(1 == ~t2_pc~0); {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 46: Hoare triple {21021#false} is_transmit2_triggered_~__retres1~2#1 := 0; {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 47: Hoare triple {21021#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 48: Hoare triple {21021#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 49: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___1~0#1); {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 50: Hoare triple {21021#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 51: Hoare triple {21021#false} assume 1 == ~t3_pc~0; {21021#false} is VALID [2022-02-21 04:22:13,170 INFO L290 TraceCheckUtils]: 52: Hoare triple {21021#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 53: Hoare triple {21021#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 54: Hoare triple {21021#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 55: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___2~0#1); {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 56: Hoare triple {21021#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 57: Hoare triple {21021#false} assume !(1 == ~t4_pc~0); {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 58: Hoare triple {21021#false} is_transmit4_triggered_~__retres1~4#1 := 0; {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 59: Hoare triple {21021#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 60: Hoare triple {21021#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21021#false} is VALID [2022-02-21 04:22:13,171 INFO L290 TraceCheckUtils]: 61: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___3~0#1); {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 62: Hoare triple {21021#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 63: Hoare triple {21021#false} assume 1 == ~t5_pc~0; {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 64: Hoare triple {21021#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 65: Hoare triple {21021#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 66: Hoare triple {21021#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 67: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___4~0#1); {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 68: Hoare triple {21021#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21021#false} is VALID [2022-02-21 04:22:13,172 INFO L290 TraceCheckUtils]: 69: Hoare triple {21021#false} assume !(1 == ~t6_pc~0); {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 70: Hoare triple {21021#false} is_transmit6_triggered_~__retres1~6#1 := 0; {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 71: Hoare triple {21021#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 72: Hoare triple {21021#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 73: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___5~0#1); {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 74: Hoare triple {21021#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 75: Hoare triple {21021#false} assume 1 == ~t7_pc~0; {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 76: Hoare triple {21021#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 77: Hoare triple {21021#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {21021#false} is VALID [2022-02-21 04:22:13,173 INFO L290 TraceCheckUtils]: 78: Hoare triple {21021#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 79: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___6~0#1); {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 80: Hoare triple {21021#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 81: Hoare triple {21021#false} assume 1 == ~t8_pc~0; {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 82: Hoare triple {21021#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 83: Hoare triple {21021#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 84: Hoare triple {21021#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 85: Hoare triple {21021#false} assume !(0 != activate_threads_~tmp___7~0#1); {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 86: Hoare triple {21021#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21021#false} is VALID [2022-02-21 04:22:13,174 INFO L290 TraceCheckUtils]: 87: Hoare triple {21021#false} assume 1 == ~M_E~0;~M_E~0 := 2; {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 88: Hoare triple {21021#false} assume !(1 == ~T1_E~0); {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 89: Hoare triple {21021#false} assume !(1 == ~T2_E~0); {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 90: Hoare triple {21021#false} assume !(1 == ~T3_E~0); {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 91: Hoare triple {21021#false} assume !(1 == ~T4_E~0); {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 92: Hoare triple {21021#false} assume !(1 == ~T5_E~0); {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 93: Hoare triple {21021#false} assume !(1 == ~T6_E~0); {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 94: Hoare triple {21021#false} assume !(1 == ~T7_E~0); {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 95: Hoare triple {21021#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {21021#false} is VALID [2022-02-21 04:22:13,175 INFO L290 TraceCheckUtils]: 96: Hoare triple {21021#false} assume !(1 == ~E_M~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 97: Hoare triple {21021#false} assume !(1 == ~E_1~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 98: Hoare triple {21021#false} assume !(1 == ~E_2~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 99: Hoare triple {21021#false} assume !(1 == ~E_3~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 100: Hoare triple {21021#false} assume !(1 == ~E_4~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 101: Hoare triple {21021#false} assume !(1 == ~E_5~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 102: Hoare triple {21021#false} assume !(1 == ~E_6~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 103: Hoare triple {21021#false} assume 1 == ~E_7~0;~E_7~0 := 2; {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 104: Hoare triple {21021#false} assume !(1 == ~E_8~0); {21021#false} is VALID [2022-02-21 04:22:13,176 INFO L290 TraceCheckUtils]: 105: Hoare triple {21021#false} assume { :end_inline_reset_delta_events } true; {21021#false} is VALID [2022-02-21 04:22:13,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:13,177 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:13,178 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461647939] [2022-02-21 04:22:13,178 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461647939] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:13,178 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:13,178 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:13,178 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [558179542] [2022-02-21 04:22:13,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:13,179 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:13,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:13,179 INFO L85 PathProgramCache]: Analyzing trace with hash 1452394673, now seen corresponding path program 2 times [2022-02-21 04:22:13,179 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:13,182 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425285068] [2022-02-21 04:22:13,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:13,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:13,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:13,225 INFO L290 TraceCheckUtils]: 0: Hoare triple {21023#true} assume !false; {21023#true} is VALID [2022-02-21 04:22:13,225 INFO L290 TraceCheckUtils]: 1: Hoare triple {21023#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {21023#true} is VALID [2022-02-21 04:22:13,225 INFO L290 TraceCheckUtils]: 2: Hoare triple {21023#true} assume !false; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 3: Hoare triple {21023#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 4: Hoare triple {21023#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 5: Hoare triple {21023#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 6: Hoare triple {21023#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 7: Hoare triple {21023#true} assume !(0 != eval_~tmp~0#1); {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 8: Hoare triple {21023#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 9: Hoare triple {21023#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 10: Hoare triple {21023#true} assume 0 == ~M_E~0;~M_E~0 := 1; {21023#true} is VALID [2022-02-21 04:22:13,226 INFO L290 TraceCheckUtils]: 11: Hoare triple {21023#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {21023#true} is VALID [2022-02-21 04:22:13,227 INFO L290 TraceCheckUtils]: 12: Hoare triple {21023#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,227 INFO L290 TraceCheckUtils]: 13: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,227 INFO L290 TraceCheckUtils]: 14: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,227 INFO L290 TraceCheckUtils]: 15: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,228 INFO L290 TraceCheckUtils]: 16: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,228 INFO L290 TraceCheckUtils]: 17: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,228 INFO L290 TraceCheckUtils]: 18: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,228 INFO L290 TraceCheckUtils]: 19: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,229 INFO L290 TraceCheckUtils]: 20: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,229 INFO L290 TraceCheckUtils]: 21: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,229 INFO L290 TraceCheckUtils]: 22: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,230 INFO L290 TraceCheckUtils]: 23: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,230 INFO L290 TraceCheckUtils]: 24: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,230 INFO L290 TraceCheckUtils]: 25: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,230 INFO L290 TraceCheckUtils]: 26: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,231 INFO L290 TraceCheckUtils]: 27: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,231 INFO L290 TraceCheckUtils]: 28: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,231 INFO L290 TraceCheckUtils]: 29: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,231 INFO L290 TraceCheckUtils]: 30: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,232 INFO L290 TraceCheckUtils]: 31: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,232 INFO L290 TraceCheckUtils]: 32: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,232 INFO L290 TraceCheckUtils]: 33: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,232 INFO L290 TraceCheckUtils]: 34: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,233 INFO L290 TraceCheckUtils]: 35: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,233 INFO L290 TraceCheckUtils]: 36: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,233 INFO L290 TraceCheckUtils]: 37: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,233 INFO L290 TraceCheckUtils]: 38: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,234 INFO L290 TraceCheckUtils]: 39: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,234 INFO L290 TraceCheckUtils]: 40: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,234 INFO L290 TraceCheckUtils]: 41: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,234 INFO L290 TraceCheckUtils]: 42: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,235 INFO L290 TraceCheckUtils]: 43: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,235 INFO L290 TraceCheckUtils]: 44: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,235 INFO L290 TraceCheckUtils]: 45: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,235 INFO L290 TraceCheckUtils]: 46: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,236 INFO L290 TraceCheckUtils]: 47: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,236 INFO L290 TraceCheckUtils]: 48: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,236 INFO L290 TraceCheckUtils]: 49: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,236 INFO L290 TraceCheckUtils]: 50: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,237 INFO L290 TraceCheckUtils]: 51: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,237 INFO L290 TraceCheckUtils]: 52: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,237 INFO L290 TraceCheckUtils]: 53: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,237 INFO L290 TraceCheckUtils]: 54: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,238 INFO L290 TraceCheckUtils]: 55: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,238 INFO L290 TraceCheckUtils]: 56: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,238 INFO L290 TraceCheckUtils]: 57: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,238 INFO L290 TraceCheckUtils]: 58: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,239 INFO L290 TraceCheckUtils]: 59: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,239 INFO L290 TraceCheckUtils]: 60: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,239 INFO L290 TraceCheckUtils]: 61: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,239 INFO L290 TraceCheckUtils]: 62: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,240 INFO L290 TraceCheckUtils]: 63: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,240 INFO L290 TraceCheckUtils]: 64: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,240 INFO L290 TraceCheckUtils]: 65: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,240 INFO L290 TraceCheckUtils]: 66: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,241 INFO L290 TraceCheckUtils]: 67: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,241 INFO L290 TraceCheckUtils]: 68: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,241 INFO L290 TraceCheckUtils]: 69: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,241 INFO L290 TraceCheckUtils]: 70: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,242 INFO L290 TraceCheckUtils]: 71: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,242 INFO L290 TraceCheckUtils]: 72: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,242 INFO L290 TraceCheckUtils]: 73: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,242 INFO L290 TraceCheckUtils]: 74: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,243 INFO L290 TraceCheckUtils]: 75: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,243 INFO L290 TraceCheckUtils]: 76: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,243 INFO L290 TraceCheckUtils]: 77: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,243 INFO L290 TraceCheckUtils]: 78: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,244 INFO L290 TraceCheckUtils]: 79: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,244 INFO L290 TraceCheckUtils]: 80: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,244 INFO L290 TraceCheckUtils]: 81: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,244 INFO L290 TraceCheckUtils]: 82: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,245 INFO L290 TraceCheckUtils]: 83: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,245 INFO L290 TraceCheckUtils]: 84: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {21025#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:13,245 INFO L290 TraceCheckUtils]: 85: Hoare triple {21025#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {21024#false} is VALID [2022-02-21 04:22:13,245 INFO L290 TraceCheckUtils]: 86: Hoare triple {21024#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,245 INFO L290 TraceCheckUtils]: 87: Hoare triple {21024#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 88: Hoare triple {21024#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 89: Hoare triple {21024#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 90: Hoare triple {21024#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 91: Hoare triple {21024#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 92: Hoare triple {21024#false} assume 1 == ~E_M~0;~E_M~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 93: Hoare triple {21024#false} assume !(1 == ~E_1~0); {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 94: Hoare triple {21024#false} assume 1 == ~E_2~0;~E_2~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 95: Hoare triple {21024#false} assume 1 == ~E_3~0;~E_3~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 96: Hoare triple {21024#false} assume 1 == ~E_4~0;~E_4~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,246 INFO L290 TraceCheckUtils]: 97: Hoare triple {21024#false} assume 1 == ~E_5~0;~E_5~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 98: Hoare triple {21024#false} assume 1 == ~E_6~0;~E_6~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 99: Hoare triple {21024#false} assume 1 == ~E_7~0;~E_7~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 100: Hoare triple {21024#false} assume 1 == ~E_8~0;~E_8~0 := 2; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 101: Hoare triple {21024#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 102: Hoare triple {21024#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 103: Hoare triple {21024#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 104: Hoare triple {21024#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 105: Hoare triple {21024#false} assume !(0 == start_simulation_~tmp~3#1); {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 106: Hoare triple {21024#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {21024#false} is VALID [2022-02-21 04:22:13,247 INFO L290 TraceCheckUtils]: 107: Hoare triple {21024#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {21024#false} is VALID [2022-02-21 04:22:13,248 INFO L290 TraceCheckUtils]: 108: Hoare triple {21024#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {21024#false} is VALID [2022-02-21 04:22:13,248 INFO L290 TraceCheckUtils]: 109: Hoare triple {21024#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {21024#false} is VALID [2022-02-21 04:22:13,248 INFO L290 TraceCheckUtils]: 110: Hoare triple {21024#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {21024#false} is VALID [2022-02-21 04:22:13,248 INFO L290 TraceCheckUtils]: 111: Hoare triple {21024#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {21024#false} is VALID [2022-02-21 04:22:13,248 INFO L290 TraceCheckUtils]: 112: Hoare triple {21024#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {21024#false} is VALID [2022-02-21 04:22:13,248 INFO L290 TraceCheckUtils]: 113: Hoare triple {21024#false} assume !(0 != start_simulation_~tmp___0~1#1); {21024#false} is VALID [2022-02-21 04:22:13,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:13,248 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:13,249 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425285068] [2022-02-21 04:22:13,249 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425285068] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:13,249 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:13,249 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:13,249 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274511172] [2022-02-21 04:22:13,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:13,250 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:13,250 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:13,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:13,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:13,251 INFO L87 Difference]: Start difference. First operand 998 states and 1486 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,927 INFO L93 Difference]: Finished difference Result 998 states and 1485 transitions. [2022-02-21 04:22:13,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:13,927 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,990 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:13,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1485 transitions. [2022-02-21 04:22:14,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:14,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1485 transitions. [2022-02-21 04:22:14,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:14,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:14,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1485 transitions. [2022-02-21 04:22:14,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:14,040 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2022-02-21 04:22:14,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1485 transitions. [2022-02-21 04:22:14,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:14,049 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:14,050 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1485 transitions. Second operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,051 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1485 transitions. Second operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,051 INFO L87 Difference]: Start difference. First operand 998 states and 1485 transitions. Second operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:14,074 INFO L93 Difference]: Finished difference Result 998 states and 1485 transitions. [2022-02-21 04:22:14,074 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1485 transitions. [2022-02-21 04:22:14,097 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:14,111 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:14,112 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1485 transitions. [2022-02-21 04:22:14,113 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1485 transitions. [2022-02-21 04:22:14,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:14,152 INFO L93 Difference]: Finished difference Result 998 states and 1485 transitions. [2022-02-21 04:22:14,153 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1485 transitions. [2022-02-21 04:22:14,154 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:14,154 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:14,154 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:14,154 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:14,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1485 transitions. [2022-02-21 04:22:14,197 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2022-02-21 04:22:14,198 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2022-02-21 04:22:14,198 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:22:14,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1485 transitions. [2022-02-21 04:22:14,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:14,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:14,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:14,202 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,202 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,202 INFO L791 eck$LassoCheckResult]: Stem: 22794#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 22795#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 22721#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22722#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22574#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 22575#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22160#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22161#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22242#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22953#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22130#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22131#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22538#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22563#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22246#L866 assume !(0 == ~M_E~0); 22247#L866-2 assume !(0 == ~T1_E~0); 22749#L871-1 assume !(0 == ~T2_E~0); 22750#L876-1 assume !(0 == ~T3_E~0); 23000#L881-1 assume !(0 == ~T4_E~0); 22759#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22529#L891-1 assume !(0 == ~T6_E~0); 22530#L896-1 assume !(0 == ~T7_E~0); 22752#L901-1 assume !(0 == ~T8_E~0); 22770#L906-1 assume !(0 == ~E_M~0); 22771#L911-1 assume !(0 == ~E_1~0); 22572#L916-1 assume !(0 == ~E_2~0); 22573#L921-1 assume !(0 == ~E_3~0); 22866#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22965#L931-1 assume !(0 == ~E_5~0); 23005#L936-1 assume !(0 == ~E_6~0); 23012#L941-1 assume !(0 == ~E_7~0); 22578#L946-1 assume !(0 == ~E_8~0); 22579#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22984#L430 assume !(1 == ~m_pc~0); 22437#L430-2 is_master_triggered_~__retres1~0#1 := 0; 22065#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22066#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22679#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22689#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22850#L449 assume 1 == ~t1_pc~0; 22851#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22250#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22024#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22025#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 22785#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22634#L468 assume !(1 == ~t2_pc~0); 22049#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22048#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22537#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22444#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 22067#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22068#L487 assume 1 == ~t3_pc~0; 22997#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22164#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22165#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22839#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 22503#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22504#L506 assume !(1 == ~t4_pc~0); 22630#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22675#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22975#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22976#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 22625#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22455#L525 assume 1 == ~t5_pc~0; 22390#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22109#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22582#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22583#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 22306#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22307#L544 assume !(1 == ~t6_pc~0); 22456#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22457#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22801#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22091#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 22092#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22941#L563 assume 1 == ~t7_pc~0; 22819#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22119#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22120#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22531#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 22251#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22252#L582 assume 1 == ~t8_pc~0; 22175#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22176#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22998#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22492#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 22394#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22395#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 22853#L964-2 assume !(1 == ~T1_E~0); 22308#L969-1 assume !(1 == ~T2_E~0); 22309#L974-1 assume !(1 == ~T3_E~0); 22878#L979-1 assume !(1 == ~T4_E~0); 22879#L984-1 assume !(1 == ~T5_E~0); 22462#L989-1 assume !(1 == ~T6_E~0); 22463#L994-1 assume !(1 == ~T7_E~0); 22348#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22349#L1004-1 assume !(1 == ~E_M~0); 22093#L1009-1 assume !(1 == ~E_1~0); 22094#L1014-1 assume !(1 == ~E_2~0); 22337#L1019-1 assume !(1 == ~E_3~0); 22842#L1024-1 assume !(1 == ~E_4~0); 22270#L1029-1 assume !(1 == ~E_5~0); 22271#L1034-1 assume !(1 == ~E_6~0); 22365#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22979#L1044-1 assume !(1 == ~E_8~0); 22547#L1049-1 assume { :end_inline_reset_delta_events } true; 22240#L1315-2 [2022-02-21 04:22:14,203 INFO L793 eck$LassoCheckResult]: Loop: 22240#L1315-2 assume !false; 22241#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22027#L841 assume !false; 22366#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 22301#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 22302#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 22142#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22062#L724 assume !(0 != eval_~tmp~0#1); 22064#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22892#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22073#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22074#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22369#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22370#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22383#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22384#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22607#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22608#L896-3 assume !(0 == ~T7_E~0); 22475#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22476#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22609#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22812#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22415#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22416#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22796#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22482#L936-3 assume !(0 == ~E_6~0); 22483#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22624#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22371#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22372#L430-30 assume 1 == ~m_pc~0; 22396#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22397#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22180#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22181#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22830#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22834#L449-30 assume !(1 == ~t1_pc~0); 22400#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 22089#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22090#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22461#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22173#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22174#L468-30 assume 1 == ~t2_pc~0; 22265#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22266#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22875#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22598#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22599#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22449#L487-30 assume !(1 == ~t3_pc~0); 22244#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 22245#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22576#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22577#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22849#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22523#L506-30 assume !(1 == ~t4_pc~0); 22524#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 22550#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22551#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22568#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 22450#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22451#L525-30 assume 1 == ~t5_pc~0; 22936#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22937#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22155#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22156#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22454#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22224#L544-30 assume 1 == ~t6_pc~0; 22032#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22033#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23006#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22946#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22947#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22923#L563-30 assume 1 == ~t7_pc~0; 22194#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22195#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22213#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22539#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22540#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22910#L582-30 assume !(1 == ~t8_pc~0); 22291#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 22292#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22527#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22940#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23013#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22098#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22099#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22236#L969-3 assume !(1 == ~T2_E~0); 22227#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22228#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22639#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22640#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22273#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22274#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22783#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22145#L1009-3 assume !(1 == ~E_1~0); 22146#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22620#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22621#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22602#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22569#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22570#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22841#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22263#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 22264#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 22393#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 22730#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 22297#L1334 assume !(0 == start_simulation_~tmp~3#1); 22299#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 22317#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 22028#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 22029#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 22623#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22967#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22802#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22803#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 22240#L1315-2 [2022-02-21 04:22:14,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,203 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2022-02-21 04:22:14,203 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,203 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990147520] [2022-02-21 04:22:14,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,229 INFO L290 TraceCheckUtils]: 0: Hoare triple {25021#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {25021#true} is VALID [2022-02-21 04:22:14,230 INFO L290 TraceCheckUtils]: 1: Hoare triple {25021#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,230 INFO L290 TraceCheckUtils]: 2: Hoare triple {25023#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,230 INFO L290 TraceCheckUtils]: 3: Hoare triple {25023#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,231 INFO L290 TraceCheckUtils]: 4: Hoare triple {25023#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,231 INFO L290 TraceCheckUtils]: 5: Hoare triple {25023#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,231 INFO L290 TraceCheckUtils]: 6: Hoare triple {25023#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,231 INFO L290 TraceCheckUtils]: 7: Hoare triple {25023#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,232 INFO L290 TraceCheckUtils]: 8: Hoare triple {25023#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,232 INFO L290 TraceCheckUtils]: 9: Hoare triple {25023#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,232 INFO L290 TraceCheckUtils]: 10: Hoare triple {25023#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {25023#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:14,232 INFO L290 TraceCheckUtils]: 11: Hoare triple {25023#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {25022#false} is VALID [2022-02-21 04:22:14,232 INFO L290 TraceCheckUtils]: 12: Hoare triple {25022#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 13: Hoare triple {25022#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 14: Hoare triple {25022#false} assume !(0 == ~M_E~0); {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 15: Hoare triple {25022#false} assume !(0 == ~T1_E~0); {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 16: Hoare triple {25022#false} assume !(0 == ~T2_E~0); {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 17: Hoare triple {25022#false} assume !(0 == ~T3_E~0); {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 18: Hoare triple {25022#false} assume !(0 == ~T4_E~0); {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 19: Hoare triple {25022#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 20: Hoare triple {25022#false} assume !(0 == ~T6_E~0); {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 21: Hoare triple {25022#false} assume !(0 == ~T7_E~0); {25022#false} is VALID [2022-02-21 04:22:14,233 INFO L290 TraceCheckUtils]: 22: Hoare triple {25022#false} assume !(0 == ~T8_E~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 23: Hoare triple {25022#false} assume !(0 == ~E_M~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 24: Hoare triple {25022#false} assume !(0 == ~E_1~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 25: Hoare triple {25022#false} assume !(0 == ~E_2~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 26: Hoare triple {25022#false} assume !(0 == ~E_3~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 27: Hoare triple {25022#false} assume 0 == ~E_4~0;~E_4~0 := 1; {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 28: Hoare triple {25022#false} assume !(0 == ~E_5~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 29: Hoare triple {25022#false} assume !(0 == ~E_6~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 30: Hoare triple {25022#false} assume !(0 == ~E_7~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 31: Hoare triple {25022#false} assume !(0 == ~E_8~0); {25022#false} is VALID [2022-02-21 04:22:14,234 INFO L290 TraceCheckUtils]: 32: Hoare triple {25022#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 33: Hoare triple {25022#false} assume !(1 == ~m_pc~0); {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 34: Hoare triple {25022#false} is_master_triggered_~__retres1~0#1 := 0; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 35: Hoare triple {25022#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 36: Hoare triple {25022#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 37: Hoare triple {25022#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 38: Hoare triple {25022#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 39: Hoare triple {25022#false} assume 1 == ~t1_pc~0; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 40: Hoare triple {25022#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {25022#false} is VALID [2022-02-21 04:22:14,235 INFO L290 TraceCheckUtils]: 41: Hoare triple {25022#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 42: Hoare triple {25022#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 43: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___0~0#1); {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 44: Hoare triple {25022#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 45: Hoare triple {25022#false} assume !(1 == ~t2_pc~0); {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 46: Hoare triple {25022#false} is_transmit2_triggered_~__retres1~2#1 := 0; {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 47: Hoare triple {25022#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 48: Hoare triple {25022#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 49: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___1~0#1); {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 50: Hoare triple {25022#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {25022#false} is VALID [2022-02-21 04:22:14,236 INFO L290 TraceCheckUtils]: 51: Hoare triple {25022#false} assume 1 == ~t3_pc~0; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 52: Hoare triple {25022#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 53: Hoare triple {25022#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 54: Hoare triple {25022#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 55: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___2~0#1); {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 56: Hoare triple {25022#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 57: Hoare triple {25022#false} assume !(1 == ~t4_pc~0); {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 58: Hoare triple {25022#false} is_transmit4_triggered_~__retres1~4#1 := 0; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 59: Hoare triple {25022#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 60: Hoare triple {25022#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {25022#false} is VALID [2022-02-21 04:22:14,237 INFO L290 TraceCheckUtils]: 61: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___3~0#1); {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 62: Hoare triple {25022#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 63: Hoare triple {25022#false} assume 1 == ~t5_pc~0; {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 64: Hoare triple {25022#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 65: Hoare triple {25022#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 66: Hoare triple {25022#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 67: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___4~0#1); {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 68: Hoare triple {25022#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 69: Hoare triple {25022#false} assume !(1 == ~t6_pc~0); {25022#false} is VALID [2022-02-21 04:22:14,238 INFO L290 TraceCheckUtils]: 70: Hoare triple {25022#false} is_transmit6_triggered_~__retres1~6#1 := 0; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 71: Hoare triple {25022#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 72: Hoare triple {25022#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 73: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___5~0#1); {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 74: Hoare triple {25022#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 75: Hoare triple {25022#false} assume 1 == ~t7_pc~0; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 76: Hoare triple {25022#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 77: Hoare triple {25022#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 78: Hoare triple {25022#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {25022#false} is VALID [2022-02-21 04:22:14,239 INFO L290 TraceCheckUtils]: 79: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___6~0#1); {25022#false} is VALID [2022-02-21 04:22:14,240 INFO L290 TraceCheckUtils]: 80: Hoare triple {25022#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {25022#false} is VALID [2022-02-21 04:22:14,240 INFO L290 TraceCheckUtils]: 81: Hoare triple {25022#false} assume 1 == ~t8_pc~0; {25022#false} is VALID [2022-02-21 04:22:14,240 INFO L290 TraceCheckUtils]: 82: Hoare triple {25022#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {25022#false} is VALID [2022-02-21 04:22:14,240 INFO L290 TraceCheckUtils]: 83: Hoare triple {25022#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {25022#false} is VALID [2022-02-21 04:22:14,240 INFO L290 TraceCheckUtils]: 84: Hoare triple {25022#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {25022#false} is VALID [2022-02-21 04:22:14,240 INFO L290 TraceCheckUtils]: 85: Hoare triple {25022#false} assume !(0 != activate_threads_~tmp___7~0#1); {25022#false} is VALID [2022-02-21 04:22:14,240 INFO L290 TraceCheckUtils]: 86: Hoare triple {25022#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 87: Hoare triple {25022#false} assume 1 == ~M_E~0;~M_E~0 := 2; {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 88: Hoare triple {25022#false} assume !(1 == ~T1_E~0); {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 89: Hoare triple {25022#false} assume !(1 == ~T2_E~0); {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 90: Hoare triple {25022#false} assume !(1 == ~T3_E~0); {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 91: Hoare triple {25022#false} assume !(1 == ~T4_E~0); {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 92: Hoare triple {25022#false} assume !(1 == ~T5_E~0); {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 93: Hoare triple {25022#false} assume !(1 == ~T6_E~0); {25022#false} is VALID [2022-02-21 04:22:14,241 INFO L290 TraceCheckUtils]: 94: Hoare triple {25022#false} assume !(1 == ~T7_E~0); {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 95: Hoare triple {25022#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 96: Hoare triple {25022#false} assume !(1 == ~E_M~0); {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 97: Hoare triple {25022#false} assume !(1 == ~E_1~0); {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 98: Hoare triple {25022#false} assume !(1 == ~E_2~0); {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 99: Hoare triple {25022#false} assume !(1 == ~E_3~0); {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 100: Hoare triple {25022#false} assume !(1 == ~E_4~0); {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 101: Hoare triple {25022#false} assume !(1 == ~E_5~0); {25022#false} is VALID [2022-02-21 04:22:14,242 INFO L290 TraceCheckUtils]: 102: Hoare triple {25022#false} assume !(1 == ~E_6~0); {25022#false} is VALID [2022-02-21 04:22:14,243 INFO L290 TraceCheckUtils]: 103: Hoare triple {25022#false} assume 1 == ~E_7~0;~E_7~0 := 2; {25022#false} is VALID [2022-02-21 04:22:14,243 INFO L290 TraceCheckUtils]: 104: Hoare triple {25022#false} assume !(1 == ~E_8~0); {25022#false} is VALID [2022-02-21 04:22:14,243 INFO L290 TraceCheckUtils]: 105: Hoare triple {25022#false} assume { :end_inline_reset_delta_events } true; {25022#false} is VALID [2022-02-21 04:22:14,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,243 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,244 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990147520] [2022-02-21 04:22:14,244 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990147520] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,244 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,244 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,244 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485656016] [2022-02-21 04:22:14,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,245 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:14,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,245 INFO L85 PathProgramCache]: Analyzing trace with hash -952835855, now seen corresponding path program 1 times [2022-02-21 04:22:14,246 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,246 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914760935] [2022-02-21 04:22:14,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,273 INFO L290 TraceCheckUtils]: 0: Hoare triple {25024#true} assume !false; {25024#true} is VALID [2022-02-21 04:22:14,273 INFO L290 TraceCheckUtils]: 1: Hoare triple {25024#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 2: Hoare triple {25024#true} assume !false; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 3: Hoare triple {25024#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 4: Hoare triple {25024#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 5: Hoare triple {25024#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 6: Hoare triple {25024#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 7: Hoare triple {25024#true} assume !(0 != eval_~tmp~0#1); {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 8: Hoare triple {25024#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 9: Hoare triple {25024#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {25024#true} is VALID [2022-02-21 04:22:14,274 INFO L290 TraceCheckUtils]: 10: Hoare triple {25024#true} assume 0 == ~M_E~0;~M_E~0 := 1; {25024#true} is VALID [2022-02-21 04:22:14,275 INFO L290 TraceCheckUtils]: 11: Hoare triple {25024#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {25024#true} is VALID [2022-02-21 04:22:14,275 INFO L290 TraceCheckUtils]: 12: Hoare triple {25024#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,275 INFO L290 TraceCheckUtils]: 13: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,276 INFO L290 TraceCheckUtils]: 14: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,276 INFO L290 TraceCheckUtils]: 15: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,276 INFO L290 TraceCheckUtils]: 16: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,276 INFO L290 TraceCheckUtils]: 17: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,277 INFO L290 TraceCheckUtils]: 18: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,277 INFO L290 TraceCheckUtils]: 19: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,277 INFO L290 TraceCheckUtils]: 20: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,277 INFO L290 TraceCheckUtils]: 21: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,278 INFO L290 TraceCheckUtils]: 22: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,278 INFO L290 TraceCheckUtils]: 23: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,278 INFO L290 TraceCheckUtils]: 24: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,278 INFO L290 TraceCheckUtils]: 25: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,279 INFO L290 TraceCheckUtils]: 26: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,279 INFO L290 TraceCheckUtils]: 27: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,279 INFO L290 TraceCheckUtils]: 28: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,280 INFO L290 TraceCheckUtils]: 29: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,280 INFO L290 TraceCheckUtils]: 30: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,280 INFO L290 TraceCheckUtils]: 31: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,280 INFO L290 TraceCheckUtils]: 32: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,281 INFO L290 TraceCheckUtils]: 33: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,281 INFO L290 TraceCheckUtils]: 34: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,281 INFO L290 TraceCheckUtils]: 35: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,281 INFO L290 TraceCheckUtils]: 36: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,282 INFO L290 TraceCheckUtils]: 37: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,282 INFO L290 TraceCheckUtils]: 38: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,282 INFO L290 TraceCheckUtils]: 39: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,282 INFO L290 TraceCheckUtils]: 40: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,283 INFO L290 TraceCheckUtils]: 41: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,283 INFO L290 TraceCheckUtils]: 42: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,283 INFO L290 TraceCheckUtils]: 43: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,283 INFO L290 TraceCheckUtils]: 44: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,284 INFO L290 TraceCheckUtils]: 45: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,284 INFO L290 TraceCheckUtils]: 46: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,284 INFO L290 TraceCheckUtils]: 47: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,284 INFO L290 TraceCheckUtils]: 48: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,285 INFO L290 TraceCheckUtils]: 49: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,285 INFO L290 TraceCheckUtils]: 50: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,285 INFO L290 TraceCheckUtils]: 51: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,285 INFO L290 TraceCheckUtils]: 52: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,286 INFO L290 TraceCheckUtils]: 53: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,286 INFO L290 TraceCheckUtils]: 54: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,286 INFO L290 TraceCheckUtils]: 55: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,286 INFO L290 TraceCheckUtils]: 56: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,287 INFO L290 TraceCheckUtils]: 57: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,287 INFO L290 TraceCheckUtils]: 58: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,287 INFO L290 TraceCheckUtils]: 59: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,287 INFO L290 TraceCheckUtils]: 60: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,288 INFO L290 TraceCheckUtils]: 61: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,288 INFO L290 TraceCheckUtils]: 62: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,288 INFO L290 TraceCheckUtils]: 63: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,288 INFO L290 TraceCheckUtils]: 64: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,289 INFO L290 TraceCheckUtils]: 65: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,289 INFO L290 TraceCheckUtils]: 66: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,289 INFO L290 TraceCheckUtils]: 67: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,289 INFO L290 TraceCheckUtils]: 68: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,290 INFO L290 TraceCheckUtils]: 69: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,290 INFO L290 TraceCheckUtils]: 70: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,290 INFO L290 TraceCheckUtils]: 71: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,290 INFO L290 TraceCheckUtils]: 72: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,291 INFO L290 TraceCheckUtils]: 73: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,291 INFO L290 TraceCheckUtils]: 74: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,291 INFO L290 TraceCheckUtils]: 75: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,291 INFO L290 TraceCheckUtils]: 76: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,292 INFO L290 TraceCheckUtils]: 77: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,292 INFO L290 TraceCheckUtils]: 78: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,292 INFO L290 TraceCheckUtils]: 79: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,292 INFO L290 TraceCheckUtils]: 80: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,293 INFO L290 TraceCheckUtils]: 81: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,293 INFO L290 TraceCheckUtils]: 82: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,293 INFO L290 TraceCheckUtils]: 83: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,293 INFO L290 TraceCheckUtils]: 84: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {25026#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 85: Hoare triple {25026#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {25025#false} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 86: Hoare triple {25025#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 87: Hoare triple {25025#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 88: Hoare triple {25025#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 89: Hoare triple {25025#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 90: Hoare triple {25025#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 91: Hoare triple {25025#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,294 INFO L290 TraceCheckUtils]: 92: Hoare triple {25025#false} assume 1 == ~E_M~0;~E_M~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 93: Hoare triple {25025#false} assume !(1 == ~E_1~0); {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 94: Hoare triple {25025#false} assume 1 == ~E_2~0;~E_2~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 95: Hoare triple {25025#false} assume 1 == ~E_3~0;~E_3~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 96: Hoare triple {25025#false} assume 1 == ~E_4~0;~E_4~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 97: Hoare triple {25025#false} assume 1 == ~E_5~0;~E_5~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 98: Hoare triple {25025#false} assume 1 == ~E_6~0;~E_6~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 99: Hoare triple {25025#false} assume 1 == ~E_7~0;~E_7~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 100: Hoare triple {25025#false} assume 1 == ~E_8~0;~E_8~0 := 2; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 101: Hoare triple {25025#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {25025#false} is VALID [2022-02-21 04:22:14,295 INFO L290 TraceCheckUtils]: 102: Hoare triple {25025#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 103: Hoare triple {25025#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 104: Hoare triple {25025#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 105: Hoare triple {25025#false} assume !(0 == start_simulation_~tmp~3#1); {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 106: Hoare triple {25025#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 107: Hoare triple {25025#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 108: Hoare triple {25025#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 109: Hoare triple {25025#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 110: Hoare triple {25025#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {25025#false} is VALID [2022-02-21 04:22:14,296 INFO L290 TraceCheckUtils]: 111: Hoare triple {25025#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {25025#false} is VALID [2022-02-21 04:22:14,297 INFO L290 TraceCheckUtils]: 112: Hoare triple {25025#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {25025#false} is VALID [2022-02-21 04:22:14,297 INFO L290 TraceCheckUtils]: 113: Hoare triple {25025#false} assume !(0 != start_simulation_~tmp___0~1#1); {25025#false} is VALID [2022-02-21 04:22:14,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,297 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,297 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914760935] [2022-02-21 04:22:14,297 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914760935] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,297 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,298 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,298 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047217032] [2022-02-21 04:22:14,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,298 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:14,298 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:14,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:14,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:14,299 INFO L87 Difference]: Start difference. First operand 998 states and 1485 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:14,990 INFO L93 Difference]: Finished difference Result 998 states and 1484 transitions. [2022-02-21 04:22:14,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:14,990 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,044 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:15,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1484 transitions. [2022-02-21 04:22:15,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:15,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1484 transitions. [2022-02-21 04:22:15,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:15,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:15,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1484 transitions. [2022-02-21 04:22:15,097 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:15,097 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2022-02-21 04:22:15,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1484 transitions. [2022-02-21 04:22:15,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:15,108 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:15,109 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1484 transitions. Second operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,110 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1484 transitions. Second operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,111 INFO L87 Difference]: Start difference. First operand 998 states and 1484 transitions. Second operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:15,134 INFO L93 Difference]: Finished difference Result 998 states and 1484 transitions. [2022-02-21 04:22:15,134 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1484 transitions. [2022-02-21 04:22:15,135 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:15,135 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:15,136 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1484 transitions. [2022-02-21 04:22:15,137 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1484 transitions. [2022-02-21 04:22:15,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:15,160 INFO L93 Difference]: Finished difference Result 998 states and 1484 transitions. [2022-02-21 04:22:15,160 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1484 transitions. [2022-02-21 04:22:15,161 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:15,161 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:15,161 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:15,161 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:15,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1484 transitions. [2022-02-21 04:22:15,205 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2022-02-21 04:22:15,205 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2022-02-21 04:22:15,205 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:22:15,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1484 transitions. [2022-02-21 04:22:15,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:15,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:15,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:15,209 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:15,209 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:15,209 INFO L791 eck$LassoCheckResult]: Stem: 26795#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 26796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 26722#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26723#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26575#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 26576#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26161#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26162#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26243#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26954#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26131#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26132#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26539#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26564#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26247#L866 assume !(0 == ~M_E~0); 26248#L866-2 assume !(0 == ~T1_E~0); 26750#L871-1 assume !(0 == ~T2_E~0); 26751#L876-1 assume !(0 == ~T3_E~0); 27001#L881-1 assume !(0 == ~T4_E~0); 26760#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26530#L891-1 assume !(0 == ~T6_E~0); 26531#L896-1 assume !(0 == ~T7_E~0); 26753#L901-1 assume !(0 == ~T8_E~0); 26771#L906-1 assume !(0 == ~E_M~0); 26772#L911-1 assume !(0 == ~E_1~0); 26573#L916-1 assume !(0 == ~E_2~0); 26574#L921-1 assume !(0 == ~E_3~0); 26867#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26966#L931-1 assume !(0 == ~E_5~0); 27006#L936-1 assume !(0 == ~E_6~0); 27013#L941-1 assume !(0 == ~E_7~0); 26579#L946-1 assume !(0 == ~E_8~0); 26580#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26985#L430 assume !(1 == ~m_pc~0); 26438#L430-2 is_master_triggered_~__retres1~0#1 := 0; 26066#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26067#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26680#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26690#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26851#L449 assume 1 == ~t1_pc~0; 26852#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26251#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26025#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26026#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 26786#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26635#L468 assume !(1 == ~t2_pc~0); 26050#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26049#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26538#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26445#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 26068#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26069#L487 assume 1 == ~t3_pc~0; 26998#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26165#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26166#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26840#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 26504#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26505#L506 assume !(1 == ~t4_pc~0); 26631#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26676#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26976#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26977#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 26626#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26456#L525 assume 1 == ~t5_pc~0; 26391#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26110#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26583#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26584#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 26307#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26308#L544 assume !(1 == ~t6_pc~0); 26457#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26458#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26802#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26092#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 26093#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26942#L563 assume 1 == ~t7_pc~0; 26820#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26120#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26121#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26532#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 26252#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26253#L582 assume 1 == ~t8_pc~0; 26176#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26177#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26999#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26493#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 26395#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26396#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 26854#L964-2 assume !(1 == ~T1_E~0); 26309#L969-1 assume !(1 == ~T2_E~0); 26310#L974-1 assume !(1 == ~T3_E~0); 26879#L979-1 assume !(1 == ~T4_E~0); 26880#L984-1 assume !(1 == ~T5_E~0); 26463#L989-1 assume !(1 == ~T6_E~0); 26464#L994-1 assume !(1 == ~T7_E~0); 26349#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26350#L1004-1 assume !(1 == ~E_M~0); 26094#L1009-1 assume !(1 == ~E_1~0); 26095#L1014-1 assume !(1 == ~E_2~0); 26338#L1019-1 assume !(1 == ~E_3~0); 26843#L1024-1 assume !(1 == ~E_4~0); 26271#L1029-1 assume !(1 == ~E_5~0); 26272#L1034-1 assume !(1 == ~E_6~0); 26366#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26980#L1044-1 assume !(1 == ~E_8~0); 26548#L1049-1 assume { :end_inline_reset_delta_events } true; 26241#L1315-2 [2022-02-21 04:22:15,209 INFO L793 eck$LassoCheckResult]: Loop: 26241#L1315-2 assume !false; 26242#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26028#L841 assume !false; 26367#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26302#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26303#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26143#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26063#L724 assume !(0 != eval_~tmp~0#1); 26065#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26893#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26074#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26075#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26370#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26371#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26384#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26385#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26608#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26609#L896-3 assume !(0 == ~T7_E~0); 26476#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26477#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26610#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26813#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26416#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26417#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26797#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26483#L936-3 assume !(0 == ~E_6~0); 26484#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26625#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26372#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26373#L430-30 assume 1 == ~m_pc~0; 26397#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26398#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26181#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26182#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26831#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26835#L449-30 assume 1 == ~t1_pc~0; 26400#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26090#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26091#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26462#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26174#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26175#L468-30 assume 1 == ~t2_pc~0; 26266#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26267#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26876#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26599#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26600#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26450#L487-30 assume !(1 == ~t3_pc~0); 26245#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 26246#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26577#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26578#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26850#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26524#L506-30 assume !(1 == ~t4_pc~0); 26525#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 26551#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26552#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26569#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 26451#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26452#L525-30 assume 1 == ~t5_pc~0; 26937#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26938#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26156#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26157#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26455#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26225#L544-30 assume 1 == ~t6_pc~0; 26033#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26034#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27007#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26947#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26948#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26924#L563-30 assume 1 == ~t7_pc~0; 26195#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26196#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26214#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26540#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26541#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26911#L582-30 assume !(1 == ~t8_pc~0); 26292#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 26293#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26528#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26941#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27014#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26099#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26100#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26237#L969-3 assume !(1 == ~T2_E~0); 26228#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26229#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26640#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26641#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26274#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26275#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26784#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26146#L1009-3 assume !(1 == ~E_1~0); 26147#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26621#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26622#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26603#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26570#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26571#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26842#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26264#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26265#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26394#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26731#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 26298#L1334 assume !(0 == start_simulation_~tmp~3#1); 26300#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26318#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 26029#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 26030#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 26624#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26968#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26803#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 26804#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 26241#L1315-2 [2022-02-21 04:22:15,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:15,210 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2022-02-21 04:22:15,210 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:15,210 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312518534] [2022-02-21 04:22:15,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:15,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:15,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:15,230 INFO L290 TraceCheckUtils]: 0: Hoare triple {29022#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {29022#true} is VALID [2022-02-21 04:22:15,231 INFO L290 TraceCheckUtils]: 1: Hoare triple {29022#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,231 INFO L290 TraceCheckUtils]: 2: Hoare triple {29024#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,231 INFO L290 TraceCheckUtils]: 3: Hoare triple {29024#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,232 INFO L290 TraceCheckUtils]: 4: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,232 INFO L290 TraceCheckUtils]: 5: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,232 INFO L290 TraceCheckUtils]: 6: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,232 INFO L290 TraceCheckUtils]: 7: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,233 INFO L290 TraceCheckUtils]: 8: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,233 INFO L290 TraceCheckUtils]: 9: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,233 INFO L290 TraceCheckUtils]: 10: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,233 INFO L290 TraceCheckUtils]: 11: Hoare triple {29024#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {29024#(= ~t8_i~0 1)} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 12: Hoare triple {29024#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 13: Hoare triple {29023#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 14: Hoare triple {29023#false} assume !(0 == ~M_E~0); {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 15: Hoare triple {29023#false} assume !(0 == ~T1_E~0); {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 16: Hoare triple {29023#false} assume !(0 == ~T2_E~0); {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 17: Hoare triple {29023#false} assume !(0 == ~T3_E~0); {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 18: Hoare triple {29023#false} assume !(0 == ~T4_E~0); {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 19: Hoare triple {29023#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 20: Hoare triple {29023#false} assume !(0 == ~T6_E~0); {29023#false} is VALID [2022-02-21 04:22:15,234 INFO L290 TraceCheckUtils]: 21: Hoare triple {29023#false} assume !(0 == ~T7_E~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 22: Hoare triple {29023#false} assume !(0 == ~T8_E~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 23: Hoare triple {29023#false} assume !(0 == ~E_M~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 24: Hoare triple {29023#false} assume !(0 == ~E_1~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 25: Hoare triple {29023#false} assume !(0 == ~E_2~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 26: Hoare triple {29023#false} assume !(0 == ~E_3~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 27: Hoare triple {29023#false} assume 0 == ~E_4~0;~E_4~0 := 1; {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 28: Hoare triple {29023#false} assume !(0 == ~E_5~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 29: Hoare triple {29023#false} assume !(0 == ~E_6~0); {29023#false} is VALID [2022-02-21 04:22:15,235 INFO L290 TraceCheckUtils]: 30: Hoare triple {29023#false} assume !(0 == ~E_7~0); {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 31: Hoare triple {29023#false} assume !(0 == ~E_8~0); {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 32: Hoare triple {29023#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 33: Hoare triple {29023#false} assume !(1 == ~m_pc~0); {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 34: Hoare triple {29023#false} is_master_triggered_~__retres1~0#1 := 0; {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 35: Hoare triple {29023#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 36: Hoare triple {29023#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 37: Hoare triple {29023#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 38: Hoare triple {29023#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 39: Hoare triple {29023#false} assume 1 == ~t1_pc~0; {29023#false} is VALID [2022-02-21 04:22:15,236 INFO L290 TraceCheckUtils]: 40: Hoare triple {29023#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 41: Hoare triple {29023#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 42: Hoare triple {29023#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 43: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___0~0#1); {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 44: Hoare triple {29023#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 45: Hoare triple {29023#false} assume !(1 == ~t2_pc~0); {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 46: Hoare triple {29023#false} is_transmit2_triggered_~__retres1~2#1 := 0; {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 47: Hoare triple {29023#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 48: Hoare triple {29023#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 49: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___1~0#1); {29023#false} is VALID [2022-02-21 04:22:15,237 INFO L290 TraceCheckUtils]: 50: Hoare triple {29023#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 51: Hoare triple {29023#false} assume 1 == ~t3_pc~0; {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 52: Hoare triple {29023#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 53: Hoare triple {29023#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 54: Hoare triple {29023#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 55: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___2~0#1); {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 56: Hoare triple {29023#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 57: Hoare triple {29023#false} assume !(1 == ~t4_pc~0); {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 58: Hoare triple {29023#false} is_transmit4_triggered_~__retres1~4#1 := 0; {29023#false} is VALID [2022-02-21 04:22:15,238 INFO L290 TraceCheckUtils]: 59: Hoare triple {29023#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 60: Hoare triple {29023#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 61: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___3~0#1); {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 62: Hoare triple {29023#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 63: Hoare triple {29023#false} assume 1 == ~t5_pc~0; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 64: Hoare triple {29023#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 65: Hoare triple {29023#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 66: Hoare triple {29023#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 67: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___4~0#1); {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 68: Hoare triple {29023#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {29023#false} is VALID [2022-02-21 04:22:15,239 INFO L290 TraceCheckUtils]: 69: Hoare triple {29023#false} assume !(1 == ~t6_pc~0); {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 70: Hoare triple {29023#false} is_transmit6_triggered_~__retres1~6#1 := 0; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 71: Hoare triple {29023#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 72: Hoare triple {29023#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 73: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___5~0#1); {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 74: Hoare triple {29023#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 75: Hoare triple {29023#false} assume 1 == ~t7_pc~0; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 76: Hoare triple {29023#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 77: Hoare triple {29023#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 78: Hoare triple {29023#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {29023#false} is VALID [2022-02-21 04:22:15,240 INFO L290 TraceCheckUtils]: 79: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___6~0#1); {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 80: Hoare triple {29023#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 81: Hoare triple {29023#false} assume 1 == ~t8_pc~0; {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 82: Hoare triple {29023#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 83: Hoare triple {29023#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 84: Hoare triple {29023#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 85: Hoare triple {29023#false} assume !(0 != activate_threads_~tmp___7~0#1); {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 86: Hoare triple {29023#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 87: Hoare triple {29023#false} assume 1 == ~M_E~0;~M_E~0 := 2; {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 88: Hoare triple {29023#false} assume !(1 == ~T1_E~0); {29023#false} is VALID [2022-02-21 04:22:15,241 INFO L290 TraceCheckUtils]: 89: Hoare triple {29023#false} assume !(1 == ~T2_E~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 90: Hoare triple {29023#false} assume !(1 == ~T3_E~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 91: Hoare triple {29023#false} assume !(1 == ~T4_E~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 92: Hoare triple {29023#false} assume !(1 == ~T5_E~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 93: Hoare triple {29023#false} assume !(1 == ~T6_E~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 94: Hoare triple {29023#false} assume !(1 == ~T7_E~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 95: Hoare triple {29023#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 96: Hoare triple {29023#false} assume !(1 == ~E_M~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 97: Hoare triple {29023#false} assume !(1 == ~E_1~0); {29023#false} is VALID [2022-02-21 04:22:15,242 INFO L290 TraceCheckUtils]: 98: Hoare triple {29023#false} assume !(1 == ~E_2~0); {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L290 TraceCheckUtils]: 99: Hoare triple {29023#false} assume !(1 == ~E_3~0); {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L290 TraceCheckUtils]: 100: Hoare triple {29023#false} assume !(1 == ~E_4~0); {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L290 TraceCheckUtils]: 101: Hoare triple {29023#false} assume !(1 == ~E_5~0); {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L290 TraceCheckUtils]: 102: Hoare triple {29023#false} assume !(1 == ~E_6~0); {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L290 TraceCheckUtils]: 103: Hoare triple {29023#false} assume 1 == ~E_7~0;~E_7~0 := 2; {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L290 TraceCheckUtils]: 104: Hoare triple {29023#false} assume !(1 == ~E_8~0); {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L290 TraceCheckUtils]: 105: Hoare triple {29023#false} assume { :end_inline_reset_delta_events } true; {29023#false} is VALID [2022-02-21 04:22:15,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:15,244 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:15,244 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312518534] [2022-02-21 04:22:15,244 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312518534] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:15,245 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:15,245 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:15,245 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642232678] [2022-02-21 04:22:15,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:15,245 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:15,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:15,246 INFO L85 PathProgramCache]: Analyzing trace with hash -15808656, now seen corresponding path program 1 times [2022-02-21 04:22:15,246 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:15,249 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466569738] [2022-02-21 04:22:15,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:15,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:15,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 0: Hoare triple {29025#true} assume !false; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 1: Hoare triple {29025#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 2: Hoare triple {29025#true} assume !false; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 3: Hoare triple {29025#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 4: Hoare triple {29025#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 5: Hoare triple {29025#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 6: Hoare triple {29025#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 7: Hoare triple {29025#true} assume !(0 != eval_~tmp~0#1); {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 8: Hoare triple {29025#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 9: Hoare triple {29025#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 10: Hoare triple {29025#true} assume 0 == ~M_E~0;~M_E~0 := 1; {29025#true} is VALID [2022-02-21 04:22:15,282 INFO L290 TraceCheckUtils]: 11: Hoare triple {29025#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {29025#true} is VALID [2022-02-21 04:22:15,283 INFO L290 TraceCheckUtils]: 12: Hoare triple {29025#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,283 INFO L290 TraceCheckUtils]: 13: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,283 INFO L290 TraceCheckUtils]: 14: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,283 INFO L290 TraceCheckUtils]: 15: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,284 INFO L290 TraceCheckUtils]: 16: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,284 INFO L290 TraceCheckUtils]: 17: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,284 INFO L290 TraceCheckUtils]: 18: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,284 INFO L290 TraceCheckUtils]: 19: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,285 INFO L290 TraceCheckUtils]: 20: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,285 INFO L290 TraceCheckUtils]: 21: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,285 INFO L290 TraceCheckUtils]: 22: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,285 INFO L290 TraceCheckUtils]: 23: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,286 INFO L290 TraceCheckUtils]: 24: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,286 INFO L290 TraceCheckUtils]: 25: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,286 INFO L290 TraceCheckUtils]: 26: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,286 INFO L290 TraceCheckUtils]: 27: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,287 INFO L290 TraceCheckUtils]: 28: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,287 INFO L290 TraceCheckUtils]: 29: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,287 INFO L290 TraceCheckUtils]: 30: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,288 INFO L290 TraceCheckUtils]: 31: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,288 INFO L290 TraceCheckUtils]: 32: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,288 INFO L290 TraceCheckUtils]: 33: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,288 INFO L290 TraceCheckUtils]: 34: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,289 INFO L290 TraceCheckUtils]: 35: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,303 INFO L290 TraceCheckUtils]: 36: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,304 INFO L290 TraceCheckUtils]: 37: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,304 INFO L290 TraceCheckUtils]: 38: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,304 INFO L290 TraceCheckUtils]: 39: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,304 INFO L290 TraceCheckUtils]: 40: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,304 INFO L290 TraceCheckUtils]: 41: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,305 INFO L290 TraceCheckUtils]: 42: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,305 INFO L290 TraceCheckUtils]: 43: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,305 INFO L290 TraceCheckUtils]: 44: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,305 INFO L290 TraceCheckUtils]: 45: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,306 INFO L290 TraceCheckUtils]: 46: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,306 INFO L290 TraceCheckUtils]: 47: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,306 INFO L290 TraceCheckUtils]: 48: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,306 INFO L290 TraceCheckUtils]: 49: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,307 INFO L290 TraceCheckUtils]: 50: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,307 INFO L290 TraceCheckUtils]: 51: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,307 INFO L290 TraceCheckUtils]: 52: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,307 INFO L290 TraceCheckUtils]: 53: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,307 INFO L290 TraceCheckUtils]: 54: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,308 INFO L290 TraceCheckUtils]: 55: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,308 INFO L290 TraceCheckUtils]: 56: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,308 INFO L290 TraceCheckUtils]: 57: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,308 INFO L290 TraceCheckUtils]: 58: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,309 INFO L290 TraceCheckUtils]: 59: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,309 INFO L290 TraceCheckUtils]: 60: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,309 INFO L290 TraceCheckUtils]: 61: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,309 INFO L290 TraceCheckUtils]: 62: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,310 INFO L290 TraceCheckUtils]: 63: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,310 INFO L290 TraceCheckUtils]: 64: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,310 INFO L290 TraceCheckUtils]: 65: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,310 INFO L290 TraceCheckUtils]: 66: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,311 INFO L290 TraceCheckUtils]: 67: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,311 INFO L290 TraceCheckUtils]: 68: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,311 INFO L290 TraceCheckUtils]: 69: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,311 INFO L290 TraceCheckUtils]: 70: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,311 INFO L290 TraceCheckUtils]: 71: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,312 INFO L290 TraceCheckUtils]: 72: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,312 INFO L290 TraceCheckUtils]: 73: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,312 INFO L290 TraceCheckUtils]: 74: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,312 INFO L290 TraceCheckUtils]: 75: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,313 INFO L290 TraceCheckUtils]: 76: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,313 INFO L290 TraceCheckUtils]: 77: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,313 INFO L290 TraceCheckUtils]: 78: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,313 INFO L290 TraceCheckUtils]: 79: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,314 INFO L290 TraceCheckUtils]: 80: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,314 INFO L290 TraceCheckUtils]: 81: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,314 INFO L290 TraceCheckUtils]: 82: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,314 INFO L290 TraceCheckUtils]: 83: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,314 INFO L290 TraceCheckUtils]: 84: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {29027#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 85: Hoare triple {29027#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 86: Hoare triple {29026#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 87: Hoare triple {29026#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 88: Hoare triple {29026#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 89: Hoare triple {29026#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 90: Hoare triple {29026#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 91: Hoare triple {29026#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 92: Hoare triple {29026#false} assume 1 == ~E_M~0;~E_M~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 93: Hoare triple {29026#false} assume !(1 == ~E_1~0); {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 94: Hoare triple {29026#false} assume 1 == ~E_2~0;~E_2~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 95: Hoare triple {29026#false} assume 1 == ~E_3~0;~E_3~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 96: Hoare triple {29026#false} assume 1 == ~E_4~0;~E_4~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 97: Hoare triple {29026#false} assume 1 == ~E_5~0;~E_5~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 98: Hoare triple {29026#false} assume 1 == ~E_6~0;~E_6~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 99: Hoare triple {29026#false} assume 1 == ~E_7~0;~E_7~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 100: Hoare triple {29026#false} assume 1 == ~E_8~0;~E_8~0 := 2; {29026#false} is VALID [2022-02-21 04:22:15,315 INFO L290 TraceCheckUtils]: 101: Hoare triple {29026#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 102: Hoare triple {29026#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 103: Hoare triple {29026#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 104: Hoare triple {29026#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 105: Hoare triple {29026#false} assume !(0 == start_simulation_~tmp~3#1); {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 106: Hoare triple {29026#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 107: Hoare triple {29026#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 108: Hoare triple {29026#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 109: Hoare triple {29026#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 110: Hoare triple {29026#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 111: Hoare triple {29026#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 112: Hoare triple {29026#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L290 TraceCheckUtils]: 113: Hoare triple {29026#false} assume !(0 != start_simulation_~tmp___0~1#1); {29026#false} is VALID [2022-02-21 04:22:15,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:15,316 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:15,316 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466569738] [2022-02-21 04:22:15,316 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466569738] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:15,317 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:15,317 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:15,317 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217820660] [2022-02-21 04:22:15,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:15,317 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:15,317 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:15,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:15,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:15,317 INFO L87 Difference]: Start difference. First operand 998 states and 1484 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:15,904 INFO L93 Difference]: Finished difference Result 998 states and 1483 transitions. [2022-02-21 04:22:15,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:15,905 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,967 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:15,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1483 transitions. [2022-02-21 04:22:15,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:16,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1483 transitions. [2022-02-21 04:22:16,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2022-02-21 04:22:16,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2022-02-21 04:22:16,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1483 transitions. [2022-02-21 04:22:16,019 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:16,019 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2022-02-21 04:22:16,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1483 transitions. [2022-02-21 04:22:16,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2022-02-21 04:22:16,026 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:16,027 INFO L82 GeneralOperation]: Start isEquivalent. First operand 998 states and 1483 transitions. Second operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,028 INFO L74 IsIncluded]: Start isIncluded. First operand 998 states and 1483 transitions. Second operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,029 INFO L87 Difference]: Start difference. First operand 998 states and 1483 transitions. Second operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:16,052 INFO L93 Difference]: Finished difference Result 998 states and 1483 transitions. [2022-02-21 04:22:16,052 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1483 transitions. [2022-02-21 04:22:16,053 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:16,053 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:16,054 INFO L74 IsIncluded]: Start isIncluded. First operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1483 transitions. [2022-02-21 04:22:16,055 INFO L87 Difference]: Start difference. First operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 998 states and 1483 transitions. [2022-02-21 04:22:16,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:16,078 INFO L93 Difference]: Finished difference Result 998 states and 1483 transitions. [2022-02-21 04:22:16,078 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1483 transitions. [2022-02-21 04:22:16,079 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:16,079 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:16,079 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:16,079 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:16,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1483 transitions. [2022-02-21 04:22:16,102 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2022-02-21 04:22:16,102 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2022-02-21 04:22:16,103 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:22:16,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1483 transitions. [2022-02-21 04:22:16,105 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2022-02-21 04:22:16,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:16,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:16,106 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:16,106 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:16,106 INFO L791 eck$LassoCheckResult]: Stem: 30796#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 30797#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 30723#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30724#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30576#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 30577#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30162#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30163#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30244#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30955#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30132#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30133#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30540#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30565#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30248#L866 assume !(0 == ~M_E~0); 30249#L866-2 assume !(0 == ~T1_E~0); 30751#L871-1 assume !(0 == ~T2_E~0); 30752#L876-1 assume !(0 == ~T3_E~0); 31002#L881-1 assume !(0 == ~T4_E~0); 30761#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30531#L891-1 assume !(0 == ~T6_E~0); 30532#L896-1 assume !(0 == ~T7_E~0); 30754#L901-1 assume !(0 == ~T8_E~0); 30772#L906-1 assume !(0 == ~E_M~0); 30773#L911-1 assume !(0 == ~E_1~0); 30574#L916-1 assume !(0 == ~E_2~0); 30575#L921-1 assume !(0 == ~E_3~0); 30868#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30967#L931-1 assume !(0 == ~E_5~0); 31007#L936-1 assume !(0 == ~E_6~0); 31014#L941-1 assume !(0 == ~E_7~0); 30580#L946-1 assume !(0 == ~E_8~0); 30581#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30986#L430 assume !(1 == ~m_pc~0); 30439#L430-2 is_master_triggered_~__retres1~0#1 := 0; 30067#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30068#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30681#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30691#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30852#L449 assume 1 == ~t1_pc~0; 30853#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30252#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30026#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30027#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 30787#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30636#L468 assume !(1 == ~t2_pc~0); 30051#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30050#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30539#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30446#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 30069#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30070#L487 assume 1 == ~t3_pc~0; 30999#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30166#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30167#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30841#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 30505#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30506#L506 assume !(1 == ~t4_pc~0); 30632#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30677#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30977#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30978#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 30627#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30457#L525 assume 1 == ~t5_pc~0; 30392#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30111#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30584#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30585#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 30308#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30309#L544 assume !(1 == ~t6_pc~0); 30458#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30459#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30803#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30093#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 30094#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30943#L563 assume 1 == ~t7_pc~0; 30821#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30121#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30122#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30533#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 30253#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30254#L582 assume 1 == ~t8_pc~0; 30177#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30178#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31000#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30494#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 30396#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30397#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 30855#L964-2 assume !(1 == ~T1_E~0); 30310#L969-1 assume !(1 == ~T2_E~0); 30311#L974-1 assume !(1 == ~T3_E~0); 30880#L979-1 assume !(1 == ~T4_E~0); 30881#L984-1 assume !(1 == ~T5_E~0); 30464#L989-1 assume !(1 == ~T6_E~0); 30465#L994-1 assume !(1 == ~T7_E~0); 30350#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30351#L1004-1 assume !(1 == ~E_M~0); 30095#L1009-1 assume !(1 == ~E_1~0); 30096#L1014-1 assume !(1 == ~E_2~0); 30339#L1019-1 assume !(1 == ~E_3~0); 30844#L1024-1 assume !(1 == ~E_4~0); 30272#L1029-1 assume !(1 == ~E_5~0); 30273#L1034-1 assume !(1 == ~E_6~0); 30367#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30981#L1044-1 assume !(1 == ~E_8~0); 30549#L1049-1 assume { :end_inline_reset_delta_events } true; 30242#L1315-2 [2022-02-21 04:22:16,107 INFO L793 eck$LassoCheckResult]: Loop: 30242#L1315-2 assume !false; 30243#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30029#L841 assume !false; 30368#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 30303#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 30304#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 30144#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30064#L724 assume !(0 != eval_~tmp~0#1); 30066#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30894#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30075#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30076#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30371#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30372#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30385#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30386#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30609#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30610#L896-3 assume !(0 == ~T7_E~0); 30477#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30478#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30611#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30814#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30417#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30418#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30798#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30484#L936-3 assume !(0 == ~E_6~0); 30485#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30626#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30373#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30374#L430-30 assume !(1 == ~m_pc~0); 30400#L430-32 is_master_triggered_~__retres1~0#1 := 0; 30399#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30182#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30183#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30832#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30836#L449-30 assume 1 == ~t1_pc~0; 30401#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30091#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30092#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30463#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30175#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30176#L468-30 assume 1 == ~t2_pc~0; 30267#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30268#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30877#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30600#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30601#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30451#L487-30 assume 1 == ~t3_pc~0; 30432#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30247#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30578#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30579#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30851#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30525#L506-30 assume !(1 == ~t4_pc~0); 30526#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 30552#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30553#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30570#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 30452#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30453#L525-30 assume 1 == ~t5_pc~0; 30938#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30939#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30157#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30158#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30456#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30226#L544-30 assume 1 == ~t6_pc~0; 30034#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30035#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31008#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30948#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30949#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30925#L563-30 assume 1 == ~t7_pc~0; 30196#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30197#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30215#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30541#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30542#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30912#L582-30 assume !(1 == ~t8_pc~0); 30293#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 30294#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30529#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30942#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31015#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30100#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30101#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30238#L969-3 assume !(1 == ~T2_E~0); 30229#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30230#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30641#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30642#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30275#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30276#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30785#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30147#L1009-3 assume !(1 == ~E_1~0); 30148#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30622#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30623#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30604#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30571#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30572#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30843#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30265#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 30266#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 30395#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 30732#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 30299#L1334 assume !(0 == start_simulation_~tmp~3#1); 30301#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 30319#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 30030#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 30031#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 30625#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30969#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30804#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 30805#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 30242#L1315-2 [2022-02-21 04:22:16,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:16,107 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2022-02-21 04:22:16,107 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:16,107 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092294527] [2022-02-21 04:22:16,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:16,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:16,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:16,138 INFO L290 TraceCheckUtils]: 0: Hoare triple {33023#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,139 INFO L290 TraceCheckUtils]: 1: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,139 INFO L290 TraceCheckUtils]: 2: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,139 INFO L290 TraceCheckUtils]: 3: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,140 INFO L290 TraceCheckUtils]: 4: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,140 INFO L290 TraceCheckUtils]: 5: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,140 INFO L290 TraceCheckUtils]: 6: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,140 INFO L290 TraceCheckUtils]: 7: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,141 INFO L290 TraceCheckUtils]: 8: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,141 INFO L290 TraceCheckUtils]: 9: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,141 INFO L290 TraceCheckUtils]: 10: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,141 INFO L290 TraceCheckUtils]: 11: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,142 INFO L290 TraceCheckUtils]: 12: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,142 INFO L290 TraceCheckUtils]: 13: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {33025#(= ~T5_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:16,142 INFO L290 TraceCheckUtils]: 14: Hoare triple {33025#(= ~T5_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {33026#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:16,143 INFO L290 TraceCheckUtils]: 15: Hoare triple {33026#(not (= ~T5_E~0 0))} assume !(0 == ~T1_E~0); {33026#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:16,143 INFO L290 TraceCheckUtils]: 16: Hoare triple {33026#(not (= ~T5_E~0 0))} assume !(0 == ~T2_E~0); {33026#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:16,143 INFO L290 TraceCheckUtils]: 17: Hoare triple {33026#(not (= ~T5_E~0 0))} assume !(0 == ~T3_E~0); {33026#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:16,143 INFO L290 TraceCheckUtils]: 18: Hoare triple {33026#(not (= ~T5_E~0 0))} assume !(0 == ~T4_E~0); {33026#(not (= ~T5_E~0 0))} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 19: Hoare triple {33026#(not (= ~T5_E~0 0))} assume 0 == ~T5_E~0;~T5_E~0 := 1; {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 20: Hoare triple {33024#false} assume !(0 == ~T6_E~0); {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 21: Hoare triple {33024#false} assume !(0 == ~T7_E~0); {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 22: Hoare triple {33024#false} assume !(0 == ~T8_E~0); {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 23: Hoare triple {33024#false} assume !(0 == ~E_M~0); {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 24: Hoare triple {33024#false} assume !(0 == ~E_1~0); {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 25: Hoare triple {33024#false} assume !(0 == ~E_2~0); {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 26: Hoare triple {33024#false} assume !(0 == ~E_3~0); {33024#false} is VALID [2022-02-21 04:22:16,144 INFO L290 TraceCheckUtils]: 27: Hoare triple {33024#false} assume 0 == ~E_4~0;~E_4~0 := 1; {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 28: Hoare triple {33024#false} assume !(0 == ~E_5~0); {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 29: Hoare triple {33024#false} assume !(0 == ~E_6~0); {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 30: Hoare triple {33024#false} assume !(0 == ~E_7~0); {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 31: Hoare triple {33024#false} assume !(0 == ~E_8~0); {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 32: Hoare triple {33024#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 33: Hoare triple {33024#false} assume !(1 == ~m_pc~0); {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 34: Hoare triple {33024#false} is_master_triggered_~__retres1~0#1 := 0; {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 35: Hoare triple {33024#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 36: Hoare triple {33024#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {33024#false} is VALID [2022-02-21 04:22:16,145 INFO L290 TraceCheckUtils]: 37: Hoare triple {33024#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 38: Hoare triple {33024#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 39: Hoare triple {33024#false} assume 1 == ~t1_pc~0; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 40: Hoare triple {33024#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 41: Hoare triple {33024#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 42: Hoare triple {33024#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 43: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___0~0#1); {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 44: Hoare triple {33024#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 45: Hoare triple {33024#false} assume !(1 == ~t2_pc~0); {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 46: Hoare triple {33024#false} is_transmit2_triggered_~__retres1~2#1 := 0; {33024#false} is VALID [2022-02-21 04:22:16,146 INFO L290 TraceCheckUtils]: 47: Hoare triple {33024#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 48: Hoare triple {33024#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 49: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___1~0#1); {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 50: Hoare triple {33024#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 51: Hoare triple {33024#false} assume 1 == ~t3_pc~0; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 52: Hoare triple {33024#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 53: Hoare triple {33024#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 54: Hoare triple {33024#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 55: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___2~0#1); {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 56: Hoare triple {33024#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {33024#false} is VALID [2022-02-21 04:22:16,147 INFO L290 TraceCheckUtils]: 57: Hoare triple {33024#false} assume !(1 == ~t4_pc~0); {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 58: Hoare triple {33024#false} is_transmit4_triggered_~__retres1~4#1 := 0; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 59: Hoare triple {33024#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 60: Hoare triple {33024#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 61: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___3~0#1); {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 62: Hoare triple {33024#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 63: Hoare triple {33024#false} assume 1 == ~t5_pc~0; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 64: Hoare triple {33024#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 65: Hoare triple {33024#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 66: Hoare triple {33024#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {33024#false} is VALID [2022-02-21 04:22:16,148 INFO L290 TraceCheckUtils]: 67: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___4~0#1); {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 68: Hoare triple {33024#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 69: Hoare triple {33024#false} assume !(1 == ~t6_pc~0); {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 70: Hoare triple {33024#false} is_transmit6_triggered_~__retres1~6#1 := 0; {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 71: Hoare triple {33024#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 72: Hoare triple {33024#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 73: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___5~0#1); {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 74: Hoare triple {33024#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 75: Hoare triple {33024#false} assume 1 == ~t7_pc~0; {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 76: Hoare triple {33024#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {33024#false} is VALID [2022-02-21 04:22:16,149 INFO L290 TraceCheckUtils]: 77: Hoare triple {33024#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 78: Hoare triple {33024#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 79: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___6~0#1); {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 80: Hoare triple {33024#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 81: Hoare triple {33024#false} assume 1 == ~t8_pc~0; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 82: Hoare triple {33024#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 83: Hoare triple {33024#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 84: Hoare triple {33024#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 85: Hoare triple {33024#false} assume !(0 != activate_threads_~tmp___7~0#1); {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 86: Hoare triple {33024#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {33024#false} is VALID [2022-02-21 04:22:16,150 INFO L290 TraceCheckUtils]: 87: Hoare triple {33024#false} assume 1 == ~M_E~0;~M_E~0 := 2; {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 88: Hoare triple {33024#false} assume !(1 == ~T1_E~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 89: Hoare triple {33024#false} assume !(1 == ~T2_E~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 90: Hoare triple {33024#false} assume !(1 == ~T3_E~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 91: Hoare triple {33024#false} assume !(1 == ~T4_E~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 92: Hoare triple {33024#false} assume !(1 == ~T5_E~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 93: Hoare triple {33024#false} assume !(1 == ~T6_E~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 94: Hoare triple {33024#false} assume !(1 == ~T7_E~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 95: Hoare triple {33024#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 96: Hoare triple {33024#false} assume !(1 == ~E_M~0); {33024#false} is VALID [2022-02-21 04:22:16,151 INFO L290 TraceCheckUtils]: 97: Hoare triple {33024#false} assume !(1 == ~E_1~0); {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 98: Hoare triple {33024#false} assume !(1 == ~E_2~0); {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 99: Hoare triple {33024#false} assume !(1 == ~E_3~0); {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 100: Hoare triple {33024#false} assume !(1 == ~E_4~0); {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 101: Hoare triple {33024#false} assume !(1 == ~E_5~0); {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 102: Hoare triple {33024#false} assume !(1 == ~E_6~0); {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 103: Hoare triple {33024#false} assume 1 == ~E_7~0;~E_7~0 := 2; {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 104: Hoare triple {33024#false} assume !(1 == ~E_8~0); {33024#false} is VALID [2022-02-21 04:22:16,152 INFO L290 TraceCheckUtils]: 105: Hoare triple {33024#false} assume { :end_inline_reset_delta_events } true; {33024#false} is VALID [2022-02-21 04:22:16,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:16,153 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:16,153 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092294527] [2022-02-21 04:22:16,153 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1092294527] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:16,153 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:16,153 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:16,153 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43654736] [2022-02-21 04:22:16,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:16,154 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:16,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:16,154 INFO L85 PathProgramCache]: Analyzing trace with hash 924477744, now seen corresponding path program 1 times [2022-02-21 04:22:16,154 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:16,154 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852522576] [2022-02-21 04:22:16,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:16,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:16,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:16,179 INFO L290 TraceCheckUtils]: 0: Hoare triple {33027#true} assume !false; {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 1: Hoare triple {33027#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 2: Hoare triple {33027#true} assume !false; {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 3: Hoare triple {33027#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 4: Hoare triple {33027#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 5: Hoare triple {33027#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 6: Hoare triple {33027#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 7: Hoare triple {33027#true} assume !(0 != eval_~tmp~0#1); {33027#true} is VALID [2022-02-21 04:22:16,180 INFO L290 TraceCheckUtils]: 8: Hoare triple {33027#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {33027#true} is VALID [2022-02-21 04:22:16,181 INFO L290 TraceCheckUtils]: 9: Hoare triple {33027#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {33027#true} is VALID [2022-02-21 04:22:16,181 INFO L290 TraceCheckUtils]: 10: Hoare triple {33027#true} assume 0 == ~M_E~0;~M_E~0 := 1; {33027#true} is VALID [2022-02-21 04:22:16,181 INFO L290 TraceCheckUtils]: 11: Hoare triple {33027#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {33027#true} is VALID [2022-02-21 04:22:16,181 INFO L290 TraceCheckUtils]: 12: Hoare triple {33027#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,181 INFO L290 TraceCheckUtils]: 13: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,182 INFO L290 TraceCheckUtils]: 14: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,182 INFO L290 TraceCheckUtils]: 15: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,182 INFO L290 TraceCheckUtils]: 16: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,182 INFO L290 TraceCheckUtils]: 17: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,183 INFO L290 TraceCheckUtils]: 18: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,183 INFO L290 TraceCheckUtils]: 19: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,183 INFO L290 TraceCheckUtils]: 20: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,183 INFO L290 TraceCheckUtils]: 21: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,184 INFO L290 TraceCheckUtils]: 22: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,184 INFO L290 TraceCheckUtils]: 23: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,184 INFO L290 TraceCheckUtils]: 24: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,184 INFO L290 TraceCheckUtils]: 25: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,185 INFO L290 TraceCheckUtils]: 26: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,185 INFO L290 TraceCheckUtils]: 27: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,185 INFO L290 TraceCheckUtils]: 28: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,185 INFO L290 TraceCheckUtils]: 29: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,186 INFO L290 TraceCheckUtils]: 30: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,186 INFO L290 TraceCheckUtils]: 31: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,186 INFO L290 TraceCheckUtils]: 32: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,187 INFO L290 TraceCheckUtils]: 33: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,187 INFO L290 TraceCheckUtils]: 34: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,187 INFO L290 TraceCheckUtils]: 35: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,187 INFO L290 TraceCheckUtils]: 36: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,188 INFO L290 TraceCheckUtils]: 37: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,188 INFO L290 TraceCheckUtils]: 38: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,188 INFO L290 TraceCheckUtils]: 39: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,188 INFO L290 TraceCheckUtils]: 40: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,189 INFO L290 TraceCheckUtils]: 41: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,189 INFO L290 TraceCheckUtils]: 42: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,189 INFO L290 TraceCheckUtils]: 43: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,189 INFO L290 TraceCheckUtils]: 44: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,190 INFO L290 TraceCheckUtils]: 45: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,190 INFO L290 TraceCheckUtils]: 46: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,190 INFO L290 TraceCheckUtils]: 47: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,190 INFO L290 TraceCheckUtils]: 48: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,191 INFO L290 TraceCheckUtils]: 49: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,191 INFO L290 TraceCheckUtils]: 50: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,191 INFO L290 TraceCheckUtils]: 51: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,191 INFO L290 TraceCheckUtils]: 52: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,192 INFO L290 TraceCheckUtils]: 53: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,192 INFO L290 TraceCheckUtils]: 54: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,192 INFO L290 TraceCheckUtils]: 55: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,193 INFO L290 TraceCheckUtils]: 56: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,193 INFO L290 TraceCheckUtils]: 57: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,193 INFO L290 TraceCheckUtils]: 58: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,193 INFO L290 TraceCheckUtils]: 59: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,194 INFO L290 TraceCheckUtils]: 60: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,194 INFO L290 TraceCheckUtils]: 61: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,194 INFO L290 TraceCheckUtils]: 62: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,194 INFO L290 TraceCheckUtils]: 63: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,195 INFO L290 TraceCheckUtils]: 64: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,195 INFO L290 TraceCheckUtils]: 65: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,195 INFO L290 TraceCheckUtils]: 66: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,195 INFO L290 TraceCheckUtils]: 67: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,196 INFO L290 TraceCheckUtils]: 68: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,196 INFO L290 TraceCheckUtils]: 69: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,196 INFO L290 TraceCheckUtils]: 70: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,196 INFO L290 TraceCheckUtils]: 71: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,197 INFO L290 TraceCheckUtils]: 72: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,197 INFO L290 TraceCheckUtils]: 73: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,197 INFO L290 TraceCheckUtils]: 74: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,197 INFO L290 TraceCheckUtils]: 75: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,198 INFO L290 TraceCheckUtils]: 76: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,198 INFO L290 TraceCheckUtils]: 77: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,198 INFO L290 TraceCheckUtils]: 78: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,198 INFO L290 TraceCheckUtils]: 79: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,199 INFO L290 TraceCheckUtils]: 80: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,199 INFO L290 TraceCheckUtils]: 81: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,199 INFO L290 TraceCheckUtils]: 82: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,200 INFO L290 TraceCheckUtils]: 83: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,200 INFO L290 TraceCheckUtils]: 84: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {33029#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:16,200 INFO L290 TraceCheckUtils]: 85: Hoare triple {33029#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {33028#false} is VALID [2022-02-21 04:22:16,200 INFO L290 TraceCheckUtils]: 86: Hoare triple {33028#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,200 INFO L290 TraceCheckUtils]: 87: Hoare triple {33028#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,200 INFO L290 TraceCheckUtils]: 88: Hoare triple {33028#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 89: Hoare triple {33028#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 90: Hoare triple {33028#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 91: Hoare triple {33028#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 92: Hoare triple {33028#false} assume 1 == ~E_M~0;~E_M~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 93: Hoare triple {33028#false} assume !(1 == ~E_1~0); {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 94: Hoare triple {33028#false} assume 1 == ~E_2~0;~E_2~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 95: Hoare triple {33028#false} assume 1 == ~E_3~0;~E_3~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 96: Hoare triple {33028#false} assume 1 == ~E_4~0;~E_4~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 97: Hoare triple {33028#false} assume 1 == ~E_5~0;~E_5~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 98: Hoare triple {33028#false} assume 1 == ~E_6~0;~E_6~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,201 INFO L290 TraceCheckUtils]: 99: Hoare triple {33028#false} assume 1 == ~E_7~0;~E_7~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 100: Hoare triple {33028#false} assume 1 == ~E_8~0;~E_8~0 := 2; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 101: Hoare triple {33028#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 102: Hoare triple {33028#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 103: Hoare triple {33028#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 104: Hoare triple {33028#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 105: Hoare triple {33028#false} assume !(0 == start_simulation_~tmp~3#1); {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 106: Hoare triple {33028#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 107: Hoare triple {33028#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {33028#false} is VALID [2022-02-21 04:22:16,202 INFO L290 TraceCheckUtils]: 108: Hoare triple {33028#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {33028#false} is VALID [2022-02-21 04:22:16,203 INFO L290 TraceCheckUtils]: 109: Hoare triple {33028#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {33028#false} is VALID [2022-02-21 04:22:16,203 INFO L290 TraceCheckUtils]: 110: Hoare triple {33028#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {33028#false} is VALID [2022-02-21 04:22:16,203 INFO L290 TraceCheckUtils]: 111: Hoare triple {33028#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {33028#false} is VALID [2022-02-21 04:22:16,203 INFO L290 TraceCheckUtils]: 112: Hoare triple {33028#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {33028#false} is VALID [2022-02-21 04:22:16,203 INFO L290 TraceCheckUtils]: 113: Hoare triple {33028#false} assume !(0 != start_simulation_~tmp___0~1#1); {33028#false} is VALID [2022-02-21 04:22:16,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:16,203 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:16,203 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852522576] [2022-02-21 04:22:16,204 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852522576] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:16,204 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:16,204 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:16,204 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638730231] [2022-02-21 04:22:16,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:16,204 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:16,204 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:16,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:16,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:16,205 INFO L87 Difference]: Start difference. First operand 998 states and 1483 transitions. cyclomatic complexity: 486 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:17,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:17,948 INFO L93 Difference]: Finished difference Result 1816 states and 2689 transitions. [2022-02-21 04:22:17,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:17,948 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:17,997 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:17,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,075 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2022-02-21 04:22:18,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1816 states to 1816 states and 2689 transitions. [2022-02-21 04:22:18,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1816 [2022-02-21 04:22:18,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1816 [2022-02-21 04:22:18,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,148 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:18,148 INFO L681 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2022-02-21 04:22:18,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1816 to 1816. [2022-02-21 04:22:18,162 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:18,164 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1816 states and 2689 transitions. Second operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,165 INFO L74 IsIncluded]: Start isIncluded. First operand 1816 states and 2689 transitions. Second operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,166 INFO L87 Difference]: Start difference. First operand 1816 states and 2689 transitions. Second operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:18,234 INFO L93 Difference]: Finished difference Result 1816 states and 2689 transitions. [2022-02-21 04:22:18,234 INFO L276 IsEmpty]: Start isEmpty. Operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,236 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:18,236 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:18,238 INFO L74 IsIncluded]: Start isIncluded. First operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,239 INFO L87 Difference]: Start difference. First operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:18,308 INFO L93 Difference]: Finished difference Result 1816 states and 2689 transitions. [2022-02-21 04:22:18,308 INFO L276 IsEmpty]: Start isEmpty. Operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,310 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:18,310 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:18,310 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:18,310 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:18,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1816 states to 1816 states and 2689 transitions. [2022-02-21 04:22:18,380 INFO L704 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2022-02-21 04:22:18,380 INFO L587 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2022-02-21 04:22:18,380 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:22:18,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1816 states and 2689 transitions. [2022-02-21 04:22:18,383 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2022-02-21 04:22:18,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:18,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:18,384 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:18,384 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:18,385 INFO L791 eck$LassoCheckResult]: Stem: 35622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 35623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 35547#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35548#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35399#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 35400#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34984#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34985#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35066#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35784#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34954#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34955#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35362#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35388#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35070#L866 assume !(0 == ~M_E~0); 35071#L866-2 assume !(0 == ~T1_E~0); 35575#L871-1 assume !(0 == ~T2_E~0); 35576#L876-1 assume !(0 == ~T3_E~0); 35832#L881-1 assume !(0 == ~T4_E~0); 35586#L886-1 assume !(0 == ~T5_E~0); 35353#L891-1 assume !(0 == ~T6_E~0); 35354#L896-1 assume !(0 == ~T7_E~0); 35578#L901-1 assume !(0 == ~T8_E~0); 35598#L906-1 assume !(0 == ~E_M~0); 35599#L911-1 assume !(0 == ~E_1~0); 35397#L916-1 assume !(0 == ~E_2~0); 35398#L921-1 assume !(0 == ~E_3~0); 35696#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 35796#L931-1 assume !(0 == ~E_5~0); 35837#L936-1 assume !(0 == ~E_6~0); 35845#L941-1 assume !(0 == ~E_7~0); 35403#L946-1 assume !(0 == ~E_8~0); 35404#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35815#L430 assume !(1 == ~m_pc~0); 35261#L430-2 is_master_triggered_~__retres1~0#1 := 0; 34889#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34890#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35504#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35514#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35679#L449 assume 1 == ~t1_pc~0; 35680#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35074#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34848#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34849#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 35613#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35459#L468 assume !(1 == ~t2_pc~0); 34873#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34872#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35361#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35268#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 34891#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34892#L487 assume 1 == ~t3_pc~0; 35828#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34988#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34989#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35668#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 35327#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35328#L506 assume !(1 == ~t4_pc~0); 35455#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35500#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35806#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35807#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 35450#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35279#L525 assume 1 == ~t5_pc~0; 35214#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34933#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35407#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35408#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 35130#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35131#L544 assume !(1 == ~t6_pc~0); 35280#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35281#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35629#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34915#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 34916#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35772#L563 assume 1 == ~t7_pc~0; 35647#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34943#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34944#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35355#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 35075#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35076#L582 assume 1 == ~t8_pc~0; 34999#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35000#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35829#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35316#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 35218#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35219#L964 assume !(1 == ~M_E~0); 35682#L964-2 assume !(1 == ~T1_E~0); 36079#L969-1 assume !(1 == ~T2_E~0); 36074#L974-1 assume !(1 == ~T3_E~0); 36070#L979-1 assume !(1 == ~T4_E~0); 36066#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35286#L989-1 assume !(1 == ~T6_E~0); 35287#L994-1 assume !(1 == ~T7_E~0); 35172#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35173#L1004-1 assume !(1 == ~E_M~0); 34917#L1009-1 assume !(1 == ~E_1~0); 34918#L1014-1 assume !(1 == ~E_2~0); 35161#L1019-1 assume !(1 == ~E_3~0); 35671#L1024-1 assume !(1 == ~E_4~0); 35094#L1029-1 assume !(1 == ~E_5~0); 35095#L1034-1 assume !(1 == ~E_6~0); 35189#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 35810#L1044-1 assume !(1 == ~E_8~0); 35371#L1049-1 assume { :end_inline_reset_delta_events } true; 35372#L1315-2 [2022-02-21 04:22:18,385 INFO L793 eck$LassoCheckResult]: Loop: 35372#L1315-2 assume !false; 35874#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35873#L841 assume !false; 35872#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 35867#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 35862#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 35861#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35859#L724 assume !(0 != eval_~tmp~0#1); 35858#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35857#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35856#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35830#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35193#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35194#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35207#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35208#L886-3 assume !(0 == ~T5_E~0); 35432#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35433#L896-3 assume !(0 == ~T7_E~0); 35299#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35300#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35434#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35640#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35239#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35240#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35624#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35306#L936-3 assume !(0 == ~E_6~0); 35307#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35449#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35195#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35196#L430-30 assume 1 == ~m_pc~0; 35220#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35221#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35004#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35005#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35659#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35663#L449-30 assume 1 == ~t1_pc~0; 35223#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34913#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34914#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35285#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34997#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34998#L468-30 assume 1 == ~t2_pc~0; 35089#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35090#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35705#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35423#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35424#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35273#L487-30 assume 1 == ~t3_pc~0; 35254#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35069#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35401#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35402#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35678#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35347#L506-30 assume !(1 == ~t4_pc~0); 35348#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 35375#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35376#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35393#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 35274#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35275#L525-30 assume 1 == ~t5_pc~0; 35767#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35768#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34979#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34980#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35758#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36385#L544-30 assume !(1 == ~t6_pc~0); 36384#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 36382#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36381#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36380#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35855#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35753#L563-30 assume 1 == ~t7_pc~0; 35018#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35019#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35037#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35363#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35364#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35740#L582-30 assume 1 == ~t8_pc~0; 35702#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35116#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35351#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35771#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35846#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34922#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34923#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35060#L969-3 assume !(1 == ~T2_E~0); 35051#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35052#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35464#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35465#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35097#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35098#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35611#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34969#L1009-3 assume !(1 == ~E_1~0); 34970#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35445#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35446#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35427#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35394#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35395#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35670#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35087#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 35088#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 35217#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 35556#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 35121#L1334 assume !(0 == start_simulation_~tmp~3#1); 35123#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 35141#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 34852#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 34853#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 35448#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35798#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35630#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 35631#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 35372#L1315-2 [2022-02-21 04:22:18,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:18,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2022-02-21 04:22:18,385 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:18,386 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831524027] [2022-02-21 04:22:18,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:18,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:18,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:18,407 INFO L290 TraceCheckUtils]: 0: Hoare triple {40299#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,408 INFO L290 TraceCheckUtils]: 1: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,408 INFO L290 TraceCheckUtils]: 2: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,408 INFO L290 TraceCheckUtils]: 3: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,408 INFO L290 TraceCheckUtils]: 4: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,409 INFO L290 TraceCheckUtils]: 5: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,409 INFO L290 TraceCheckUtils]: 6: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,409 INFO L290 TraceCheckUtils]: 7: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,409 INFO L290 TraceCheckUtils]: 8: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,410 INFO L290 TraceCheckUtils]: 9: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,410 INFO L290 TraceCheckUtils]: 10: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,410 INFO L290 TraceCheckUtils]: 11: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,410 INFO L290 TraceCheckUtils]: 12: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,411 INFO L290 TraceCheckUtils]: 13: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {40301#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:22:18,411 INFO L290 TraceCheckUtils]: 14: Hoare triple {40301#(= ~E_4~0 ~M_E~0)} assume !(0 == ~M_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,411 INFO L290 TraceCheckUtils]: 15: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T1_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,411 INFO L290 TraceCheckUtils]: 16: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T2_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,412 INFO L290 TraceCheckUtils]: 17: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T3_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,412 INFO L290 TraceCheckUtils]: 18: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T4_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,412 INFO L290 TraceCheckUtils]: 19: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T5_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,412 INFO L290 TraceCheckUtils]: 20: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T6_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,413 INFO L290 TraceCheckUtils]: 21: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T7_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,413 INFO L290 TraceCheckUtils]: 22: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~T8_E~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,413 INFO L290 TraceCheckUtils]: 23: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~E_M~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,413 INFO L290 TraceCheckUtils]: 24: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~E_1~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,414 INFO L290 TraceCheckUtils]: 25: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~E_2~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,414 INFO L290 TraceCheckUtils]: 26: Hoare triple {40302#(not (= ~E_4~0 0))} assume !(0 == ~E_3~0); {40302#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:22:18,414 INFO L290 TraceCheckUtils]: 27: Hoare triple {40302#(not (= ~E_4~0 0))} assume 0 == ~E_4~0;~E_4~0 := 1; {40300#false} is VALID [2022-02-21 04:22:18,414 INFO L290 TraceCheckUtils]: 28: Hoare triple {40300#false} assume !(0 == ~E_5~0); {40300#false} is VALID [2022-02-21 04:22:18,414 INFO L290 TraceCheckUtils]: 29: Hoare triple {40300#false} assume !(0 == ~E_6~0); {40300#false} is VALID [2022-02-21 04:22:18,414 INFO L290 TraceCheckUtils]: 30: Hoare triple {40300#false} assume !(0 == ~E_7~0); {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 31: Hoare triple {40300#false} assume !(0 == ~E_8~0); {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 32: Hoare triple {40300#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 33: Hoare triple {40300#false} assume !(1 == ~m_pc~0); {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 34: Hoare triple {40300#false} is_master_triggered_~__retres1~0#1 := 0; {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 35: Hoare triple {40300#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 36: Hoare triple {40300#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 37: Hoare triple {40300#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 38: Hoare triple {40300#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 39: Hoare triple {40300#false} assume 1 == ~t1_pc~0; {40300#false} is VALID [2022-02-21 04:22:18,415 INFO L290 TraceCheckUtils]: 40: Hoare triple {40300#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 41: Hoare triple {40300#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 42: Hoare triple {40300#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 43: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___0~0#1); {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 44: Hoare triple {40300#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 45: Hoare triple {40300#false} assume !(1 == ~t2_pc~0); {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 46: Hoare triple {40300#false} is_transmit2_triggered_~__retres1~2#1 := 0; {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 47: Hoare triple {40300#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 48: Hoare triple {40300#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 49: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___1~0#1); {40300#false} is VALID [2022-02-21 04:22:18,416 INFO L290 TraceCheckUtils]: 50: Hoare triple {40300#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 51: Hoare triple {40300#false} assume 1 == ~t3_pc~0; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 52: Hoare triple {40300#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 53: Hoare triple {40300#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 54: Hoare triple {40300#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 55: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___2~0#1); {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 56: Hoare triple {40300#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 57: Hoare triple {40300#false} assume !(1 == ~t4_pc~0); {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 58: Hoare triple {40300#false} is_transmit4_triggered_~__retres1~4#1 := 0; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 59: Hoare triple {40300#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 60: Hoare triple {40300#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40300#false} is VALID [2022-02-21 04:22:18,417 INFO L290 TraceCheckUtils]: 61: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___3~0#1); {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 62: Hoare triple {40300#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 63: Hoare triple {40300#false} assume 1 == ~t5_pc~0; {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 64: Hoare triple {40300#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 65: Hoare triple {40300#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 66: Hoare triple {40300#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 67: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___4~0#1); {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 68: Hoare triple {40300#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 69: Hoare triple {40300#false} assume !(1 == ~t6_pc~0); {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 70: Hoare triple {40300#false} is_transmit6_triggered_~__retres1~6#1 := 0; {40300#false} is VALID [2022-02-21 04:22:18,418 INFO L290 TraceCheckUtils]: 71: Hoare triple {40300#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 72: Hoare triple {40300#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 73: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___5~0#1); {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 74: Hoare triple {40300#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 75: Hoare triple {40300#false} assume 1 == ~t7_pc~0; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 76: Hoare triple {40300#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 77: Hoare triple {40300#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 78: Hoare triple {40300#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 79: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___6~0#1); {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 80: Hoare triple {40300#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40300#false} is VALID [2022-02-21 04:22:18,419 INFO L290 TraceCheckUtils]: 81: Hoare triple {40300#false} assume 1 == ~t8_pc~0; {40300#false} is VALID [2022-02-21 04:22:18,420 INFO L290 TraceCheckUtils]: 82: Hoare triple {40300#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {40300#false} is VALID [2022-02-21 04:22:18,420 INFO L290 TraceCheckUtils]: 83: Hoare triple {40300#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40300#false} is VALID [2022-02-21 04:22:18,420 INFO L290 TraceCheckUtils]: 84: Hoare triple {40300#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {40300#false} is VALID [2022-02-21 04:22:18,420 INFO L290 TraceCheckUtils]: 85: Hoare triple {40300#false} assume !(0 != activate_threads_~tmp___7~0#1); {40300#false} is VALID [2022-02-21 04:22:18,420 INFO L290 TraceCheckUtils]: 86: Hoare triple {40300#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40300#false} is VALID [2022-02-21 04:22:18,420 INFO L290 TraceCheckUtils]: 87: Hoare triple {40300#false} assume !(1 == ~M_E~0); {40300#false} is VALID [2022-02-21 04:22:18,420 INFO L290 TraceCheckUtils]: 88: Hoare triple {40300#false} assume !(1 == ~T1_E~0); {40300#false} is VALID [2022-02-21 04:22:18,422 INFO L290 TraceCheckUtils]: 89: Hoare triple {40300#false} assume !(1 == ~T2_E~0); {40300#false} is VALID [2022-02-21 04:22:18,422 INFO L290 TraceCheckUtils]: 90: Hoare triple {40300#false} assume !(1 == ~T3_E~0); {40300#false} is VALID [2022-02-21 04:22:18,422 INFO L290 TraceCheckUtils]: 91: Hoare triple {40300#false} assume !(1 == ~T4_E~0); {40300#false} is VALID [2022-02-21 04:22:18,422 INFO L290 TraceCheckUtils]: 92: Hoare triple {40300#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 93: Hoare triple {40300#false} assume !(1 == ~T6_E~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 94: Hoare triple {40300#false} assume !(1 == ~T7_E~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 95: Hoare triple {40300#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 96: Hoare triple {40300#false} assume !(1 == ~E_M~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 97: Hoare triple {40300#false} assume !(1 == ~E_1~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 98: Hoare triple {40300#false} assume !(1 == ~E_2~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 99: Hoare triple {40300#false} assume !(1 == ~E_3~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 100: Hoare triple {40300#false} assume !(1 == ~E_4~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 101: Hoare triple {40300#false} assume !(1 == ~E_5~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 102: Hoare triple {40300#false} assume !(1 == ~E_6~0); {40300#false} is VALID [2022-02-21 04:22:18,423 INFO L290 TraceCheckUtils]: 103: Hoare triple {40300#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40300#false} is VALID [2022-02-21 04:22:18,424 INFO L290 TraceCheckUtils]: 104: Hoare triple {40300#false} assume !(1 == ~E_8~0); {40300#false} is VALID [2022-02-21 04:22:18,424 INFO L290 TraceCheckUtils]: 105: Hoare triple {40300#false} assume { :end_inline_reset_delta_events } true; {40300#false} is VALID [2022-02-21 04:22:18,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:18,424 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:18,424 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831524027] [2022-02-21 04:22:18,424 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831524027] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:18,424 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:18,425 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:18,425 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398897337] [2022-02-21 04:22:18,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:18,425 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:18,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:18,425 INFO L85 PathProgramCache]: Analyzing trace with hash -779318671, now seen corresponding path program 1 times [2022-02-21 04:22:18,425 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:18,426 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494196838] [2022-02-21 04:22:18,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:18,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:18,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 0: Hoare triple {40303#true} assume !false; {40303#true} is VALID [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 1: Hoare triple {40303#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {40303#true} is VALID [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 2: Hoare triple {40303#true} assume !false; {40303#true} is VALID [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 3: Hoare triple {40303#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {40303#true} is VALID [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 4: Hoare triple {40303#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {40303#true} is VALID [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 5: Hoare triple {40303#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {40303#true} is VALID [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 6: Hoare triple {40303#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {40303#true} is VALID [2022-02-21 04:22:18,451 INFO L290 TraceCheckUtils]: 7: Hoare triple {40303#true} assume !(0 != eval_~tmp~0#1); {40303#true} is VALID [2022-02-21 04:22:18,452 INFO L290 TraceCheckUtils]: 8: Hoare triple {40303#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {40303#true} is VALID [2022-02-21 04:22:18,452 INFO L290 TraceCheckUtils]: 9: Hoare triple {40303#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {40303#true} is VALID [2022-02-21 04:22:18,452 INFO L290 TraceCheckUtils]: 10: Hoare triple {40303#true} assume 0 == ~M_E~0;~M_E~0 := 1; {40303#true} is VALID [2022-02-21 04:22:18,452 INFO L290 TraceCheckUtils]: 11: Hoare triple {40303#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {40303#true} is VALID [2022-02-21 04:22:18,452 INFO L290 TraceCheckUtils]: 12: Hoare triple {40303#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,452 INFO L290 TraceCheckUtils]: 13: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,453 INFO L290 TraceCheckUtils]: 14: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,453 INFO L290 TraceCheckUtils]: 15: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,453 INFO L290 TraceCheckUtils]: 16: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,453 INFO L290 TraceCheckUtils]: 17: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,454 INFO L290 TraceCheckUtils]: 18: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,454 INFO L290 TraceCheckUtils]: 19: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,454 INFO L290 TraceCheckUtils]: 20: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,454 INFO L290 TraceCheckUtils]: 21: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,455 INFO L290 TraceCheckUtils]: 22: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,455 INFO L290 TraceCheckUtils]: 23: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,455 INFO L290 TraceCheckUtils]: 24: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,455 INFO L290 TraceCheckUtils]: 25: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,456 INFO L290 TraceCheckUtils]: 26: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,456 INFO L290 TraceCheckUtils]: 27: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,456 INFO L290 TraceCheckUtils]: 28: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,456 INFO L290 TraceCheckUtils]: 29: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,457 INFO L290 TraceCheckUtils]: 30: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,457 INFO L290 TraceCheckUtils]: 31: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,457 INFO L290 TraceCheckUtils]: 32: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,457 INFO L290 TraceCheckUtils]: 33: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,458 INFO L290 TraceCheckUtils]: 34: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,458 INFO L290 TraceCheckUtils]: 35: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,458 INFO L290 TraceCheckUtils]: 36: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,458 INFO L290 TraceCheckUtils]: 37: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,459 INFO L290 TraceCheckUtils]: 38: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,459 INFO L290 TraceCheckUtils]: 39: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,459 INFO L290 TraceCheckUtils]: 40: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,459 INFO L290 TraceCheckUtils]: 41: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,460 INFO L290 TraceCheckUtils]: 42: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,460 INFO L290 TraceCheckUtils]: 43: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,460 INFO L290 TraceCheckUtils]: 44: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,460 INFO L290 TraceCheckUtils]: 45: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,461 INFO L290 TraceCheckUtils]: 46: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,461 INFO L290 TraceCheckUtils]: 47: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,461 INFO L290 TraceCheckUtils]: 48: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,461 INFO L290 TraceCheckUtils]: 49: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,462 INFO L290 TraceCheckUtils]: 50: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,462 INFO L290 TraceCheckUtils]: 51: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,462 INFO L290 TraceCheckUtils]: 52: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,462 INFO L290 TraceCheckUtils]: 53: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,463 INFO L290 TraceCheckUtils]: 54: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,463 INFO L290 TraceCheckUtils]: 55: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,463 INFO L290 TraceCheckUtils]: 56: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,463 INFO L290 TraceCheckUtils]: 57: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,464 INFO L290 TraceCheckUtils]: 58: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,464 INFO L290 TraceCheckUtils]: 59: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,464 INFO L290 TraceCheckUtils]: 60: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,465 INFO L290 TraceCheckUtils]: 61: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,465 INFO L290 TraceCheckUtils]: 62: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,465 INFO L290 TraceCheckUtils]: 63: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,466 INFO L290 TraceCheckUtils]: 64: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,466 INFO L290 TraceCheckUtils]: 65: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,466 INFO L290 TraceCheckUtils]: 66: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,466 INFO L290 TraceCheckUtils]: 67: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,467 INFO L290 TraceCheckUtils]: 68: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,467 INFO L290 TraceCheckUtils]: 69: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,467 INFO L290 TraceCheckUtils]: 70: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,468 INFO L290 TraceCheckUtils]: 71: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,468 INFO L290 TraceCheckUtils]: 72: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,468 INFO L290 TraceCheckUtils]: 73: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,469 INFO L290 TraceCheckUtils]: 74: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,469 INFO L290 TraceCheckUtils]: 75: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,469 INFO L290 TraceCheckUtils]: 76: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,470 INFO L290 TraceCheckUtils]: 77: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,470 INFO L290 TraceCheckUtils]: 78: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,470 INFO L290 TraceCheckUtils]: 79: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,470 INFO L290 TraceCheckUtils]: 80: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,471 INFO L290 TraceCheckUtils]: 81: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,471 INFO L290 TraceCheckUtils]: 82: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,471 INFO L290 TraceCheckUtils]: 83: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,472 INFO L290 TraceCheckUtils]: 84: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {40305#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:18,472 INFO L290 TraceCheckUtils]: 85: Hoare triple {40305#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {40304#false} is VALID [2022-02-21 04:22:18,472 INFO L290 TraceCheckUtils]: 86: Hoare triple {40304#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,472 INFO L290 TraceCheckUtils]: 87: Hoare triple {40304#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,472 INFO L290 TraceCheckUtils]: 88: Hoare triple {40304#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 89: Hoare triple {40304#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 90: Hoare triple {40304#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 91: Hoare triple {40304#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 92: Hoare triple {40304#false} assume 1 == ~E_M~0;~E_M~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 93: Hoare triple {40304#false} assume !(1 == ~E_1~0); {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 94: Hoare triple {40304#false} assume 1 == ~E_2~0;~E_2~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 95: Hoare triple {40304#false} assume 1 == ~E_3~0;~E_3~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,473 INFO L290 TraceCheckUtils]: 96: Hoare triple {40304#false} assume 1 == ~E_4~0;~E_4~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 97: Hoare triple {40304#false} assume 1 == ~E_5~0;~E_5~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 98: Hoare triple {40304#false} assume 1 == ~E_6~0;~E_6~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 99: Hoare triple {40304#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 100: Hoare triple {40304#false} assume 1 == ~E_8~0;~E_8~0 := 2; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 101: Hoare triple {40304#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 102: Hoare triple {40304#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 103: Hoare triple {40304#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {40304#false} is VALID [2022-02-21 04:22:18,474 INFO L290 TraceCheckUtils]: 104: Hoare triple {40304#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 105: Hoare triple {40304#false} assume !(0 == start_simulation_~tmp~3#1); {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 106: Hoare triple {40304#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 107: Hoare triple {40304#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 108: Hoare triple {40304#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 109: Hoare triple {40304#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 110: Hoare triple {40304#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 111: Hoare triple {40304#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {40304#false} is VALID [2022-02-21 04:22:18,475 INFO L290 TraceCheckUtils]: 112: Hoare triple {40304#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {40304#false} is VALID [2022-02-21 04:22:18,476 INFO L290 TraceCheckUtils]: 113: Hoare triple {40304#false} assume !(0 != start_simulation_~tmp___0~1#1); {40304#false} is VALID [2022-02-21 04:22:18,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:18,476 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:18,476 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494196838] [2022-02-21 04:22:18,476 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494196838] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:18,477 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:18,477 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:18,477 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950488923] [2022-02-21 04:22:18,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:18,477 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:18,477 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:18,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:18,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:18,478 INFO L87 Difference]: Start difference. First operand 1816 states and 2689 transitions. cyclomatic complexity: 875 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:20,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:20,418 INFO L93 Difference]: Finished difference Result 3306 states and 4884 transitions. [2022-02-21 04:22:20,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:20,418 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:20,492 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:20,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3306 states and 4884 transitions. [2022-02-21 04:22:20,755 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2022-02-21 04:22:21,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3306 states to 3306 states and 4884 transitions. [2022-02-21 04:22:21,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3306 [2022-02-21 04:22:21,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3306 [2022-02-21 04:22:21,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3306 states and 4884 transitions. [2022-02-21 04:22:21,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:21,037 INFO L681 BuchiCegarLoop]: Abstraction has 3306 states and 4884 transitions. [2022-02-21 04:22:21,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3306 states and 4884 transitions. [2022-02-21 04:22:21,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3306 to 3304. [2022-02-21 04:22:21,065 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:21,068 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3306 states and 4884 transitions. Second operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:21,070 INFO L74 IsIncluded]: Start isIncluded. First operand 3306 states and 4884 transitions. Second operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:21,072 INFO L87 Difference]: Start difference. First operand 3306 states and 4884 transitions. Second operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:21,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:21,295 INFO L93 Difference]: Finished difference Result 3306 states and 4884 transitions. [2022-02-21 04:22:21,296 INFO L276 IsEmpty]: Start isEmpty. Operand 3306 states and 4884 transitions. [2022-02-21 04:22:21,298 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:21,298 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:21,301 INFO L74 IsIncluded]: Start isIncluded. First operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3306 states and 4884 transitions. [2022-02-21 04:22:21,304 INFO L87 Difference]: Start difference. First operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3306 states and 4884 transitions. [2022-02-21 04:22:21,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:21,530 INFO L93 Difference]: Finished difference Result 3306 states and 4884 transitions. [2022-02-21 04:22:21,530 INFO L276 IsEmpty]: Start isEmpty. Operand 3306 states and 4884 transitions. [2022-02-21 04:22:21,532 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:21,532 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:21,532 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:21,532 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:21,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:21,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3304 states to 3304 states and 4882 transitions. [2022-02-21 04:22:21,767 INFO L704 BuchiCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2022-02-21 04:22:21,767 INFO L587 BuchiCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2022-02-21 04:22:21,767 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:22:21,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3304 states and 4882 transitions. [2022-02-21 04:22:21,772 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2022-02-21 04:22:21,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:21,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:21,773 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:21,774 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:21,774 INFO L791 eck$LassoCheckResult]: Stem: 44405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 44406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 44327#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44328#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44175#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 44176#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43753#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43754#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43837#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44585#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43723#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43724#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44140#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44163#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43841#L866 assume !(0 == ~M_E~0); 43842#L866-2 assume !(0 == ~T1_E~0); 44354#L871-1 assume !(0 == ~T2_E~0); 44355#L876-1 assume !(0 == ~T3_E~0); 44642#L881-1 assume !(0 == ~T4_E~0); 44366#L886-1 assume !(0 == ~T5_E~0); 44129#L891-1 assume !(0 == ~T6_E~0); 44130#L896-1 assume !(0 == ~T7_E~0); 44357#L901-1 assume !(0 == ~T8_E~0); 44378#L906-1 assume !(0 == ~E_M~0); 44379#L911-1 assume !(0 == ~E_1~0); 44173#L916-1 assume !(0 == ~E_2~0); 44174#L921-1 assume !(0 == ~E_3~0); 44489#L926-1 assume !(0 == ~E_4~0); 44597#L931-1 assume !(0 == ~E_5~0); 44652#L936-1 assume !(0 == ~E_6~0); 44660#L941-1 assume !(0 == ~E_7~0); 44180#L946-1 assume !(0 == ~E_8~0); 44181#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44618#L430 assume !(1 == ~m_pc~0); 44039#L430-2 is_master_triggered_~__retres1~0#1 := 0; 43657#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43658#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44284#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44295#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44469#L449 assume 1 == ~t1_pc~0; 44470#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43845#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43614#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43615#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 44395#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44239#L468 assume !(1 == ~t2_pc~0); 43641#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43640#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44137#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44044#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 43659#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43660#L487 assume 1 == ~t3_pc~0; 44637#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43757#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43758#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44452#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 44103#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44104#L506 assume !(1 == ~t4_pc~0); 44233#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44280#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44609#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44610#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 44231#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44053#L525 assume 1 == ~t5_pc~0; 43991#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43700#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44183#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44184#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 43902#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43903#L544 assume !(1 == ~t6_pc~0); 44054#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44055#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44412#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43681#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 43682#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44571#L563 assume 1 == ~t7_pc~0; 44430#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43710#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43711#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44136#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 43848#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43849#L582 assume 1 == ~t8_pc~0; 43768#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43769#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44638#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44094#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 43992#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43993#L964 assume !(1 == ~M_E~0); 44473#L964-2 assume !(1 == ~T1_E~0); 44755#L969-1 assume !(1 == ~T2_E~0); 44754#L974-1 assume !(1 == ~T3_E~0); 44502#L979-1 assume !(1 == ~T4_E~0); 44503#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44749#L989-1 assume !(1 == ~T6_E~0); 44748#L994-1 assume !(1 == ~T7_E~0); 44747#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44746#L1004-1 assume !(1 == ~E_M~0); 44745#L1009-1 assume !(1 == ~E_1~0); 44744#L1014-1 assume !(1 == ~E_2~0); 44743#L1019-1 assume !(1 == ~E_3~0); 44732#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 44730#L1029-1 assume !(1 == ~E_5~0); 44728#L1034-1 assume !(1 == ~E_6~0); 44726#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44724#L1044-1 assume !(1 == ~E_8~0); 44722#L1049-1 assume { :end_inline_reset_delta_events } true; 44715#L1315-2 [2022-02-21 04:22:21,774 INFO L793 eck$LassoCheckResult]: Loop: 44715#L1315-2 assume !false; 44710#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44709#L841 assume !false; 44708#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44703#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44698#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44697#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44695#L724 assume !(0 != eval_~tmp~0#1); 44694#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44693#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44691#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44692#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45872#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45870#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45458#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45456#L886-3 assume !(0 == ~T5_E~0); 45454#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45452#L896-3 assume !(0 == ~T7_E~0); 45450#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45448#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45446#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45444#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45442#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45440#L926-3 assume !(0 == ~E_4~0); 45438#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45419#L936-3 assume !(0 == ~E_6~0); 45416#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45391#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43967#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43968#L430-30 assume 1 == ~m_pc~0; 45341#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45339#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45337#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45335#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45333#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45312#L449-30 assume !(1 == ~t1_pc~0); 45309#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 45308#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45277#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45275#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45273#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45270#L468-30 assume 1 == ~t2_pc~0; 45267#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45265#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45237#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45235#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45233#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45231#L487-30 assume !(1 == ~t3_pc~0); 45227#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 45200#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45198#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45178#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45176#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45174#L506-30 assume 1 == ~t4_pc~0; 45168#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45167#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45144#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45142#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 45140#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45139#L525-30 assume !(1 == ~t5_pc~0); 45120#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 45117#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45096#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45067#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45065#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45063#L544-30 assume 1 == ~t6_pc~0; 45060#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45026#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44983#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44981#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44979#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44978#L563-30 assume 1 == ~t7_pc~0; 44976#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44974#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44972#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44932#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44930#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44928#L582-30 assume !(1 == ~t8_pc~0); 44925#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 44898#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44877#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44875#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44873#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44854#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43689#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44851#L969-3 assume !(1 == ~T2_E~0); 44850#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44833#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44813#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44811#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44809#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44807#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44805#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44803#L1009-3 assume !(1 == ~E_1~0); 44792#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44790#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44789#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44787#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44786#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44785#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44784#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44783#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44771#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44767#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44764#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 44750#L1334 assume !(0 == start_simulation_~tmp~3#1); 44548#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 44741#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 44731#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 44729#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 44727#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44725#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44723#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 44721#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 44715#L1315-2 [2022-02-21 04:22:21,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:21,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2022-02-21 04:22:21,775 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:21,775 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264690159] [2022-02-21 04:22:21,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:21,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:21,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:21,804 INFO L290 TraceCheckUtils]: 0: Hoare triple {53533#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,804 INFO L290 TraceCheckUtils]: 1: Hoare triple {53533#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {53533#true} is VALID [2022-02-21 04:22:21,804 INFO L290 TraceCheckUtils]: 2: Hoare triple {53533#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {53533#true} is VALID [2022-02-21 04:22:21,804 INFO L290 TraceCheckUtils]: 3: Hoare triple {53533#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {53533#true} is VALID [2022-02-21 04:22:21,804 INFO L290 TraceCheckUtils]: 4: Hoare triple {53533#true} assume 1 == ~m_i~0;~m_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,804 INFO L290 TraceCheckUtils]: 5: Hoare triple {53533#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 6: Hoare triple {53533#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 7: Hoare triple {53533#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 8: Hoare triple {53533#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 9: Hoare triple {53533#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 10: Hoare triple {53533#true} assume 1 == ~t6_i~0;~t6_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 11: Hoare triple {53533#true} assume 1 == ~t7_i~0;~t7_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 12: Hoare triple {53533#true} assume 1 == ~t8_i~0;~t8_st~0 := 0; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 13: Hoare triple {53533#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 14: Hoare triple {53533#true} assume !(0 == ~M_E~0); {53533#true} is VALID [2022-02-21 04:22:21,805 INFO L290 TraceCheckUtils]: 15: Hoare triple {53533#true} assume !(0 == ~T1_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 16: Hoare triple {53533#true} assume !(0 == ~T2_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 17: Hoare triple {53533#true} assume !(0 == ~T3_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 18: Hoare triple {53533#true} assume !(0 == ~T4_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 19: Hoare triple {53533#true} assume !(0 == ~T5_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 20: Hoare triple {53533#true} assume !(0 == ~T6_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 21: Hoare triple {53533#true} assume !(0 == ~T7_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 22: Hoare triple {53533#true} assume !(0 == ~T8_E~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 23: Hoare triple {53533#true} assume !(0 == ~E_M~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 24: Hoare triple {53533#true} assume !(0 == ~E_1~0); {53533#true} is VALID [2022-02-21 04:22:21,806 INFO L290 TraceCheckUtils]: 25: Hoare triple {53533#true} assume !(0 == ~E_2~0); {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 26: Hoare triple {53533#true} assume !(0 == ~E_3~0); {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 27: Hoare triple {53533#true} assume !(0 == ~E_4~0); {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 28: Hoare triple {53533#true} assume !(0 == ~E_5~0); {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 29: Hoare triple {53533#true} assume !(0 == ~E_6~0); {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 30: Hoare triple {53533#true} assume !(0 == ~E_7~0); {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 31: Hoare triple {53533#true} assume !(0 == ~E_8~0); {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 32: Hoare triple {53533#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {53533#true} is VALID [2022-02-21 04:22:21,807 INFO L290 TraceCheckUtils]: 33: Hoare triple {53533#true} assume !(1 == ~m_pc~0); {53533#true} is VALID [2022-02-21 04:22:21,808 INFO L290 TraceCheckUtils]: 34: Hoare triple {53533#true} is_master_triggered_~__retres1~0#1 := 0; {53535#(= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0)} is VALID [2022-02-21 04:22:21,808 INFO L290 TraceCheckUtils]: 35: Hoare triple {53535#(= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {53536#(= |ULTIMATE.start_is_master_triggered_#res#1| 0)} is VALID [2022-02-21 04:22:21,808 INFO L290 TraceCheckUtils]: 36: Hoare triple {53536#(= |ULTIMATE.start_is_master_triggered_#res#1| 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {53537#(= |ULTIMATE.start_activate_threads_~tmp~1#1| 0)} is VALID [2022-02-21 04:22:21,808 INFO L290 TraceCheckUtils]: 37: Hoare triple {53537#(= |ULTIMATE.start_activate_threads_~tmp~1#1| 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 38: Hoare triple {53534#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 39: Hoare triple {53534#false} assume 1 == ~t1_pc~0; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 40: Hoare triple {53534#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 41: Hoare triple {53534#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 42: Hoare triple {53534#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 43: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___0~0#1); {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 44: Hoare triple {53534#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 45: Hoare triple {53534#false} assume !(1 == ~t2_pc~0); {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 46: Hoare triple {53534#false} is_transmit2_triggered_~__retres1~2#1 := 0; {53534#false} is VALID [2022-02-21 04:22:21,809 INFO L290 TraceCheckUtils]: 47: Hoare triple {53534#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 48: Hoare triple {53534#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 49: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___1~0#1); {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 50: Hoare triple {53534#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 51: Hoare triple {53534#false} assume 1 == ~t3_pc~0; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 52: Hoare triple {53534#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 53: Hoare triple {53534#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 54: Hoare triple {53534#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 55: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___2~0#1); {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 56: Hoare triple {53534#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 57: Hoare triple {53534#false} assume !(1 == ~t4_pc~0); {53534#false} is VALID [2022-02-21 04:22:21,810 INFO L290 TraceCheckUtils]: 58: Hoare triple {53534#false} is_transmit4_triggered_~__retres1~4#1 := 0; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 59: Hoare triple {53534#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 60: Hoare triple {53534#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 61: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___3~0#1); {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 62: Hoare triple {53534#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 63: Hoare triple {53534#false} assume 1 == ~t5_pc~0; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 64: Hoare triple {53534#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 65: Hoare triple {53534#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 66: Hoare triple {53534#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 67: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___4~0#1); {53534#false} is VALID [2022-02-21 04:22:21,811 INFO L290 TraceCheckUtils]: 68: Hoare triple {53534#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 69: Hoare triple {53534#false} assume !(1 == ~t6_pc~0); {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 70: Hoare triple {53534#false} is_transmit6_triggered_~__retres1~6#1 := 0; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 71: Hoare triple {53534#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 72: Hoare triple {53534#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 73: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___5~0#1); {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 74: Hoare triple {53534#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 75: Hoare triple {53534#false} assume 1 == ~t7_pc~0; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 76: Hoare triple {53534#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 77: Hoare triple {53534#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {53534#false} is VALID [2022-02-21 04:22:21,812 INFO L290 TraceCheckUtils]: 78: Hoare triple {53534#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 79: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___6~0#1); {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 80: Hoare triple {53534#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 81: Hoare triple {53534#false} assume 1 == ~t8_pc~0; {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 82: Hoare triple {53534#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 83: Hoare triple {53534#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 84: Hoare triple {53534#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 85: Hoare triple {53534#false} assume !(0 != activate_threads_~tmp___7~0#1); {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 86: Hoare triple {53534#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 87: Hoare triple {53534#false} assume !(1 == ~M_E~0); {53534#false} is VALID [2022-02-21 04:22:21,813 INFO L290 TraceCheckUtils]: 88: Hoare triple {53534#false} assume !(1 == ~T1_E~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 89: Hoare triple {53534#false} assume !(1 == ~T2_E~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 90: Hoare triple {53534#false} assume !(1 == ~T3_E~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 91: Hoare triple {53534#false} assume !(1 == ~T4_E~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 92: Hoare triple {53534#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 93: Hoare triple {53534#false} assume !(1 == ~T6_E~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 94: Hoare triple {53534#false} assume !(1 == ~T7_E~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 95: Hoare triple {53534#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 96: Hoare triple {53534#false} assume !(1 == ~E_M~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 97: Hoare triple {53534#false} assume !(1 == ~E_1~0); {53534#false} is VALID [2022-02-21 04:22:21,814 INFO L290 TraceCheckUtils]: 98: Hoare triple {53534#false} assume !(1 == ~E_2~0); {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L290 TraceCheckUtils]: 99: Hoare triple {53534#false} assume !(1 == ~E_3~0); {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L290 TraceCheckUtils]: 100: Hoare triple {53534#false} assume 1 == ~E_4~0;~E_4~0 := 2; {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L290 TraceCheckUtils]: 101: Hoare triple {53534#false} assume !(1 == ~E_5~0); {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L290 TraceCheckUtils]: 102: Hoare triple {53534#false} assume !(1 == ~E_6~0); {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L290 TraceCheckUtils]: 103: Hoare triple {53534#false} assume 1 == ~E_7~0;~E_7~0 := 2; {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L290 TraceCheckUtils]: 104: Hoare triple {53534#false} assume !(1 == ~E_8~0); {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L290 TraceCheckUtils]: 105: Hoare triple {53534#false} assume { :end_inline_reset_delta_events } true; {53534#false} is VALID [2022-02-21 04:22:21,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:21,816 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:21,816 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264690159] [2022-02-21 04:22:21,816 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264690159] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:21,816 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:21,816 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:22:21,816 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696347199] [2022-02-21 04:22:21,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:21,816 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:21,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:21,817 INFO L85 PathProgramCache]: Analyzing trace with hash 295929525, now seen corresponding path program 1 times [2022-02-21 04:22:21,817 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:21,817 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278704441] [2022-02-21 04:22:21,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:21,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:21,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 0: Hoare triple {53538#true} assume !false; {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 1: Hoare triple {53538#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 2: Hoare triple {53538#true} assume !false; {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 3: Hoare triple {53538#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 4: Hoare triple {53538#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 5: Hoare triple {53538#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 6: Hoare triple {53538#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 7: Hoare triple {53538#true} assume !(0 != eval_~tmp~0#1); {53538#true} is VALID [2022-02-21 04:22:21,836 INFO L290 TraceCheckUtils]: 8: Hoare triple {53538#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {53538#true} is VALID [2022-02-21 04:22:21,837 INFO L290 TraceCheckUtils]: 9: Hoare triple {53538#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {53538#true} is VALID [2022-02-21 04:22:21,837 INFO L290 TraceCheckUtils]: 10: Hoare triple {53538#true} assume 0 == ~M_E~0;~M_E~0 := 1; {53538#true} is VALID [2022-02-21 04:22:21,837 INFO L290 TraceCheckUtils]: 11: Hoare triple {53538#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {53538#true} is VALID [2022-02-21 04:22:21,837 INFO L290 TraceCheckUtils]: 12: Hoare triple {53538#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,837 INFO L290 TraceCheckUtils]: 13: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,838 INFO L290 TraceCheckUtils]: 14: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,838 INFO L290 TraceCheckUtils]: 15: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,838 INFO L290 TraceCheckUtils]: 16: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,838 INFO L290 TraceCheckUtils]: 17: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,839 INFO L290 TraceCheckUtils]: 18: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,839 INFO L290 TraceCheckUtils]: 19: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,839 INFO L290 TraceCheckUtils]: 20: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,839 INFO L290 TraceCheckUtils]: 21: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,840 INFO L290 TraceCheckUtils]: 22: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,840 INFO L290 TraceCheckUtils]: 23: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,840 INFO L290 TraceCheckUtils]: 24: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,840 INFO L290 TraceCheckUtils]: 25: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,840 INFO L290 TraceCheckUtils]: 26: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,841 INFO L290 TraceCheckUtils]: 27: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,841 INFO L290 TraceCheckUtils]: 28: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,841 INFO L290 TraceCheckUtils]: 29: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,842 INFO L290 TraceCheckUtils]: 30: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,842 INFO L290 TraceCheckUtils]: 31: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,842 INFO L290 TraceCheckUtils]: 32: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,842 INFO L290 TraceCheckUtils]: 33: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,842 INFO L290 TraceCheckUtils]: 34: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,843 INFO L290 TraceCheckUtils]: 35: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,843 INFO L290 TraceCheckUtils]: 36: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,843 INFO L290 TraceCheckUtils]: 37: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,843 INFO L290 TraceCheckUtils]: 38: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,844 INFO L290 TraceCheckUtils]: 39: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,844 INFO L290 TraceCheckUtils]: 40: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,844 INFO L290 TraceCheckUtils]: 41: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,845 INFO L290 TraceCheckUtils]: 42: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,845 INFO L290 TraceCheckUtils]: 43: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,845 INFO L290 TraceCheckUtils]: 44: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,845 INFO L290 TraceCheckUtils]: 45: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,845 INFO L290 TraceCheckUtils]: 46: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,846 INFO L290 TraceCheckUtils]: 47: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,846 INFO L290 TraceCheckUtils]: 48: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,846 INFO L290 TraceCheckUtils]: 49: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,846 INFO L290 TraceCheckUtils]: 50: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,847 INFO L290 TraceCheckUtils]: 51: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,847 INFO L290 TraceCheckUtils]: 52: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,847 INFO L290 TraceCheckUtils]: 53: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,847 INFO L290 TraceCheckUtils]: 54: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,848 INFO L290 TraceCheckUtils]: 55: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,848 INFO L290 TraceCheckUtils]: 56: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,848 INFO L290 TraceCheckUtils]: 57: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,848 INFO L290 TraceCheckUtils]: 58: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,849 INFO L290 TraceCheckUtils]: 59: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,849 INFO L290 TraceCheckUtils]: 60: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,849 INFO L290 TraceCheckUtils]: 61: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,849 INFO L290 TraceCheckUtils]: 62: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,850 INFO L290 TraceCheckUtils]: 63: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,850 INFO L290 TraceCheckUtils]: 64: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,850 INFO L290 TraceCheckUtils]: 65: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,850 INFO L290 TraceCheckUtils]: 66: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,851 INFO L290 TraceCheckUtils]: 67: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,851 INFO L290 TraceCheckUtils]: 68: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,851 INFO L290 TraceCheckUtils]: 69: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,851 INFO L290 TraceCheckUtils]: 70: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,852 INFO L290 TraceCheckUtils]: 71: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,852 INFO L290 TraceCheckUtils]: 72: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,852 INFO L290 TraceCheckUtils]: 73: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,852 INFO L290 TraceCheckUtils]: 74: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,853 INFO L290 TraceCheckUtils]: 75: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,853 INFO L290 TraceCheckUtils]: 76: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,853 INFO L290 TraceCheckUtils]: 77: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,853 INFO L290 TraceCheckUtils]: 78: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,854 INFO L290 TraceCheckUtils]: 79: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,854 INFO L290 TraceCheckUtils]: 80: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,854 INFO L290 TraceCheckUtils]: 81: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,854 INFO L290 TraceCheckUtils]: 82: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,855 INFO L290 TraceCheckUtils]: 83: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,855 INFO L290 TraceCheckUtils]: 84: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {53540#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:21,855 INFO L290 TraceCheckUtils]: 85: Hoare triple {53540#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {53539#false} is VALID [2022-02-21 04:22:21,855 INFO L290 TraceCheckUtils]: 86: Hoare triple {53539#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,855 INFO L290 TraceCheckUtils]: 87: Hoare triple {53539#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,855 INFO L290 TraceCheckUtils]: 88: Hoare triple {53539#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,855 INFO L290 TraceCheckUtils]: 89: Hoare triple {53539#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 90: Hoare triple {53539#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 91: Hoare triple {53539#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 92: Hoare triple {53539#false} assume 1 == ~E_M~0;~E_M~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 93: Hoare triple {53539#false} assume !(1 == ~E_1~0); {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 94: Hoare triple {53539#false} assume 1 == ~E_2~0;~E_2~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 95: Hoare triple {53539#false} assume 1 == ~E_3~0;~E_3~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 96: Hoare triple {53539#false} assume 1 == ~E_4~0;~E_4~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 97: Hoare triple {53539#false} assume 1 == ~E_5~0;~E_5~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 98: Hoare triple {53539#false} assume 1 == ~E_6~0;~E_6~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,856 INFO L290 TraceCheckUtils]: 99: Hoare triple {53539#false} assume 1 == ~E_7~0;~E_7~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 100: Hoare triple {53539#false} assume 1 == ~E_8~0;~E_8~0 := 2; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 101: Hoare triple {53539#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 102: Hoare triple {53539#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 103: Hoare triple {53539#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 104: Hoare triple {53539#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 105: Hoare triple {53539#false} assume !(0 == start_simulation_~tmp~3#1); {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 106: Hoare triple {53539#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 107: Hoare triple {53539#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 108: Hoare triple {53539#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {53539#false} is VALID [2022-02-21 04:22:21,857 INFO L290 TraceCheckUtils]: 109: Hoare triple {53539#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {53539#false} is VALID [2022-02-21 04:22:21,858 INFO L290 TraceCheckUtils]: 110: Hoare triple {53539#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {53539#false} is VALID [2022-02-21 04:22:21,858 INFO L290 TraceCheckUtils]: 111: Hoare triple {53539#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {53539#false} is VALID [2022-02-21 04:22:21,858 INFO L290 TraceCheckUtils]: 112: Hoare triple {53539#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {53539#false} is VALID [2022-02-21 04:22:21,858 INFO L290 TraceCheckUtils]: 113: Hoare triple {53539#false} assume !(0 != start_simulation_~tmp___0~1#1); {53539#false} is VALID [2022-02-21 04:22:21,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:21,858 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:21,858 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278704441] [2022-02-21 04:22:21,859 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278704441] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:21,859 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:21,859 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:21,859 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697494118] [2022-02-21 04:22:21,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:21,859 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:21,859 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:21,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:22:21,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:22:21,860 INFO L87 Difference]: Start difference. First operand 3304 states and 4882 transitions. cyclomatic complexity: 1582 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:26,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:26,759 INFO L93 Difference]: Finished difference Result 9486 states and 13948 transitions. [2022-02-21 04:22:26,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:22:26,759 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:26,805 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:26,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9486 states and 13948 transitions. [2022-02-21 04:22:28,670 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9108 [2022-02-21 04:22:30,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9486 states to 9486 states and 13948 transitions. [2022-02-21 04:22:30,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9486 [2022-02-21 04:22:30,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9486 [2022-02-21 04:22:30,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9486 states and 13948 transitions. [2022-02-21 04:22:30,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:30,657 INFO L681 BuchiCegarLoop]: Abstraction has 9486 states and 13948 transitions. [2022-02-21 04:22:30,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9486 states and 13948 transitions. [2022-02-21 04:22:30,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9486 to 3424. [2022-02-21 04:22:30,706 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:30,709 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9486 states and 13948 transitions. Second operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:30,711 INFO L74 IsIncluded]: Start isIncluded. First operand 9486 states and 13948 transitions. Second operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:30,713 INFO L87 Difference]: Start difference. First operand 9486 states and 13948 transitions. Second operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:32,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:32,684 INFO L93 Difference]: Finished difference Result 9486 states and 13948 transitions. [2022-02-21 04:22:32,684 INFO L276 IsEmpty]: Start isEmpty. Operand 9486 states and 13948 transitions. [2022-02-21 04:22:32,692 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:32,693 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:32,696 INFO L74 IsIncluded]: Start isIncluded. First operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9486 states and 13948 transitions. [2022-02-21 04:22:32,698 INFO L87 Difference]: Start difference. First operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9486 states and 13948 transitions. [2022-02-21 04:22:34,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:34,562 INFO L93 Difference]: Finished difference Result 9486 states and 13948 transitions. [2022-02-21 04:22:34,563 INFO L276 IsEmpty]: Start isEmpty. Operand 9486 states and 13948 transitions. [2022-02-21 04:22:34,570 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:34,570 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:34,570 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:34,570 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:34,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:34,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3424 states to 3424 states and 5002 transitions. [2022-02-21 04:22:34,820 INFO L704 BuchiCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2022-02-21 04:22:34,820 INFO L587 BuchiCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2022-02-21 04:22:34,820 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:22:34,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3424 states and 5002 transitions. [2022-02-21 04:22:34,826 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3270 [2022-02-21 04:22:34,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:34,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:34,827 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:34,827 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:34,828 INFO L791 eck$LassoCheckResult]: Stem: 63831#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 63832#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 63752#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63753#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63591#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 63592#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63168#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63169#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63250#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64034#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63138#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63139#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63555#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63580#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63254#L866 assume !(0 == ~M_E~0); 63255#L866-2 assume !(0 == ~T1_E~0); 63782#L871-1 assume !(0 == ~T2_E~0); 63783#L876-1 assume !(0 == ~T3_E~0); 64106#L881-1 assume !(0 == ~T4_E~0); 63795#L886-1 assume !(0 == ~T5_E~0); 63546#L891-1 assume !(0 == ~T6_E~0); 63547#L896-1 assume !(0 == ~T7_E~0); 63785#L901-1 assume !(0 == ~T8_E~0); 63806#L906-1 assume !(0 == ~E_M~0); 63807#L911-1 assume !(0 == ~E_1~0); 63589#L916-1 assume !(0 == ~E_2~0); 63590#L921-1 assume !(0 == ~E_3~0); 63918#L926-1 assume !(0 == ~E_4~0); 64050#L931-1 assume !(0 == ~E_5~0); 64117#L936-1 assume !(0 == ~E_6~0); 64138#L941-1 assume !(0 == ~E_7~0); 63595#L946-1 assume !(0 == ~E_8~0); 63596#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64081#L430 assume !(1 == ~m_pc~0); 63452#L430-2 is_master_triggered_~__retres1~0#1 := 0; 63072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63073#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63717#L1073 assume !(0 != activate_threads_~tmp~1#1); 63718#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63896#L449 assume 1 == ~t1_pc~0; 63897#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 63258#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63031#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63032#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 63821#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63655#L468 assume !(1 == ~t2_pc~0); 63056#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63055#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63554#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63459#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 63074#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63075#L487 assume 1 == ~t3_pc~0; 64103#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 63172#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63173#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63881#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 63520#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63521#L506 assume !(1 == ~t4_pc~0); 63651#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63700#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64066#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64067#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 63644#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63470#L525 assume 1 == ~t5_pc~0; 63403#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63117#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63599#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63600#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 63316#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63317#L544 assume !(1 == ~t6_pc~0); 63471#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 63472#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63838#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63098#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 63099#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64019#L563 assume 1 == ~t7_pc~0; 63856#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63127#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63128#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63548#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 63259#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63260#L582 assume 1 == ~t8_pc~0; 63183#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63184#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64104#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63509#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 63407#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63408#L964 assume !(1 == ~M_E~0); 63899#L964-2 assume !(1 == ~T1_E~0); 63318#L969-1 assume !(1 == ~T2_E~0); 63319#L974-1 assume !(1 == ~T3_E~0); 63936#L979-1 assume !(1 == ~T4_E~0); 63937#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64261#L989-1 assume !(1 == ~T6_E~0); 63789#L994-1 assume !(1 == ~T7_E~0); 63790#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63906#L1004-1 assume !(1 == ~E_M~0); 63907#L1009-1 assume !(1 == ~E_1~0); 63347#L1014-1 assume !(1 == ~E_2~0); 63348#L1019-1 assume !(1 == ~E_3~0); 64244#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 64242#L1029-1 assume !(1 == ~E_5~0); 64240#L1034-1 assume !(1 == ~E_6~0); 64238#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 64234#L1044-1 assume !(1 == ~E_8~0); 64232#L1049-1 assume { :end_inline_reset_delta_events } true; 64225#L1315-2 [2022-02-21 04:22:34,828 INFO L793 eck$LassoCheckResult]: Loop: 64225#L1315-2 assume !false; 64220#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64219#L841 assume !false; 64218#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 64213#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 64208#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 64207#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64205#L724 assume !(0 != eval_~tmp~0#1); 64204#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64203#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64201#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64202#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65604#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65603#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65602#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65601#L886-3 assume !(0 == ~T5_E~0); 65600#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65599#L896-3 assume !(0 == ~T7_E~0); 65598#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 65597#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65596#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65595#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65594#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65593#L926-3 assume !(0 == ~E_4~0); 65592#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65591#L936-3 assume !(0 == ~E_6~0); 65590#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65589#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 65588#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65587#L430-30 assume 1 == ~m_pc~0; 65585#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65583#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65581#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 65579#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65578#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65577#L449-30 assume !(1 == ~t1_pc~0); 65575#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 65574#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65573#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65572#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65571#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65570#L468-30 assume !(1 == ~t2_pc~0); 65569#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 65567#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65566#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65565#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65564#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65563#L487-30 assume !(1 == ~t3_pc~0); 65561#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 65560#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65559#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65558#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65557#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65556#L506-30 assume !(1 == ~t4_pc~0); 65555#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 65553#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65552#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65551#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 65550#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65549#L525-30 assume 1 == ~t5_pc~0; 65547#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65546#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65545#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65544#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65543#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65542#L544-30 assume !(1 == ~t6_pc~0); 65541#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 65539#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65538#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65537#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65536#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65535#L563-30 assume 1 == ~t7_pc~0; 65533#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65532#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65531#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65530#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65529#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65528#L582-30 assume !(1 == ~t8_pc~0); 65526#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 65525#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65524#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65523#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65522#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65521#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63106#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65520#L969-3 assume !(1 == ~T2_E~0); 65519#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65518#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65517#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63661#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65516#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65515#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65505#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65503#L1009-3 assume !(1 == ~E_1~0); 65501#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65498#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65496#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64965#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65493#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65491#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65489#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65486#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 65477#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 65473#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 65471#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 65469#L1334 assume !(0 == start_simulation_~tmp~3#1); 63991#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 64783#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 64774#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 64772#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 64770#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64768#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64766#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 64231#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 64225#L1315-2 [2022-02-21 04:22:34,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:34,828 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2022-02-21 04:22:34,829 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:34,829 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604970999] [2022-02-21 04:22:34,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:34,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:34,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:34,850 INFO L290 TraceCheckUtils]: 0: Hoare triple {85430#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,850 INFO L290 TraceCheckUtils]: 1: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,851 INFO L290 TraceCheckUtils]: 2: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,851 INFO L290 TraceCheckUtils]: 3: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,851 INFO L290 TraceCheckUtils]: 4: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,852 INFO L290 TraceCheckUtils]: 5: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,852 INFO L290 TraceCheckUtils]: 6: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,852 INFO L290 TraceCheckUtils]: 7: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,852 INFO L290 TraceCheckUtils]: 8: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,853 INFO L290 TraceCheckUtils]: 9: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,853 INFO L290 TraceCheckUtils]: 10: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,853 INFO L290 TraceCheckUtils]: 11: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,854 INFO L290 TraceCheckUtils]: 12: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,854 INFO L290 TraceCheckUtils]: 13: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,854 INFO L290 TraceCheckUtils]: 14: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,855 INFO L290 TraceCheckUtils]: 15: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,855 INFO L290 TraceCheckUtils]: 16: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,855 INFO L290 TraceCheckUtils]: 17: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,855 INFO L290 TraceCheckUtils]: 18: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,856 INFO L290 TraceCheckUtils]: 19: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,856 INFO L290 TraceCheckUtils]: 20: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,856 INFO L290 TraceCheckUtils]: 21: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,857 INFO L290 TraceCheckUtils]: 22: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,857 INFO L290 TraceCheckUtils]: 23: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,857 INFO L290 TraceCheckUtils]: 24: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,857 INFO L290 TraceCheckUtils]: 25: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,858 INFO L290 TraceCheckUtils]: 26: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,858 INFO L290 TraceCheckUtils]: 27: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,858 INFO L290 TraceCheckUtils]: 28: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,859 INFO L290 TraceCheckUtils]: 29: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,859 INFO L290 TraceCheckUtils]: 30: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,859 INFO L290 TraceCheckUtils]: 31: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,860 INFO L290 TraceCheckUtils]: 32: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {85432#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:34,860 INFO L290 TraceCheckUtils]: 33: Hoare triple {85432#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {85433#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:34,860 INFO L290 TraceCheckUtils]: 34: Hoare triple {85433#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {85433#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:34,860 INFO L290 TraceCheckUtils]: 35: Hoare triple {85433#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {85433#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:34,861 INFO L290 TraceCheckUtils]: 36: Hoare triple {85433#(not (= ~t1_pc~0 1))} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {85433#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:34,861 INFO L290 TraceCheckUtils]: 37: Hoare triple {85433#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {85433#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:34,861 INFO L290 TraceCheckUtils]: 38: Hoare triple {85433#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {85433#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:34,861 INFO L290 TraceCheckUtils]: 39: Hoare triple {85433#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 40: Hoare triple {85431#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 41: Hoare triple {85431#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 42: Hoare triple {85431#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 43: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___0~0#1); {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 44: Hoare triple {85431#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 45: Hoare triple {85431#false} assume !(1 == ~t2_pc~0); {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 46: Hoare triple {85431#false} is_transmit2_triggered_~__retres1~2#1 := 0; {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 47: Hoare triple {85431#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {85431#false} is VALID [2022-02-21 04:22:34,862 INFO L290 TraceCheckUtils]: 48: Hoare triple {85431#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 49: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___1~0#1); {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 50: Hoare triple {85431#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 51: Hoare triple {85431#false} assume 1 == ~t3_pc~0; {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 52: Hoare triple {85431#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 53: Hoare triple {85431#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 54: Hoare triple {85431#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 55: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___2~0#1); {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 56: Hoare triple {85431#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {85431#false} is VALID [2022-02-21 04:22:34,863 INFO L290 TraceCheckUtils]: 57: Hoare triple {85431#false} assume !(1 == ~t4_pc~0); {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 58: Hoare triple {85431#false} is_transmit4_triggered_~__retres1~4#1 := 0; {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 59: Hoare triple {85431#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 60: Hoare triple {85431#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 61: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___3~0#1); {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 62: Hoare triple {85431#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 63: Hoare triple {85431#false} assume 1 == ~t5_pc~0; {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 64: Hoare triple {85431#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 65: Hoare triple {85431#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {85431#false} is VALID [2022-02-21 04:22:34,864 INFO L290 TraceCheckUtils]: 66: Hoare triple {85431#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 67: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___4~0#1); {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 68: Hoare triple {85431#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 69: Hoare triple {85431#false} assume !(1 == ~t6_pc~0); {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 70: Hoare triple {85431#false} is_transmit6_triggered_~__retres1~6#1 := 0; {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 71: Hoare triple {85431#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 72: Hoare triple {85431#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 73: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___5~0#1); {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 74: Hoare triple {85431#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {85431#false} is VALID [2022-02-21 04:22:34,865 INFO L290 TraceCheckUtils]: 75: Hoare triple {85431#false} assume 1 == ~t7_pc~0; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 76: Hoare triple {85431#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 77: Hoare triple {85431#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 78: Hoare triple {85431#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 79: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___6~0#1); {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 80: Hoare triple {85431#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 81: Hoare triple {85431#false} assume 1 == ~t8_pc~0; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 82: Hoare triple {85431#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 83: Hoare triple {85431#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {85431#false} is VALID [2022-02-21 04:22:34,866 INFO L290 TraceCheckUtils]: 84: Hoare triple {85431#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 85: Hoare triple {85431#false} assume !(0 != activate_threads_~tmp___7~0#1); {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 86: Hoare triple {85431#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 87: Hoare triple {85431#false} assume !(1 == ~M_E~0); {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 88: Hoare triple {85431#false} assume !(1 == ~T1_E~0); {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 89: Hoare triple {85431#false} assume !(1 == ~T2_E~0); {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 90: Hoare triple {85431#false} assume !(1 == ~T3_E~0); {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 91: Hoare triple {85431#false} assume !(1 == ~T4_E~0); {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 92: Hoare triple {85431#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {85431#false} is VALID [2022-02-21 04:22:34,867 INFO L290 TraceCheckUtils]: 93: Hoare triple {85431#false} assume !(1 == ~T6_E~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 94: Hoare triple {85431#false} assume !(1 == ~T7_E~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 95: Hoare triple {85431#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 96: Hoare triple {85431#false} assume !(1 == ~E_M~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 97: Hoare triple {85431#false} assume !(1 == ~E_1~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 98: Hoare triple {85431#false} assume !(1 == ~E_2~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 99: Hoare triple {85431#false} assume !(1 == ~E_3~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 100: Hoare triple {85431#false} assume 1 == ~E_4~0;~E_4~0 := 2; {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 101: Hoare triple {85431#false} assume !(1 == ~E_5~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 102: Hoare triple {85431#false} assume !(1 == ~E_6~0); {85431#false} is VALID [2022-02-21 04:22:34,868 INFO L290 TraceCheckUtils]: 103: Hoare triple {85431#false} assume 1 == ~E_7~0;~E_7~0 := 2; {85431#false} is VALID [2022-02-21 04:22:34,869 INFO L290 TraceCheckUtils]: 104: Hoare triple {85431#false} assume !(1 == ~E_8~0); {85431#false} is VALID [2022-02-21 04:22:34,869 INFO L290 TraceCheckUtils]: 105: Hoare triple {85431#false} assume { :end_inline_reset_delta_events } true; {85431#false} is VALID [2022-02-21 04:22:34,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:34,869 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:34,869 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604970999] [2022-02-21 04:22:34,869 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604970999] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:34,870 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:34,870 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:34,870 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317768449] [2022-02-21 04:22:34,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:34,870 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:34,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:34,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1737814391, now seen corresponding path program 1 times [2022-02-21 04:22:34,871 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:34,871 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164402932] [2022-02-21 04:22:34,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:34,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:34,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:34,890 INFO L290 TraceCheckUtils]: 0: Hoare triple {85434#true} assume !false; {85434#true} is VALID [2022-02-21 04:22:34,890 INFO L290 TraceCheckUtils]: 1: Hoare triple {85434#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 2: Hoare triple {85434#true} assume !false; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 3: Hoare triple {85434#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 4: Hoare triple {85434#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 5: Hoare triple {85434#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 6: Hoare triple {85434#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 7: Hoare triple {85434#true} assume !(0 != eval_~tmp~0#1); {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 8: Hoare triple {85434#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 9: Hoare triple {85434#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {85434#true} is VALID [2022-02-21 04:22:34,891 INFO L290 TraceCheckUtils]: 10: Hoare triple {85434#true} assume 0 == ~M_E~0;~M_E~0 := 1; {85434#true} is VALID [2022-02-21 04:22:34,892 INFO L290 TraceCheckUtils]: 11: Hoare triple {85434#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {85434#true} is VALID [2022-02-21 04:22:34,892 INFO L290 TraceCheckUtils]: 12: Hoare triple {85434#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,892 INFO L290 TraceCheckUtils]: 13: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,892 INFO L290 TraceCheckUtils]: 14: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,893 INFO L290 TraceCheckUtils]: 15: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,893 INFO L290 TraceCheckUtils]: 16: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,893 INFO L290 TraceCheckUtils]: 17: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,893 INFO L290 TraceCheckUtils]: 18: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,894 INFO L290 TraceCheckUtils]: 19: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,894 INFO L290 TraceCheckUtils]: 20: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,894 INFO L290 TraceCheckUtils]: 21: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,894 INFO L290 TraceCheckUtils]: 22: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,895 INFO L290 TraceCheckUtils]: 23: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,895 INFO L290 TraceCheckUtils]: 24: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,895 INFO L290 TraceCheckUtils]: 25: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,895 INFO L290 TraceCheckUtils]: 26: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,896 INFO L290 TraceCheckUtils]: 27: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,896 INFO L290 TraceCheckUtils]: 28: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,896 INFO L290 TraceCheckUtils]: 29: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,897 INFO L290 TraceCheckUtils]: 30: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,897 INFO L290 TraceCheckUtils]: 31: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,897 INFO L290 TraceCheckUtils]: 32: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,897 INFO L290 TraceCheckUtils]: 33: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,898 INFO L290 TraceCheckUtils]: 34: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,898 INFO L290 TraceCheckUtils]: 35: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,898 INFO L290 TraceCheckUtils]: 36: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,898 INFO L290 TraceCheckUtils]: 37: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,899 INFO L290 TraceCheckUtils]: 38: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,899 INFO L290 TraceCheckUtils]: 39: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,899 INFO L290 TraceCheckUtils]: 40: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,899 INFO L290 TraceCheckUtils]: 41: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,900 INFO L290 TraceCheckUtils]: 42: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,900 INFO L290 TraceCheckUtils]: 43: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,900 INFO L290 TraceCheckUtils]: 44: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,900 INFO L290 TraceCheckUtils]: 45: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,901 INFO L290 TraceCheckUtils]: 46: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,901 INFO L290 TraceCheckUtils]: 47: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,901 INFO L290 TraceCheckUtils]: 48: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,902 INFO L290 TraceCheckUtils]: 49: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,902 INFO L290 TraceCheckUtils]: 50: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,902 INFO L290 TraceCheckUtils]: 51: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,902 INFO L290 TraceCheckUtils]: 52: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,903 INFO L290 TraceCheckUtils]: 53: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,903 INFO L290 TraceCheckUtils]: 54: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,903 INFO L290 TraceCheckUtils]: 55: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,903 INFO L290 TraceCheckUtils]: 56: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,904 INFO L290 TraceCheckUtils]: 57: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,904 INFO L290 TraceCheckUtils]: 58: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,904 INFO L290 TraceCheckUtils]: 59: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,904 INFO L290 TraceCheckUtils]: 60: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,905 INFO L290 TraceCheckUtils]: 61: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,905 INFO L290 TraceCheckUtils]: 62: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,905 INFO L290 TraceCheckUtils]: 63: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,905 INFO L290 TraceCheckUtils]: 64: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,906 INFO L290 TraceCheckUtils]: 65: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,906 INFO L290 TraceCheckUtils]: 66: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,906 INFO L290 TraceCheckUtils]: 67: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,906 INFO L290 TraceCheckUtils]: 68: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,907 INFO L290 TraceCheckUtils]: 69: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,907 INFO L290 TraceCheckUtils]: 70: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,907 INFO L290 TraceCheckUtils]: 71: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,908 INFO L290 TraceCheckUtils]: 72: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,908 INFO L290 TraceCheckUtils]: 73: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,908 INFO L290 TraceCheckUtils]: 74: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,908 INFO L290 TraceCheckUtils]: 75: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,909 INFO L290 TraceCheckUtils]: 76: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,909 INFO L290 TraceCheckUtils]: 77: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,909 INFO L290 TraceCheckUtils]: 78: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,909 INFO L290 TraceCheckUtils]: 79: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,910 INFO L290 TraceCheckUtils]: 80: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,910 INFO L290 TraceCheckUtils]: 81: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,910 INFO L290 TraceCheckUtils]: 82: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,910 INFO L290 TraceCheckUtils]: 83: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,911 INFO L290 TraceCheckUtils]: 84: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {85436#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:34,911 INFO L290 TraceCheckUtils]: 85: Hoare triple {85436#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {85435#false} is VALID [2022-02-21 04:22:34,911 INFO L290 TraceCheckUtils]: 86: Hoare triple {85435#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,911 INFO L290 TraceCheckUtils]: 87: Hoare triple {85435#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,911 INFO L290 TraceCheckUtils]: 88: Hoare triple {85435#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,911 INFO L290 TraceCheckUtils]: 89: Hoare triple {85435#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 90: Hoare triple {85435#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 91: Hoare triple {85435#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 92: Hoare triple {85435#false} assume 1 == ~E_M~0;~E_M~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 93: Hoare triple {85435#false} assume !(1 == ~E_1~0); {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 94: Hoare triple {85435#false} assume 1 == ~E_2~0;~E_2~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 95: Hoare triple {85435#false} assume 1 == ~E_3~0;~E_3~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 96: Hoare triple {85435#false} assume 1 == ~E_4~0;~E_4~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 97: Hoare triple {85435#false} assume 1 == ~E_5~0;~E_5~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 98: Hoare triple {85435#false} assume 1 == ~E_6~0;~E_6~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,912 INFO L290 TraceCheckUtils]: 99: Hoare triple {85435#false} assume 1 == ~E_7~0;~E_7~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 100: Hoare triple {85435#false} assume 1 == ~E_8~0;~E_8~0 := 2; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 101: Hoare triple {85435#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 102: Hoare triple {85435#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 103: Hoare triple {85435#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 104: Hoare triple {85435#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 105: Hoare triple {85435#false} assume !(0 == start_simulation_~tmp~3#1); {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 106: Hoare triple {85435#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 107: Hoare triple {85435#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {85435#false} is VALID [2022-02-21 04:22:34,913 INFO L290 TraceCheckUtils]: 108: Hoare triple {85435#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {85435#false} is VALID [2022-02-21 04:22:34,914 INFO L290 TraceCheckUtils]: 109: Hoare triple {85435#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {85435#false} is VALID [2022-02-21 04:22:34,914 INFO L290 TraceCheckUtils]: 110: Hoare triple {85435#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {85435#false} is VALID [2022-02-21 04:22:34,914 INFO L290 TraceCheckUtils]: 111: Hoare triple {85435#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {85435#false} is VALID [2022-02-21 04:22:34,914 INFO L290 TraceCheckUtils]: 112: Hoare triple {85435#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {85435#false} is VALID [2022-02-21 04:22:34,914 INFO L290 TraceCheckUtils]: 113: Hoare triple {85435#false} assume !(0 != start_simulation_~tmp___0~1#1); {85435#false} is VALID [2022-02-21 04:22:34,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:34,915 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:34,915 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164402932] [2022-02-21 04:22:34,915 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164402932] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:34,915 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:34,915 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:34,915 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434059256] [2022-02-21 04:22:34,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:34,915 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:34,916 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:34,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:34,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:34,916 INFO L87 Difference]: Start difference. First operand 3424 states and 5002 transitions. cyclomatic complexity: 1582 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:38,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:38,844 INFO L93 Difference]: Finished difference Result 9389 states and 13529 transitions. [2022-02-21 04:22:38,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:38,844 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:38,919 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:38,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9389 states and 13529 transitions. [2022-02-21 04:22:40,797 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8960 [2022-02-21 04:22:42,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9389 states to 9389 states and 13529 transitions. [2022-02-21 04:22:42,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9389 [2022-02-21 04:22:42,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9389 [2022-02-21 04:22:42,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9389 states and 13529 transitions. [2022-02-21 04:22:42,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:42,657 INFO L681 BuchiCegarLoop]: Abstraction has 9389 states and 13529 transitions. [2022-02-21 04:22:42,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9389 states and 13529 transitions. [2022-02-21 04:22:42,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9389 to 8901. [2022-02-21 04:22:42,723 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:42,733 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9389 states and 13529 transitions. Second operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:42,742 INFO L74 IsIncluded]: Start isIncluded. First operand 9389 states and 13529 transitions. Second operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:42,751 INFO L87 Difference]: Start difference. First operand 9389 states and 13529 transitions. Second operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:44,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:44,689 INFO L93 Difference]: Finished difference Result 9389 states and 13529 transitions. [2022-02-21 04:22:44,689 INFO L276 IsEmpty]: Start isEmpty. Operand 9389 states and 13529 transitions. [2022-02-21 04:22:44,697 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:44,697 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:44,707 INFO L74 IsIncluded]: Start isIncluded. First operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9389 states and 13529 transitions. [2022-02-21 04:22:44,715 INFO L87 Difference]: Start difference. First operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9389 states and 13529 transitions. [2022-02-21 04:22:46,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:46,570 INFO L93 Difference]: Finished difference Result 9389 states and 13529 transitions. [2022-02-21 04:22:46,570 INFO L276 IsEmpty]: Start isEmpty. Operand 9389 states and 13529 transitions. [2022-02-21 04:22:46,579 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:46,579 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:46,579 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:46,579 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:46,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:48,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8901 states to 8901 states and 12861 transitions. [2022-02-21 04:22:48,393 INFO L704 BuchiCegarLoop]: Abstraction has 8901 states and 12861 transitions. [2022-02-21 04:22:48,393 INFO L587 BuchiCegarLoop]: Abstraction has 8901 states and 12861 transitions. [2022-02-21 04:22:48,393 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:22:48,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8901 states and 12861 transitions. [2022-02-21 04:22:48,408 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8732 [2022-02-21 04:22:48,408 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:48,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:48,409 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:48,409 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:48,410 INFO L791 eck$LassoCheckResult]: Stem: 95652#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 95653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 95564#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95565#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95394#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 95395#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94965#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94966#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95047#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95889#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94935#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 94936#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95357#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95383#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95051#L866 assume !(0 == ~M_E~0); 95052#L866-2 assume !(0 == ~T1_E~0); 95597#L871-1 assume !(0 == ~T2_E~0); 95598#L876-1 assume !(0 == ~T3_E~0); 95965#L881-1 assume !(0 == ~T4_E~0); 95609#L886-1 assume !(0 == ~T5_E~0); 95348#L891-1 assume !(0 == ~T6_E~0); 95349#L896-1 assume !(0 == ~T7_E~0); 95601#L901-1 assume !(0 == ~T8_E~0); 95623#L906-1 assume !(0 == ~E_M~0); 95624#L911-1 assume !(0 == ~E_1~0); 95392#L916-1 assume !(0 == ~E_2~0); 95393#L921-1 assume !(0 == ~E_3~0); 95756#L926-1 assume !(0 == ~E_4~0); 95903#L931-1 assume !(0 == ~E_5~0); 95985#L936-1 assume !(0 == ~E_6~0); 95997#L941-1 assume !(0 == ~E_7~0); 95398#L946-1 assume !(0 == ~E_8~0); 95399#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95936#L430 assume !(1 == ~m_pc~0); 95856#L430-2 is_master_triggered_~__retres1~0#1 := 0; 94869#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94870#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95515#L1073 assume !(0 != activate_threads_~tmp~1#1); 95528#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95735#L449 assume !(1 == ~t1_pc~0); 95054#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95055#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94828#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94829#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 95639#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95458#L468 assume !(1 == ~t2_pc~0); 94853#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94852#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95356#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95256#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 94871#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94872#L487 assume 1 == ~t3_pc~0; 95961#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94969#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94970#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95719#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 95322#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95323#L506 assume !(1 == ~t4_pc~0); 95454#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 95508#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95919#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95920#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 95448#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95267#L525 assume 1 == ~t5_pc~0; 95200#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94913#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95403#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95404#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 95113#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95114#L544 assume !(1 == ~t6_pc~0); 95268#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95269#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95662#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94895#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 94896#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95870#L563 assume 1 == ~t7_pc~0; 95681#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94923#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94924#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95350#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 95056#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95057#L582 assume 1 == ~t8_pc~0; 94980#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94981#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 95962#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95309#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 95204#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95205#L964 assume !(1 == ~M_E~0); 95737#L964-2 assume !(1 == ~T1_E~0); 95115#L969-1 assume !(1 == ~T2_E~0); 95116#L974-1 assume !(1 == ~T3_E~0); 95776#L979-1 assume !(1 == ~T4_E~0); 95777#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 99120#L989-1 assume !(1 == ~T6_E~0); 99119#L994-1 assume !(1 == ~T7_E~0); 99118#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 99117#L1004-1 assume !(1 == ~E_M~0); 99116#L1009-1 assume !(1 == ~E_1~0); 99115#L1014-1 assume !(1 == ~E_2~0); 99114#L1019-1 assume !(1 == ~E_3~0); 99113#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 95076#L1029-1 assume !(1 == ~E_5~0); 95077#L1034-1 assume !(1 == ~E_6~0); 95174#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 95926#L1044-1 assume !(1 == ~E_8~0); 95366#L1049-1 assume { :end_inline_reset_delta_events } true; 95045#L1315-2 [2022-02-21 04:22:48,410 INFO L793 eck$LassoCheckResult]: Loop: 95045#L1315-2 assume !false; 95046#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102289#L841 assume !false; 102288#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 95108#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 95109#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 102270#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 102267#L724 assume !(0 != eval_~tmp~0#1); 102268#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103572#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103573#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103578#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 95178#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 95179#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95192#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 95193#L886-3 assume !(0 == ~T5_E~0); 95428#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95429#L896-3 assume !(0 == ~T7_E~0); 95292#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 95293#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 95430#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95765#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103388#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103386#L926-3 assume !(0 == ~E_4~0); 103385#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103384#L936-3 assume !(0 == ~E_6~0); 103383#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103382#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103381#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103378#L430-30 assume !(1 == ~m_pc~0); 103377#L430-32 is_master_triggered_~__retres1~0#1 := 0; 103376#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103375#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 103374#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 103373#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103372#L449-30 assume !(1 == ~t1_pc~0); 103371#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 103370#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103369#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 103368#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103367#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103366#L468-30 assume !(1 == ~t2_pc~0); 103365#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 103363#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103362#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 103361#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103360#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103359#L487-30 assume !(1 == ~t3_pc~0); 103357#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 103356#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103355#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103354#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103353#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103352#L506-30 assume !(1 == ~t4_pc~0); 103351#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 103349#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103348#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 103347#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 103346#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103345#L525-30 assume !(1 == ~t5_pc~0); 103344#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 103342#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103341#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103340#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 103339#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103338#L544-30 assume !(1 == ~t6_pc~0); 103337#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 103335#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103334#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103333#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103332#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103331#L563-30 assume 1 == ~t7_pc~0; 103329#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 103328#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103327#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103326#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 103325#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103324#L582-30 assume 1 == ~t8_pc~0; 103323#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 103321#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103320#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103319#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 103318#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103317#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 99604#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103316#L969-3 assume !(1 == ~T2_E~0); 103315#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103314#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103313#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101656#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103312#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103311#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103310#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 103309#L1009-3 assume !(1 == ~E_1~0); 103308#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103307#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103306#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99565#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103305#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103304#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101558#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101553#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 101554#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 101536#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 101537#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 96052#L1334 assume !(0 == start_simulation_~tmp~3#1); 95838#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 95124#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 94832#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 94833#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 95446#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 95905#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 95663#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 95664#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 95045#L1315-2 [2022-02-21 04:22:48,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:48,410 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2022-02-21 04:22:48,411 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:48,411 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193002073] [2022-02-21 04:22:48,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:48,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:48,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:48,440 INFO L290 TraceCheckUtils]: 0: Hoare triple {122510#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,441 INFO L290 TraceCheckUtils]: 1: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,441 INFO L290 TraceCheckUtils]: 2: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,441 INFO L290 TraceCheckUtils]: 3: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,442 INFO L290 TraceCheckUtils]: 4: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,442 INFO L290 TraceCheckUtils]: 5: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,442 INFO L290 TraceCheckUtils]: 6: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,442 INFO L290 TraceCheckUtils]: 7: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,443 INFO L290 TraceCheckUtils]: 8: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,443 INFO L290 TraceCheckUtils]: 9: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,443 INFO L290 TraceCheckUtils]: 10: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,444 INFO L290 TraceCheckUtils]: 11: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,444 INFO L290 TraceCheckUtils]: 12: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,444 INFO L290 TraceCheckUtils]: 13: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,445 INFO L290 TraceCheckUtils]: 14: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,445 INFO L290 TraceCheckUtils]: 15: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,445 INFO L290 TraceCheckUtils]: 16: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,445 INFO L290 TraceCheckUtils]: 17: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,446 INFO L290 TraceCheckUtils]: 18: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,446 INFO L290 TraceCheckUtils]: 19: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,446 INFO L290 TraceCheckUtils]: 20: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T6_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,447 INFO L290 TraceCheckUtils]: 21: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T7_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,447 INFO L290 TraceCheckUtils]: 22: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T8_E~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,447 INFO L290 TraceCheckUtils]: 23: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_M~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,448 INFO L290 TraceCheckUtils]: 24: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,448 INFO L290 TraceCheckUtils]: 25: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,448 INFO L290 TraceCheckUtils]: 26: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,448 INFO L290 TraceCheckUtils]: 27: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,449 INFO L290 TraceCheckUtils]: 28: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,449 INFO L290 TraceCheckUtils]: 29: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_6~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,449 INFO L290 TraceCheckUtils]: 30: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_7~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,450 INFO L290 TraceCheckUtils]: 31: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_8~0); {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,450 INFO L290 TraceCheckUtils]: 32: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122512#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:48,450 INFO L290 TraceCheckUtils]: 33: Hoare triple {122512#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,450 INFO L290 TraceCheckUtils]: 34: Hoare triple {122513#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,451 INFO L290 TraceCheckUtils]: 35: Hoare triple {122513#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,451 INFO L290 TraceCheckUtils]: 36: Hoare triple {122513#(not (= ~t3_pc~0 1))} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,451 INFO L290 TraceCheckUtils]: 37: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,452 INFO L290 TraceCheckUtils]: 38: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,452 INFO L290 TraceCheckUtils]: 39: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,452 INFO L290 TraceCheckUtils]: 40: Hoare triple {122513#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,452 INFO L290 TraceCheckUtils]: 41: Hoare triple {122513#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,453 INFO L290 TraceCheckUtils]: 42: Hoare triple {122513#(not (= ~t3_pc~0 1))} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,453 INFO L290 TraceCheckUtils]: 43: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,453 INFO L290 TraceCheckUtils]: 44: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,453 INFO L290 TraceCheckUtils]: 45: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,454 INFO L290 TraceCheckUtils]: 46: Hoare triple {122513#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,454 INFO L290 TraceCheckUtils]: 47: Hoare triple {122513#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,454 INFO L290 TraceCheckUtils]: 48: Hoare triple {122513#(not (= ~t3_pc~0 1))} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,454 INFO L290 TraceCheckUtils]: 49: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,455 INFO L290 TraceCheckUtils]: 50: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122513#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:48,455 INFO L290 TraceCheckUtils]: 51: Hoare triple {122513#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {122511#false} is VALID [2022-02-21 04:22:48,455 INFO L290 TraceCheckUtils]: 52: Hoare triple {122511#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {122511#false} is VALID [2022-02-21 04:22:48,455 INFO L290 TraceCheckUtils]: 53: Hoare triple {122511#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122511#false} is VALID [2022-02-21 04:22:48,455 INFO L290 TraceCheckUtils]: 54: Hoare triple {122511#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {122511#false} is VALID [2022-02-21 04:22:48,455 INFO L290 TraceCheckUtils]: 55: Hoare triple {122511#false} assume !(0 != activate_threads_~tmp___2~0#1); {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 56: Hoare triple {122511#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 57: Hoare triple {122511#false} assume !(1 == ~t4_pc~0); {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 58: Hoare triple {122511#false} is_transmit4_triggered_~__retres1~4#1 := 0; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 59: Hoare triple {122511#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 60: Hoare triple {122511#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 61: Hoare triple {122511#false} assume !(0 != activate_threads_~tmp___3~0#1); {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 62: Hoare triple {122511#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 63: Hoare triple {122511#false} assume 1 == ~t5_pc~0; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 64: Hoare triple {122511#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 65: Hoare triple {122511#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122511#false} is VALID [2022-02-21 04:22:48,456 INFO L290 TraceCheckUtils]: 66: Hoare triple {122511#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 67: Hoare triple {122511#false} assume !(0 != activate_threads_~tmp___4~0#1); {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 68: Hoare triple {122511#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 69: Hoare triple {122511#false} assume !(1 == ~t6_pc~0); {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 70: Hoare triple {122511#false} is_transmit6_triggered_~__retres1~6#1 := 0; {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 71: Hoare triple {122511#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 72: Hoare triple {122511#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 73: Hoare triple {122511#false} assume !(0 != activate_threads_~tmp___5~0#1); {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 74: Hoare triple {122511#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 75: Hoare triple {122511#false} assume 1 == ~t7_pc~0; {122511#false} is VALID [2022-02-21 04:22:48,457 INFO L290 TraceCheckUtils]: 76: Hoare triple {122511#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 77: Hoare triple {122511#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 78: Hoare triple {122511#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 79: Hoare triple {122511#false} assume !(0 != activate_threads_~tmp___6~0#1); {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 80: Hoare triple {122511#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 81: Hoare triple {122511#false} assume 1 == ~t8_pc~0; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 82: Hoare triple {122511#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 83: Hoare triple {122511#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 84: Hoare triple {122511#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 85: Hoare triple {122511#false} assume !(0 != activate_threads_~tmp___7~0#1); {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 86: Hoare triple {122511#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122511#false} is VALID [2022-02-21 04:22:48,458 INFO L290 TraceCheckUtils]: 87: Hoare triple {122511#false} assume !(1 == ~M_E~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 88: Hoare triple {122511#false} assume !(1 == ~T1_E~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 89: Hoare triple {122511#false} assume !(1 == ~T2_E~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 90: Hoare triple {122511#false} assume !(1 == ~T3_E~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 91: Hoare triple {122511#false} assume !(1 == ~T4_E~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 92: Hoare triple {122511#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 93: Hoare triple {122511#false} assume !(1 == ~T6_E~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 94: Hoare triple {122511#false} assume !(1 == ~T7_E~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 95: Hoare triple {122511#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 96: Hoare triple {122511#false} assume !(1 == ~E_M~0); {122511#false} is VALID [2022-02-21 04:22:48,459 INFO L290 TraceCheckUtils]: 97: Hoare triple {122511#false} assume !(1 == ~E_1~0); {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 98: Hoare triple {122511#false} assume !(1 == ~E_2~0); {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 99: Hoare triple {122511#false} assume !(1 == ~E_3~0); {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 100: Hoare triple {122511#false} assume 1 == ~E_4~0;~E_4~0 := 2; {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 101: Hoare triple {122511#false} assume !(1 == ~E_5~0); {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 102: Hoare triple {122511#false} assume !(1 == ~E_6~0); {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 103: Hoare triple {122511#false} assume 1 == ~E_7~0;~E_7~0 := 2; {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 104: Hoare triple {122511#false} assume !(1 == ~E_8~0); {122511#false} is VALID [2022-02-21 04:22:48,460 INFO L290 TraceCheckUtils]: 105: Hoare triple {122511#false} assume { :end_inline_reset_delta_events } true; {122511#false} is VALID [2022-02-21 04:22:48,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:48,461 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:48,461 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193002073] [2022-02-21 04:22:48,461 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193002073] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:48,461 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:48,461 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:48,461 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280395515] [2022-02-21 04:22:48,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:48,462 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:48,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:48,462 INFO L85 PathProgramCache]: Analyzing trace with hash 1524368378, now seen corresponding path program 1 times [2022-02-21 04:22:48,462 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:48,462 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825766105] [2022-02-21 04:22:48,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:48,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:48,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:48,481 INFO L290 TraceCheckUtils]: 0: Hoare triple {122514#true} assume !false; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 1: Hoare triple {122514#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 2: Hoare triple {122514#true} assume !false; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 3: Hoare triple {122514#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 4: Hoare triple {122514#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 5: Hoare triple {122514#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 6: Hoare triple {122514#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 7: Hoare triple {122514#true} assume !(0 != eval_~tmp~0#1); {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 8: Hoare triple {122514#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {122514#true} is VALID [2022-02-21 04:22:48,482 INFO L290 TraceCheckUtils]: 9: Hoare triple {122514#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {122514#true} is VALID [2022-02-21 04:22:48,483 INFO L290 TraceCheckUtils]: 10: Hoare triple {122514#true} assume 0 == ~M_E~0;~M_E~0 := 1; {122514#true} is VALID [2022-02-21 04:22:48,483 INFO L290 TraceCheckUtils]: 11: Hoare triple {122514#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {122514#true} is VALID [2022-02-21 04:22:48,483 INFO L290 TraceCheckUtils]: 12: Hoare triple {122514#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,483 INFO L290 TraceCheckUtils]: 13: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,484 INFO L290 TraceCheckUtils]: 14: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,484 INFO L290 TraceCheckUtils]: 15: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T5_E~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,484 INFO L290 TraceCheckUtils]: 16: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,484 INFO L290 TraceCheckUtils]: 17: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T7_E~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,485 INFO L290 TraceCheckUtils]: 18: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,485 INFO L290 TraceCheckUtils]: 19: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,485 INFO L290 TraceCheckUtils]: 20: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,485 INFO L290 TraceCheckUtils]: 21: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,486 INFO L290 TraceCheckUtils]: 22: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,486 INFO L290 TraceCheckUtils]: 23: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,486 INFO L290 TraceCheckUtils]: 24: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,486 INFO L290 TraceCheckUtils]: 25: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,487 INFO L290 TraceCheckUtils]: 26: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,487 INFO L290 TraceCheckUtils]: 27: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,487 INFO L290 TraceCheckUtils]: 28: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,488 INFO L290 TraceCheckUtils]: 29: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,488 INFO L290 TraceCheckUtils]: 30: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,488 INFO L290 TraceCheckUtils]: 31: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,488 INFO L290 TraceCheckUtils]: 32: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,489 INFO L290 TraceCheckUtils]: 33: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,489 INFO L290 TraceCheckUtils]: 34: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,489 INFO L290 TraceCheckUtils]: 35: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,489 INFO L290 TraceCheckUtils]: 36: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,490 INFO L290 TraceCheckUtils]: 37: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,490 INFO L290 TraceCheckUtils]: 38: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,490 INFO L290 TraceCheckUtils]: 39: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,491 INFO L290 TraceCheckUtils]: 40: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,491 INFO L290 TraceCheckUtils]: 41: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,491 INFO L290 TraceCheckUtils]: 42: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,491 INFO L290 TraceCheckUtils]: 43: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,492 INFO L290 TraceCheckUtils]: 44: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,492 INFO L290 TraceCheckUtils]: 45: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,492 INFO L290 TraceCheckUtils]: 46: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,492 INFO L290 TraceCheckUtils]: 47: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,493 INFO L290 TraceCheckUtils]: 48: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,493 INFO L290 TraceCheckUtils]: 49: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,493 INFO L290 TraceCheckUtils]: 50: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,494 INFO L290 TraceCheckUtils]: 51: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,494 INFO L290 TraceCheckUtils]: 52: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,494 INFO L290 TraceCheckUtils]: 53: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,494 INFO L290 TraceCheckUtils]: 54: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,495 INFO L290 TraceCheckUtils]: 55: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,495 INFO L290 TraceCheckUtils]: 56: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,495 INFO L290 TraceCheckUtils]: 57: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,495 INFO L290 TraceCheckUtils]: 58: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,496 INFO L290 TraceCheckUtils]: 59: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,496 INFO L290 TraceCheckUtils]: 60: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,496 INFO L290 TraceCheckUtils]: 61: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,496 INFO L290 TraceCheckUtils]: 62: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,497 INFO L290 TraceCheckUtils]: 63: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,497 INFO L290 TraceCheckUtils]: 64: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,497 INFO L290 TraceCheckUtils]: 65: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,498 INFO L290 TraceCheckUtils]: 66: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,498 INFO L290 TraceCheckUtils]: 67: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,498 INFO L290 TraceCheckUtils]: 68: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,499 INFO L290 TraceCheckUtils]: 69: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,499 INFO L290 TraceCheckUtils]: 70: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,499 INFO L290 TraceCheckUtils]: 71: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,499 INFO L290 TraceCheckUtils]: 72: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,500 INFO L290 TraceCheckUtils]: 73: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,500 INFO L290 TraceCheckUtils]: 74: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,500 INFO L290 TraceCheckUtils]: 75: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,501 INFO L290 TraceCheckUtils]: 76: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,501 INFO L290 TraceCheckUtils]: 77: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,501 INFO L290 TraceCheckUtils]: 78: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,501 INFO L290 TraceCheckUtils]: 79: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,502 INFO L290 TraceCheckUtils]: 80: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,502 INFO L290 TraceCheckUtils]: 81: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,502 INFO L290 TraceCheckUtils]: 82: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,503 INFO L290 TraceCheckUtils]: 83: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,503 INFO L290 TraceCheckUtils]: 84: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {122516#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:48,503 INFO L290 TraceCheckUtils]: 85: Hoare triple {122516#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {122515#false} is VALID [2022-02-21 04:22:48,503 INFO L290 TraceCheckUtils]: 86: Hoare triple {122515#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,503 INFO L290 TraceCheckUtils]: 87: Hoare triple {122515#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,503 INFO L290 TraceCheckUtils]: 88: Hoare triple {122515#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,503 INFO L290 TraceCheckUtils]: 89: Hoare triple {122515#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 90: Hoare triple {122515#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 91: Hoare triple {122515#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 92: Hoare triple {122515#false} assume 1 == ~E_M~0;~E_M~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 93: Hoare triple {122515#false} assume !(1 == ~E_1~0); {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 94: Hoare triple {122515#false} assume 1 == ~E_2~0;~E_2~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 95: Hoare triple {122515#false} assume 1 == ~E_3~0;~E_3~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 96: Hoare triple {122515#false} assume 1 == ~E_4~0;~E_4~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 97: Hoare triple {122515#false} assume 1 == ~E_5~0;~E_5~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 98: Hoare triple {122515#false} assume 1 == ~E_6~0;~E_6~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,504 INFO L290 TraceCheckUtils]: 99: Hoare triple {122515#false} assume 1 == ~E_7~0;~E_7~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 100: Hoare triple {122515#false} assume 1 == ~E_8~0;~E_8~0 := 2; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 101: Hoare triple {122515#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 102: Hoare triple {122515#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 103: Hoare triple {122515#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 104: Hoare triple {122515#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 105: Hoare triple {122515#false} assume !(0 == start_simulation_~tmp~3#1); {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 106: Hoare triple {122515#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 107: Hoare triple {122515#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 108: Hoare triple {122515#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {122515#false} is VALID [2022-02-21 04:22:48,505 INFO L290 TraceCheckUtils]: 109: Hoare triple {122515#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {122515#false} is VALID [2022-02-21 04:22:48,506 INFO L290 TraceCheckUtils]: 110: Hoare triple {122515#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {122515#false} is VALID [2022-02-21 04:22:48,506 INFO L290 TraceCheckUtils]: 111: Hoare triple {122515#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {122515#false} is VALID [2022-02-21 04:22:48,506 INFO L290 TraceCheckUtils]: 112: Hoare triple {122515#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {122515#false} is VALID [2022-02-21 04:22:48,506 INFO L290 TraceCheckUtils]: 113: Hoare triple {122515#false} assume !(0 != start_simulation_~tmp___0~1#1); {122515#false} is VALID [2022-02-21 04:22:48,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:48,507 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:48,507 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825766105] [2022-02-21 04:22:48,507 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825766105] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:48,507 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:48,507 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:48,507 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505956410] [2022-02-21 04:22:48,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:48,508 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:48,508 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:48,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:48,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:48,509 INFO L87 Difference]: Start difference. First operand 8901 states and 12861 transitions. cyclomatic complexity: 3968 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,253 INFO L93 Difference]: Finished difference Result 25288 states and 36118 transitions. [2022-02-21 04:23:15,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:15,254 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,320 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 106 edges. 106 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:15,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25288 states and 36118 transitions.