./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:22:48,733 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:22:48,735 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:22:48,765 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:22:48,765 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:22:48,769 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:22:48,771 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:22:48,774 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:22:48,776 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:22:48,781 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:22:48,782 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:22:48,784 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:22:48,784 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:22:48,786 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:22:48,788 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:22:48,790 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:22:48,791 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:22:48,791 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:22:48,796 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:22:48,802 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:22:48,804 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:22:48,805 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:22:48,806 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:22:48,807 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:22:48,809 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:22:48,809 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:22:48,809 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:22:48,811 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:22:48,812 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:22:48,812 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:22:48,813 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:22:48,814 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:22:48,815 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:22:48,816 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:22:48,817 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:22:48,817 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:22:48,818 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:22:48,818 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:22:48,818 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:22:48,819 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:22:48,820 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:22:48,820 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:22:48,852 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:22:48,854 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:22:48,854 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:22:48,855 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:22:48,856 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:22:48,856 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:22:48,856 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:22:48,856 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:22:48,857 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:22:48,857 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:22:48,858 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:22:48,858 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:22:48,858 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:22:48,858 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:22:48,858 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:22:48,858 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:22:48,859 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:22:48,859 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:22:48,859 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:22:48,859 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:22:48,859 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:22:48,860 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:22:48,860 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:22:48,860 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:22:48,860 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:22:48,860 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:22:48,860 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:22:48,861 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:22:48,861 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:22:48,861 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:22:48,861 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:22:48,862 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:22:48,862 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2022-02-21 04:22:49,074 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:22:49,091 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:22:49,094 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:22:49,095 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:22:49,095 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:22:49,096 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2022-02-21 04:22:49,157 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae67a112d/1add2bf736c74f429037ed0245a388c3/FLAGfb4c1f48a [2022-02-21 04:22:49,548 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:22:49,548 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2022-02-21 04:22:49,564 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae67a112d/1add2bf736c74f429037ed0245a388c3/FLAGfb4c1f48a [2022-02-21 04:22:49,915 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae67a112d/1add2bf736c74f429037ed0245a388c3 [2022-02-21 04:22:49,917 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:22:49,918 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:22:49,920 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:49,920 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:22:49,923 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:22:49,924 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:49" (1/1) ... [2022-02-21 04:22:49,925 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6587dd26 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:49, skipping insertion in model container [2022-02-21 04:22:49,925 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:49" (1/1) ... [2022-02-21 04:22:49,931 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:22:49,970 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:22:50,102 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2022-02-21 04:22:50,260 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:50,288 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:22:50,297 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2022-02-21 04:22:50,367 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:50,387 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:22:50,388 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50 WrapperNode [2022-02-21 04:22:50,388 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:50,389 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:50,389 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:22:50,389 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:22:50,398 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,421 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,519 INFO L137 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 182, statements flattened = 2757 [2022-02-21 04:22:50,520 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:50,521 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:22:50,521 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:22:50,521 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:22:50,529 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,529 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,540 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,541 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,581 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,621 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,625 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,646 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:22:50,648 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:22:50,649 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:22:50,649 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:22:50,656 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (1/1) ... [2022-02-21 04:22:50,663 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:22:50,673 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:22:50,683 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:22:50,690 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:22:50,722 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:22:50,722 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:22:50,722 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:22:50,722 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:22:50,844 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:22:50,846 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:22:52,381 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:22:52,397 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:22:52,397 INFO L299 CfgBuilder]: Removed 12 assume(true) statements. [2022-02-21 04:22:52,400 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:52 BoogieIcfgContainer [2022-02-21 04:22:52,400 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:22:52,401 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:22:52,402 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:22:52,405 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:22:52,406 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:52,406 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:22:49" (1/3) ... [2022-02-21 04:22:52,407 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@32bd4194 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:52, skipping insertion in model container [2022-02-21 04:22:52,407 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:52,408 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:50" (2/3) ... [2022-02-21 04:22:52,408 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@32bd4194 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:52, skipping insertion in model container [2022-02-21 04:22:52,408 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:52,408 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:52" (3/3) ... [2022-02-21 04:22:52,410 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2022-02-21 04:22:52,449 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:22:52,449 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:22:52,449 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:22:52,449 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:22:52,450 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:22:52,450 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:22:52,450 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:22:52,450 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:22:52,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:52,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2022-02-21 04:22:52,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:52,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:52,726 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:52,726 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:52,726 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:22:52,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:52,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2022-02-21 04:22:52,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:52,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:52,829 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:52,829 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:52,837 INFO L791 eck$LassoCheckResult]: Stem: 548#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1061#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 500#L1391true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 867#L651true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 751#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 400#L658-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 772#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 716#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 275#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 811#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 623#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1030#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 106#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 335#L703-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1020#L939true assume !(0 == ~M_E~0); 531#L939-2true assume !(0 == ~T1_E~0); 745#L944-1true assume !(0 == ~T2_E~0); 356#L949-1true assume !(0 == ~T3_E~0); 354#L954-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1069#L959-1true assume !(0 == ~T5_E~0); 773#L964-1true assume !(0 == ~T6_E~0); 187#L969-1true assume !(0 == ~T7_E~0); 888#L974-1true assume !(0 == ~T8_E~0); 703#L979-1true assume !(0 == ~T9_E~0); 1096#L984-1true assume !(0 == ~E_M~0); 282#L989-1true assume !(0 == ~E_1~0); 510#L994-1true assume 0 == ~E_2~0;~E_2~0 := 1; 214#L999-1true assume !(0 == ~E_3~0); 670#L1004-1true assume !(0 == ~E_4~0); 40#L1009-1true assume !(0 == ~E_5~0); 209#L1014-1true assume !(0 == ~E_6~0); 630#L1019-1true assume !(0 == ~E_7~0); 938#L1024-1true assume !(0 == ~E_8~0); 170#L1029-1true assume !(0 == ~E_9~0); 222#L1034-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 953#L460true assume 1 == ~m_pc~0; 3#L461true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 596#L471true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1051#L472true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024#L1167true assume !(0 != activate_threads_~tmp~1#1); 346#L1167-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 493#L479true assume 1 == ~t1_pc~0; 336#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1040#L490true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 891#L491true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 177#L1175true assume !(0 != activate_threads_~tmp___0~0#1); 388#L1175-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98#L498true assume !(1 == ~t2_pc~0); 639#L498-2true is_transmit2_triggered_~__retres1~2#1 := 0; 334#L509true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 831#L510true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 671#L1183true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 587#L1183-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1120#L517true assume 1 == ~t3_pc~0; 899#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1063#L528true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 383#L529true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 195#L1191true assume !(0 != activate_threads_~tmp___2~0#1); 641#L1191-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 812#L536true assume !(1 == ~t4_pc~0); 1098#L536-2true is_transmit4_triggered_~__retres1~4#1 := 0; 762#L547true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1087#L548true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 373#L1199true assume !(0 != activate_threads_~tmp___3~0#1); 1085#L1199-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 559#L555true assume 1 == ~t5_pc~0; 1165#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 700#L566true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55#L567true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 171#L1207true assume !(0 != activate_threads_~tmp___4~0#1); 109#L1207-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59#L574true assume !(1 == ~t6_pc~0); 632#L574-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1102#L585true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112#L586true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 665#L1215true assume !(0 != activate_threads_~tmp___5~0#1); 1093#L1215-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 968#L593true assume 1 == ~t7_pc~0; 1138#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 778#L604true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1084#L605true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1078#L1223true assume !(0 != activate_threads_~tmp___6~0#1); 902#L1223-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 280#L612true assume !(1 == ~t8_pc~0); 1017#L612-2true is_transmit8_triggered_~__retres1~8#1 := 0; 892#L623true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 474#L624true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 807#L1231true assume !(0 != activate_threads_~tmp___7~0#1); 444#L1231-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 499#L631true assume 1 == ~t9_pc~0; 456#L632true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54#L642true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39#L643true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 337#L1239true assume !(0 != activate_threads_~tmp___8~0#1); 1050#L1239-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 643#L1047true assume !(1 == ~M_E~0); 26#L1047-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L1052-1true assume !(1 == ~T2_E~0); 18#L1057-1true assume !(1 == ~T3_E~0); 161#L1062-1true assume !(1 == ~T4_E~0); 774#L1067-1true assume !(1 == ~T5_E~0); 348#L1072-1true assume !(1 == ~T6_E~0); 611#L1077-1true assume !(1 == ~T7_E~0); 104#L1082-1true assume !(1 == ~T8_E~0); 419#L1087-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 6#L1092-1true assume !(1 == ~E_M~0); 19#L1097-1true assume !(1 == ~E_1~0); 942#L1102-1true assume !(1 == ~E_2~0); 495#L1107-1true assume !(1 == ~E_3~0); 440#L1112-1true assume !(1 == ~E_4~0); 475#L1117-1true assume !(1 == ~E_5~0); 1153#L1122-1true assume !(1 == ~E_6~0); 384#L1127-1true assume 1 == ~E_7~0;~E_7~0 := 2; 224#L1132-1true assume !(1 == ~E_8~0); 946#L1137-1true assume !(1 == ~E_9~0); 160#L1142-1true assume { :end_inline_reset_delta_events } true; 90#L1428-2true [2022-02-21 04:22:52,847 INFO L793 eck$LassoCheckResult]: Loop: 90#L1428-2true assume !false; 437#L1429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 971#L914true assume false; 216#L929true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 494#L651-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 759#L939-3true assume !(0 == ~M_E~0); 117#L939-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 144#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 5#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 719#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 360#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 41#L964-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 268#L969-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 143#L974-3true assume !(0 == ~T8_E~0); 1055#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 414#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1142#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 174#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 969#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 538#L1004-3true assume 0 == ~E_4~0;~E_4~0 := 1; 82#L1009-3true assume 0 == ~E_5~0;~E_5~0 := 1; 617#L1014-3true assume !(0 == ~E_6~0); 401#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1113#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 391#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 362#L1034-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 922#L460-33true assume !(1 == ~m_pc~0); 571#L460-35true is_master_triggered_~__retres1~0#1 := 0; 550#L471-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226#L472-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9#L1167-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 501#L1167-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190#L479-33true assume 1 == ~t1_pc~0; 934#L480-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 172#L490-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 605#L491-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 870#L1175-33true assume !(0 != activate_threads_~tmp___0~0#1); 992#L1175-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194#L498-33true assume !(1 == ~t2_pc~0); 61#L498-35true is_transmit2_triggered_~__retres1~2#1 := 0; 321#L509-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130#L510-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 429#L1183-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118#L1183-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1000#L517-33true assume !(1 == ~t3_pc~0); 1111#L517-35true is_transmit3_triggered_~__retres1~3#1 := 0; 737#L528-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1091#L529-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 525#L1191-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 666#L1191-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 250#L536-33true assume 1 == ~t4_pc~0; 598#L537-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 290#L547-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418#L548-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 709#L1199-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 813#L1199-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L555-33true assume !(1 == ~t5_pc~0); 800#L555-35true is_transmit5_triggered_~__retres1~5#1 := 0; 470#L566-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 166#L567-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 490#L1207-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1034#L1207-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17#L574-33true assume 1 == ~t6_pc~0; 722#L575-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 846#L585-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#L586-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 572#L1215-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 332#L1215-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51#L593-33true assume 1 == ~t7_pc~0; 399#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 954#L604-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103#L605-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 549#L1223-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 695#L1223-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1119#L612-33true assume 1 == ~t8_pc~0; 919#L613-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 853#L623-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1088#L624-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 610#L1231-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102#L1231-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1162#L631-33true assume !(1 == ~t9_pc~0); 497#L631-35true is_transmit9_triggered_~__retres1~9#1 := 0; 73#L642-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 404#L643-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 208#L1239-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 131#L1239-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227#L1047-3true assume !(1 == ~M_E~0); 771#L1047-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1173#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 677#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1167#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 79#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1025#L1072-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 295#L1077-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 199#L1082-3true assume !(1 == ~T8_E~0); 248#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 434#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1178#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 382#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 952#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 728#L1112-3true assume 1 == ~E_4~0;~E_4~0 := 2; 196#L1117-3true assume 1 == ~E_5~0;~E_5~0 := 2; 735#L1122-3true assume !(1 == ~E_6~0); 228#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 509#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1080#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 486#L1142-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 133#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 492#L768-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 487#L769-1true start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 307#L1447true assume !(0 == start_simulation_~tmp~3#1); 702#L1447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1140#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 732#L768-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 511#L769-2true stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 213#L1402true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 85#L1409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 533#L1410true start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 349#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 90#L1428-2true [2022-02-21 04:22:52,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:52,864 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2022-02-21 04:22:52,871 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:52,872 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738899087] [2022-02-21 04:22:52,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:52,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:53,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:53,111 INFO L290 TraceCheckUtils]: 0: Hoare triple {1180#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {1180#true} is VALID [2022-02-21 04:22:53,113 INFO L290 TraceCheckUtils]: 1: Hoare triple {1180#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {1182#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:53,114 INFO L290 TraceCheckUtils]: 2: Hoare triple {1182#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1182#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:53,115 INFO L290 TraceCheckUtils]: 3: Hoare triple {1182#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1182#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:53,116 INFO L290 TraceCheckUtils]: 4: Hoare triple {1182#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,116 INFO L290 TraceCheckUtils]: 5: Hoare triple {1181#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1181#false} is VALID [2022-02-21 04:22:53,116 INFO L290 TraceCheckUtils]: 6: Hoare triple {1181#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,117 INFO L290 TraceCheckUtils]: 7: Hoare triple {1181#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,117 INFO L290 TraceCheckUtils]: 8: Hoare triple {1181#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,117 INFO L290 TraceCheckUtils]: 9: Hoare triple {1181#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,118 INFO L290 TraceCheckUtils]: 10: Hoare triple {1181#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,118 INFO L290 TraceCheckUtils]: 11: Hoare triple {1181#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,118 INFO L290 TraceCheckUtils]: 12: Hoare triple {1181#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,118 INFO L290 TraceCheckUtils]: 13: Hoare triple {1181#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1181#false} is VALID [2022-02-21 04:22:53,118 INFO L290 TraceCheckUtils]: 14: Hoare triple {1181#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1181#false} is VALID [2022-02-21 04:22:53,119 INFO L290 TraceCheckUtils]: 15: Hoare triple {1181#false} assume !(0 == ~M_E~0); {1181#false} is VALID [2022-02-21 04:22:53,120 INFO L290 TraceCheckUtils]: 16: Hoare triple {1181#false} assume !(0 == ~T1_E~0); {1181#false} is VALID [2022-02-21 04:22:53,120 INFO L290 TraceCheckUtils]: 17: Hoare triple {1181#false} assume !(0 == ~T2_E~0); {1181#false} is VALID [2022-02-21 04:22:53,120 INFO L290 TraceCheckUtils]: 18: Hoare triple {1181#false} assume !(0 == ~T3_E~0); {1181#false} is VALID [2022-02-21 04:22:53,121 INFO L290 TraceCheckUtils]: 19: Hoare triple {1181#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1181#false} is VALID [2022-02-21 04:22:53,121 INFO L290 TraceCheckUtils]: 20: Hoare triple {1181#false} assume !(0 == ~T5_E~0); {1181#false} is VALID [2022-02-21 04:22:53,121 INFO L290 TraceCheckUtils]: 21: Hoare triple {1181#false} assume !(0 == ~T6_E~0); {1181#false} is VALID [2022-02-21 04:22:53,121 INFO L290 TraceCheckUtils]: 22: Hoare triple {1181#false} assume !(0 == ~T7_E~0); {1181#false} is VALID [2022-02-21 04:22:53,121 INFO L290 TraceCheckUtils]: 23: Hoare triple {1181#false} assume !(0 == ~T8_E~0); {1181#false} is VALID [2022-02-21 04:22:53,122 INFO L290 TraceCheckUtils]: 24: Hoare triple {1181#false} assume !(0 == ~T9_E~0); {1181#false} is VALID [2022-02-21 04:22:53,122 INFO L290 TraceCheckUtils]: 25: Hoare triple {1181#false} assume !(0 == ~E_M~0); {1181#false} is VALID [2022-02-21 04:22:53,122 INFO L290 TraceCheckUtils]: 26: Hoare triple {1181#false} assume !(0 == ~E_1~0); {1181#false} is VALID [2022-02-21 04:22:53,123 INFO L290 TraceCheckUtils]: 27: Hoare triple {1181#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1181#false} is VALID [2022-02-21 04:22:53,125 INFO L290 TraceCheckUtils]: 28: Hoare triple {1181#false} assume !(0 == ~E_3~0); {1181#false} is VALID [2022-02-21 04:22:53,125 INFO L290 TraceCheckUtils]: 29: Hoare triple {1181#false} assume !(0 == ~E_4~0); {1181#false} is VALID [2022-02-21 04:22:53,125 INFO L290 TraceCheckUtils]: 30: Hoare triple {1181#false} assume !(0 == ~E_5~0); {1181#false} is VALID [2022-02-21 04:22:53,126 INFO L290 TraceCheckUtils]: 31: Hoare triple {1181#false} assume !(0 == ~E_6~0); {1181#false} is VALID [2022-02-21 04:22:53,126 INFO L290 TraceCheckUtils]: 32: Hoare triple {1181#false} assume !(0 == ~E_7~0); {1181#false} is VALID [2022-02-21 04:22:53,126 INFO L290 TraceCheckUtils]: 33: Hoare triple {1181#false} assume !(0 == ~E_8~0); {1181#false} is VALID [2022-02-21 04:22:53,126 INFO L290 TraceCheckUtils]: 34: Hoare triple {1181#false} assume !(0 == ~E_9~0); {1181#false} is VALID [2022-02-21 04:22:53,126 INFO L290 TraceCheckUtils]: 35: Hoare triple {1181#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1181#false} is VALID [2022-02-21 04:22:53,127 INFO L290 TraceCheckUtils]: 36: Hoare triple {1181#false} assume 1 == ~m_pc~0; {1181#false} is VALID [2022-02-21 04:22:53,127 INFO L290 TraceCheckUtils]: 37: Hoare triple {1181#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1181#false} is VALID [2022-02-21 04:22:53,127 INFO L290 TraceCheckUtils]: 38: Hoare triple {1181#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1181#false} is VALID [2022-02-21 04:22:53,127 INFO L290 TraceCheckUtils]: 39: Hoare triple {1181#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1181#false} is VALID [2022-02-21 04:22:53,128 INFO L290 TraceCheckUtils]: 40: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp~1#1); {1181#false} is VALID [2022-02-21 04:22:53,128 INFO L290 TraceCheckUtils]: 41: Hoare triple {1181#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1181#false} is VALID [2022-02-21 04:22:53,129 INFO L290 TraceCheckUtils]: 42: Hoare triple {1181#false} assume 1 == ~t1_pc~0; {1181#false} is VALID [2022-02-21 04:22:53,129 INFO L290 TraceCheckUtils]: 43: Hoare triple {1181#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1181#false} is VALID [2022-02-21 04:22:53,130 INFO L290 TraceCheckUtils]: 44: Hoare triple {1181#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1181#false} is VALID [2022-02-21 04:22:53,130 INFO L290 TraceCheckUtils]: 45: Hoare triple {1181#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1181#false} is VALID [2022-02-21 04:22:53,130 INFO L290 TraceCheckUtils]: 46: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___0~0#1); {1181#false} is VALID [2022-02-21 04:22:53,131 INFO L290 TraceCheckUtils]: 47: Hoare triple {1181#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1181#false} is VALID [2022-02-21 04:22:53,131 INFO L290 TraceCheckUtils]: 48: Hoare triple {1181#false} assume !(1 == ~t2_pc~0); {1181#false} is VALID [2022-02-21 04:22:53,131 INFO L290 TraceCheckUtils]: 49: Hoare triple {1181#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1181#false} is VALID [2022-02-21 04:22:53,135 INFO L290 TraceCheckUtils]: 50: Hoare triple {1181#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1181#false} is VALID [2022-02-21 04:22:53,136 INFO L290 TraceCheckUtils]: 51: Hoare triple {1181#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1181#false} is VALID [2022-02-21 04:22:53,136 INFO L290 TraceCheckUtils]: 52: Hoare triple {1181#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1181#false} is VALID [2022-02-21 04:22:53,136 INFO L290 TraceCheckUtils]: 53: Hoare triple {1181#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1181#false} is VALID [2022-02-21 04:22:53,137 INFO L290 TraceCheckUtils]: 54: Hoare triple {1181#false} assume 1 == ~t3_pc~0; {1181#false} is VALID [2022-02-21 04:22:53,137 INFO L290 TraceCheckUtils]: 55: Hoare triple {1181#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1181#false} is VALID [2022-02-21 04:22:53,138 INFO L290 TraceCheckUtils]: 56: Hoare triple {1181#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1181#false} is VALID [2022-02-21 04:22:53,138 INFO L290 TraceCheckUtils]: 57: Hoare triple {1181#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1181#false} is VALID [2022-02-21 04:22:53,140 INFO L290 TraceCheckUtils]: 58: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___2~0#1); {1181#false} is VALID [2022-02-21 04:22:53,141 INFO L290 TraceCheckUtils]: 59: Hoare triple {1181#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1181#false} is VALID [2022-02-21 04:22:53,142 INFO L290 TraceCheckUtils]: 60: Hoare triple {1181#false} assume !(1 == ~t4_pc~0); {1181#false} is VALID [2022-02-21 04:22:53,143 INFO L290 TraceCheckUtils]: 61: Hoare triple {1181#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1181#false} is VALID [2022-02-21 04:22:53,143 INFO L290 TraceCheckUtils]: 62: Hoare triple {1181#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1181#false} is VALID [2022-02-21 04:22:53,143 INFO L290 TraceCheckUtils]: 63: Hoare triple {1181#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1181#false} is VALID [2022-02-21 04:22:53,144 INFO L290 TraceCheckUtils]: 64: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___3~0#1); {1181#false} is VALID [2022-02-21 04:22:53,146 INFO L290 TraceCheckUtils]: 65: Hoare triple {1181#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1181#false} is VALID [2022-02-21 04:22:53,147 INFO L290 TraceCheckUtils]: 66: Hoare triple {1181#false} assume 1 == ~t5_pc~0; {1181#false} is VALID [2022-02-21 04:22:53,147 INFO L290 TraceCheckUtils]: 67: Hoare triple {1181#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1181#false} is VALID [2022-02-21 04:22:53,147 INFO L290 TraceCheckUtils]: 68: Hoare triple {1181#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1181#false} is VALID [2022-02-21 04:22:53,148 INFO L290 TraceCheckUtils]: 69: Hoare triple {1181#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1181#false} is VALID [2022-02-21 04:22:53,148 INFO L290 TraceCheckUtils]: 70: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___4~0#1); {1181#false} is VALID [2022-02-21 04:22:53,148 INFO L290 TraceCheckUtils]: 71: Hoare triple {1181#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1181#false} is VALID [2022-02-21 04:22:53,149 INFO L290 TraceCheckUtils]: 72: Hoare triple {1181#false} assume !(1 == ~t6_pc~0); {1181#false} is VALID [2022-02-21 04:22:53,149 INFO L290 TraceCheckUtils]: 73: Hoare triple {1181#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1181#false} is VALID [2022-02-21 04:22:53,152 INFO L290 TraceCheckUtils]: 74: Hoare triple {1181#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1181#false} is VALID [2022-02-21 04:22:53,152 INFO L290 TraceCheckUtils]: 75: Hoare triple {1181#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1181#false} is VALID [2022-02-21 04:22:53,153 INFO L290 TraceCheckUtils]: 76: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___5~0#1); {1181#false} is VALID [2022-02-21 04:22:53,153 INFO L290 TraceCheckUtils]: 77: Hoare triple {1181#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1181#false} is VALID [2022-02-21 04:22:53,153 INFO L290 TraceCheckUtils]: 78: Hoare triple {1181#false} assume 1 == ~t7_pc~0; {1181#false} is VALID [2022-02-21 04:22:53,153 INFO L290 TraceCheckUtils]: 79: Hoare triple {1181#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1181#false} is VALID [2022-02-21 04:22:53,154 INFO L290 TraceCheckUtils]: 80: Hoare triple {1181#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1181#false} is VALID [2022-02-21 04:22:53,154 INFO L290 TraceCheckUtils]: 81: Hoare triple {1181#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1181#false} is VALID [2022-02-21 04:22:53,154 INFO L290 TraceCheckUtils]: 82: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___6~0#1); {1181#false} is VALID [2022-02-21 04:22:53,154 INFO L290 TraceCheckUtils]: 83: Hoare triple {1181#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1181#false} is VALID [2022-02-21 04:22:53,154 INFO L290 TraceCheckUtils]: 84: Hoare triple {1181#false} assume !(1 == ~t8_pc~0); {1181#false} is VALID [2022-02-21 04:22:53,155 INFO L290 TraceCheckUtils]: 85: Hoare triple {1181#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1181#false} is VALID [2022-02-21 04:22:53,155 INFO L290 TraceCheckUtils]: 86: Hoare triple {1181#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1181#false} is VALID [2022-02-21 04:22:53,155 INFO L290 TraceCheckUtils]: 87: Hoare triple {1181#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1181#false} is VALID [2022-02-21 04:22:53,155 INFO L290 TraceCheckUtils]: 88: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___7~0#1); {1181#false} is VALID [2022-02-21 04:22:53,155 INFO L290 TraceCheckUtils]: 89: Hoare triple {1181#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1181#false} is VALID [2022-02-21 04:22:53,156 INFO L290 TraceCheckUtils]: 90: Hoare triple {1181#false} assume 1 == ~t9_pc~0; {1181#false} is VALID [2022-02-21 04:22:53,156 INFO L290 TraceCheckUtils]: 91: Hoare triple {1181#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1181#false} is VALID [2022-02-21 04:22:53,156 INFO L290 TraceCheckUtils]: 92: Hoare triple {1181#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1181#false} is VALID [2022-02-21 04:22:53,156 INFO L290 TraceCheckUtils]: 93: Hoare triple {1181#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1181#false} is VALID [2022-02-21 04:22:53,157 INFO L290 TraceCheckUtils]: 94: Hoare triple {1181#false} assume !(0 != activate_threads_~tmp___8~0#1); {1181#false} is VALID [2022-02-21 04:22:53,157 INFO L290 TraceCheckUtils]: 95: Hoare triple {1181#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1181#false} is VALID [2022-02-21 04:22:53,157 INFO L290 TraceCheckUtils]: 96: Hoare triple {1181#false} assume !(1 == ~M_E~0); {1181#false} is VALID [2022-02-21 04:22:53,157 INFO L290 TraceCheckUtils]: 97: Hoare triple {1181#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,157 INFO L290 TraceCheckUtils]: 98: Hoare triple {1181#false} assume !(1 == ~T2_E~0); {1181#false} is VALID [2022-02-21 04:22:53,158 INFO L290 TraceCheckUtils]: 99: Hoare triple {1181#false} assume !(1 == ~T3_E~0); {1181#false} is VALID [2022-02-21 04:22:53,158 INFO L290 TraceCheckUtils]: 100: Hoare triple {1181#false} assume !(1 == ~T4_E~0); {1181#false} is VALID [2022-02-21 04:22:53,158 INFO L290 TraceCheckUtils]: 101: Hoare triple {1181#false} assume !(1 == ~T5_E~0); {1181#false} is VALID [2022-02-21 04:22:53,158 INFO L290 TraceCheckUtils]: 102: Hoare triple {1181#false} assume !(1 == ~T6_E~0); {1181#false} is VALID [2022-02-21 04:22:53,158 INFO L290 TraceCheckUtils]: 103: Hoare triple {1181#false} assume !(1 == ~T7_E~0); {1181#false} is VALID [2022-02-21 04:22:53,159 INFO L290 TraceCheckUtils]: 104: Hoare triple {1181#false} assume !(1 == ~T8_E~0); {1181#false} is VALID [2022-02-21 04:22:53,159 INFO L290 TraceCheckUtils]: 105: Hoare triple {1181#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,161 INFO L290 TraceCheckUtils]: 106: Hoare triple {1181#false} assume !(1 == ~E_M~0); {1181#false} is VALID [2022-02-21 04:22:53,162 INFO L290 TraceCheckUtils]: 107: Hoare triple {1181#false} assume !(1 == ~E_1~0); {1181#false} is VALID [2022-02-21 04:22:53,162 INFO L290 TraceCheckUtils]: 108: Hoare triple {1181#false} assume !(1 == ~E_2~0); {1181#false} is VALID [2022-02-21 04:22:53,162 INFO L290 TraceCheckUtils]: 109: Hoare triple {1181#false} assume !(1 == ~E_3~0); {1181#false} is VALID [2022-02-21 04:22:53,162 INFO L290 TraceCheckUtils]: 110: Hoare triple {1181#false} assume !(1 == ~E_4~0); {1181#false} is VALID [2022-02-21 04:22:53,162 INFO L290 TraceCheckUtils]: 111: Hoare triple {1181#false} assume !(1 == ~E_5~0); {1181#false} is VALID [2022-02-21 04:22:53,163 INFO L290 TraceCheckUtils]: 112: Hoare triple {1181#false} assume !(1 == ~E_6~0); {1181#false} is VALID [2022-02-21 04:22:53,163 INFO L290 TraceCheckUtils]: 113: Hoare triple {1181#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1181#false} is VALID [2022-02-21 04:22:53,167 INFO L290 TraceCheckUtils]: 114: Hoare triple {1181#false} assume !(1 == ~E_8~0); {1181#false} is VALID [2022-02-21 04:22:53,168 INFO L290 TraceCheckUtils]: 115: Hoare triple {1181#false} assume !(1 == ~E_9~0); {1181#false} is VALID [2022-02-21 04:22:53,168 INFO L290 TraceCheckUtils]: 116: Hoare triple {1181#false} assume { :end_inline_reset_delta_events } true; {1181#false} is VALID [2022-02-21 04:22:53,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:53,170 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:53,170 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738899087] [2022-02-21 04:22:53,171 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738899087] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:53,172 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:53,172 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:53,174 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755929578] [2022-02-21 04:22:53,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:53,186 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:53,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:53,189 INFO L85 PathProgramCache]: Analyzing trace with hash -1744542878, now seen corresponding path program 1 times [2022-02-21 04:22:53,190 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:53,190 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970493846] [2022-02-21 04:22:53,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:53,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:53,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:53,237 INFO L290 TraceCheckUtils]: 0: Hoare triple {1183#true} assume !false; {1183#true} is VALID [2022-02-21 04:22:53,237 INFO L290 TraceCheckUtils]: 1: Hoare triple {1183#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1183#true} is VALID [2022-02-21 04:22:53,238 INFO L290 TraceCheckUtils]: 2: Hoare triple {1183#true} assume false; {1184#false} is VALID [2022-02-21 04:22:53,238 INFO L290 TraceCheckUtils]: 3: Hoare triple {1184#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1184#false} is VALID [2022-02-21 04:22:53,238 INFO L290 TraceCheckUtils]: 4: Hoare triple {1184#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1184#false} is VALID [2022-02-21 04:22:53,238 INFO L290 TraceCheckUtils]: 5: Hoare triple {1184#false} assume !(0 == ~M_E~0); {1184#false} is VALID [2022-02-21 04:22:53,239 INFO L290 TraceCheckUtils]: 6: Hoare triple {1184#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,239 INFO L290 TraceCheckUtils]: 7: Hoare triple {1184#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,239 INFO L290 TraceCheckUtils]: 8: Hoare triple {1184#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,239 INFO L290 TraceCheckUtils]: 9: Hoare triple {1184#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,239 INFO L290 TraceCheckUtils]: 10: Hoare triple {1184#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,240 INFO L290 TraceCheckUtils]: 11: Hoare triple {1184#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,240 INFO L290 TraceCheckUtils]: 12: Hoare triple {1184#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,240 INFO L290 TraceCheckUtils]: 13: Hoare triple {1184#false} assume !(0 == ~T8_E~0); {1184#false} is VALID [2022-02-21 04:22:53,240 INFO L290 TraceCheckUtils]: 14: Hoare triple {1184#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,240 INFO L290 TraceCheckUtils]: 15: Hoare triple {1184#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,241 INFO L290 TraceCheckUtils]: 16: Hoare triple {1184#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,241 INFO L290 TraceCheckUtils]: 17: Hoare triple {1184#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,241 INFO L290 TraceCheckUtils]: 18: Hoare triple {1184#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,241 INFO L290 TraceCheckUtils]: 19: Hoare triple {1184#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,241 INFO L290 TraceCheckUtils]: 20: Hoare triple {1184#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,241 INFO L290 TraceCheckUtils]: 21: Hoare triple {1184#false} assume !(0 == ~E_6~0); {1184#false} is VALID [2022-02-21 04:22:53,242 INFO L290 TraceCheckUtils]: 22: Hoare triple {1184#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,242 INFO L290 TraceCheckUtils]: 23: Hoare triple {1184#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,242 INFO L290 TraceCheckUtils]: 24: Hoare triple {1184#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1184#false} is VALID [2022-02-21 04:22:53,242 INFO L290 TraceCheckUtils]: 25: Hoare triple {1184#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1184#false} is VALID [2022-02-21 04:22:53,243 INFO L290 TraceCheckUtils]: 26: Hoare triple {1184#false} assume !(1 == ~m_pc~0); {1184#false} is VALID [2022-02-21 04:22:53,243 INFO L290 TraceCheckUtils]: 27: Hoare triple {1184#false} is_master_triggered_~__retres1~0#1 := 0; {1184#false} is VALID [2022-02-21 04:22:53,243 INFO L290 TraceCheckUtils]: 28: Hoare triple {1184#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1184#false} is VALID [2022-02-21 04:22:53,243 INFO L290 TraceCheckUtils]: 29: Hoare triple {1184#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1184#false} is VALID [2022-02-21 04:22:53,243 INFO L290 TraceCheckUtils]: 30: Hoare triple {1184#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,244 INFO L290 TraceCheckUtils]: 31: Hoare triple {1184#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1184#false} is VALID [2022-02-21 04:22:53,244 INFO L290 TraceCheckUtils]: 32: Hoare triple {1184#false} assume 1 == ~t1_pc~0; {1184#false} is VALID [2022-02-21 04:22:53,244 INFO L290 TraceCheckUtils]: 33: Hoare triple {1184#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,244 INFO L290 TraceCheckUtils]: 34: Hoare triple {1184#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1184#false} is VALID [2022-02-21 04:22:53,244 INFO L290 TraceCheckUtils]: 35: Hoare triple {1184#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1184#false} is VALID [2022-02-21 04:22:53,245 INFO L290 TraceCheckUtils]: 36: Hoare triple {1184#false} assume !(0 != activate_threads_~tmp___0~0#1); {1184#false} is VALID [2022-02-21 04:22:53,245 INFO L290 TraceCheckUtils]: 37: Hoare triple {1184#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1184#false} is VALID [2022-02-21 04:22:53,245 INFO L290 TraceCheckUtils]: 38: Hoare triple {1184#false} assume !(1 == ~t2_pc~0); {1184#false} is VALID [2022-02-21 04:22:53,245 INFO L290 TraceCheckUtils]: 39: Hoare triple {1184#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1184#false} is VALID [2022-02-21 04:22:53,245 INFO L290 TraceCheckUtils]: 40: Hoare triple {1184#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1184#false} is VALID [2022-02-21 04:22:53,246 INFO L290 TraceCheckUtils]: 41: Hoare triple {1184#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1184#false} is VALID [2022-02-21 04:22:53,246 INFO L290 TraceCheckUtils]: 42: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,246 INFO L290 TraceCheckUtils]: 43: Hoare triple {1184#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1184#false} is VALID [2022-02-21 04:22:53,246 INFO L290 TraceCheckUtils]: 44: Hoare triple {1184#false} assume !(1 == ~t3_pc~0); {1184#false} is VALID [2022-02-21 04:22:53,246 INFO L290 TraceCheckUtils]: 45: Hoare triple {1184#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1184#false} is VALID [2022-02-21 04:22:53,247 INFO L290 TraceCheckUtils]: 46: Hoare triple {1184#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1184#false} is VALID [2022-02-21 04:22:53,247 INFO L290 TraceCheckUtils]: 47: Hoare triple {1184#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1184#false} is VALID [2022-02-21 04:22:53,247 INFO L290 TraceCheckUtils]: 48: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,247 INFO L290 TraceCheckUtils]: 49: Hoare triple {1184#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1184#false} is VALID [2022-02-21 04:22:53,247 INFO L290 TraceCheckUtils]: 50: Hoare triple {1184#false} assume 1 == ~t4_pc~0; {1184#false} is VALID [2022-02-21 04:22:53,248 INFO L290 TraceCheckUtils]: 51: Hoare triple {1184#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,248 INFO L290 TraceCheckUtils]: 52: Hoare triple {1184#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1184#false} is VALID [2022-02-21 04:22:53,248 INFO L290 TraceCheckUtils]: 53: Hoare triple {1184#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1184#false} is VALID [2022-02-21 04:22:53,248 INFO L290 TraceCheckUtils]: 54: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,248 INFO L290 TraceCheckUtils]: 55: Hoare triple {1184#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1184#false} is VALID [2022-02-21 04:22:53,249 INFO L290 TraceCheckUtils]: 56: Hoare triple {1184#false} assume !(1 == ~t5_pc~0); {1184#false} is VALID [2022-02-21 04:22:53,249 INFO L290 TraceCheckUtils]: 57: Hoare triple {1184#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1184#false} is VALID [2022-02-21 04:22:53,249 INFO L290 TraceCheckUtils]: 58: Hoare triple {1184#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1184#false} is VALID [2022-02-21 04:22:53,249 INFO L290 TraceCheckUtils]: 59: Hoare triple {1184#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1184#false} is VALID [2022-02-21 04:22:53,249 INFO L290 TraceCheckUtils]: 60: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,250 INFO L290 TraceCheckUtils]: 61: Hoare triple {1184#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1184#false} is VALID [2022-02-21 04:22:53,250 INFO L290 TraceCheckUtils]: 62: Hoare triple {1184#false} assume 1 == ~t6_pc~0; {1184#false} is VALID [2022-02-21 04:22:53,250 INFO L290 TraceCheckUtils]: 63: Hoare triple {1184#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,250 INFO L290 TraceCheckUtils]: 64: Hoare triple {1184#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1184#false} is VALID [2022-02-21 04:22:53,250 INFO L290 TraceCheckUtils]: 65: Hoare triple {1184#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1184#false} is VALID [2022-02-21 04:22:53,251 INFO L290 TraceCheckUtils]: 66: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,251 INFO L290 TraceCheckUtils]: 67: Hoare triple {1184#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1184#false} is VALID [2022-02-21 04:22:53,251 INFO L290 TraceCheckUtils]: 68: Hoare triple {1184#false} assume 1 == ~t7_pc~0; {1184#false} is VALID [2022-02-21 04:22:53,251 INFO L290 TraceCheckUtils]: 69: Hoare triple {1184#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,251 INFO L290 TraceCheckUtils]: 70: Hoare triple {1184#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1184#false} is VALID [2022-02-21 04:22:53,252 INFO L290 TraceCheckUtils]: 71: Hoare triple {1184#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1184#false} is VALID [2022-02-21 04:22:53,252 INFO L290 TraceCheckUtils]: 72: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,252 INFO L290 TraceCheckUtils]: 73: Hoare triple {1184#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1184#false} is VALID [2022-02-21 04:22:53,252 INFO L290 TraceCheckUtils]: 74: Hoare triple {1184#false} assume 1 == ~t8_pc~0; {1184#false} is VALID [2022-02-21 04:22:53,252 INFO L290 TraceCheckUtils]: 75: Hoare triple {1184#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,253 INFO L290 TraceCheckUtils]: 76: Hoare triple {1184#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1184#false} is VALID [2022-02-21 04:22:53,253 INFO L290 TraceCheckUtils]: 77: Hoare triple {1184#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1184#false} is VALID [2022-02-21 04:22:53,253 INFO L290 TraceCheckUtils]: 78: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,253 INFO L290 TraceCheckUtils]: 79: Hoare triple {1184#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1184#false} is VALID [2022-02-21 04:22:53,253 INFO L290 TraceCheckUtils]: 80: Hoare triple {1184#false} assume !(1 == ~t9_pc~0); {1184#false} is VALID [2022-02-21 04:22:53,254 INFO L290 TraceCheckUtils]: 81: Hoare triple {1184#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1184#false} is VALID [2022-02-21 04:22:53,254 INFO L290 TraceCheckUtils]: 82: Hoare triple {1184#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1184#false} is VALID [2022-02-21 04:22:53,254 INFO L290 TraceCheckUtils]: 83: Hoare triple {1184#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1184#false} is VALID [2022-02-21 04:22:53,254 INFO L290 TraceCheckUtils]: 84: Hoare triple {1184#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1184#false} is VALID [2022-02-21 04:22:53,254 INFO L290 TraceCheckUtils]: 85: Hoare triple {1184#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1184#false} is VALID [2022-02-21 04:22:53,255 INFO L290 TraceCheckUtils]: 86: Hoare triple {1184#false} assume !(1 == ~M_E~0); {1184#false} is VALID [2022-02-21 04:22:53,255 INFO L290 TraceCheckUtils]: 87: Hoare triple {1184#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,255 INFO L290 TraceCheckUtils]: 88: Hoare triple {1184#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,255 INFO L290 TraceCheckUtils]: 89: Hoare triple {1184#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,255 INFO L290 TraceCheckUtils]: 90: Hoare triple {1184#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,256 INFO L290 TraceCheckUtils]: 91: Hoare triple {1184#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,256 INFO L290 TraceCheckUtils]: 92: Hoare triple {1184#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,256 INFO L290 TraceCheckUtils]: 93: Hoare triple {1184#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,256 INFO L290 TraceCheckUtils]: 94: Hoare triple {1184#false} assume !(1 == ~T8_E~0); {1184#false} is VALID [2022-02-21 04:22:53,256 INFO L290 TraceCheckUtils]: 95: Hoare triple {1184#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,257 INFO L290 TraceCheckUtils]: 96: Hoare triple {1184#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,257 INFO L290 TraceCheckUtils]: 97: Hoare triple {1184#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,257 INFO L290 TraceCheckUtils]: 98: Hoare triple {1184#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,257 INFO L290 TraceCheckUtils]: 99: Hoare triple {1184#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,257 INFO L290 TraceCheckUtils]: 100: Hoare triple {1184#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,258 INFO L290 TraceCheckUtils]: 101: Hoare triple {1184#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,258 INFO L290 TraceCheckUtils]: 102: Hoare triple {1184#false} assume !(1 == ~E_6~0); {1184#false} is VALID [2022-02-21 04:22:53,258 INFO L290 TraceCheckUtils]: 103: Hoare triple {1184#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,258 INFO L290 TraceCheckUtils]: 104: Hoare triple {1184#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,258 INFO L290 TraceCheckUtils]: 105: Hoare triple {1184#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1184#false} is VALID [2022-02-21 04:22:53,259 INFO L290 TraceCheckUtils]: 106: Hoare triple {1184#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {1184#false} is VALID [2022-02-21 04:22:53,259 INFO L290 TraceCheckUtils]: 107: Hoare triple {1184#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,259 INFO L290 TraceCheckUtils]: 108: Hoare triple {1184#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {1184#false} is VALID [2022-02-21 04:22:53,259 INFO L290 TraceCheckUtils]: 109: Hoare triple {1184#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {1184#false} is VALID [2022-02-21 04:22:53,259 INFO L290 TraceCheckUtils]: 110: Hoare triple {1184#false} assume !(0 == start_simulation_~tmp~3#1); {1184#false} is VALID [2022-02-21 04:22:53,260 INFO L290 TraceCheckUtils]: 111: Hoare triple {1184#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {1184#false} is VALID [2022-02-21 04:22:53,260 INFO L290 TraceCheckUtils]: 112: Hoare triple {1184#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,260 INFO L290 TraceCheckUtils]: 113: Hoare triple {1184#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {1184#false} is VALID [2022-02-21 04:22:53,260 INFO L290 TraceCheckUtils]: 114: Hoare triple {1184#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {1184#false} is VALID [2022-02-21 04:22:53,260 INFO L290 TraceCheckUtils]: 115: Hoare triple {1184#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {1184#false} is VALID [2022-02-21 04:22:53,261 INFO L290 TraceCheckUtils]: 116: Hoare triple {1184#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1184#false} is VALID [2022-02-21 04:22:53,261 INFO L290 TraceCheckUtils]: 117: Hoare triple {1184#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {1184#false} is VALID [2022-02-21 04:22:53,261 INFO L290 TraceCheckUtils]: 118: Hoare triple {1184#false} assume !(0 != start_simulation_~tmp___0~1#1); {1184#false} is VALID [2022-02-21 04:22:53,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:53,262 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:53,262 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [970493846] [2022-02-21 04:22:53,263 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [970493846] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:53,263 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:53,275 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:53,275 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228792984] [2022-02-21 04:22:53,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:53,277 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:53,278 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:53,301 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:53,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:53,307 INFO L87 Difference]: Start difference. First operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:54,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:54,477 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions. [2022-02-21 04:22:54,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:54,478 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:54,571 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:54,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions. [2022-02-21 04:22:54,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:54,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1170 states and 1742 transitions. [2022-02-21 04:22:54,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:22:54,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:22:54,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1742 transitions. [2022-02-21 04:22:54,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:54,713 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2022-02-21 04:22:54,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1742 transitions. [2022-02-21 04:22:54,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:22:54,779 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:54,784 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1742 transitions. Second operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:54,787 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1742 transitions. Second operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:54,791 INFO L87 Difference]: Start difference. First operand 1170 states and 1742 transitions. Second operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:54,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:54,854 INFO L93 Difference]: Finished difference Result 1170 states and 1742 transitions. [2022-02-21 04:22:54,854 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1742 transitions. [2022-02-21 04:22:54,859 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:54,860 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:54,862 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1742 transitions. [2022-02-21 04:22:54,865 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1742 transitions. [2022-02-21 04:22:54,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:54,919 INFO L93 Difference]: Finished difference Result 1170 states and 1742 transitions. [2022-02-21 04:22:54,919 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1742 transitions. [2022-02-21 04:22:54,921 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:54,921 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:54,922 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:54,922 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:54,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:54,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1742 transitions. [2022-02-21 04:22:54,980 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2022-02-21 04:22:54,980 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2022-02-21 04:22:54,980 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:22:54,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1742 transitions. [2022-02-21 04:22:54,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:54,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:54,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:54,989 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:54,989 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:54,989 INFO L791 eck$LassoCheckResult]: Stem: 3232#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3182#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3183#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3401#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3068#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3069#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3378#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2877#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2878#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3306#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3307#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2376#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2377#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2580#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2968#L939 assume !(0 == ~M_E~0); 3212#L939-2 assume !(0 == ~T1_E~0); 3213#L944-1 assume !(0 == ~T2_E~0); 2997#L949-1 assume !(0 == ~T3_E~0); 2995#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2996#L959-1 assume !(0 == ~T5_E~0); 3415#L964-1 assume !(0 == ~T6_E~0); 2728#L969-1 assume !(0 == ~T7_E~0); 2729#L974-1 assume !(0 == ~T8_E~0); 3366#L979-1 assume !(0 == ~T9_E~0); 3367#L984-1 assume !(0 == ~E_M~0); 2889#L989-1 assume !(0 == ~E_1~0); 2890#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2778#L999-1 assume !(0 == ~E_3~0); 2779#L1004-1 assume !(0 == ~E_4~0); 2444#L1009-1 assume !(0 == ~E_5~0); 2445#L1014-1 assume !(0 == ~E_6~0); 2772#L1019-1 assume !(0 == ~E_7~0); 3311#L1024-1 assume !(0 == ~E_8~0); 2701#L1029-1 assume !(0 == ~E_9~0); 2702#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2792#L460 assume 1 == ~m_pc~0; 2360#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2361#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3277#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3516#L1167 assume !(0 != activate_threads_~tmp~1#1); 2985#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2986#L479 assume 1 == ~t1_pc~0; 2969#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2970#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2713#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2714#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L498 assume !(1 == ~t2_pc~0); 2563#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2966#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2967#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3344#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3268#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3269#L517 assume 1 == ~t3_pc~0; 3477#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3478#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2746#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2747#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3322#L536 assume !(1 == ~t4_pc~0); 3030#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3029#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3406#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3022#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3023#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3242#L555 assume 1 == ~t5_pc~0; 3243#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3312#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2475#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2476#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2583#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2483#L574 assume !(1 == ~t6_pc~0); 2484#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3115#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2588#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2589#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3340#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3500#L593 assume 1 == ~t7_pc~0; 3501#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2720#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3418#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3521#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3481#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2884#L612 assume !(1 == ~t8_pc~0); 2885#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3294#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3152#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3153#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3117#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3118#L631 assume 1 == ~t9_pc~0; 3136#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2474#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2442#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2443#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2972#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3323#L1047 assume !(1 == ~M_E~0); 2412#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2413#L1052-1 assume !(1 == ~T2_E~0); 2395#L1057-1 assume !(1 == ~T3_E~0); 2396#L1062-1 assume !(1 == ~T4_E~0); 2685#L1067-1 assume !(1 == ~T5_E~0); 2988#L1072-1 assume !(1 == ~T6_E~0); 2989#L1077-1 assume !(1 == ~T7_E~0); 2576#L1082-1 assume !(1 == ~T8_E~0); 2577#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2370#L1092-1 assume !(1 == ~E_M~0); 2371#L1097-1 assume !(1 == ~E_1~0); 2397#L1102-1 assume !(1 == ~E_2~0); 3178#L1107-1 assume !(1 == ~E_3~0); 3113#L1112-1 assume !(1 == ~E_4~0); 3114#L1117-1 assume !(1 == ~E_5~0); 3154#L1122-1 assume !(1 == ~E_6~0); 3041#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2797#L1132-1 assume !(1 == ~E_8~0); 2798#L1137-1 assume !(1 == ~E_9~0); 2684#L1142-1 assume { :end_inline_reset_delta_events } true; 2544#L1428-2 [2022-02-21 04:22:54,990 INFO L793 eck$LassoCheckResult]: Loop: 2544#L1428-2 assume !false; 2545#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2619#L914 assume !false; 3109#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3110#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2381#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2382#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3341#L783 assume !(0 != eval_~tmp~0#1); 2781#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2782#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3177#L939-3 assume !(0 == ~M_E~0); 2600#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2601#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2366#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2367#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3003#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2446#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2447#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2653#L974-3 assume !(0 == ~T8_E~0); 2654#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3084#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3085#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2707#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2708#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3219#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2530#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2531#L1014-3 assume !(0 == ~E_6~0); 3070#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3071#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3052#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3004#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3005#L460-33 assume 1 == ~m_pc~0; 3042#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3043#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2799#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2374#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2375#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2736#L479-33 assume !(1 == ~t1_pc~0); 2737#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2703#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3288#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 3461#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2744#L498-33 assume 1 == ~t2_pc~0; 2745#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2490#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2626#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2627#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2602#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2603#L517-33 assume !(1 == ~t3_pc~0); 3509#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3392#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3393#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3205#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3206#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2831#L536-33 assume 1 == ~t4_pc~0; 2832#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2901#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2902#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3092#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3371#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2421#L555-33 assume !(1 == ~t5_pc~0); 2422#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3147#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2694#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2695#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3174#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2387#L574-33 assume 1 == ~t6_pc~0; 2388#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3383#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2709#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2710#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2963#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2463#L593-33 assume !(1 == ~t7_pc~0); 2464#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2919#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2574#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2575#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3234#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3361#L612-33 assume 1 == ~t8_pc~0; 3488#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3452#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3453#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3295#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2570#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2571#L631-33 assume 1 == ~t9_pc~0; 3413#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2512#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2513#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2767#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2624#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2625#L1047-3 assume !(1 == ~M_E~0); 2800#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3414#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3346#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3347#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2525#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2526#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2908#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2753#L1082-3 assume !(1 == ~T8_E~0); 2754#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2827#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3108#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3038#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3039#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3384#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2748#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2749#L1122-3 assume !(1 == ~E_6~0); 2801#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2802#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3191#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3168#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2628#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2506#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3169#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2926#L1447 assume !(0 == start_simulation_~tmp~3#1); 2927#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3365#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2667#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3192#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2777#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2534#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2535#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2990#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2544#L1428-2 [2022-02-21 04:22:54,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:54,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2022-02-21 04:22:54,991 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:54,991 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713078472] [2022-02-21 04:22:54,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:54,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:55,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:55,062 INFO L290 TraceCheckUtils]: 0: Hoare triple {5873#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {5873#true} is VALID [2022-02-21 04:22:55,062 INFO L290 TraceCheckUtils]: 1: Hoare triple {5873#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {5875#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:55,063 INFO L290 TraceCheckUtils]: 2: Hoare triple {5875#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {5875#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:55,064 INFO L290 TraceCheckUtils]: 3: Hoare triple {5875#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {5875#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:55,064 INFO L290 TraceCheckUtils]: 4: Hoare triple {5875#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {5875#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:55,064 INFO L290 TraceCheckUtils]: 5: Hoare triple {5875#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5875#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:55,064 INFO L290 TraceCheckUtils]: 6: Hoare triple {5875#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,065 INFO L290 TraceCheckUtils]: 7: Hoare triple {5874#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,065 INFO L290 TraceCheckUtils]: 8: Hoare triple {5874#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,066 INFO L290 TraceCheckUtils]: 9: Hoare triple {5874#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,066 INFO L290 TraceCheckUtils]: 10: Hoare triple {5874#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,066 INFO L290 TraceCheckUtils]: 11: Hoare triple {5874#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,070 INFO L290 TraceCheckUtils]: 12: Hoare triple {5874#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,070 INFO L290 TraceCheckUtils]: 13: Hoare triple {5874#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {5874#false} is VALID [2022-02-21 04:22:55,070 INFO L290 TraceCheckUtils]: 14: Hoare triple {5874#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {5874#false} is VALID [2022-02-21 04:22:55,070 INFO L290 TraceCheckUtils]: 15: Hoare triple {5874#false} assume !(0 == ~M_E~0); {5874#false} is VALID [2022-02-21 04:22:55,070 INFO L290 TraceCheckUtils]: 16: Hoare triple {5874#false} assume !(0 == ~T1_E~0); {5874#false} is VALID [2022-02-21 04:22:55,070 INFO L290 TraceCheckUtils]: 17: Hoare triple {5874#false} assume !(0 == ~T2_E~0); {5874#false} is VALID [2022-02-21 04:22:55,070 INFO L290 TraceCheckUtils]: 18: Hoare triple {5874#false} assume !(0 == ~T3_E~0); {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 19: Hoare triple {5874#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 20: Hoare triple {5874#false} assume !(0 == ~T5_E~0); {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 21: Hoare triple {5874#false} assume !(0 == ~T6_E~0); {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 22: Hoare triple {5874#false} assume !(0 == ~T7_E~0); {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 23: Hoare triple {5874#false} assume !(0 == ~T8_E~0); {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 24: Hoare triple {5874#false} assume !(0 == ~T9_E~0); {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 25: Hoare triple {5874#false} assume !(0 == ~E_M~0); {5874#false} is VALID [2022-02-21 04:22:55,071 INFO L290 TraceCheckUtils]: 26: Hoare triple {5874#false} assume !(0 == ~E_1~0); {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 27: Hoare triple {5874#false} assume 0 == ~E_2~0;~E_2~0 := 1; {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 28: Hoare triple {5874#false} assume !(0 == ~E_3~0); {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 29: Hoare triple {5874#false} assume !(0 == ~E_4~0); {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 30: Hoare triple {5874#false} assume !(0 == ~E_5~0); {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 31: Hoare triple {5874#false} assume !(0 == ~E_6~0); {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 32: Hoare triple {5874#false} assume !(0 == ~E_7~0); {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 33: Hoare triple {5874#false} assume !(0 == ~E_8~0); {5874#false} is VALID [2022-02-21 04:22:55,072 INFO L290 TraceCheckUtils]: 34: Hoare triple {5874#false} assume !(0 == ~E_9~0); {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 35: Hoare triple {5874#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 36: Hoare triple {5874#false} assume 1 == ~m_pc~0; {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 37: Hoare triple {5874#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 38: Hoare triple {5874#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 39: Hoare triple {5874#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 40: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp~1#1); {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 41: Hoare triple {5874#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 42: Hoare triple {5874#false} assume 1 == ~t1_pc~0; {5874#false} is VALID [2022-02-21 04:22:55,073 INFO L290 TraceCheckUtils]: 43: Hoare triple {5874#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 44: Hoare triple {5874#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 45: Hoare triple {5874#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 46: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___0~0#1); {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 47: Hoare triple {5874#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 48: Hoare triple {5874#false} assume !(1 == ~t2_pc~0); {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 49: Hoare triple {5874#false} is_transmit2_triggered_~__retres1~2#1 := 0; {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 50: Hoare triple {5874#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5874#false} is VALID [2022-02-21 04:22:55,074 INFO L290 TraceCheckUtils]: 51: Hoare triple {5874#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 52: Hoare triple {5874#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 53: Hoare triple {5874#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 54: Hoare triple {5874#false} assume 1 == ~t3_pc~0; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 55: Hoare triple {5874#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 56: Hoare triple {5874#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 57: Hoare triple {5874#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 58: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___2~0#1); {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 59: Hoare triple {5874#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5874#false} is VALID [2022-02-21 04:22:55,075 INFO L290 TraceCheckUtils]: 60: Hoare triple {5874#false} assume !(1 == ~t4_pc~0); {5874#false} is VALID [2022-02-21 04:22:55,076 INFO L290 TraceCheckUtils]: 61: Hoare triple {5874#false} is_transmit4_triggered_~__retres1~4#1 := 0; {5874#false} is VALID [2022-02-21 04:22:55,076 INFO L290 TraceCheckUtils]: 62: Hoare triple {5874#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5874#false} is VALID [2022-02-21 04:22:55,076 INFO L290 TraceCheckUtils]: 63: Hoare triple {5874#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {5874#false} is VALID [2022-02-21 04:22:55,096 INFO L290 TraceCheckUtils]: 64: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___3~0#1); {5874#false} is VALID [2022-02-21 04:22:55,096 INFO L290 TraceCheckUtils]: 65: Hoare triple {5874#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5874#false} is VALID [2022-02-21 04:22:55,097 INFO L290 TraceCheckUtils]: 66: Hoare triple {5874#false} assume 1 == ~t5_pc~0; {5874#false} is VALID [2022-02-21 04:22:55,097 INFO L290 TraceCheckUtils]: 67: Hoare triple {5874#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {5874#false} is VALID [2022-02-21 04:22:55,097 INFO L290 TraceCheckUtils]: 68: Hoare triple {5874#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5874#false} is VALID [2022-02-21 04:22:55,098 INFO L290 TraceCheckUtils]: 69: Hoare triple {5874#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {5874#false} is VALID [2022-02-21 04:22:55,098 INFO L290 TraceCheckUtils]: 70: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___4~0#1); {5874#false} is VALID [2022-02-21 04:22:55,099 INFO L290 TraceCheckUtils]: 71: Hoare triple {5874#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5874#false} is VALID [2022-02-21 04:22:55,099 INFO L290 TraceCheckUtils]: 72: Hoare triple {5874#false} assume !(1 == ~t6_pc~0); {5874#false} is VALID [2022-02-21 04:22:55,099 INFO L290 TraceCheckUtils]: 73: Hoare triple {5874#false} is_transmit6_triggered_~__retres1~6#1 := 0; {5874#false} is VALID [2022-02-21 04:22:55,099 INFO L290 TraceCheckUtils]: 74: Hoare triple {5874#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5874#false} is VALID [2022-02-21 04:22:55,099 INFO L290 TraceCheckUtils]: 75: Hoare triple {5874#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {5874#false} is VALID [2022-02-21 04:22:55,100 INFO L290 TraceCheckUtils]: 76: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___5~0#1); {5874#false} is VALID [2022-02-21 04:22:55,100 INFO L290 TraceCheckUtils]: 77: Hoare triple {5874#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {5874#false} is VALID [2022-02-21 04:22:55,101 INFO L290 TraceCheckUtils]: 78: Hoare triple {5874#false} assume 1 == ~t7_pc~0; {5874#false} is VALID [2022-02-21 04:22:55,101 INFO L290 TraceCheckUtils]: 79: Hoare triple {5874#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {5874#false} is VALID [2022-02-21 04:22:55,101 INFO L290 TraceCheckUtils]: 80: Hoare triple {5874#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {5874#false} is VALID [2022-02-21 04:22:55,101 INFO L290 TraceCheckUtils]: 81: Hoare triple {5874#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {5874#false} is VALID [2022-02-21 04:22:55,101 INFO L290 TraceCheckUtils]: 82: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___6~0#1); {5874#false} is VALID [2022-02-21 04:22:55,101 INFO L290 TraceCheckUtils]: 83: Hoare triple {5874#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 84: Hoare triple {5874#false} assume !(1 == ~t8_pc~0); {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 85: Hoare triple {5874#false} is_transmit8_triggered_~__retres1~8#1 := 0; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 86: Hoare triple {5874#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 87: Hoare triple {5874#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 88: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___7~0#1); {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 89: Hoare triple {5874#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 90: Hoare triple {5874#false} assume 1 == ~t9_pc~0; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 91: Hoare triple {5874#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 92: Hoare triple {5874#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {5874#false} is VALID [2022-02-21 04:22:55,102 INFO L290 TraceCheckUtils]: 93: Hoare triple {5874#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 94: Hoare triple {5874#false} assume !(0 != activate_threads_~tmp___8~0#1); {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 95: Hoare triple {5874#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 96: Hoare triple {5874#false} assume !(1 == ~M_E~0); {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 97: Hoare triple {5874#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 98: Hoare triple {5874#false} assume !(1 == ~T2_E~0); {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 99: Hoare triple {5874#false} assume !(1 == ~T3_E~0); {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 100: Hoare triple {5874#false} assume !(1 == ~T4_E~0); {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 101: Hoare triple {5874#false} assume !(1 == ~T5_E~0); {5874#false} is VALID [2022-02-21 04:22:55,103 INFO L290 TraceCheckUtils]: 102: Hoare triple {5874#false} assume !(1 == ~T6_E~0); {5874#false} is VALID [2022-02-21 04:22:55,104 INFO L290 TraceCheckUtils]: 103: Hoare triple {5874#false} assume !(1 == ~T7_E~0); {5874#false} is VALID [2022-02-21 04:22:55,104 INFO L290 TraceCheckUtils]: 104: Hoare triple {5874#false} assume !(1 == ~T8_E~0); {5874#false} is VALID [2022-02-21 04:22:55,109 INFO L290 TraceCheckUtils]: 105: Hoare triple {5874#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,109 INFO L290 TraceCheckUtils]: 106: Hoare triple {5874#false} assume !(1 == ~E_M~0); {5874#false} is VALID [2022-02-21 04:22:55,109 INFO L290 TraceCheckUtils]: 107: Hoare triple {5874#false} assume !(1 == ~E_1~0); {5874#false} is VALID [2022-02-21 04:22:55,109 INFO L290 TraceCheckUtils]: 108: Hoare triple {5874#false} assume !(1 == ~E_2~0); {5874#false} is VALID [2022-02-21 04:22:55,109 INFO L290 TraceCheckUtils]: 109: Hoare triple {5874#false} assume !(1 == ~E_3~0); {5874#false} is VALID [2022-02-21 04:22:55,109 INFO L290 TraceCheckUtils]: 110: Hoare triple {5874#false} assume !(1 == ~E_4~0); {5874#false} is VALID [2022-02-21 04:22:55,110 INFO L290 TraceCheckUtils]: 111: Hoare triple {5874#false} assume !(1 == ~E_5~0); {5874#false} is VALID [2022-02-21 04:22:55,110 INFO L290 TraceCheckUtils]: 112: Hoare triple {5874#false} assume !(1 == ~E_6~0); {5874#false} is VALID [2022-02-21 04:22:55,110 INFO L290 TraceCheckUtils]: 113: Hoare triple {5874#false} assume 1 == ~E_7~0;~E_7~0 := 2; {5874#false} is VALID [2022-02-21 04:22:55,110 INFO L290 TraceCheckUtils]: 114: Hoare triple {5874#false} assume !(1 == ~E_8~0); {5874#false} is VALID [2022-02-21 04:22:55,110 INFO L290 TraceCheckUtils]: 115: Hoare triple {5874#false} assume !(1 == ~E_9~0); {5874#false} is VALID [2022-02-21 04:22:55,110 INFO L290 TraceCheckUtils]: 116: Hoare triple {5874#false} assume { :end_inline_reset_delta_events } true; {5874#false} is VALID [2022-02-21 04:22:55,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:55,111 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:55,111 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713078472] [2022-02-21 04:22:55,111 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713078472] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:55,111 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:55,111 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:55,112 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125284192] [2022-02-21 04:22:55,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:55,112 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:55,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:55,113 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 1 times [2022-02-21 04:22:55,113 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:55,113 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291582024] [2022-02-21 04:22:55,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:55,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:55,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:55,209 INFO L290 TraceCheckUtils]: 0: Hoare triple {5876#true} assume !false; {5876#true} is VALID [2022-02-21 04:22:55,210 INFO L290 TraceCheckUtils]: 1: Hoare triple {5876#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5876#true} is VALID [2022-02-21 04:22:55,210 INFO L290 TraceCheckUtils]: 2: Hoare triple {5876#true} assume !false; {5876#true} is VALID [2022-02-21 04:22:55,210 INFO L290 TraceCheckUtils]: 3: Hoare triple {5876#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {5876#true} is VALID [2022-02-21 04:22:55,210 INFO L290 TraceCheckUtils]: 4: Hoare triple {5876#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {5876#true} is VALID [2022-02-21 04:22:55,210 INFO L290 TraceCheckUtils]: 5: Hoare triple {5876#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {5876#true} is VALID [2022-02-21 04:22:55,210 INFO L290 TraceCheckUtils]: 6: Hoare triple {5876#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {5876#true} is VALID [2022-02-21 04:22:55,211 INFO L290 TraceCheckUtils]: 7: Hoare triple {5876#true} assume !(0 != eval_~tmp~0#1); {5876#true} is VALID [2022-02-21 04:22:55,211 INFO L290 TraceCheckUtils]: 8: Hoare triple {5876#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5876#true} is VALID [2022-02-21 04:22:55,211 INFO L290 TraceCheckUtils]: 9: Hoare triple {5876#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5876#true} is VALID [2022-02-21 04:22:55,211 INFO L290 TraceCheckUtils]: 10: Hoare triple {5876#true} assume !(0 == ~M_E~0); {5876#true} is VALID [2022-02-21 04:22:55,211 INFO L290 TraceCheckUtils]: 11: Hoare triple {5876#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,211 INFO L290 TraceCheckUtils]: 12: Hoare triple {5876#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,211 INFO L290 TraceCheckUtils]: 13: Hoare triple {5876#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,212 INFO L290 TraceCheckUtils]: 14: Hoare triple {5876#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,212 INFO L290 TraceCheckUtils]: 15: Hoare triple {5876#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,212 INFO L290 TraceCheckUtils]: 16: Hoare triple {5876#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,212 INFO L290 TraceCheckUtils]: 17: Hoare triple {5876#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,212 INFO L290 TraceCheckUtils]: 18: Hoare triple {5876#true} assume !(0 == ~T8_E~0); {5876#true} is VALID [2022-02-21 04:22:55,212 INFO L290 TraceCheckUtils]: 19: Hoare triple {5876#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,212 INFO L290 TraceCheckUtils]: 20: Hoare triple {5876#true} assume 0 == ~E_M~0;~E_M~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,213 INFO L290 TraceCheckUtils]: 21: Hoare triple {5876#true} assume 0 == ~E_1~0;~E_1~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,213 INFO L290 TraceCheckUtils]: 22: Hoare triple {5876#true} assume 0 == ~E_2~0;~E_2~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,213 INFO L290 TraceCheckUtils]: 23: Hoare triple {5876#true} assume 0 == ~E_3~0;~E_3~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,213 INFO L290 TraceCheckUtils]: 24: Hoare triple {5876#true} assume 0 == ~E_4~0;~E_4~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,213 INFO L290 TraceCheckUtils]: 25: Hoare triple {5876#true} assume 0 == ~E_5~0;~E_5~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,213 INFO L290 TraceCheckUtils]: 26: Hoare triple {5876#true} assume !(0 == ~E_6~0); {5876#true} is VALID [2022-02-21 04:22:55,213 INFO L290 TraceCheckUtils]: 27: Hoare triple {5876#true} assume 0 == ~E_7~0;~E_7~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,214 INFO L290 TraceCheckUtils]: 28: Hoare triple {5876#true} assume 0 == ~E_8~0;~E_8~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,214 INFO L290 TraceCheckUtils]: 29: Hoare triple {5876#true} assume 0 == ~E_9~0;~E_9~0 := 1; {5876#true} is VALID [2022-02-21 04:22:55,214 INFO L290 TraceCheckUtils]: 30: Hoare triple {5876#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5876#true} is VALID [2022-02-21 04:22:55,214 INFO L290 TraceCheckUtils]: 31: Hoare triple {5876#true} assume 1 == ~m_pc~0; {5876#true} is VALID [2022-02-21 04:22:55,214 INFO L290 TraceCheckUtils]: 32: Hoare triple {5876#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {5876#true} is VALID [2022-02-21 04:22:55,214 INFO L290 TraceCheckUtils]: 33: Hoare triple {5876#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5876#true} is VALID [2022-02-21 04:22:55,214 INFO L290 TraceCheckUtils]: 34: Hoare triple {5876#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5876#true} is VALID [2022-02-21 04:22:55,215 INFO L290 TraceCheckUtils]: 35: Hoare triple {5876#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5876#true} is VALID [2022-02-21 04:22:55,215 INFO L290 TraceCheckUtils]: 36: Hoare triple {5876#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5876#true} is VALID [2022-02-21 04:22:55,215 INFO L290 TraceCheckUtils]: 37: Hoare triple {5876#true} assume !(1 == ~t1_pc~0); {5876#true} is VALID [2022-02-21 04:22:55,215 INFO L290 TraceCheckUtils]: 38: Hoare triple {5876#true} is_transmit1_triggered_~__retres1~1#1 := 0; {5876#true} is VALID [2022-02-21 04:22:55,215 INFO L290 TraceCheckUtils]: 39: Hoare triple {5876#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5876#true} is VALID [2022-02-21 04:22:55,215 INFO L290 TraceCheckUtils]: 40: Hoare triple {5876#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5876#true} is VALID [2022-02-21 04:22:55,216 INFO L290 TraceCheckUtils]: 41: Hoare triple {5876#true} assume !(0 != activate_threads_~tmp___0~0#1); {5876#true} is VALID [2022-02-21 04:22:55,216 INFO L290 TraceCheckUtils]: 42: Hoare triple {5876#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5876#true} is VALID [2022-02-21 04:22:55,216 INFO L290 TraceCheckUtils]: 43: Hoare triple {5876#true} assume 1 == ~t2_pc~0; {5876#true} is VALID [2022-02-21 04:22:55,216 INFO L290 TraceCheckUtils]: 44: Hoare triple {5876#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {5876#true} is VALID [2022-02-21 04:22:55,216 INFO L290 TraceCheckUtils]: 45: Hoare triple {5876#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5876#true} is VALID [2022-02-21 04:22:55,216 INFO L290 TraceCheckUtils]: 46: Hoare triple {5876#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5876#true} is VALID [2022-02-21 04:22:55,216 INFO L290 TraceCheckUtils]: 47: Hoare triple {5876#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5876#true} is VALID [2022-02-21 04:22:55,217 INFO L290 TraceCheckUtils]: 48: Hoare triple {5876#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5876#true} is VALID [2022-02-21 04:22:55,217 INFO L290 TraceCheckUtils]: 49: Hoare triple {5876#true} assume !(1 == ~t3_pc~0); {5876#true} is VALID [2022-02-21 04:22:55,217 INFO L290 TraceCheckUtils]: 50: Hoare triple {5876#true} is_transmit3_triggered_~__retres1~3#1 := 0; {5876#true} is VALID [2022-02-21 04:22:55,217 INFO L290 TraceCheckUtils]: 51: Hoare triple {5876#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5876#true} is VALID [2022-02-21 04:22:55,217 INFO L290 TraceCheckUtils]: 52: Hoare triple {5876#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {5876#true} is VALID [2022-02-21 04:22:55,217 INFO L290 TraceCheckUtils]: 53: Hoare triple {5876#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {5876#true} is VALID [2022-02-21 04:22:55,218 INFO L290 TraceCheckUtils]: 54: Hoare triple {5876#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5876#true} is VALID [2022-02-21 04:22:55,218 INFO L290 TraceCheckUtils]: 55: Hoare triple {5876#true} assume 1 == ~t4_pc~0; {5876#true} is VALID [2022-02-21 04:22:55,218 INFO L290 TraceCheckUtils]: 56: Hoare triple {5876#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5876#true} is VALID [2022-02-21 04:22:55,218 INFO L290 TraceCheckUtils]: 57: Hoare triple {5876#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5876#true} is VALID [2022-02-21 04:22:55,218 INFO L290 TraceCheckUtils]: 58: Hoare triple {5876#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {5876#true} is VALID [2022-02-21 04:22:55,218 INFO L290 TraceCheckUtils]: 59: Hoare triple {5876#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {5876#true} is VALID [2022-02-21 04:22:55,218 INFO L290 TraceCheckUtils]: 60: Hoare triple {5876#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5876#true} is VALID [2022-02-21 04:22:55,219 INFO L290 TraceCheckUtils]: 61: Hoare triple {5876#true} assume !(1 == ~t5_pc~0); {5876#true} is VALID [2022-02-21 04:22:55,219 INFO L290 TraceCheckUtils]: 62: Hoare triple {5876#true} is_transmit5_triggered_~__retres1~5#1 := 0; {5876#true} is VALID [2022-02-21 04:22:55,219 INFO L290 TraceCheckUtils]: 63: Hoare triple {5876#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5876#true} is VALID [2022-02-21 04:22:55,219 INFO L290 TraceCheckUtils]: 64: Hoare triple {5876#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {5876#true} is VALID [2022-02-21 04:22:55,219 INFO L290 TraceCheckUtils]: 65: Hoare triple {5876#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {5876#true} is VALID [2022-02-21 04:22:55,219 INFO L290 TraceCheckUtils]: 66: Hoare triple {5876#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5876#true} is VALID [2022-02-21 04:22:55,219 INFO L290 TraceCheckUtils]: 67: Hoare triple {5876#true} assume 1 == ~t6_pc~0; {5876#true} is VALID [2022-02-21 04:22:55,220 INFO L290 TraceCheckUtils]: 68: Hoare triple {5876#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,220 INFO L290 TraceCheckUtils]: 69: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,221 INFO L290 TraceCheckUtils]: 70: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,221 INFO L290 TraceCheckUtils]: 71: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,222 INFO L290 TraceCheckUtils]: 72: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,222 INFO L290 TraceCheckUtils]: 73: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,222 INFO L290 TraceCheckUtils]: 74: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,223 INFO L290 TraceCheckUtils]: 75: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,223 INFO L290 TraceCheckUtils]: 76: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,223 INFO L290 TraceCheckUtils]: 77: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,224 INFO L290 TraceCheckUtils]: 78: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,224 INFO L290 TraceCheckUtils]: 79: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,224 INFO L290 TraceCheckUtils]: 80: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,225 INFO L290 TraceCheckUtils]: 81: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,225 INFO L290 TraceCheckUtils]: 82: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,226 INFO L290 TraceCheckUtils]: 83: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,226 INFO L290 TraceCheckUtils]: 84: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,226 INFO L290 TraceCheckUtils]: 85: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t9_pc~0; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,227 INFO L290 TraceCheckUtils]: 86: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,227 INFO L290 TraceCheckUtils]: 87: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,227 INFO L290 TraceCheckUtils]: 88: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,227 INFO L290 TraceCheckUtils]: 89: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,228 INFO L290 TraceCheckUtils]: 90: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,228 INFO L290 TraceCheckUtils]: 91: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,228 INFO L290 TraceCheckUtils]: 92: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,229 INFO L290 TraceCheckUtils]: 93: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,229 INFO L290 TraceCheckUtils]: 94: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,229 INFO L290 TraceCheckUtils]: 95: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,230 INFO L290 TraceCheckUtils]: 96: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,230 INFO L290 TraceCheckUtils]: 97: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,230 INFO L290 TraceCheckUtils]: 98: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,230 INFO L290 TraceCheckUtils]: 99: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,231 INFO L290 TraceCheckUtils]: 100: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,231 INFO L290 TraceCheckUtils]: 101: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,231 INFO L290 TraceCheckUtils]: 102: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,232 INFO L290 TraceCheckUtils]: 103: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,232 INFO L290 TraceCheckUtils]: 104: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,232 INFO L290 TraceCheckUtils]: 105: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,233 INFO L290 TraceCheckUtils]: 106: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {5878#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:55,233 INFO L290 TraceCheckUtils]: 107: Hoare triple {5878#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {5877#false} is VALID [2022-02-21 04:22:55,233 INFO L290 TraceCheckUtils]: 108: Hoare triple {5877#false} assume 1 == ~E_7~0;~E_7~0 := 2; {5877#false} is VALID [2022-02-21 04:22:55,233 INFO L290 TraceCheckUtils]: 109: Hoare triple {5877#false} assume 1 == ~E_8~0;~E_8~0 := 2; {5877#false} is VALID [2022-02-21 04:22:55,233 INFO L290 TraceCheckUtils]: 110: Hoare triple {5877#false} assume 1 == ~E_9~0;~E_9~0 := 2; {5877#false} is VALID [2022-02-21 04:22:55,233 INFO L290 TraceCheckUtils]: 111: Hoare triple {5877#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 112: Hoare triple {5877#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 113: Hoare triple {5877#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 114: Hoare triple {5877#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 115: Hoare triple {5877#false} assume !(0 == start_simulation_~tmp~3#1); {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 116: Hoare triple {5877#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 117: Hoare triple {5877#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 118: Hoare triple {5877#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 119: Hoare triple {5877#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {5877#false} is VALID [2022-02-21 04:22:55,234 INFO L290 TraceCheckUtils]: 120: Hoare triple {5877#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {5877#false} is VALID [2022-02-21 04:22:55,235 INFO L290 TraceCheckUtils]: 121: Hoare triple {5877#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5877#false} is VALID [2022-02-21 04:22:55,235 INFO L290 TraceCheckUtils]: 122: Hoare triple {5877#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {5877#false} is VALID [2022-02-21 04:22:55,235 INFO L290 TraceCheckUtils]: 123: Hoare triple {5877#false} assume !(0 != start_simulation_~tmp___0~1#1); {5877#false} is VALID [2022-02-21 04:22:55,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:55,236 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:55,236 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291582024] [2022-02-21 04:22:55,236 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291582024] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:55,239 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:55,240 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:55,240 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1406542498] [2022-02-21 04:22:55,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:55,240 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:55,240 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:55,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:55,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:55,241 INFO L87 Difference]: Start difference. First operand 1170 states and 1742 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:56,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:56,292 INFO L93 Difference]: Finished difference Result 1170 states and 1741 transitions. [2022-02-21 04:22:56,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:56,292 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:56,386 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:56,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:56,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1741 transitions. [2022-02-21 04:22:56,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:22:56,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:22:56,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:56,499 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2022-02-21 04:22:56,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:22:56,522 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:56,525 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1741 transitions. Second operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:56,528 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1741 transitions. Second operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:56,531 INFO L87 Difference]: Start difference. First operand 1170 states and 1741 transitions. Second operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:56,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:56,584 INFO L93 Difference]: Finished difference Result 1170 states and 1741 transitions. [2022-02-21 04:22:56,584 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,587 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:56,587 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:56,590 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,594 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:56,649 INFO L93 Difference]: Finished difference Result 1170 states and 1741 transitions. [2022-02-21 04:22:56,649 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,651 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:56,651 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:56,652 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:56,652 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:56,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:56,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1741 transitions. [2022-02-21 04:22:56,709 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2022-02-21 04:22:56,709 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2022-02-21 04:22:56,709 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:22:56,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1741 transitions. [2022-02-21 04:22:56,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:56,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:56,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:56,718 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:56,719 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:56,720 INFO L791 eck$LassoCheckResult]: Stem: 7921#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7871#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7872#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8090#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 7759#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7760#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8067#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7566#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7567#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7995#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7996#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7065#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7066#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7269#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7657#L939 assume !(0 == ~M_E~0); 7901#L939-2 assume !(0 == ~T1_E~0); 7902#L944-1 assume !(0 == ~T2_E~0); 7686#L949-1 assume !(0 == ~T3_E~0); 7684#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7685#L959-1 assume !(0 == ~T5_E~0); 8104#L964-1 assume !(0 == ~T6_E~0); 7417#L969-1 assume !(0 == ~T7_E~0); 7418#L974-1 assume !(0 == ~T8_E~0); 8057#L979-1 assume !(0 == ~T9_E~0); 8058#L984-1 assume !(0 == ~E_M~0); 7580#L989-1 assume !(0 == ~E_1~0); 7581#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7467#L999-1 assume !(0 == ~E_3~0); 7468#L1004-1 assume !(0 == ~E_4~0); 7133#L1009-1 assume !(0 == ~E_5~0); 7134#L1014-1 assume !(0 == ~E_6~0); 7463#L1019-1 assume !(0 == ~E_7~0); 8000#L1024-1 assume !(0 == ~E_8~0); 7390#L1029-1 assume !(0 == ~E_9~0); 7391#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7483#L460 assume 1 == ~m_pc~0; 7052#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7053#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7966#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8205#L1167 assume !(0 != activate_threads_~tmp~1#1); 7674#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7675#L479 assume 1 == ~t1_pc~0; 7658#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7659#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8162#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7403#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 7404#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7251#L498 assume !(1 == ~t2_pc~0); 7252#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7655#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7656#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8033#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7957#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7958#L517 assume 1 == ~t3_pc~0; 8167#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8168#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7729#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7435#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 7436#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8011#L536 assume !(1 == ~t4_pc~0); 7719#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7718#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8095#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7711#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 7712#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7933#L555 assume 1 == ~t5_pc~0; 7934#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8001#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7166#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7167#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 7274#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7172#L574 assume !(1 == ~t6_pc~0); 7173#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7804#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7277#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7278#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 8029#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8189#L593 assume 1 == ~t7_pc~0; 8190#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7409#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8109#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8210#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 8170#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7573#L612 assume !(1 == ~t8_pc~0); 7574#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7983#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7842#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7843#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 7808#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7809#L631 assume 1 == ~t9_pc~0; 7825#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7163#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7131#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7132#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 7661#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8012#L1047 assume !(1 == ~M_E~0); 7103#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7104#L1052-1 assume !(1 == ~T2_E~0); 7084#L1057-1 assume !(1 == ~T3_E~0); 7085#L1062-1 assume !(1 == ~T4_E~0); 7374#L1067-1 assume !(1 == ~T5_E~0); 7677#L1072-1 assume !(1 == ~T6_E~0); 7678#L1077-1 assume !(1 == ~T7_E~0); 7265#L1082-1 assume !(1 == ~T8_E~0); 7266#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7061#L1092-1 assume !(1 == ~E_M~0); 7062#L1097-1 assume !(1 == ~E_1~0); 7086#L1102-1 assume !(1 == ~E_2~0); 7867#L1107-1 assume !(1 == ~E_3~0); 7802#L1112-1 assume !(1 == ~E_4~0); 7803#L1117-1 assume !(1 == ~E_5~0); 7844#L1122-1 assume !(1 == ~E_6~0); 7730#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7486#L1132-1 assume !(1 == ~E_8~0); 7487#L1137-1 assume !(1 == ~E_9~0); 7373#L1142-1 assume { :end_inline_reset_delta_events } true; 7236#L1428-2 [2022-02-21 04:22:56,720 INFO L793 eck$LassoCheckResult]: Loop: 7236#L1428-2 assume !false; 7237#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7308#L914 assume !false; 7798#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7799#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7072#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7073#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8030#L783 assume !(0 != eval_~tmp~0#1); 7470#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7471#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7866#L939-3 assume !(0 == ~M_E~0); 7291#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7292#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7055#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7056#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7692#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7137#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7138#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7342#L974-3 assume !(0 == ~T8_E~0); 7343#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7773#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7774#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7396#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7397#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7908#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7219#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7220#L1014-3 assume !(0 == ~E_6~0); 7757#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7758#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7739#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7693#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7694#L460-33 assume 1 == ~m_pc~0; 7731#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7732#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7488#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7063#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7064#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7424#L479-33 assume !(1 == ~t1_pc~0); 7425#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7392#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7393#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7975#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 8150#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7433#L498-33 assume 1 == ~t2_pc~0; 7434#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7179#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7313#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7314#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7289#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7290#L517-33 assume !(1 == ~t3_pc~0); 8198#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8081#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8082#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7894#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7895#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7520#L536-33 assume 1 == ~t4_pc~0; 7521#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7590#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7591#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7781#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8060#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7110#L555-33 assume !(1 == ~t5_pc~0); 7111#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7836#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7383#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7384#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7863#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7081#L574-33 assume 1 == ~t6_pc~0; 7082#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8072#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7398#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7399#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7652#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7157#L593-33 assume !(1 == ~t7_pc~0); 7158#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7613#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7263#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7264#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7923#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8050#L612-33 assume 1 == ~t8_pc~0; 8177#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8141#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8142#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7984#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7259#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7260#L631-33 assume 1 == ~t9_pc~0; 8102#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7203#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7204#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7456#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7315#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7316#L1047-3 assume !(1 == ~M_E~0); 7489#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8103#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8035#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8036#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7214#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7215#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7597#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7442#L1082-3 assume !(1 == ~T8_E~0); 7443#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7516#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7797#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7727#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7728#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8073#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7437#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7438#L1122-3 assume !(1 == ~E_6~0); 7490#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7491#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7880#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7857#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7320#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7195#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7858#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7615#L1447 assume !(0 == start_simulation_~tmp~3#1); 7616#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8054#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7356#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7881#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7466#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7223#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7224#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7679#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7236#L1428-2 [2022-02-21 04:22:56,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:56,721 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2022-02-21 04:22:56,721 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:56,722 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227430713] [2022-02-21 04:22:56,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:56,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:56,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:56,787 INFO L290 TraceCheckUtils]: 0: Hoare triple {10562#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {10562#true} is VALID [2022-02-21 04:22:56,788 INFO L290 TraceCheckUtils]: 1: Hoare triple {10562#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {10564#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:56,788 INFO L290 TraceCheckUtils]: 2: Hoare triple {10564#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10564#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:56,789 INFO L290 TraceCheckUtils]: 3: Hoare triple {10564#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10564#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:56,789 INFO L290 TraceCheckUtils]: 4: Hoare triple {10564#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {10564#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:56,789 INFO L290 TraceCheckUtils]: 5: Hoare triple {10564#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10564#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:56,790 INFO L290 TraceCheckUtils]: 6: Hoare triple {10564#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10564#(= ~t3_i~0 1)} is VALID [2022-02-21 04:22:56,790 INFO L290 TraceCheckUtils]: 7: Hoare triple {10564#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,790 INFO L290 TraceCheckUtils]: 8: Hoare triple {10563#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,790 INFO L290 TraceCheckUtils]: 9: Hoare triple {10563#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,790 INFO L290 TraceCheckUtils]: 10: Hoare triple {10563#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,791 INFO L290 TraceCheckUtils]: 11: Hoare triple {10563#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,791 INFO L290 TraceCheckUtils]: 12: Hoare triple {10563#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,791 INFO L290 TraceCheckUtils]: 13: Hoare triple {10563#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {10563#false} is VALID [2022-02-21 04:22:56,791 INFO L290 TraceCheckUtils]: 14: Hoare triple {10563#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10563#false} is VALID [2022-02-21 04:22:56,791 INFO L290 TraceCheckUtils]: 15: Hoare triple {10563#false} assume !(0 == ~M_E~0); {10563#false} is VALID [2022-02-21 04:22:56,791 INFO L290 TraceCheckUtils]: 16: Hoare triple {10563#false} assume !(0 == ~T1_E~0); {10563#false} is VALID [2022-02-21 04:22:56,791 INFO L290 TraceCheckUtils]: 17: Hoare triple {10563#false} assume !(0 == ~T2_E~0); {10563#false} is VALID [2022-02-21 04:22:56,792 INFO L290 TraceCheckUtils]: 18: Hoare triple {10563#false} assume !(0 == ~T3_E~0); {10563#false} is VALID [2022-02-21 04:22:56,792 INFO L290 TraceCheckUtils]: 19: Hoare triple {10563#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10563#false} is VALID [2022-02-21 04:22:56,792 INFO L290 TraceCheckUtils]: 20: Hoare triple {10563#false} assume !(0 == ~T5_E~0); {10563#false} is VALID [2022-02-21 04:22:56,792 INFO L290 TraceCheckUtils]: 21: Hoare triple {10563#false} assume !(0 == ~T6_E~0); {10563#false} is VALID [2022-02-21 04:22:56,792 INFO L290 TraceCheckUtils]: 22: Hoare triple {10563#false} assume !(0 == ~T7_E~0); {10563#false} is VALID [2022-02-21 04:22:56,792 INFO L290 TraceCheckUtils]: 23: Hoare triple {10563#false} assume !(0 == ~T8_E~0); {10563#false} is VALID [2022-02-21 04:22:56,792 INFO L290 TraceCheckUtils]: 24: Hoare triple {10563#false} assume !(0 == ~T9_E~0); {10563#false} is VALID [2022-02-21 04:22:56,793 INFO L290 TraceCheckUtils]: 25: Hoare triple {10563#false} assume !(0 == ~E_M~0); {10563#false} is VALID [2022-02-21 04:22:56,793 INFO L290 TraceCheckUtils]: 26: Hoare triple {10563#false} assume !(0 == ~E_1~0); {10563#false} is VALID [2022-02-21 04:22:56,793 INFO L290 TraceCheckUtils]: 27: Hoare triple {10563#false} assume 0 == ~E_2~0;~E_2~0 := 1; {10563#false} is VALID [2022-02-21 04:22:56,793 INFO L290 TraceCheckUtils]: 28: Hoare triple {10563#false} assume !(0 == ~E_3~0); {10563#false} is VALID [2022-02-21 04:22:56,793 INFO L290 TraceCheckUtils]: 29: Hoare triple {10563#false} assume !(0 == ~E_4~0); {10563#false} is VALID [2022-02-21 04:22:56,793 INFO L290 TraceCheckUtils]: 30: Hoare triple {10563#false} assume !(0 == ~E_5~0); {10563#false} is VALID [2022-02-21 04:22:56,794 INFO L290 TraceCheckUtils]: 31: Hoare triple {10563#false} assume !(0 == ~E_6~0); {10563#false} is VALID [2022-02-21 04:22:56,794 INFO L290 TraceCheckUtils]: 32: Hoare triple {10563#false} assume !(0 == ~E_7~0); {10563#false} is VALID [2022-02-21 04:22:56,794 INFO L290 TraceCheckUtils]: 33: Hoare triple {10563#false} assume !(0 == ~E_8~0); {10563#false} is VALID [2022-02-21 04:22:56,794 INFO L290 TraceCheckUtils]: 34: Hoare triple {10563#false} assume !(0 == ~E_9~0); {10563#false} is VALID [2022-02-21 04:22:56,794 INFO L290 TraceCheckUtils]: 35: Hoare triple {10563#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10563#false} is VALID [2022-02-21 04:22:56,794 INFO L290 TraceCheckUtils]: 36: Hoare triple {10563#false} assume 1 == ~m_pc~0; {10563#false} is VALID [2022-02-21 04:22:56,794 INFO L290 TraceCheckUtils]: 37: Hoare triple {10563#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {10563#false} is VALID [2022-02-21 04:22:56,795 INFO L290 TraceCheckUtils]: 38: Hoare triple {10563#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10563#false} is VALID [2022-02-21 04:22:56,795 INFO L290 TraceCheckUtils]: 39: Hoare triple {10563#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10563#false} is VALID [2022-02-21 04:22:56,795 INFO L290 TraceCheckUtils]: 40: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp~1#1); {10563#false} is VALID [2022-02-21 04:22:56,795 INFO L290 TraceCheckUtils]: 41: Hoare triple {10563#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10563#false} is VALID [2022-02-21 04:22:56,795 INFO L290 TraceCheckUtils]: 42: Hoare triple {10563#false} assume 1 == ~t1_pc~0; {10563#false} is VALID [2022-02-21 04:22:56,795 INFO L290 TraceCheckUtils]: 43: Hoare triple {10563#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10563#false} is VALID [2022-02-21 04:22:56,796 INFO L290 TraceCheckUtils]: 44: Hoare triple {10563#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10563#false} is VALID [2022-02-21 04:22:56,796 INFO L290 TraceCheckUtils]: 45: Hoare triple {10563#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10563#false} is VALID [2022-02-21 04:22:56,796 INFO L290 TraceCheckUtils]: 46: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___0~0#1); {10563#false} is VALID [2022-02-21 04:22:56,796 INFO L290 TraceCheckUtils]: 47: Hoare triple {10563#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10563#false} is VALID [2022-02-21 04:22:56,796 INFO L290 TraceCheckUtils]: 48: Hoare triple {10563#false} assume !(1 == ~t2_pc~0); {10563#false} is VALID [2022-02-21 04:22:56,796 INFO L290 TraceCheckUtils]: 49: Hoare triple {10563#false} is_transmit2_triggered_~__retres1~2#1 := 0; {10563#false} is VALID [2022-02-21 04:22:56,796 INFO L290 TraceCheckUtils]: 50: Hoare triple {10563#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10563#false} is VALID [2022-02-21 04:22:56,797 INFO L290 TraceCheckUtils]: 51: Hoare triple {10563#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10563#false} is VALID [2022-02-21 04:22:56,797 INFO L290 TraceCheckUtils]: 52: Hoare triple {10563#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10563#false} is VALID [2022-02-21 04:22:56,797 INFO L290 TraceCheckUtils]: 53: Hoare triple {10563#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10563#false} is VALID [2022-02-21 04:22:56,797 INFO L290 TraceCheckUtils]: 54: Hoare triple {10563#false} assume 1 == ~t3_pc~0; {10563#false} is VALID [2022-02-21 04:22:56,797 INFO L290 TraceCheckUtils]: 55: Hoare triple {10563#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10563#false} is VALID [2022-02-21 04:22:56,797 INFO L290 TraceCheckUtils]: 56: Hoare triple {10563#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10563#false} is VALID [2022-02-21 04:22:56,798 INFO L290 TraceCheckUtils]: 57: Hoare triple {10563#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10563#false} is VALID [2022-02-21 04:22:56,798 INFO L290 TraceCheckUtils]: 58: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___2~0#1); {10563#false} is VALID [2022-02-21 04:22:56,798 INFO L290 TraceCheckUtils]: 59: Hoare triple {10563#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10563#false} is VALID [2022-02-21 04:22:56,798 INFO L290 TraceCheckUtils]: 60: Hoare triple {10563#false} assume !(1 == ~t4_pc~0); {10563#false} is VALID [2022-02-21 04:22:56,798 INFO L290 TraceCheckUtils]: 61: Hoare triple {10563#false} is_transmit4_triggered_~__retres1~4#1 := 0; {10563#false} is VALID [2022-02-21 04:22:56,798 INFO L290 TraceCheckUtils]: 62: Hoare triple {10563#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10563#false} is VALID [2022-02-21 04:22:56,798 INFO L290 TraceCheckUtils]: 63: Hoare triple {10563#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10563#false} is VALID [2022-02-21 04:22:56,799 INFO L290 TraceCheckUtils]: 64: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___3~0#1); {10563#false} is VALID [2022-02-21 04:22:56,799 INFO L290 TraceCheckUtils]: 65: Hoare triple {10563#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10563#false} is VALID [2022-02-21 04:22:56,799 INFO L290 TraceCheckUtils]: 66: Hoare triple {10563#false} assume 1 == ~t5_pc~0; {10563#false} is VALID [2022-02-21 04:22:56,799 INFO L290 TraceCheckUtils]: 67: Hoare triple {10563#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10563#false} is VALID [2022-02-21 04:22:56,799 INFO L290 TraceCheckUtils]: 68: Hoare triple {10563#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10563#false} is VALID [2022-02-21 04:22:56,799 INFO L290 TraceCheckUtils]: 69: Hoare triple {10563#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10563#false} is VALID [2022-02-21 04:22:56,799 INFO L290 TraceCheckUtils]: 70: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___4~0#1); {10563#false} is VALID [2022-02-21 04:22:56,800 INFO L290 TraceCheckUtils]: 71: Hoare triple {10563#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10563#false} is VALID [2022-02-21 04:22:56,800 INFO L290 TraceCheckUtils]: 72: Hoare triple {10563#false} assume !(1 == ~t6_pc~0); {10563#false} is VALID [2022-02-21 04:22:56,800 INFO L290 TraceCheckUtils]: 73: Hoare triple {10563#false} is_transmit6_triggered_~__retres1~6#1 := 0; {10563#false} is VALID [2022-02-21 04:22:56,800 INFO L290 TraceCheckUtils]: 74: Hoare triple {10563#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10563#false} is VALID [2022-02-21 04:22:56,800 INFO L290 TraceCheckUtils]: 75: Hoare triple {10563#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10563#false} is VALID [2022-02-21 04:22:56,800 INFO L290 TraceCheckUtils]: 76: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___5~0#1); {10563#false} is VALID [2022-02-21 04:22:56,801 INFO L290 TraceCheckUtils]: 77: Hoare triple {10563#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10563#false} is VALID [2022-02-21 04:22:56,801 INFO L290 TraceCheckUtils]: 78: Hoare triple {10563#false} assume 1 == ~t7_pc~0; {10563#false} is VALID [2022-02-21 04:22:56,801 INFO L290 TraceCheckUtils]: 79: Hoare triple {10563#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {10563#false} is VALID [2022-02-21 04:22:56,801 INFO L290 TraceCheckUtils]: 80: Hoare triple {10563#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10563#false} is VALID [2022-02-21 04:22:56,801 INFO L290 TraceCheckUtils]: 81: Hoare triple {10563#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10563#false} is VALID [2022-02-21 04:22:56,801 INFO L290 TraceCheckUtils]: 82: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___6~0#1); {10563#false} is VALID [2022-02-21 04:22:56,802 INFO L290 TraceCheckUtils]: 83: Hoare triple {10563#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10563#false} is VALID [2022-02-21 04:22:56,802 INFO L290 TraceCheckUtils]: 84: Hoare triple {10563#false} assume !(1 == ~t8_pc~0); {10563#false} is VALID [2022-02-21 04:22:56,802 INFO L290 TraceCheckUtils]: 85: Hoare triple {10563#false} is_transmit8_triggered_~__retres1~8#1 := 0; {10563#false} is VALID [2022-02-21 04:22:56,802 INFO L290 TraceCheckUtils]: 86: Hoare triple {10563#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10563#false} is VALID [2022-02-21 04:22:56,802 INFO L290 TraceCheckUtils]: 87: Hoare triple {10563#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10563#false} is VALID [2022-02-21 04:22:56,802 INFO L290 TraceCheckUtils]: 88: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___7~0#1); {10563#false} is VALID [2022-02-21 04:22:56,802 INFO L290 TraceCheckUtils]: 89: Hoare triple {10563#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10563#false} is VALID [2022-02-21 04:22:56,803 INFO L290 TraceCheckUtils]: 90: Hoare triple {10563#false} assume 1 == ~t9_pc~0; {10563#false} is VALID [2022-02-21 04:22:56,803 INFO L290 TraceCheckUtils]: 91: Hoare triple {10563#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10563#false} is VALID [2022-02-21 04:22:56,803 INFO L290 TraceCheckUtils]: 92: Hoare triple {10563#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10563#false} is VALID [2022-02-21 04:22:56,803 INFO L290 TraceCheckUtils]: 93: Hoare triple {10563#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10563#false} is VALID [2022-02-21 04:22:56,803 INFO L290 TraceCheckUtils]: 94: Hoare triple {10563#false} assume !(0 != activate_threads_~tmp___8~0#1); {10563#false} is VALID [2022-02-21 04:22:56,803 INFO L290 TraceCheckUtils]: 95: Hoare triple {10563#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10563#false} is VALID [2022-02-21 04:22:56,803 INFO L290 TraceCheckUtils]: 96: Hoare triple {10563#false} assume !(1 == ~M_E~0); {10563#false} is VALID [2022-02-21 04:22:56,804 INFO L290 TraceCheckUtils]: 97: Hoare triple {10563#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,804 INFO L290 TraceCheckUtils]: 98: Hoare triple {10563#false} assume !(1 == ~T2_E~0); {10563#false} is VALID [2022-02-21 04:22:56,804 INFO L290 TraceCheckUtils]: 99: Hoare triple {10563#false} assume !(1 == ~T3_E~0); {10563#false} is VALID [2022-02-21 04:22:56,804 INFO L290 TraceCheckUtils]: 100: Hoare triple {10563#false} assume !(1 == ~T4_E~0); {10563#false} is VALID [2022-02-21 04:22:56,804 INFO L290 TraceCheckUtils]: 101: Hoare triple {10563#false} assume !(1 == ~T5_E~0); {10563#false} is VALID [2022-02-21 04:22:56,804 INFO L290 TraceCheckUtils]: 102: Hoare triple {10563#false} assume !(1 == ~T6_E~0); {10563#false} is VALID [2022-02-21 04:22:56,805 INFO L290 TraceCheckUtils]: 103: Hoare triple {10563#false} assume !(1 == ~T7_E~0); {10563#false} is VALID [2022-02-21 04:22:56,805 INFO L290 TraceCheckUtils]: 104: Hoare triple {10563#false} assume !(1 == ~T8_E~0); {10563#false} is VALID [2022-02-21 04:22:56,805 INFO L290 TraceCheckUtils]: 105: Hoare triple {10563#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,805 INFO L290 TraceCheckUtils]: 106: Hoare triple {10563#false} assume !(1 == ~E_M~0); {10563#false} is VALID [2022-02-21 04:22:56,805 INFO L290 TraceCheckUtils]: 107: Hoare triple {10563#false} assume !(1 == ~E_1~0); {10563#false} is VALID [2022-02-21 04:22:56,805 INFO L290 TraceCheckUtils]: 108: Hoare triple {10563#false} assume !(1 == ~E_2~0); {10563#false} is VALID [2022-02-21 04:22:56,805 INFO L290 TraceCheckUtils]: 109: Hoare triple {10563#false} assume !(1 == ~E_3~0); {10563#false} is VALID [2022-02-21 04:22:56,806 INFO L290 TraceCheckUtils]: 110: Hoare triple {10563#false} assume !(1 == ~E_4~0); {10563#false} is VALID [2022-02-21 04:22:56,806 INFO L290 TraceCheckUtils]: 111: Hoare triple {10563#false} assume !(1 == ~E_5~0); {10563#false} is VALID [2022-02-21 04:22:56,806 INFO L290 TraceCheckUtils]: 112: Hoare triple {10563#false} assume !(1 == ~E_6~0); {10563#false} is VALID [2022-02-21 04:22:56,806 INFO L290 TraceCheckUtils]: 113: Hoare triple {10563#false} assume 1 == ~E_7~0;~E_7~0 := 2; {10563#false} is VALID [2022-02-21 04:22:56,806 INFO L290 TraceCheckUtils]: 114: Hoare triple {10563#false} assume !(1 == ~E_8~0); {10563#false} is VALID [2022-02-21 04:22:56,806 INFO L290 TraceCheckUtils]: 115: Hoare triple {10563#false} assume !(1 == ~E_9~0); {10563#false} is VALID [2022-02-21 04:22:56,807 INFO L290 TraceCheckUtils]: 116: Hoare triple {10563#false} assume { :end_inline_reset_delta_events } true; {10563#false} is VALID [2022-02-21 04:22:56,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:56,807 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:56,807 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227430713] [2022-02-21 04:22:56,808 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227430713] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:56,808 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:56,808 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:56,808 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437492759] [2022-02-21 04:22:56,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:56,809 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:56,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:56,809 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 2 times [2022-02-21 04:22:56,809 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:56,810 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450657788] [2022-02-21 04:22:56,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:56,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:56,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:56,856 INFO L290 TraceCheckUtils]: 0: Hoare triple {10565#true} assume !false; {10565#true} is VALID [2022-02-21 04:22:56,856 INFO L290 TraceCheckUtils]: 1: Hoare triple {10565#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10565#true} is VALID [2022-02-21 04:22:56,856 INFO L290 TraceCheckUtils]: 2: Hoare triple {10565#true} assume !false; {10565#true} is VALID [2022-02-21 04:22:56,857 INFO L290 TraceCheckUtils]: 3: Hoare triple {10565#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {10565#true} is VALID [2022-02-21 04:22:56,857 INFO L290 TraceCheckUtils]: 4: Hoare triple {10565#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {10565#true} is VALID [2022-02-21 04:22:56,857 INFO L290 TraceCheckUtils]: 5: Hoare triple {10565#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {10565#true} is VALID [2022-02-21 04:22:56,857 INFO L290 TraceCheckUtils]: 6: Hoare triple {10565#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {10565#true} is VALID [2022-02-21 04:22:56,857 INFO L290 TraceCheckUtils]: 7: Hoare triple {10565#true} assume !(0 != eval_~tmp~0#1); {10565#true} is VALID [2022-02-21 04:22:56,857 INFO L290 TraceCheckUtils]: 8: Hoare triple {10565#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10565#true} is VALID [2022-02-21 04:22:56,857 INFO L290 TraceCheckUtils]: 9: Hoare triple {10565#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10565#true} is VALID [2022-02-21 04:22:56,858 INFO L290 TraceCheckUtils]: 10: Hoare triple {10565#true} assume !(0 == ~M_E~0); {10565#true} is VALID [2022-02-21 04:22:56,858 INFO L290 TraceCheckUtils]: 11: Hoare triple {10565#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,858 INFO L290 TraceCheckUtils]: 12: Hoare triple {10565#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,858 INFO L290 TraceCheckUtils]: 13: Hoare triple {10565#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,858 INFO L290 TraceCheckUtils]: 14: Hoare triple {10565#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,858 INFO L290 TraceCheckUtils]: 15: Hoare triple {10565#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,858 INFO L290 TraceCheckUtils]: 16: Hoare triple {10565#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,859 INFO L290 TraceCheckUtils]: 17: Hoare triple {10565#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,859 INFO L290 TraceCheckUtils]: 18: Hoare triple {10565#true} assume !(0 == ~T8_E~0); {10565#true} is VALID [2022-02-21 04:22:56,859 INFO L290 TraceCheckUtils]: 19: Hoare triple {10565#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,859 INFO L290 TraceCheckUtils]: 20: Hoare triple {10565#true} assume 0 == ~E_M~0;~E_M~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,859 INFO L290 TraceCheckUtils]: 21: Hoare triple {10565#true} assume 0 == ~E_1~0;~E_1~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,859 INFO L290 TraceCheckUtils]: 22: Hoare triple {10565#true} assume 0 == ~E_2~0;~E_2~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,859 INFO L290 TraceCheckUtils]: 23: Hoare triple {10565#true} assume 0 == ~E_3~0;~E_3~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,860 INFO L290 TraceCheckUtils]: 24: Hoare triple {10565#true} assume 0 == ~E_4~0;~E_4~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,860 INFO L290 TraceCheckUtils]: 25: Hoare triple {10565#true} assume 0 == ~E_5~0;~E_5~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,860 INFO L290 TraceCheckUtils]: 26: Hoare triple {10565#true} assume !(0 == ~E_6~0); {10565#true} is VALID [2022-02-21 04:22:56,860 INFO L290 TraceCheckUtils]: 27: Hoare triple {10565#true} assume 0 == ~E_7~0;~E_7~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,860 INFO L290 TraceCheckUtils]: 28: Hoare triple {10565#true} assume 0 == ~E_8~0;~E_8~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,860 INFO L290 TraceCheckUtils]: 29: Hoare triple {10565#true} assume 0 == ~E_9~0;~E_9~0 := 1; {10565#true} is VALID [2022-02-21 04:22:56,861 INFO L290 TraceCheckUtils]: 30: Hoare triple {10565#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10565#true} is VALID [2022-02-21 04:22:56,861 INFO L290 TraceCheckUtils]: 31: Hoare triple {10565#true} assume 1 == ~m_pc~0; {10565#true} is VALID [2022-02-21 04:22:56,861 INFO L290 TraceCheckUtils]: 32: Hoare triple {10565#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {10565#true} is VALID [2022-02-21 04:22:56,861 INFO L290 TraceCheckUtils]: 33: Hoare triple {10565#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10565#true} is VALID [2022-02-21 04:22:56,861 INFO L290 TraceCheckUtils]: 34: Hoare triple {10565#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10565#true} is VALID [2022-02-21 04:22:56,861 INFO L290 TraceCheckUtils]: 35: Hoare triple {10565#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10565#true} is VALID [2022-02-21 04:22:56,861 INFO L290 TraceCheckUtils]: 36: Hoare triple {10565#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10565#true} is VALID [2022-02-21 04:22:56,862 INFO L290 TraceCheckUtils]: 37: Hoare triple {10565#true} assume !(1 == ~t1_pc~0); {10565#true} is VALID [2022-02-21 04:22:56,862 INFO L290 TraceCheckUtils]: 38: Hoare triple {10565#true} is_transmit1_triggered_~__retres1~1#1 := 0; {10565#true} is VALID [2022-02-21 04:22:56,862 INFO L290 TraceCheckUtils]: 39: Hoare triple {10565#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10565#true} is VALID [2022-02-21 04:22:56,862 INFO L290 TraceCheckUtils]: 40: Hoare triple {10565#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10565#true} is VALID [2022-02-21 04:22:56,862 INFO L290 TraceCheckUtils]: 41: Hoare triple {10565#true} assume !(0 != activate_threads_~tmp___0~0#1); {10565#true} is VALID [2022-02-21 04:22:56,862 INFO L290 TraceCheckUtils]: 42: Hoare triple {10565#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10565#true} is VALID [2022-02-21 04:22:56,863 INFO L290 TraceCheckUtils]: 43: Hoare triple {10565#true} assume 1 == ~t2_pc~0; {10565#true} is VALID [2022-02-21 04:22:56,863 INFO L290 TraceCheckUtils]: 44: Hoare triple {10565#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10565#true} is VALID [2022-02-21 04:22:56,863 INFO L290 TraceCheckUtils]: 45: Hoare triple {10565#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10565#true} is VALID [2022-02-21 04:22:56,863 INFO L290 TraceCheckUtils]: 46: Hoare triple {10565#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10565#true} is VALID [2022-02-21 04:22:56,863 INFO L290 TraceCheckUtils]: 47: Hoare triple {10565#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10565#true} is VALID [2022-02-21 04:22:56,863 INFO L290 TraceCheckUtils]: 48: Hoare triple {10565#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10565#true} is VALID [2022-02-21 04:22:56,863 INFO L290 TraceCheckUtils]: 49: Hoare triple {10565#true} assume !(1 == ~t3_pc~0); {10565#true} is VALID [2022-02-21 04:22:56,864 INFO L290 TraceCheckUtils]: 50: Hoare triple {10565#true} is_transmit3_triggered_~__retres1~3#1 := 0; {10565#true} is VALID [2022-02-21 04:22:56,864 INFO L290 TraceCheckUtils]: 51: Hoare triple {10565#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10565#true} is VALID [2022-02-21 04:22:56,864 INFO L290 TraceCheckUtils]: 52: Hoare triple {10565#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10565#true} is VALID [2022-02-21 04:22:56,864 INFO L290 TraceCheckUtils]: 53: Hoare triple {10565#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10565#true} is VALID [2022-02-21 04:22:56,864 INFO L290 TraceCheckUtils]: 54: Hoare triple {10565#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10565#true} is VALID [2022-02-21 04:22:56,864 INFO L290 TraceCheckUtils]: 55: Hoare triple {10565#true} assume 1 == ~t4_pc~0; {10565#true} is VALID [2022-02-21 04:22:56,865 INFO L290 TraceCheckUtils]: 56: Hoare triple {10565#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10565#true} is VALID [2022-02-21 04:22:56,865 INFO L290 TraceCheckUtils]: 57: Hoare triple {10565#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10565#true} is VALID [2022-02-21 04:22:56,865 INFO L290 TraceCheckUtils]: 58: Hoare triple {10565#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10565#true} is VALID [2022-02-21 04:22:56,865 INFO L290 TraceCheckUtils]: 59: Hoare triple {10565#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10565#true} is VALID [2022-02-21 04:22:56,865 INFO L290 TraceCheckUtils]: 60: Hoare triple {10565#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10565#true} is VALID [2022-02-21 04:22:56,865 INFO L290 TraceCheckUtils]: 61: Hoare triple {10565#true} assume !(1 == ~t5_pc~0); {10565#true} is VALID [2022-02-21 04:22:56,865 INFO L290 TraceCheckUtils]: 62: Hoare triple {10565#true} is_transmit5_triggered_~__retres1~5#1 := 0; {10565#true} is VALID [2022-02-21 04:22:56,866 INFO L290 TraceCheckUtils]: 63: Hoare triple {10565#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10565#true} is VALID [2022-02-21 04:22:56,866 INFO L290 TraceCheckUtils]: 64: Hoare triple {10565#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10565#true} is VALID [2022-02-21 04:22:56,866 INFO L290 TraceCheckUtils]: 65: Hoare triple {10565#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10565#true} is VALID [2022-02-21 04:22:56,866 INFO L290 TraceCheckUtils]: 66: Hoare triple {10565#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10565#true} is VALID [2022-02-21 04:22:56,866 INFO L290 TraceCheckUtils]: 67: Hoare triple {10565#true} assume 1 == ~t6_pc~0; {10565#true} is VALID [2022-02-21 04:22:56,867 INFO L290 TraceCheckUtils]: 68: Hoare triple {10565#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,867 INFO L290 TraceCheckUtils]: 69: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,867 INFO L290 TraceCheckUtils]: 70: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,868 INFO L290 TraceCheckUtils]: 71: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,868 INFO L290 TraceCheckUtils]: 72: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,868 INFO L290 TraceCheckUtils]: 73: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,869 INFO L290 TraceCheckUtils]: 74: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,869 INFO L290 TraceCheckUtils]: 75: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,870 INFO L290 TraceCheckUtils]: 76: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,870 INFO L290 TraceCheckUtils]: 77: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,870 INFO L290 TraceCheckUtils]: 78: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,871 INFO L290 TraceCheckUtils]: 79: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,871 INFO L290 TraceCheckUtils]: 80: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,871 INFO L290 TraceCheckUtils]: 81: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,872 INFO L290 TraceCheckUtils]: 82: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,872 INFO L290 TraceCheckUtils]: 83: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,872 INFO L290 TraceCheckUtils]: 84: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,873 INFO L290 TraceCheckUtils]: 85: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t9_pc~0; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,873 INFO L290 TraceCheckUtils]: 86: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,873 INFO L290 TraceCheckUtils]: 87: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,874 INFO L290 TraceCheckUtils]: 88: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,874 INFO L290 TraceCheckUtils]: 89: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,875 INFO L290 TraceCheckUtils]: 90: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,875 INFO L290 TraceCheckUtils]: 91: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,875 INFO L290 TraceCheckUtils]: 92: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,876 INFO L290 TraceCheckUtils]: 93: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,876 INFO L290 TraceCheckUtils]: 94: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,876 INFO L290 TraceCheckUtils]: 95: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,877 INFO L290 TraceCheckUtils]: 96: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,877 INFO L290 TraceCheckUtils]: 97: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,877 INFO L290 TraceCheckUtils]: 98: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,878 INFO L290 TraceCheckUtils]: 99: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,878 INFO L290 TraceCheckUtils]: 100: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,878 INFO L290 TraceCheckUtils]: 101: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,879 INFO L290 TraceCheckUtils]: 102: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,879 INFO L290 TraceCheckUtils]: 103: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,879 INFO L290 TraceCheckUtils]: 104: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,880 INFO L290 TraceCheckUtils]: 105: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,880 INFO L290 TraceCheckUtils]: 106: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {10567#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:56,881 INFO L290 TraceCheckUtils]: 107: Hoare triple {10567#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {10566#false} is VALID [2022-02-21 04:22:56,881 INFO L290 TraceCheckUtils]: 108: Hoare triple {10566#false} assume 1 == ~E_7~0;~E_7~0 := 2; {10566#false} is VALID [2022-02-21 04:22:56,881 INFO L290 TraceCheckUtils]: 109: Hoare triple {10566#false} assume 1 == ~E_8~0;~E_8~0 := 2; {10566#false} is VALID [2022-02-21 04:22:56,881 INFO L290 TraceCheckUtils]: 110: Hoare triple {10566#false} assume 1 == ~E_9~0;~E_9~0 := 2; {10566#false} is VALID [2022-02-21 04:22:56,881 INFO L290 TraceCheckUtils]: 111: Hoare triple {10566#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {10566#false} is VALID [2022-02-21 04:22:56,881 INFO L290 TraceCheckUtils]: 112: Hoare triple {10566#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {10566#false} is VALID [2022-02-21 04:22:56,882 INFO L290 TraceCheckUtils]: 113: Hoare triple {10566#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {10566#false} is VALID [2022-02-21 04:22:56,882 INFO L290 TraceCheckUtils]: 114: Hoare triple {10566#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {10566#false} is VALID [2022-02-21 04:22:56,882 INFO L290 TraceCheckUtils]: 115: Hoare triple {10566#false} assume !(0 == start_simulation_~tmp~3#1); {10566#false} is VALID [2022-02-21 04:22:56,882 INFO L290 TraceCheckUtils]: 116: Hoare triple {10566#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {10566#false} is VALID [2022-02-21 04:22:56,882 INFO L290 TraceCheckUtils]: 117: Hoare triple {10566#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {10566#false} is VALID [2022-02-21 04:22:56,882 INFO L290 TraceCheckUtils]: 118: Hoare triple {10566#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {10566#false} is VALID [2022-02-21 04:22:56,882 INFO L290 TraceCheckUtils]: 119: Hoare triple {10566#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {10566#false} is VALID [2022-02-21 04:22:56,883 INFO L290 TraceCheckUtils]: 120: Hoare triple {10566#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {10566#false} is VALID [2022-02-21 04:22:56,883 INFO L290 TraceCheckUtils]: 121: Hoare triple {10566#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10566#false} is VALID [2022-02-21 04:22:56,883 INFO L290 TraceCheckUtils]: 122: Hoare triple {10566#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {10566#false} is VALID [2022-02-21 04:22:56,883 INFO L290 TraceCheckUtils]: 123: Hoare triple {10566#false} assume !(0 != start_simulation_~tmp___0~1#1); {10566#false} is VALID [2022-02-21 04:22:56,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:56,884 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:56,884 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450657788] [2022-02-21 04:22:56,884 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450657788] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:56,884 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:56,884 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:56,885 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381615215] [2022-02-21 04:22:56,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:56,885 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:56,885 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:56,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:56,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:56,886 INFO L87 Difference]: Start difference. First operand 1170 states and 1741 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:57,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:57,912 INFO L93 Difference]: Finished difference Result 1170 states and 1740 transitions. [2022-02-21 04:22:57,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:57,913 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,003 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:58,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:58,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1740 transitions. [2022-02-21 04:22:58,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:22:58,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:22:58,119 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:58,121 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2022-02-21 04:22:58,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:22:58,136 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:58,139 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1740 transitions. Second operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,142 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1740 transitions. Second operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,145 INFO L87 Difference]: Start difference. First operand 1170 states and 1740 transitions. Second operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:58,195 INFO L93 Difference]: Finished difference Result 1170 states and 1740 transitions. [2022-02-21 04:22:58,195 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,197 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:58,197 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:58,201 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,205 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:58,258 INFO L93 Difference]: Finished difference Result 1170 states and 1740 transitions. [2022-02-21 04:22:58,258 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,260 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:58,260 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:58,260 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:58,260 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:58,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1740 transitions. [2022-02-21 04:22:58,331 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2022-02-21 04:22:58,331 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2022-02-21 04:22:58,331 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:22:58,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1740 transitions. [2022-02-21 04:22:58,336 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:58,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:58,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:58,342 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:58,342 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:58,342 INFO L791 eck$LassoCheckResult]: Stem: 12610#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12560#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12561#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12779#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 12446#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12447#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12756#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12255#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12256#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12682#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12683#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11754#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11755#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11958#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12346#L939 assume !(0 == ~M_E~0); 12590#L939-2 assume !(0 == ~T1_E~0); 12591#L944-1 assume !(0 == ~T2_E~0); 12375#L949-1 assume !(0 == ~T3_E~0); 12373#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12374#L959-1 assume !(0 == ~T5_E~0); 12793#L964-1 assume !(0 == ~T6_E~0); 12106#L969-1 assume !(0 == ~T7_E~0); 12107#L974-1 assume !(0 == ~T8_E~0); 12744#L979-1 assume !(0 == ~T9_E~0); 12745#L984-1 assume !(0 == ~E_M~0); 12267#L989-1 assume !(0 == ~E_1~0); 12268#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12156#L999-1 assume !(0 == ~E_3~0); 12157#L1004-1 assume !(0 == ~E_4~0); 11822#L1009-1 assume !(0 == ~E_5~0); 11823#L1014-1 assume !(0 == ~E_6~0); 12148#L1019-1 assume !(0 == ~E_7~0); 12689#L1024-1 assume !(0 == ~E_8~0); 12079#L1029-1 assume !(0 == ~E_9~0); 12080#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12170#L460 assume 1 == ~m_pc~0; 11738#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11739#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12655#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12894#L1167 assume !(0 != activate_threads_~tmp~1#1); 12363#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12364#L479 assume 1 == ~t1_pc~0; 12347#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12348#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12851#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12091#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 12092#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11940#L498 assume !(1 == ~t2_pc~0); 11941#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12344#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12345#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12722#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12645#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12646#L517 assume 1 == ~t3_pc~0; 12853#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12854#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12418#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12124#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 12125#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12698#L536 assume !(1 == ~t4_pc~0); 12408#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12407#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12784#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12400#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 12401#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12618#L555 assume 1 == ~t5_pc~0; 12619#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12690#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11853#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11854#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 11961#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11861#L574 assume !(1 == ~t6_pc~0); 11862#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12493#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11966#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11967#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 12716#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12878#L593 assume 1 == ~t7_pc~0; 12879#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12098#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12796#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12899#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 12859#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12262#L612 assume !(1 == ~t8_pc~0); 12263#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12672#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12530#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12531#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 12495#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12496#L631 assume 1 == ~t9_pc~0; 12514#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11852#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11820#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11821#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 12350#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12701#L1047 assume !(1 == ~M_E~0); 11790#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11791#L1052-1 assume !(1 == ~T2_E~0); 11773#L1057-1 assume !(1 == ~T3_E~0); 11774#L1062-1 assume !(1 == ~T4_E~0); 12063#L1067-1 assume !(1 == ~T5_E~0); 12366#L1072-1 assume !(1 == ~T6_E~0); 12367#L1077-1 assume !(1 == ~T7_E~0); 11954#L1082-1 assume !(1 == ~T8_E~0); 11955#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11746#L1092-1 assume !(1 == ~E_M~0); 11747#L1097-1 assume !(1 == ~E_1~0); 11775#L1102-1 assume !(1 == ~E_2~0); 12556#L1107-1 assume !(1 == ~E_3~0); 12491#L1112-1 assume !(1 == ~E_4~0); 12492#L1117-1 assume !(1 == ~E_5~0); 12532#L1122-1 assume !(1 == ~E_6~0); 12419#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12173#L1132-1 assume !(1 == ~E_8~0); 12174#L1137-1 assume !(1 == ~E_9~0); 12062#L1142-1 assume { :end_inline_reset_delta_events } true; 11922#L1428-2 [2022-02-21 04:22:58,343 INFO L793 eck$LassoCheckResult]: Loop: 11922#L1428-2 assume !false; 11923#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11997#L914 assume !false; 12487#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12488#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11759#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11760#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12719#L783 assume !(0 != eval_~tmp~0#1); 12159#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12160#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12555#L939-3 assume !(0 == ~M_E~0); 11978#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11979#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11744#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11745#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12381#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11824#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11825#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12031#L974-3 assume !(0 == ~T8_E~0); 12032#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12462#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12463#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12085#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12086#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12597#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11908#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11909#L1014-3 assume !(0 == ~E_6~0); 12448#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12449#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12430#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12382#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12383#L460-33 assume 1 == ~m_pc~0; 12420#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12421#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12177#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11752#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11753#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12113#L479-33 assume !(1 == ~t1_pc~0); 12114#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12081#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12082#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12666#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 12839#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12122#L498-33 assume 1 == ~t2_pc~0; 12123#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11868#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12002#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12003#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11980#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11981#L517-33 assume !(1 == ~t3_pc~0); 12887#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12770#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12771#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12583#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12584#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12209#L536-33 assume 1 == ~t4_pc~0; 12210#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12279#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12280#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12470#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12749#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11799#L555-33 assume !(1 == ~t5_pc~0); 11800#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12525#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12072#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12073#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12552#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11770#L574-33 assume 1 == ~t6_pc~0; 11771#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12761#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12087#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12088#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12341#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11846#L593-33 assume !(1 == ~t7_pc~0); 11847#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12302#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11952#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11953#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12612#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12739#L612-33 assume 1 == ~t8_pc~0; 12866#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12830#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12831#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12673#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11950#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11951#L631-33 assume 1 == ~t9_pc~0; 12791#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11892#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11893#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12147#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12004#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12005#L1047-3 assume !(1 == ~M_E~0); 12178#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12792#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12724#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12725#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11903#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11904#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12286#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12131#L1082-3 assume !(1 == ~T8_E~0); 12132#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12205#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12486#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12416#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12417#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12762#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12126#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12127#L1122-3 assume !(1 == ~E_6~0); 12179#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12180#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12569#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12546#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12009#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11887#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12547#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12304#L1447 assume !(0 == start_simulation_~tmp~3#1); 12305#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12743#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12045#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12570#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 12155#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11912#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11913#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12368#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 11922#L1428-2 [2022-02-21 04:22:58,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:58,344 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2022-02-21 04:22:58,345 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:58,345 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051008723] [2022-02-21 04:22:58,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:58,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:58,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:58,417 INFO L290 TraceCheckUtils]: 0: Hoare triple {15251#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {15251#true} is VALID [2022-02-21 04:22:58,418 INFO L290 TraceCheckUtils]: 1: Hoare triple {15251#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {15253#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:58,418 INFO L290 TraceCheckUtils]: 2: Hoare triple {15253#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {15253#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:58,419 INFO L290 TraceCheckUtils]: 3: Hoare triple {15253#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {15253#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:58,419 INFO L290 TraceCheckUtils]: 4: Hoare triple {15253#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {15253#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:58,419 INFO L290 TraceCheckUtils]: 5: Hoare triple {15253#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {15253#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:58,420 INFO L290 TraceCheckUtils]: 6: Hoare triple {15253#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {15253#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:58,420 INFO L290 TraceCheckUtils]: 7: Hoare triple {15253#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {15253#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:58,420 INFO L290 TraceCheckUtils]: 8: Hoare triple {15253#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 9: Hoare triple {15252#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 10: Hoare triple {15252#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 11: Hoare triple {15252#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 12: Hoare triple {15252#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 13: Hoare triple {15252#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 14: Hoare triple {15252#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 15: Hoare triple {15252#false} assume !(0 == ~M_E~0); {15252#false} is VALID [2022-02-21 04:22:58,421 INFO L290 TraceCheckUtils]: 16: Hoare triple {15252#false} assume !(0 == ~T1_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 17: Hoare triple {15252#false} assume !(0 == ~T2_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 18: Hoare triple {15252#false} assume !(0 == ~T3_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 19: Hoare triple {15252#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 20: Hoare triple {15252#false} assume !(0 == ~T5_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 21: Hoare triple {15252#false} assume !(0 == ~T6_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 22: Hoare triple {15252#false} assume !(0 == ~T7_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 23: Hoare triple {15252#false} assume !(0 == ~T8_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 24: Hoare triple {15252#false} assume !(0 == ~T9_E~0); {15252#false} is VALID [2022-02-21 04:22:58,422 INFO L290 TraceCheckUtils]: 25: Hoare triple {15252#false} assume !(0 == ~E_M~0); {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 26: Hoare triple {15252#false} assume !(0 == ~E_1~0); {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 27: Hoare triple {15252#false} assume 0 == ~E_2~0;~E_2~0 := 1; {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 28: Hoare triple {15252#false} assume !(0 == ~E_3~0); {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 29: Hoare triple {15252#false} assume !(0 == ~E_4~0); {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 30: Hoare triple {15252#false} assume !(0 == ~E_5~0); {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 31: Hoare triple {15252#false} assume !(0 == ~E_6~0); {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 32: Hoare triple {15252#false} assume !(0 == ~E_7~0); {15252#false} is VALID [2022-02-21 04:22:58,423 INFO L290 TraceCheckUtils]: 33: Hoare triple {15252#false} assume !(0 == ~E_8~0); {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 34: Hoare triple {15252#false} assume !(0 == ~E_9~0); {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 35: Hoare triple {15252#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 36: Hoare triple {15252#false} assume 1 == ~m_pc~0; {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 37: Hoare triple {15252#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 38: Hoare triple {15252#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 39: Hoare triple {15252#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 40: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp~1#1); {15252#false} is VALID [2022-02-21 04:22:58,424 INFO L290 TraceCheckUtils]: 41: Hoare triple {15252#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15252#false} is VALID [2022-02-21 04:22:58,425 INFO L290 TraceCheckUtils]: 42: Hoare triple {15252#false} assume 1 == ~t1_pc~0; {15252#false} is VALID [2022-02-21 04:22:58,425 INFO L290 TraceCheckUtils]: 43: Hoare triple {15252#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {15252#false} is VALID [2022-02-21 04:22:58,425 INFO L290 TraceCheckUtils]: 44: Hoare triple {15252#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15252#false} is VALID [2022-02-21 04:22:58,425 INFO L290 TraceCheckUtils]: 45: Hoare triple {15252#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {15252#false} is VALID [2022-02-21 04:22:58,426 INFO L290 TraceCheckUtils]: 46: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___0~0#1); {15252#false} is VALID [2022-02-21 04:22:58,426 INFO L290 TraceCheckUtils]: 47: Hoare triple {15252#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15252#false} is VALID [2022-02-21 04:22:58,427 INFO L290 TraceCheckUtils]: 48: Hoare triple {15252#false} assume !(1 == ~t2_pc~0); {15252#false} is VALID [2022-02-21 04:22:58,429 INFO L290 TraceCheckUtils]: 49: Hoare triple {15252#false} is_transmit2_triggered_~__retres1~2#1 := 0; {15252#false} is VALID [2022-02-21 04:22:58,430 INFO L290 TraceCheckUtils]: 50: Hoare triple {15252#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15252#false} is VALID [2022-02-21 04:22:58,430 INFO L290 TraceCheckUtils]: 51: Hoare triple {15252#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15252#false} is VALID [2022-02-21 04:22:58,430 INFO L290 TraceCheckUtils]: 52: Hoare triple {15252#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {15252#false} is VALID [2022-02-21 04:22:58,430 INFO L290 TraceCheckUtils]: 53: Hoare triple {15252#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15252#false} is VALID [2022-02-21 04:22:58,430 INFO L290 TraceCheckUtils]: 54: Hoare triple {15252#false} assume 1 == ~t3_pc~0; {15252#false} is VALID [2022-02-21 04:22:58,430 INFO L290 TraceCheckUtils]: 55: Hoare triple {15252#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {15252#false} is VALID [2022-02-21 04:22:58,430 INFO L290 TraceCheckUtils]: 56: Hoare triple {15252#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 57: Hoare triple {15252#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 58: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___2~0#1); {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 59: Hoare triple {15252#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 60: Hoare triple {15252#false} assume !(1 == ~t4_pc~0); {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 61: Hoare triple {15252#false} is_transmit4_triggered_~__retres1~4#1 := 0; {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 62: Hoare triple {15252#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 63: Hoare triple {15252#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 64: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___3~0#1); {15252#false} is VALID [2022-02-21 04:22:58,431 INFO L290 TraceCheckUtils]: 65: Hoare triple {15252#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 66: Hoare triple {15252#false} assume 1 == ~t5_pc~0; {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 67: Hoare triple {15252#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 68: Hoare triple {15252#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 69: Hoare triple {15252#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 70: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___4~0#1); {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 71: Hoare triple {15252#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 72: Hoare triple {15252#false} assume !(1 == ~t6_pc~0); {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 73: Hoare triple {15252#false} is_transmit6_triggered_~__retres1~6#1 := 0; {15252#false} is VALID [2022-02-21 04:22:58,432 INFO L290 TraceCheckUtils]: 74: Hoare triple {15252#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 75: Hoare triple {15252#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 76: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___5~0#1); {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 77: Hoare triple {15252#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 78: Hoare triple {15252#false} assume 1 == ~t7_pc~0; {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 79: Hoare triple {15252#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 80: Hoare triple {15252#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 81: Hoare triple {15252#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 82: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___6~0#1); {15252#false} is VALID [2022-02-21 04:22:58,433 INFO L290 TraceCheckUtils]: 83: Hoare triple {15252#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 84: Hoare triple {15252#false} assume !(1 == ~t8_pc~0); {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 85: Hoare triple {15252#false} is_transmit8_triggered_~__retres1~8#1 := 0; {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 86: Hoare triple {15252#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 87: Hoare triple {15252#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 88: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___7~0#1); {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 89: Hoare triple {15252#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 90: Hoare triple {15252#false} assume 1 == ~t9_pc~0; {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 91: Hoare triple {15252#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {15252#false} is VALID [2022-02-21 04:22:58,434 INFO L290 TraceCheckUtils]: 92: Hoare triple {15252#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {15252#false} is VALID [2022-02-21 04:22:58,435 INFO L290 TraceCheckUtils]: 93: Hoare triple {15252#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {15252#false} is VALID [2022-02-21 04:22:58,435 INFO L290 TraceCheckUtils]: 94: Hoare triple {15252#false} assume !(0 != activate_threads_~tmp___8~0#1); {15252#false} is VALID [2022-02-21 04:22:58,435 INFO L290 TraceCheckUtils]: 95: Hoare triple {15252#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15252#false} is VALID [2022-02-21 04:22:58,435 INFO L290 TraceCheckUtils]: 96: Hoare triple {15252#false} assume !(1 == ~M_E~0); {15252#false} is VALID [2022-02-21 04:22:58,435 INFO L290 TraceCheckUtils]: 97: Hoare triple {15252#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,435 INFO L290 TraceCheckUtils]: 98: Hoare triple {15252#false} assume !(1 == ~T2_E~0); {15252#false} is VALID [2022-02-21 04:22:58,435 INFO L290 TraceCheckUtils]: 99: Hoare triple {15252#false} assume !(1 == ~T3_E~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 100: Hoare triple {15252#false} assume !(1 == ~T4_E~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 101: Hoare triple {15252#false} assume !(1 == ~T5_E~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 102: Hoare triple {15252#false} assume !(1 == ~T6_E~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 103: Hoare triple {15252#false} assume !(1 == ~T7_E~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 104: Hoare triple {15252#false} assume !(1 == ~T8_E~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 105: Hoare triple {15252#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 106: Hoare triple {15252#false} assume !(1 == ~E_M~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 107: Hoare triple {15252#false} assume !(1 == ~E_1~0); {15252#false} is VALID [2022-02-21 04:22:58,436 INFO L290 TraceCheckUtils]: 108: Hoare triple {15252#false} assume !(1 == ~E_2~0); {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 109: Hoare triple {15252#false} assume !(1 == ~E_3~0); {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 110: Hoare triple {15252#false} assume !(1 == ~E_4~0); {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 111: Hoare triple {15252#false} assume !(1 == ~E_5~0); {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 112: Hoare triple {15252#false} assume !(1 == ~E_6~0); {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 113: Hoare triple {15252#false} assume 1 == ~E_7~0;~E_7~0 := 2; {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 114: Hoare triple {15252#false} assume !(1 == ~E_8~0); {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 115: Hoare triple {15252#false} assume !(1 == ~E_9~0); {15252#false} is VALID [2022-02-21 04:22:58,437 INFO L290 TraceCheckUtils]: 116: Hoare triple {15252#false} assume { :end_inline_reset_delta_events } true; {15252#false} is VALID [2022-02-21 04:22:58,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:58,438 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:58,438 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051008723] [2022-02-21 04:22:58,439 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051008723] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:58,439 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:58,439 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:58,439 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6120126] [2022-02-21 04:22:58,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:58,440 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:58,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:58,441 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 3 times [2022-02-21 04:22:58,441 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:58,444 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619630887] [2022-02-21 04:22:58,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:58,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:58,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:58,508 INFO L290 TraceCheckUtils]: 0: Hoare triple {15254#true} assume !false; {15254#true} is VALID [2022-02-21 04:22:58,508 INFO L290 TraceCheckUtils]: 1: Hoare triple {15254#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {15254#true} is VALID [2022-02-21 04:22:58,508 INFO L290 TraceCheckUtils]: 2: Hoare triple {15254#true} assume !false; {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 3: Hoare triple {15254#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 4: Hoare triple {15254#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 5: Hoare triple {15254#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 6: Hoare triple {15254#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 7: Hoare triple {15254#true} assume !(0 != eval_~tmp~0#1); {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 8: Hoare triple {15254#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 9: Hoare triple {15254#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 10: Hoare triple {15254#true} assume !(0 == ~M_E~0); {15254#true} is VALID [2022-02-21 04:22:58,509 INFO L290 TraceCheckUtils]: 11: Hoare triple {15254#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 12: Hoare triple {15254#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 13: Hoare triple {15254#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 14: Hoare triple {15254#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 15: Hoare triple {15254#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 16: Hoare triple {15254#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 17: Hoare triple {15254#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 18: Hoare triple {15254#true} assume !(0 == ~T8_E~0); {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 19: Hoare triple {15254#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,510 INFO L290 TraceCheckUtils]: 20: Hoare triple {15254#true} assume 0 == ~E_M~0;~E_M~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 21: Hoare triple {15254#true} assume 0 == ~E_1~0;~E_1~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 22: Hoare triple {15254#true} assume 0 == ~E_2~0;~E_2~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 23: Hoare triple {15254#true} assume 0 == ~E_3~0;~E_3~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 24: Hoare triple {15254#true} assume 0 == ~E_4~0;~E_4~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 25: Hoare triple {15254#true} assume 0 == ~E_5~0;~E_5~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 26: Hoare triple {15254#true} assume !(0 == ~E_6~0); {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 27: Hoare triple {15254#true} assume 0 == ~E_7~0;~E_7~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 28: Hoare triple {15254#true} assume 0 == ~E_8~0;~E_8~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,511 INFO L290 TraceCheckUtils]: 29: Hoare triple {15254#true} assume 0 == ~E_9~0;~E_9~0 := 1; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 30: Hoare triple {15254#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 31: Hoare triple {15254#true} assume 1 == ~m_pc~0; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 32: Hoare triple {15254#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 33: Hoare triple {15254#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 34: Hoare triple {15254#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 35: Hoare triple {15254#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 36: Hoare triple {15254#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 37: Hoare triple {15254#true} assume !(1 == ~t1_pc~0); {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 38: Hoare triple {15254#true} is_transmit1_triggered_~__retres1~1#1 := 0; {15254#true} is VALID [2022-02-21 04:22:58,512 INFO L290 TraceCheckUtils]: 39: Hoare triple {15254#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 40: Hoare triple {15254#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 41: Hoare triple {15254#true} assume !(0 != activate_threads_~tmp___0~0#1); {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 42: Hoare triple {15254#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 43: Hoare triple {15254#true} assume 1 == ~t2_pc~0; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 44: Hoare triple {15254#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 45: Hoare triple {15254#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 46: Hoare triple {15254#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 47: Hoare triple {15254#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {15254#true} is VALID [2022-02-21 04:22:58,513 INFO L290 TraceCheckUtils]: 48: Hoare triple {15254#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 49: Hoare triple {15254#true} assume !(1 == ~t3_pc~0); {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 50: Hoare triple {15254#true} is_transmit3_triggered_~__retres1~3#1 := 0; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 51: Hoare triple {15254#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 52: Hoare triple {15254#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 53: Hoare triple {15254#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 54: Hoare triple {15254#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 55: Hoare triple {15254#true} assume 1 == ~t4_pc~0; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 56: Hoare triple {15254#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {15254#true} is VALID [2022-02-21 04:22:58,514 INFO L290 TraceCheckUtils]: 57: Hoare triple {15254#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 58: Hoare triple {15254#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 59: Hoare triple {15254#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 60: Hoare triple {15254#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 61: Hoare triple {15254#true} assume !(1 == ~t5_pc~0); {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 62: Hoare triple {15254#true} is_transmit5_triggered_~__retres1~5#1 := 0; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 63: Hoare triple {15254#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 64: Hoare triple {15254#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 65: Hoare triple {15254#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {15254#true} is VALID [2022-02-21 04:22:58,515 INFO L290 TraceCheckUtils]: 66: Hoare triple {15254#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15254#true} is VALID [2022-02-21 04:22:58,516 INFO L290 TraceCheckUtils]: 67: Hoare triple {15254#true} assume 1 == ~t6_pc~0; {15254#true} is VALID [2022-02-21 04:22:58,516 INFO L290 TraceCheckUtils]: 68: Hoare triple {15254#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,516 INFO L290 TraceCheckUtils]: 69: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,517 INFO L290 TraceCheckUtils]: 70: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,517 INFO L290 TraceCheckUtils]: 71: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,517 INFO L290 TraceCheckUtils]: 72: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,518 INFO L290 TraceCheckUtils]: 73: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,518 INFO L290 TraceCheckUtils]: 74: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,518 INFO L290 TraceCheckUtils]: 75: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,519 INFO L290 TraceCheckUtils]: 76: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,519 INFO L290 TraceCheckUtils]: 77: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,519 INFO L290 TraceCheckUtils]: 78: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,520 INFO L290 TraceCheckUtils]: 79: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,520 INFO L290 TraceCheckUtils]: 80: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,520 INFO L290 TraceCheckUtils]: 81: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,521 INFO L290 TraceCheckUtils]: 82: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,521 INFO L290 TraceCheckUtils]: 83: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,521 INFO L290 TraceCheckUtils]: 84: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,522 INFO L290 TraceCheckUtils]: 85: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t9_pc~0; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,522 INFO L290 TraceCheckUtils]: 86: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,522 INFO L290 TraceCheckUtils]: 87: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,523 INFO L290 TraceCheckUtils]: 88: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,523 INFO L290 TraceCheckUtils]: 89: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,523 INFO L290 TraceCheckUtils]: 90: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,524 INFO L290 TraceCheckUtils]: 91: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,524 INFO L290 TraceCheckUtils]: 92: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,524 INFO L290 TraceCheckUtils]: 93: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,524 INFO L290 TraceCheckUtils]: 94: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,525 INFO L290 TraceCheckUtils]: 95: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,525 INFO L290 TraceCheckUtils]: 96: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,525 INFO L290 TraceCheckUtils]: 97: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,526 INFO L290 TraceCheckUtils]: 98: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,526 INFO L290 TraceCheckUtils]: 99: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,526 INFO L290 TraceCheckUtils]: 100: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,527 INFO L290 TraceCheckUtils]: 101: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,527 INFO L290 TraceCheckUtils]: 102: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,527 INFO L290 TraceCheckUtils]: 103: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,528 INFO L290 TraceCheckUtils]: 104: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,528 INFO L290 TraceCheckUtils]: 105: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,528 INFO L290 TraceCheckUtils]: 106: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {15256#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 107: Hoare triple {15256#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {15255#false} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 108: Hoare triple {15255#false} assume 1 == ~E_7~0;~E_7~0 := 2; {15255#false} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 109: Hoare triple {15255#false} assume 1 == ~E_8~0;~E_8~0 := 2; {15255#false} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 110: Hoare triple {15255#false} assume 1 == ~E_9~0;~E_9~0 := 2; {15255#false} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 111: Hoare triple {15255#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {15255#false} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 112: Hoare triple {15255#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {15255#false} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 113: Hoare triple {15255#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {15255#false} is VALID [2022-02-21 04:22:58,529 INFO L290 TraceCheckUtils]: 114: Hoare triple {15255#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 115: Hoare triple {15255#false} assume !(0 == start_simulation_~tmp~3#1); {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 116: Hoare triple {15255#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 117: Hoare triple {15255#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 118: Hoare triple {15255#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 119: Hoare triple {15255#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 120: Hoare triple {15255#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 121: Hoare triple {15255#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {15255#false} is VALID [2022-02-21 04:22:58,530 INFO L290 TraceCheckUtils]: 122: Hoare triple {15255#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {15255#false} is VALID [2022-02-21 04:22:58,531 INFO L290 TraceCheckUtils]: 123: Hoare triple {15255#false} assume !(0 != start_simulation_~tmp___0~1#1); {15255#false} is VALID [2022-02-21 04:22:58,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:58,532 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:58,532 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619630887] [2022-02-21 04:22:58,532 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619630887] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:58,532 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:58,532 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:58,532 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896820400] [2022-02-21 04:22:58,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:58,533 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:58,533 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:58,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:58,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:58,534 INFO L87 Difference]: Start difference. First operand 1170 states and 1740 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:59,572 INFO L93 Difference]: Finished difference Result 1170 states and 1739 transitions. [2022-02-21 04:22:59,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:59,572 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,655 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:59,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:59,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1739 transitions. [2022-02-21 04:22:59,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:22:59,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:22:59,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:59,774 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2022-02-21 04:22:59,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:22:59,799 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:59,802 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1739 transitions. Second operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,804 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1739 transitions. Second operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,806 INFO L87 Difference]: Start difference. First operand 1170 states and 1739 transitions. Second operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:59,856 INFO L93 Difference]: Finished difference Result 1170 states and 1739 transitions. [2022-02-21 04:22:59,856 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,858 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:59,858 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:59,860 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,862 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:59,914 INFO L93 Difference]: Finished difference Result 1170 states and 1739 transitions. [2022-02-21 04:22:59,914 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,916 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:59,916 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:59,916 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:59,917 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:59,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1739 transitions. [2022-02-21 04:22:59,971 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2022-02-21 04:22:59,971 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2022-02-21 04:22:59,971 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:22:59,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1739 transitions. [2022-02-21 04:22:59,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:22:59,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:59,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:59,978 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:59,979 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:59,979 INFO L791 eck$LassoCheckResult]: Stem: 17299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17249#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17250#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17468#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 17135#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17136#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17445#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16944#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16945#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17373#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17374#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16443#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16444#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16647#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17035#L939 assume !(0 == ~M_E~0); 17279#L939-2 assume !(0 == ~T1_E~0); 17280#L944-1 assume !(0 == ~T2_E~0); 17064#L949-1 assume !(0 == ~T3_E~0); 17062#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17063#L959-1 assume !(0 == ~T5_E~0); 17482#L964-1 assume !(0 == ~T6_E~0); 16795#L969-1 assume !(0 == ~T7_E~0); 16796#L974-1 assume !(0 == ~T8_E~0); 17433#L979-1 assume !(0 == ~T9_E~0); 17434#L984-1 assume !(0 == ~E_M~0); 16956#L989-1 assume !(0 == ~E_1~0); 16957#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16845#L999-1 assume !(0 == ~E_3~0); 16846#L1004-1 assume !(0 == ~E_4~0); 16511#L1009-1 assume !(0 == ~E_5~0); 16512#L1014-1 assume !(0 == ~E_6~0); 16837#L1019-1 assume !(0 == ~E_7~0); 17378#L1024-1 assume !(0 == ~E_8~0); 16768#L1029-1 assume !(0 == ~E_9~0); 16769#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16859#L460 assume 1 == ~m_pc~0; 16427#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16428#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17344#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17583#L1167 assume !(0 != activate_threads_~tmp~1#1); 17052#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17053#L479 assume 1 == ~t1_pc~0; 17036#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17037#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17540#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16780#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 16781#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16629#L498 assume !(1 == ~t2_pc~0); 16630#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17033#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17034#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17411#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17334#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17335#L517 assume 1 == ~t3_pc~0; 17542#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17543#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17107#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16813#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 16814#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17387#L536 assume !(1 == ~t4_pc~0); 17097#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17096#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17473#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17089#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 17090#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17307#L555 assume 1 == ~t5_pc~0; 17308#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17379#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16542#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16543#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 16650#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16550#L574 assume !(1 == ~t6_pc~0); 16551#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17182#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16655#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16656#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 17405#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17567#L593 assume 1 == ~t7_pc~0; 17568#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16787#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17485#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17588#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 17548#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16951#L612 assume !(1 == ~t8_pc~0); 16952#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17361#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17219#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17220#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 17184#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17185#L631 assume 1 == ~t9_pc~0; 17203#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16541#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16509#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16510#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 17039#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17390#L1047 assume !(1 == ~M_E~0); 16479#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16480#L1052-1 assume !(1 == ~T2_E~0); 16462#L1057-1 assume !(1 == ~T3_E~0); 16463#L1062-1 assume !(1 == ~T4_E~0); 16752#L1067-1 assume !(1 == ~T5_E~0); 17055#L1072-1 assume !(1 == ~T6_E~0); 17056#L1077-1 assume !(1 == ~T7_E~0); 16643#L1082-1 assume !(1 == ~T8_E~0); 16644#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16435#L1092-1 assume !(1 == ~E_M~0); 16436#L1097-1 assume !(1 == ~E_1~0); 16464#L1102-1 assume !(1 == ~E_2~0); 17245#L1107-1 assume !(1 == ~E_3~0); 17180#L1112-1 assume !(1 == ~E_4~0); 17181#L1117-1 assume !(1 == ~E_5~0); 17221#L1122-1 assume !(1 == ~E_6~0); 17108#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16862#L1132-1 assume !(1 == ~E_8~0); 16863#L1137-1 assume !(1 == ~E_9~0); 16751#L1142-1 assume { :end_inline_reset_delta_events } true; 16611#L1428-2 [2022-02-21 04:22:59,979 INFO L793 eck$LassoCheckResult]: Loop: 16611#L1428-2 assume !false; 16612#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16686#L914 assume !false; 17176#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17177#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16448#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16449#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17408#L783 assume !(0 != eval_~tmp~0#1); 16848#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16849#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17244#L939-3 assume !(0 == ~M_E~0); 16667#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16668#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16433#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16434#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17070#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16513#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16514#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16720#L974-3 assume !(0 == ~T8_E~0); 16721#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17151#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17152#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16774#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16775#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17286#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16597#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16598#L1014-3 assume !(0 == ~E_6~0); 17137#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17138#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17119#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17071#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17072#L460-33 assume 1 == ~m_pc~0; 17109#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17110#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16866#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16441#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16442#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16803#L479-33 assume !(1 == ~t1_pc~0); 16804#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16770#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16771#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17355#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 17528#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16811#L498-33 assume 1 == ~t2_pc~0; 16812#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16557#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16691#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16692#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16669#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16670#L517-33 assume !(1 == ~t3_pc~0); 17576#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17459#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17460#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17272#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17273#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16898#L536-33 assume 1 == ~t4_pc~0; 16899#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16968#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16969#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17159#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17438#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16488#L555-33 assume !(1 == ~t5_pc~0); 16489#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 17214#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16761#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16762#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17241#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16459#L574-33 assume 1 == ~t6_pc~0; 16460#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17450#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16776#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16777#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17030#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16535#L593-33 assume !(1 == ~t7_pc~0); 16536#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 16992#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16641#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16642#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17301#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17428#L612-33 assume 1 == ~t8_pc~0; 17555#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17519#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17520#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17362#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16639#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16640#L631-33 assume !(1 == ~t9_pc~0); 17248#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 16581#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16582#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16836#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16693#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16694#L1047-3 assume !(1 == ~M_E~0); 16867#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17481#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17413#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17414#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16592#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16593#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16975#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16820#L1082-3 assume !(1 == ~T8_E~0); 16821#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16894#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17175#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17105#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17106#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17451#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16815#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16816#L1122-3 assume !(1 == ~E_6~0); 16868#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16869#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17258#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17235#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16698#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16576#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17236#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 16993#L1447 assume !(0 == start_simulation_~tmp~3#1); 16994#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17432#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16734#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17259#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 16844#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16601#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16602#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17057#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 16611#L1428-2 [2022-02-21 04:22:59,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:59,980 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2022-02-21 04:22:59,980 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:59,980 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596740942] [2022-02-21 04:22:59,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:59,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:59,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:00,012 INFO L290 TraceCheckUtils]: 0: Hoare triple {19940#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {19940#true} is VALID [2022-02-21 04:23:00,012 INFO L290 TraceCheckUtils]: 1: Hoare triple {19940#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,013 INFO L290 TraceCheckUtils]: 2: Hoare triple {19942#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,013 INFO L290 TraceCheckUtils]: 3: Hoare triple {19942#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,013 INFO L290 TraceCheckUtils]: 4: Hoare triple {19942#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,014 INFO L290 TraceCheckUtils]: 5: Hoare triple {19942#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,014 INFO L290 TraceCheckUtils]: 6: Hoare triple {19942#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,014 INFO L290 TraceCheckUtils]: 7: Hoare triple {19942#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,015 INFO L290 TraceCheckUtils]: 8: Hoare triple {19942#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {19942#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:00,015 INFO L290 TraceCheckUtils]: 9: Hoare triple {19942#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {19941#false} is VALID [2022-02-21 04:23:00,015 INFO L290 TraceCheckUtils]: 10: Hoare triple {19941#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {19941#false} is VALID [2022-02-21 04:23:00,015 INFO L290 TraceCheckUtils]: 11: Hoare triple {19941#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {19941#false} is VALID [2022-02-21 04:23:00,015 INFO L290 TraceCheckUtils]: 12: Hoare triple {19941#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {19941#false} is VALID [2022-02-21 04:23:00,016 INFO L290 TraceCheckUtils]: 13: Hoare triple {19941#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {19941#false} is VALID [2022-02-21 04:23:00,016 INFO L290 TraceCheckUtils]: 14: Hoare triple {19941#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {19941#false} is VALID [2022-02-21 04:23:00,016 INFO L290 TraceCheckUtils]: 15: Hoare triple {19941#false} assume !(0 == ~M_E~0); {19941#false} is VALID [2022-02-21 04:23:00,016 INFO L290 TraceCheckUtils]: 16: Hoare triple {19941#false} assume !(0 == ~T1_E~0); {19941#false} is VALID [2022-02-21 04:23:00,016 INFO L290 TraceCheckUtils]: 17: Hoare triple {19941#false} assume !(0 == ~T2_E~0); {19941#false} is VALID [2022-02-21 04:23:00,016 INFO L290 TraceCheckUtils]: 18: Hoare triple {19941#false} assume !(0 == ~T3_E~0); {19941#false} is VALID [2022-02-21 04:23:00,016 INFO L290 TraceCheckUtils]: 19: Hoare triple {19941#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 20: Hoare triple {19941#false} assume !(0 == ~T5_E~0); {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 21: Hoare triple {19941#false} assume !(0 == ~T6_E~0); {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 22: Hoare triple {19941#false} assume !(0 == ~T7_E~0); {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 23: Hoare triple {19941#false} assume !(0 == ~T8_E~0); {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 24: Hoare triple {19941#false} assume !(0 == ~T9_E~0); {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 25: Hoare triple {19941#false} assume !(0 == ~E_M~0); {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 26: Hoare triple {19941#false} assume !(0 == ~E_1~0); {19941#false} is VALID [2022-02-21 04:23:00,017 INFO L290 TraceCheckUtils]: 27: Hoare triple {19941#false} assume 0 == ~E_2~0;~E_2~0 := 1; {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 28: Hoare triple {19941#false} assume !(0 == ~E_3~0); {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 29: Hoare triple {19941#false} assume !(0 == ~E_4~0); {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 30: Hoare triple {19941#false} assume !(0 == ~E_5~0); {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 31: Hoare triple {19941#false} assume !(0 == ~E_6~0); {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 32: Hoare triple {19941#false} assume !(0 == ~E_7~0); {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 33: Hoare triple {19941#false} assume !(0 == ~E_8~0); {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 34: Hoare triple {19941#false} assume !(0 == ~E_9~0); {19941#false} is VALID [2022-02-21 04:23:00,018 INFO L290 TraceCheckUtils]: 35: Hoare triple {19941#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 36: Hoare triple {19941#false} assume 1 == ~m_pc~0; {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 37: Hoare triple {19941#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 38: Hoare triple {19941#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 39: Hoare triple {19941#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 40: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp~1#1); {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 41: Hoare triple {19941#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 42: Hoare triple {19941#false} assume 1 == ~t1_pc~0; {19941#false} is VALID [2022-02-21 04:23:00,019 INFO L290 TraceCheckUtils]: 43: Hoare triple {19941#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 44: Hoare triple {19941#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 45: Hoare triple {19941#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 46: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___0~0#1); {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 47: Hoare triple {19941#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 48: Hoare triple {19941#false} assume !(1 == ~t2_pc~0); {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 49: Hoare triple {19941#false} is_transmit2_triggered_~__retres1~2#1 := 0; {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 50: Hoare triple {19941#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {19941#false} is VALID [2022-02-21 04:23:00,020 INFO L290 TraceCheckUtils]: 51: Hoare triple {19941#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {19941#false} is VALID [2022-02-21 04:23:00,021 INFO L290 TraceCheckUtils]: 52: Hoare triple {19941#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {19941#false} is VALID [2022-02-21 04:23:00,021 INFO L290 TraceCheckUtils]: 53: Hoare triple {19941#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {19941#false} is VALID [2022-02-21 04:23:00,021 INFO L290 TraceCheckUtils]: 54: Hoare triple {19941#false} assume 1 == ~t3_pc~0; {19941#false} is VALID [2022-02-21 04:23:00,021 INFO L290 TraceCheckUtils]: 55: Hoare triple {19941#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {19941#false} is VALID [2022-02-21 04:23:00,021 INFO L290 TraceCheckUtils]: 56: Hoare triple {19941#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {19941#false} is VALID [2022-02-21 04:23:00,021 INFO L290 TraceCheckUtils]: 57: Hoare triple {19941#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {19941#false} is VALID [2022-02-21 04:23:00,021 INFO L290 TraceCheckUtils]: 58: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___2~0#1); {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 59: Hoare triple {19941#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 60: Hoare triple {19941#false} assume !(1 == ~t4_pc~0); {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 61: Hoare triple {19941#false} is_transmit4_triggered_~__retres1~4#1 := 0; {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 62: Hoare triple {19941#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 63: Hoare triple {19941#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 64: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___3~0#1); {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 65: Hoare triple {19941#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {19941#false} is VALID [2022-02-21 04:23:00,022 INFO L290 TraceCheckUtils]: 66: Hoare triple {19941#false} assume 1 == ~t5_pc~0; {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 67: Hoare triple {19941#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 68: Hoare triple {19941#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 69: Hoare triple {19941#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 70: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___4~0#1); {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 71: Hoare triple {19941#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 72: Hoare triple {19941#false} assume !(1 == ~t6_pc~0); {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 73: Hoare triple {19941#false} is_transmit6_triggered_~__retres1~6#1 := 0; {19941#false} is VALID [2022-02-21 04:23:00,023 INFO L290 TraceCheckUtils]: 74: Hoare triple {19941#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 75: Hoare triple {19941#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 76: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___5~0#1); {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 77: Hoare triple {19941#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 78: Hoare triple {19941#false} assume 1 == ~t7_pc~0; {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 79: Hoare triple {19941#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 80: Hoare triple {19941#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 81: Hoare triple {19941#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {19941#false} is VALID [2022-02-21 04:23:00,024 INFO L290 TraceCheckUtils]: 82: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___6~0#1); {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 83: Hoare triple {19941#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 84: Hoare triple {19941#false} assume !(1 == ~t8_pc~0); {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 85: Hoare triple {19941#false} is_transmit8_triggered_~__retres1~8#1 := 0; {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 86: Hoare triple {19941#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 87: Hoare triple {19941#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 88: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___7~0#1); {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 89: Hoare triple {19941#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {19941#false} is VALID [2022-02-21 04:23:00,025 INFO L290 TraceCheckUtils]: 90: Hoare triple {19941#false} assume 1 == ~t9_pc~0; {19941#false} is VALID [2022-02-21 04:23:00,026 INFO L290 TraceCheckUtils]: 91: Hoare triple {19941#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {19941#false} is VALID [2022-02-21 04:23:00,026 INFO L290 TraceCheckUtils]: 92: Hoare triple {19941#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {19941#false} is VALID [2022-02-21 04:23:00,026 INFO L290 TraceCheckUtils]: 93: Hoare triple {19941#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {19941#false} is VALID [2022-02-21 04:23:00,026 INFO L290 TraceCheckUtils]: 94: Hoare triple {19941#false} assume !(0 != activate_threads_~tmp___8~0#1); {19941#false} is VALID [2022-02-21 04:23:00,026 INFO L290 TraceCheckUtils]: 95: Hoare triple {19941#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19941#false} is VALID [2022-02-21 04:23:00,026 INFO L290 TraceCheckUtils]: 96: Hoare triple {19941#false} assume !(1 == ~M_E~0); {19941#false} is VALID [2022-02-21 04:23:00,026 INFO L290 TraceCheckUtils]: 97: Hoare triple {19941#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 98: Hoare triple {19941#false} assume !(1 == ~T2_E~0); {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 99: Hoare triple {19941#false} assume !(1 == ~T3_E~0); {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 100: Hoare triple {19941#false} assume !(1 == ~T4_E~0); {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 101: Hoare triple {19941#false} assume !(1 == ~T5_E~0); {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 102: Hoare triple {19941#false} assume !(1 == ~T6_E~0); {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 103: Hoare triple {19941#false} assume !(1 == ~T7_E~0); {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 104: Hoare triple {19941#false} assume !(1 == ~T8_E~0); {19941#false} is VALID [2022-02-21 04:23:00,027 INFO L290 TraceCheckUtils]: 105: Hoare triple {19941#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 106: Hoare triple {19941#false} assume !(1 == ~E_M~0); {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 107: Hoare triple {19941#false} assume !(1 == ~E_1~0); {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 108: Hoare triple {19941#false} assume !(1 == ~E_2~0); {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 109: Hoare triple {19941#false} assume !(1 == ~E_3~0); {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 110: Hoare triple {19941#false} assume !(1 == ~E_4~0); {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 111: Hoare triple {19941#false} assume !(1 == ~E_5~0); {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 112: Hoare triple {19941#false} assume !(1 == ~E_6~0); {19941#false} is VALID [2022-02-21 04:23:00,028 INFO L290 TraceCheckUtils]: 113: Hoare triple {19941#false} assume 1 == ~E_7~0;~E_7~0 := 2; {19941#false} is VALID [2022-02-21 04:23:00,029 INFO L290 TraceCheckUtils]: 114: Hoare triple {19941#false} assume !(1 == ~E_8~0); {19941#false} is VALID [2022-02-21 04:23:00,029 INFO L290 TraceCheckUtils]: 115: Hoare triple {19941#false} assume !(1 == ~E_9~0); {19941#false} is VALID [2022-02-21 04:23:00,029 INFO L290 TraceCheckUtils]: 116: Hoare triple {19941#false} assume { :end_inline_reset_delta_events } true; {19941#false} is VALID [2022-02-21 04:23:00,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:00,029 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:00,030 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596740942] [2022-02-21 04:23:00,030 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [596740942] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:00,030 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:00,030 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:00,030 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876374110] [2022-02-21 04:23:00,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:00,031 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:00,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:00,031 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 1 times [2022-02-21 04:23:00,031 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:00,031 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1349025779] [2022-02-21 04:23:00,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:00,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:00,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:00,074 INFO L290 TraceCheckUtils]: 0: Hoare triple {19943#true} assume !false; {19943#true} is VALID [2022-02-21 04:23:00,074 INFO L290 TraceCheckUtils]: 1: Hoare triple {19943#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {19943#true} is VALID [2022-02-21 04:23:00,074 INFO L290 TraceCheckUtils]: 2: Hoare triple {19943#true} assume !false; {19943#true} is VALID [2022-02-21 04:23:00,075 INFO L290 TraceCheckUtils]: 3: Hoare triple {19943#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {19943#true} is VALID [2022-02-21 04:23:00,075 INFO L290 TraceCheckUtils]: 4: Hoare triple {19943#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {19943#true} is VALID [2022-02-21 04:23:00,075 INFO L290 TraceCheckUtils]: 5: Hoare triple {19943#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {19943#true} is VALID [2022-02-21 04:23:00,075 INFO L290 TraceCheckUtils]: 6: Hoare triple {19943#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {19943#true} is VALID [2022-02-21 04:23:00,075 INFO L290 TraceCheckUtils]: 7: Hoare triple {19943#true} assume !(0 != eval_~tmp~0#1); {19943#true} is VALID [2022-02-21 04:23:00,075 INFO L290 TraceCheckUtils]: 8: Hoare triple {19943#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {19943#true} is VALID [2022-02-21 04:23:00,075 INFO L290 TraceCheckUtils]: 9: Hoare triple {19943#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 10: Hoare triple {19943#true} assume !(0 == ~M_E~0); {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 11: Hoare triple {19943#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 12: Hoare triple {19943#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 13: Hoare triple {19943#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 14: Hoare triple {19943#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 15: Hoare triple {19943#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 16: Hoare triple {19943#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,076 INFO L290 TraceCheckUtils]: 17: Hoare triple {19943#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,077 INFO L290 TraceCheckUtils]: 18: Hoare triple {19943#true} assume !(0 == ~T8_E~0); {19943#true} is VALID [2022-02-21 04:23:00,077 INFO L290 TraceCheckUtils]: 19: Hoare triple {19943#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,077 INFO L290 TraceCheckUtils]: 20: Hoare triple {19943#true} assume 0 == ~E_M~0;~E_M~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,077 INFO L290 TraceCheckUtils]: 21: Hoare triple {19943#true} assume 0 == ~E_1~0;~E_1~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,077 INFO L290 TraceCheckUtils]: 22: Hoare triple {19943#true} assume 0 == ~E_2~0;~E_2~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,077 INFO L290 TraceCheckUtils]: 23: Hoare triple {19943#true} assume 0 == ~E_3~0;~E_3~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,077 INFO L290 TraceCheckUtils]: 24: Hoare triple {19943#true} assume 0 == ~E_4~0;~E_4~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,078 INFO L290 TraceCheckUtils]: 25: Hoare triple {19943#true} assume 0 == ~E_5~0;~E_5~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,078 INFO L290 TraceCheckUtils]: 26: Hoare triple {19943#true} assume !(0 == ~E_6~0); {19943#true} is VALID [2022-02-21 04:23:00,078 INFO L290 TraceCheckUtils]: 27: Hoare triple {19943#true} assume 0 == ~E_7~0;~E_7~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,078 INFO L290 TraceCheckUtils]: 28: Hoare triple {19943#true} assume 0 == ~E_8~0;~E_8~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,078 INFO L290 TraceCheckUtils]: 29: Hoare triple {19943#true} assume 0 == ~E_9~0;~E_9~0 := 1; {19943#true} is VALID [2022-02-21 04:23:00,078 INFO L290 TraceCheckUtils]: 30: Hoare triple {19943#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19943#true} is VALID [2022-02-21 04:23:00,078 INFO L290 TraceCheckUtils]: 31: Hoare triple {19943#true} assume 1 == ~m_pc~0; {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 32: Hoare triple {19943#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 33: Hoare triple {19943#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 34: Hoare triple {19943#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 35: Hoare triple {19943#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 36: Hoare triple {19943#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 37: Hoare triple {19943#true} assume !(1 == ~t1_pc~0); {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 38: Hoare triple {19943#true} is_transmit1_triggered_~__retres1~1#1 := 0; {19943#true} is VALID [2022-02-21 04:23:00,079 INFO L290 TraceCheckUtils]: 39: Hoare triple {19943#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 40: Hoare triple {19943#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 41: Hoare triple {19943#true} assume !(0 != activate_threads_~tmp___0~0#1); {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 42: Hoare triple {19943#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 43: Hoare triple {19943#true} assume 1 == ~t2_pc~0; {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 44: Hoare triple {19943#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 45: Hoare triple {19943#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 46: Hoare triple {19943#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {19943#true} is VALID [2022-02-21 04:23:00,080 INFO L290 TraceCheckUtils]: 47: Hoare triple {19943#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 48: Hoare triple {19943#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 49: Hoare triple {19943#true} assume !(1 == ~t3_pc~0); {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 50: Hoare triple {19943#true} is_transmit3_triggered_~__retres1~3#1 := 0; {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 51: Hoare triple {19943#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 52: Hoare triple {19943#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 53: Hoare triple {19943#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 54: Hoare triple {19943#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {19943#true} is VALID [2022-02-21 04:23:00,081 INFO L290 TraceCheckUtils]: 55: Hoare triple {19943#true} assume 1 == ~t4_pc~0; {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 56: Hoare triple {19943#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 57: Hoare triple {19943#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 58: Hoare triple {19943#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 59: Hoare triple {19943#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 60: Hoare triple {19943#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 61: Hoare triple {19943#true} assume !(1 == ~t5_pc~0); {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 62: Hoare triple {19943#true} is_transmit5_triggered_~__retres1~5#1 := 0; {19943#true} is VALID [2022-02-21 04:23:00,082 INFO L290 TraceCheckUtils]: 63: Hoare triple {19943#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {19943#true} is VALID [2022-02-21 04:23:00,083 INFO L290 TraceCheckUtils]: 64: Hoare triple {19943#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {19943#true} is VALID [2022-02-21 04:23:00,083 INFO L290 TraceCheckUtils]: 65: Hoare triple {19943#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {19943#true} is VALID [2022-02-21 04:23:00,083 INFO L290 TraceCheckUtils]: 66: Hoare triple {19943#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {19943#true} is VALID [2022-02-21 04:23:00,083 INFO L290 TraceCheckUtils]: 67: Hoare triple {19943#true} assume 1 == ~t6_pc~0; {19943#true} is VALID [2022-02-21 04:23:00,084 INFO L290 TraceCheckUtils]: 68: Hoare triple {19943#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,084 INFO L290 TraceCheckUtils]: 69: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,084 INFO L290 TraceCheckUtils]: 70: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,085 INFO L290 TraceCheckUtils]: 71: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,085 INFO L290 TraceCheckUtils]: 72: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,085 INFO L290 TraceCheckUtils]: 73: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,085 INFO L290 TraceCheckUtils]: 74: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,086 INFO L290 TraceCheckUtils]: 75: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,086 INFO L290 TraceCheckUtils]: 76: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,086 INFO L290 TraceCheckUtils]: 77: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,087 INFO L290 TraceCheckUtils]: 78: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,087 INFO L290 TraceCheckUtils]: 79: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,087 INFO L290 TraceCheckUtils]: 80: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,088 INFO L290 TraceCheckUtils]: 81: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,088 INFO L290 TraceCheckUtils]: 82: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,088 INFO L290 TraceCheckUtils]: 83: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,089 INFO L290 TraceCheckUtils]: 84: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,089 INFO L290 TraceCheckUtils]: 85: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t9_pc~0); {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,089 INFO L290 TraceCheckUtils]: 86: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,090 INFO L290 TraceCheckUtils]: 87: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,090 INFO L290 TraceCheckUtils]: 88: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,090 INFO L290 TraceCheckUtils]: 89: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,091 INFO L290 TraceCheckUtils]: 90: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,091 INFO L290 TraceCheckUtils]: 91: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,092 INFO L290 TraceCheckUtils]: 92: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,092 INFO L290 TraceCheckUtils]: 93: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,092 INFO L290 TraceCheckUtils]: 94: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,093 INFO L290 TraceCheckUtils]: 95: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,093 INFO L290 TraceCheckUtils]: 96: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,093 INFO L290 TraceCheckUtils]: 97: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,094 INFO L290 TraceCheckUtils]: 98: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,094 INFO L290 TraceCheckUtils]: 99: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,094 INFO L290 TraceCheckUtils]: 100: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,095 INFO L290 TraceCheckUtils]: 101: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,095 INFO L290 TraceCheckUtils]: 102: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,095 INFO L290 TraceCheckUtils]: 103: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,096 INFO L290 TraceCheckUtils]: 104: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,096 INFO L290 TraceCheckUtils]: 105: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,096 INFO L290 TraceCheckUtils]: 106: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {19945#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:00,097 INFO L290 TraceCheckUtils]: 107: Hoare triple {19945#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {19944#false} is VALID [2022-02-21 04:23:00,097 INFO L290 TraceCheckUtils]: 108: Hoare triple {19944#false} assume 1 == ~E_7~0;~E_7~0 := 2; {19944#false} is VALID [2022-02-21 04:23:00,097 INFO L290 TraceCheckUtils]: 109: Hoare triple {19944#false} assume 1 == ~E_8~0;~E_8~0 := 2; {19944#false} is VALID [2022-02-21 04:23:00,097 INFO L290 TraceCheckUtils]: 110: Hoare triple {19944#false} assume 1 == ~E_9~0;~E_9~0 := 2; {19944#false} is VALID [2022-02-21 04:23:00,097 INFO L290 TraceCheckUtils]: 111: Hoare triple {19944#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 112: Hoare triple {19944#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 113: Hoare triple {19944#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 114: Hoare triple {19944#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 115: Hoare triple {19944#false} assume !(0 == start_simulation_~tmp~3#1); {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 116: Hoare triple {19944#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 117: Hoare triple {19944#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 118: Hoare triple {19944#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {19944#false} is VALID [2022-02-21 04:23:00,098 INFO L290 TraceCheckUtils]: 119: Hoare triple {19944#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {19944#false} is VALID [2022-02-21 04:23:00,099 INFO L290 TraceCheckUtils]: 120: Hoare triple {19944#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {19944#false} is VALID [2022-02-21 04:23:00,099 INFO L290 TraceCheckUtils]: 121: Hoare triple {19944#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {19944#false} is VALID [2022-02-21 04:23:00,099 INFO L290 TraceCheckUtils]: 122: Hoare triple {19944#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {19944#false} is VALID [2022-02-21 04:23:00,099 INFO L290 TraceCheckUtils]: 123: Hoare triple {19944#false} assume !(0 != start_simulation_~tmp___0~1#1); {19944#false} is VALID [2022-02-21 04:23:00,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:00,100 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:00,100 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1349025779] [2022-02-21 04:23:00,100 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1349025779] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:00,100 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:00,100 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:00,101 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917668314] [2022-02-21 04:23:00,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:00,101 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:00,101 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:00,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:00,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:00,103 INFO L87 Difference]: Start difference. First operand 1170 states and 1739 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:01,129 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2022-02-21 04:23:01,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:01,129 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,200 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:01,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:01,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1738 transitions. [2022-02-21 04:23:01,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:23:01,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:23:01,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:01,304 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-02-21 04:23:01,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:23:01,318 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:01,320 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1738 transitions. Second operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,322 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1738 transitions. Second operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,323 INFO L87 Difference]: Start difference. First operand 1170 states and 1738 transitions. Second operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:01,373 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2022-02-21 04:23:01,373 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,375 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:01,375 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:01,378 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,380 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:01,430 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2022-02-21 04:23:01,430 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,432 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:01,432 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:01,432 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:01,432 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:01,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1738 transitions. [2022-02-21 04:23:01,485 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-02-21 04:23:01,485 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2022-02-21 04:23:01,485 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:01,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1738 transitions. [2022-02-21 04:23:01,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:01,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:01,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:01,492 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:01,492 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:01,493 INFO L791 eck$LassoCheckResult]: Stem: 21988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 21989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 21938#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21939#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22157#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 21824#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21825#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22134#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21633#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21634#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22062#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22063#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21132#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21133#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21336#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21724#L939 assume !(0 == ~M_E~0); 21968#L939-2 assume !(0 == ~T1_E~0); 21969#L944-1 assume !(0 == ~T2_E~0); 21753#L949-1 assume !(0 == ~T3_E~0); 21751#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21752#L959-1 assume !(0 == ~T5_E~0); 22171#L964-1 assume !(0 == ~T6_E~0); 21484#L969-1 assume !(0 == ~T7_E~0); 21485#L974-1 assume !(0 == ~T8_E~0); 22124#L979-1 assume !(0 == ~T9_E~0); 22125#L984-1 assume !(0 == ~E_M~0); 21645#L989-1 assume !(0 == ~E_1~0); 21646#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21534#L999-1 assume !(0 == ~E_3~0); 21535#L1004-1 assume !(0 == ~E_4~0); 21200#L1009-1 assume !(0 == ~E_5~0); 21201#L1014-1 assume !(0 == ~E_6~0); 21530#L1019-1 assume !(0 == ~E_7~0); 22067#L1024-1 assume !(0 == ~E_8~0); 21457#L1029-1 assume !(0 == ~E_9~0); 21458#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21548#L460 assume 1 == ~m_pc~0; 21119#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21120#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22033#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22272#L1167 assume !(0 != activate_threads_~tmp~1#1); 21741#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21742#L479 assume 1 == ~t1_pc~0; 21725#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21726#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22229#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21469#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 21470#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21318#L498 assume !(1 == ~t2_pc~0); 21319#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21722#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21723#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22100#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22024#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22025#L517 assume 1 == ~t3_pc~0; 22233#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22234#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21796#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21502#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 21503#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22078#L536 assume !(1 == ~t4_pc~0); 21786#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21785#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22162#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21778#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 21779#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21998#L555 assume 1 == ~t5_pc~0; 21999#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22068#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21233#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21234#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 21339#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21239#L574 assume !(1 == ~t6_pc~0); 21240#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21871#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21344#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21345#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 22096#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22256#L593 assume 1 == ~t7_pc~0; 22257#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21476#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22174#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22277#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 22237#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21640#L612 assume !(1 == ~t8_pc~0); 21641#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22050#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21909#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21910#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 21875#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21876#L631 assume 1 == ~t9_pc~0; 21892#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21230#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21198#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21199#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 21728#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22079#L1047 assume !(1 == ~M_E~0); 21168#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21169#L1052-1 assume !(1 == ~T2_E~0); 21151#L1057-1 assume !(1 == ~T3_E~0); 21152#L1062-1 assume !(1 == ~T4_E~0); 21441#L1067-1 assume !(1 == ~T5_E~0); 21744#L1072-1 assume !(1 == ~T6_E~0); 21745#L1077-1 assume !(1 == ~T7_E~0); 21332#L1082-1 assume !(1 == ~T8_E~0); 21333#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21128#L1092-1 assume !(1 == ~E_M~0); 21129#L1097-1 assume !(1 == ~E_1~0); 21153#L1102-1 assume !(1 == ~E_2~0); 21934#L1107-1 assume !(1 == ~E_3~0); 21869#L1112-1 assume !(1 == ~E_4~0); 21870#L1117-1 assume !(1 == ~E_5~0); 21911#L1122-1 assume !(1 == ~E_6~0); 21797#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21553#L1132-1 assume !(1 == ~E_8~0); 21554#L1137-1 assume !(1 == ~E_9~0); 21440#L1142-1 assume { :end_inline_reset_delta_events } true; 21303#L1428-2 [2022-02-21 04:23:01,493 INFO L793 eck$LassoCheckResult]: Loop: 21303#L1428-2 assume !false; 21304#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21375#L914 assume !false; 21865#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21866#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21137#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21138#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22097#L783 assume !(0 != eval_~tmp~0#1); 21537#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21538#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21933#L939-3 assume !(0 == ~M_E~0); 21358#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21359#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21122#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21123#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21759#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21204#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21205#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21409#L974-3 assume !(0 == ~T8_E~0); 21410#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21840#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21841#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21463#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21464#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21975#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21286#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21287#L1014-3 assume !(0 == ~E_6~0); 21826#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21827#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21808#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21763#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21764#L460-33 assume 1 == ~m_pc~0; 21799#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21800#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21555#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21130#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21131#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21492#L479-33 assume !(1 == ~t1_pc~0); 21493#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 21459#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21460#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22044#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 22217#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21497#L498-33 assume 1 == ~t2_pc~0; 21498#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21243#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21380#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21381#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21356#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21357#L517-33 assume !(1 == ~t3_pc~0); 22265#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 22148#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22149#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21961#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21962#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21584#L536-33 assume 1 == ~t4_pc~0; 21585#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21657#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21658#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21848#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22127#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21177#L555-33 assume !(1 == ~t5_pc~0); 21178#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 21903#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21450#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21451#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21930#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21146#L574-33 assume 1 == ~t6_pc~0; 21147#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22139#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21465#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21466#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21719#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21222#L593-33 assume !(1 == ~t7_pc~0); 21223#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 21676#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21330#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21331#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21990#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22117#L612-33 assume 1 == ~t8_pc~0; 22244#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22208#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22209#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22051#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21326#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21327#L631-33 assume !(1 == ~t9_pc~0); 21937#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 21270#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21271#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21523#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21382#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21383#L1047-3 assume !(1 == ~M_E~0); 21556#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22170#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22102#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22103#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21281#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21282#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21664#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21509#L1082-3 assume !(1 == ~T8_E~0); 21510#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21583#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21864#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21794#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21795#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22140#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21504#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21505#L1122-3 assume !(1 == ~E_6~0); 21557#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21558#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21947#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21924#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21384#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21262#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21925#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 21682#L1447 assume !(0 == start_simulation_~tmp~3#1); 21683#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22121#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21423#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21948#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 21533#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21290#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21291#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21746#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 21303#L1428-2 [2022-02-21 04:23:01,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:01,494 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2022-02-21 04:23:01,494 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:01,494 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220395813] [2022-02-21 04:23:01,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:01,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:01,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:01,524 INFO L290 TraceCheckUtils]: 0: Hoare triple {24629#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {24629#true} is VALID [2022-02-21 04:23:01,524 INFO L290 TraceCheckUtils]: 1: Hoare triple {24629#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,525 INFO L290 TraceCheckUtils]: 2: Hoare triple {24631#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,525 INFO L290 TraceCheckUtils]: 3: Hoare triple {24631#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,525 INFO L290 TraceCheckUtils]: 4: Hoare triple {24631#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,526 INFO L290 TraceCheckUtils]: 5: Hoare triple {24631#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,526 INFO L290 TraceCheckUtils]: 6: Hoare triple {24631#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,526 INFO L290 TraceCheckUtils]: 7: Hoare triple {24631#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,527 INFO L290 TraceCheckUtils]: 8: Hoare triple {24631#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,527 INFO L290 TraceCheckUtils]: 9: Hoare triple {24631#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {24631#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:01,527 INFO L290 TraceCheckUtils]: 10: Hoare triple {24631#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {24630#false} is VALID [2022-02-21 04:23:01,527 INFO L290 TraceCheckUtils]: 11: Hoare triple {24630#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {24630#false} is VALID [2022-02-21 04:23:01,528 INFO L290 TraceCheckUtils]: 12: Hoare triple {24630#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {24630#false} is VALID [2022-02-21 04:23:01,528 INFO L290 TraceCheckUtils]: 13: Hoare triple {24630#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {24630#false} is VALID [2022-02-21 04:23:01,528 INFO L290 TraceCheckUtils]: 14: Hoare triple {24630#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {24630#false} is VALID [2022-02-21 04:23:01,528 INFO L290 TraceCheckUtils]: 15: Hoare triple {24630#false} assume !(0 == ~M_E~0); {24630#false} is VALID [2022-02-21 04:23:01,528 INFO L290 TraceCheckUtils]: 16: Hoare triple {24630#false} assume !(0 == ~T1_E~0); {24630#false} is VALID [2022-02-21 04:23:01,528 INFO L290 TraceCheckUtils]: 17: Hoare triple {24630#false} assume !(0 == ~T2_E~0); {24630#false} is VALID [2022-02-21 04:23:01,528 INFO L290 TraceCheckUtils]: 18: Hoare triple {24630#false} assume !(0 == ~T3_E~0); {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 19: Hoare triple {24630#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 20: Hoare triple {24630#false} assume !(0 == ~T5_E~0); {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 21: Hoare triple {24630#false} assume !(0 == ~T6_E~0); {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 22: Hoare triple {24630#false} assume !(0 == ~T7_E~0); {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 23: Hoare triple {24630#false} assume !(0 == ~T8_E~0); {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 24: Hoare triple {24630#false} assume !(0 == ~T9_E~0); {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 25: Hoare triple {24630#false} assume !(0 == ~E_M~0); {24630#false} is VALID [2022-02-21 04:23:01,529 INFO L290 TraceCheckUtils]: 26: Hoare triple {24630#false} assume !(0 == ~E_1~0); {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 27: Hoare triple {24630#false} assume 0 == ~E_2~0;~E_2~0 := 1; {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 28: Hoare triple {24630#false} assume !(0 == ~E_3~0); {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 29: Hoare triple {24630#false} assume !(0 == ~E_4~0); {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 30: Hoare triple {24630#false} assume !(0 == ~E_5~0); {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 31: Hoare triple {24630#false} assume !(0 == ~E_6~0); {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 32: Hoare triple {24630#false} assume !(0 == ~E_7~0); {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 33: Hoare triple {24630#false} assume !(0 == ~E_8~0); {24630#false} is VALID [2022-02-21 04:23:01,530 INFO L290 TraceCheckUtils]: 34: Hoare triple {24630#false} assume !(0 == ~E_9~0); {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 35: Hoare triple {24630#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 36: Hoare triple {24630#false} assume 1 == ~m_pc~0; {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 37: Hoare triple {24630#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 38: Hoare triple {24630#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 39: Hoare triple {24630#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 40: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp~1#1); {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 41: Hoare triple {24630#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24630#false} is VALID [2022-02-21 04:23:01,531 INFO L290 TraceCheckUtils]: 42: Hoare triple {24630#false} assume 1 == ~t1_pc~0; {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 43: Hoare triple {24630#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 44: Hoare triple {24630#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 45: Hoare triple {24630#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 46: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___0~0#1); {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 47: Hoare triple {24630#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 48: Hoare triple {24630#false} assume !(1 == ~t2_pc~0); {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 49: Hoare triple {24630#false} is_transmit2_triggered_~__retres1~2#1 := 0; {24630#false} is VALID [2022-02-21 04:23:01,532 INFO L290 TraceCheckUtils]: 50: Hoare triple {24630#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 51: Hoare triple {24630#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 52: Hoare triple {24630#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 53: Hoare triple {24630#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 54: Hoare triple {24630#false} assume 1 == ~t3_pc~0; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 55: Hoare triple {24630#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 56: Hoare triple {24630#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 57: Hoare triple {24630#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24630#false} is VALID [2022-02-21 04:23:01,533 INFO L290 TraceCheckUtils]: 58: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___2~0#1); {24630#false} is VALID [2022-02-21 04:23:01,534 INFO L290 TraceCheckUtils]: 59: Hoare triple {24630#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24630#false} is VALID [2022-02-21 04:23:01,534 INFO L290 TraceCheckUtils]: 60: Hoare triple {24630#false} assume !(1 == ~t4_pc~0); {24630#false} is VALID [2022-02-21 04:23:01,534 INFO L290 TraceCheckUtils]: 61: Hoare triple {24630#false} is_transmit4_triggered_~__retres1~4#1 := 0; {24630#false} is VALID [2022-02-21 04:23:01,534 INFO L290 TraceCheckUtils]: 62: Hoare triple {24630#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24630#false} is VALID [2022-02-21 04:23:01,534 INFO L290 TraceCheckUtils]: 63: Hoare triple {24630#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24630#false} is VALID [2022-02-21 04:23:01,534 INFO L290 TraceCheckUtils]: 64: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___3~0#1); {24630#false} is VALID [2022-02-21 04:23:01,534 INFO L290 TraceCheckUtils]: 65: Hoare triple {24630#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 66: Hoare triple {24630#false} assume 1 == ~t5_pc~0; {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 67: Hoare triple {24630#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 68: Hoare triple {24630#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 69: Hoare triple {24630#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 70: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___4~0#1); {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 71: Hoare triple {24630#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 72: Hoare triple {24630#false} assume !(1 == ~t6_pc~0); {24630#false} is VALID [2022-02-21 04:23:01,535 INFO L290 TraceCheckUtils]: 73: Hoare triple {24630#false} is_transmit6_triggered_~__retres1~6#1 := 0; {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 74: Hoare triple {24630#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 75: Hoare triple {24630#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 76: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___5~0#1); {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 77: Hoare triple {24630#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 78: Hoare triple {24630#false} assume 1 == ~t7_pc~0; {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 79: Hoare triple {24630#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 80: Hoare triple {24630#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24630#false} is VALID [2022-02-21 04:23:01,536 INFO L290 TraceCheckUtils]: 81: Hoare triple {24630#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 82: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___6~0#1); {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 83: Hoare triple {24630#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 84: Hoare triple {24630#false} assume !(1 == ~t8_pc~0); {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 85: Hoare triple {24630#false} is_transmit8_triggered_~__retres1~8#1 := 0; {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 86: Hoare triple {24630#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 87: Hoare triple {24630#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 88: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___7~0#1); {24630#false} is VALID [2022-02-21 04:23:01,537 INFO L290 TraceCheckUtils]: 89: Hoare triple {24630#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {24630#false} is VALID [2022-02-21 04:23:01,538 INFO L290 TraceCheckUtils]: 90: Hoare triple {24630#false} assume 1 == ~t9_pc~0; {24630#false} is VALID [2022-02-21 04:23:01,538 INFO L290 TraceCheckUtils]: 91: Hoare triple {24630#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {24630#false} is VALID [2022-02-21 04:23:01,538 INFO L290 TraceCheckUtils]: 92: Hoare triple {24630#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {24630#false} is VALID [2022-02-21 04:23:01,538 INFO L290 TraceCheckUtils]: 93: Hoare triple {24630#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {24630#false} is VALID [2022-02-21 04:23:01,538 INFO L290 TraceCheckUtils]: 94: Hoare triple {24630#false} assume !(0 != activate_threads_~tmp___8~0#1); {24630#false} is VALID [2022-02-21 04:23:01,538 INFO L290 TraceCheckUtils]: 95: Hoare triple {24630#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24630#false} is VALID [2022-02-21 04:23:01,538 INFO L290 TraceCheckUtils]: 96: Hoare triple {24630#false} assume !(1 == ~M_E~0); {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 97: Hoare triple {24630#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 98: Hoare triple {24630#false} assume !(1 == ~T2_E~0); {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 99: Hoare triple {24630#false} assume !(1 == ~T3_E~0); {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 100: Hoare triple {24630#false} assume !(1 == ~T4_E~0); {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 101: Hoare triple {24630#false} assume !(1 == ~T5_E~0); {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 102: Hoare triple {24630#false} assume !(1 == ~T6_E~0); {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 103: Hoare triple {24630#false} assume !(1 == ~T7_E~0); {24630#false} is VALID [2022-02-21 04:23:01,539 INFO L290 TraceCheckUtils]: 104: Hoare triple {24630#false} assume !(1 == ~T8_E~0); {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 105: Hoare triple {24630#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 106: Hoare triple {24630#false} assume !(1 == ~E_M~0); {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 107: Hoare triple {24630#false} assume !(1 == ~E_1~0); {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 108: Hoare triple {24630#false} assume !(1 == ~E_2~0); {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 109: Hoare triple {24630#false} assume !(1 == ~E_3~0); {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 110: Hoare triple {24630#false} assume !(1 == ~E_4~0); {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 111: Hoare triple {24630#false} assume !(1 == ~E_5~0); {24630#false} is VALID [2022-02-21 04:23:01,540 INFO L290 TraceCheckUtils]: 112: Hoare triple {24630#false} assume !(1 == ~E_6~0); {24630#false} is VALID [2022-02-21 04:23:01,541 INFO L290 TraceCheckUtils]: 113: Hoare triple {24630#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24630#false} is VALID [2022-02-21 04:23:01,541 INFO L290 TraceCheckUtils]: 114: Hoare triple {24630#false} assume !(1 == ~E_8~0); {24630#false} is VALID [2022-02-21 04:23:01,541 INFO L290 TraceCheckUtils]: 115: Hoare triple {24630#false} assume !(1 == ~E_9~0); {24630#false} is VALID [2022-02-21 04:23:01,541 INFO L290 TraceCheckUtils]: 116: Hoare triple {24630#false} assume { :end_inline_reset_delta_events } true; {24630#false} is VALID [2022-02-21 04:23:01,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:01,542 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:01,542 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220395813] [2022-02-21 04:23:01,542 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220395813] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:01,542 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:01,542 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:01,542 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850041113] [2022-02-21 04:23:01,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:01,543 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:01,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:01,543 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 2 times [2022-02-21 04:23:01,544 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:01,547 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480995874] [2022-02-21 04:23:01,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:01,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:01,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:01,593 INFO L290 TraceCheckUtils]: 0: Hoare triple {24632#true} assume !false; {24632#true} is VALID [2022-02-21 04:23:01,593 INFO L290 TraceCheckUtils]: 1: Hoare triple {24632#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {24632#true} is VALID [2022-02-21 04:23:01,593 INFO L290 TraceCheckUtils]: 2: Hoare triple {24632#true} assume !false; {24632#true} is VALID [2022-02-21 04:23:01,593 INFO L290 TraceCheckUtils]: 3: Hoare triple {24632#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {24632#true} is VALID [2022-02-21 04:23:01,593 INFO L290 TraceCheckUtils]: 4: Hoare triple {24632#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {24632#true} is VALID [2022-02-21 04:23:01,594 INFO L290 TraceCheckUtils]: 5: Hoare triple {24632#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {24632#true} is VALID [2022-02-21 04:23:01,594 INFO L290 TraceCheckUtils]: 6: Hoare triple {24632#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {24632#true} is VALID [2022-02-21 04:23:01,594 INFO L290 TraceCheckUtils]: 7: Hoare triple {24632#true} assume !(0 != eval_~tmp~0#1); {24632#true} is VALID [2022-02-21 04:23:01,594 INFO L290 TraceCheckUtils]: 8: Hoare triple {24632#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24632#true} is VALID [2022-02-21 04:23:01,594 INFO L290 TraceCheckUtils]: 9: Hoare triple {24632#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24632#true} is VALID [2022-02-21 04:23:01,594 INFO L290 TraceCheckUtils]: 10: Hoare triple {24632#true} assume !(0 == ~M_E~0); {24632#true} is VALID [2022-02-21 04:23:01,594 INFO L290 TraceCheckUtils]: 11: Hoare triple {24632#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 12: Hoare triple {24632#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 13: Hoare triple {24632#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 14: Hoare triple {24632#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 15: Hoare triple {24632#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 16: Hoare triple {24632#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 17: Hoare triple {24632#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 18: Hoare triple {24632#true} assume !(0 == ~T8_E~0); {24632#true} is VALID [2022-02-21 04:23:01,595 INFO L290 TraceCheckUtils]: 19: Hoare triple {24632#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 20: Hoare triple {24632#true} assume 0 == ~E_M~0;~E_M~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 21: Hoare triple {24632#true} assume 0 == ~E_1~0;~E_1~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 22: Hoare triple {24632#true} assume 0 == ~E_2~0;~E_2~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 23: Hoare triple {24632#true} assume 0 == ~E_3~0;~E_3~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 24: Hoare triple {24632#true} assume 0 == ~E_4~0;~E_4~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 25: Hoare triple {24632#true} assume 0 == ~E_5~0;~E_5~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 26: Hoare triple {24632#true} assume !(0 == ~E_6~0); {24632#true} is VALID [2022-02-21 04:23:01,596 INFO L290 TraceCheckUtils]: 27: Hoare triple {24632#true} assume 0 == ~E_7~0;~E_7~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 28: Hoare triple {24632#true} assume 0 == ~E_8~0;~E_8~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 29: Hoare triple {24632#true} assume 0 == ~E_9~0;~E_9~0 := 1; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 30: Hoare triple {24632#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 31: Hoare triple {24632#true} assume 1 == ~m_pc~0; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 32: Hoare triple {24632#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 33: Hoare triple {24632#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 34: Hoare triple {24632#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24632#true} is VALID [2022-02-21 04:23:01,597 INFO L290 TraceCheckUtils]: 35: Hoare triple {24632#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {24632#true} is VALID [2022-02-21 04:23:01,598 INFO L290 TraceCheckUtils]: 36: Hoare triple {24632#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24632#true} is VALID [2022-02-21 04:23:01,598 INFO L290 TraceCheckUtils]: 37: Hoare triple {24632#true} assume !(1 == ~t1_pc~0); {24632#true} is VALID [2022-02-21 04:23:01,598 INFO L290 TraceCheckUtils]: 38: Hoare triple {24632#true} is_transmit1_triggered_~__retres1~1#1 := 0; {24632#true} is VALID [2022-02-21 04:23:01,598 INFO L290 TraceCheckUtils]: 39: Hoare triple {24632#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24632#true} is VALID [2022-02-21 04:23:01,598 INFO L290 TraceCheckUtils]: 40: Hoare triple {24632#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24632#true} is VALID [2022-02-21 04:23:01,598 INFO L290 TraceCheckUtils]: 41: Hoare triple {24632#true} assume !(0 != activate_threads_~tmp___0~0#1); {24632#true} is VALID [2022-02-21 04:23:01,598 INFO L290 TraceCheckUtils]: 42: Hoare triple {24632#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 43: Hoare triple {24632#true} assume 1 == ~t2_pc~0; {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 44: Hoare triple {24632#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 45: Hoare triple {24632#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 46: Hoare triple {24632#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 47: Hoare triple {24632#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 48: Hoare triple {24632#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 49: Hoare triple {24632#true} assume !(1 == ~t3_pc~0); {24632#true} is VALID [2022-02-21 04:23:01,599 INFO L290 TraceCheckUtils]: 50: Hoare triple {24632#true} is_transmit3_triggered_~__retres1~3#1 := 0; {24632#true} is VALID [2022-02-21 04:23:01,600 INFO L290 TraceCheckUtils]: 51: Hoare triple {24632#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24632#true} is VALID [2022-02-21 04:23:01,600 INFO L290 TraceCheckUtils]: 52: Hoare triple {24632#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24632#true} is VALID [2022-02-21 04:23:01,600 INFO L290 TraceCheckUtils]: 53: Hoare triple {24632#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {24632#true} is VALID [2022-02-21 04:23:01,600 INFO L290 TraceCheckUtils]: 54: Hoare triple {24632#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24632#true} is VALID [2022-02-21 04:23:01,600 INFO L290 TraceCheckUtils]: 55: Hoare triple {24632#true} assume 1 == ~t4_pc~0; {24632#true} is VALID [2022-02-21 04:23:01,600 INFO L290 TraceCheckUtils]: 56: Hoare triple {24632#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {24632#true} is VALID [2022-02-21 04:23:01,600 INFO L290 TraceCheckUtils]: 57: Hoare triple {24632#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 58: Hoare triple {24632#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 59: Hoare triple {24632#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 60: Hoare triple {24632#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 61: Hoare triple {24632#true} assume !(1 == ~t5_pc~0); {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 62: Hoare triple {24632#true} is_transmit5_triggered_~__retres1~5#1 := 0; {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 63: Hoare triple {24632#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 64: Hoare triple {24632#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24632#true} is VALID [2022-02-21 04:23:01,601 INFO L290 TraceCheckUtils]: 65: Hoare triple {24632#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {24632#true} is VALID [2022-02-21 04:23:01,602 INFO L290 TraceCheckUtils]: 66: Hoare triple {24632#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24632#true} is VALID [2022-02-21 04:23:01,602 INFO L290 TraceCheckUtils]: 67: Hoare triple {24632#true} assume 1 == ~t6_pc~0; {24632#true} is VALID [2022-02-21 04:23:01,602 INFO L290 TraceCheckUtils]: 68: Hoare triple {24632#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,602 INFO L290 TraceCheckUtils]: 69: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,603 INFO L290 TraceCheckUtils]: 70: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,603 INFO L290 TraceCheckUtils]: 71: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,603 INFO L290 TraceCheckUtils]: 72: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,604 INFO L290 TraceCheckUtils]: 73: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,604 INFO L290 TraceCheckUtils]: 74: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,604 INFO L290 TraceCheckUtils]: 75: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,605 INFO L290 TraceCheckUtils]: 76: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,605 INFO L290 TraceCheckUtils]: 77: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,605 INFO L290 TraceCheckUtils]: 78: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,606 INFO L290 TraceCheckUtils]: 79: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,606 INFO L290 TraceCheckUtils]: 80: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,606 INFO L290 TraceCheckUtils]: 81: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,607 INFO L290 TraceCheckUtils]: 82: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,607 INFO L290 TraceCheckUtils]: 83: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,607 INFO L290 TraceCheckUtils]: 84: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,608 INFO L290 TraceCheckUtils]: 85: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t9_pc~0); {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,608 INFO L290 TraceCheckUtils]: 86: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,608 INFO L290 TraceCheckUtils]: 87: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,609 INFO L290 TraceCheckUtils]: 88: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,609 INFO L290 TraceCheckUtils]: 89: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,609 INFO L290 TraceCheckUtils]: 90: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,610 INFO L290 TraceCheckUtils]: 91: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,610 INFO L290 TraceCheckUtils]: 92: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,610 INFO L290 TraceCheckUtils]: 93: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,611 INFO L290 TraceCheckUtils]: 94: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,611 INFO L290 TraceCheckUtils]: 95: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,611 INFO L290 TraceCheckUtils]: 96: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,612 INFO L290 TraceCheckUtils]: 97: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,612 INFO L290 TraceCheckUtils]: 98: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,612 INFO L290 TraceCheckUtils]: 99: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,613 INFO L290 TraceCheckUtils]: 100: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,613 INFO L290 TraceCheckUtils]: 101: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,613 INFO L290 TraceCheckUtils]: 102: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,613 INFO L290 TraceCheckUtils]: 103: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,614 INFO L290 TraceCheckUtils]: 104: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,614 INFO L290 TraceCheckUtils]: 105: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,614 INFO L290 TraceCheckUtils]: 106: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {24634#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:01,615 INFO L290 TraceCheckUtils]: 107: Hoare triple {24634#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {24633#false} is VALID [2022-02-21 04:23:01,615 INFO L290 TraceCheckUtils]: 108: Hoare triple {24633#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24633#false} is VALID [2022-02-21 04:23:01,615 INFO L290 TraceCheckUtils]: 109: Hoare triple {24633#false} assume 1 == ~E_8~0;~E_8~0 := 2; {24633#false} is VALID [2022-02-21 04:23:01,615 INFO L290 TraceCheckUtils]: 110: Hoare triple {24633#false} assume 1 == ~E_9~0;~E_9~0 := 2; {24633#false} is VALID [2022-02-21 04:23:01,615 INFO L290 TraceCheckUtils]: 111: Hoare triple {24633#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 112: Hoare triple {24633#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 113: Hoare triple {24633#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 114: Hoare triple {24633#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 115: Hoare triple {24633#false} assume !(0 == start_simulation_~tmp~3#1); {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 116: Hoare triple {24633#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 117: Hoare triple {24633#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 118: Hoare triple {24633#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {24633#false} is VALID [2022-02-21 04:23:01,616 INFO L290 TraceCheckUtils]: 119: Hoare triple {24633#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {24633#false} is VALID [2022-02-21 04:23:01,617 INFO L290 TraceCheckUtils]: 120: Hoare triple {24633#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {24633#false} is VALID [2022-02-21 04:23:01,617 INFO L290 TraceCheckUtils]: 121: Hoare triple {24633#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24633#false} is VALID [2022-02-21 04:23:01,617 INFO L290 TraceCheckUtils]: 122: Hoare triple {24633#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {24633#false} is VALID [2022-02-21 04:23:01,617 INFO L290 TraceCheckUtils]: 123: Hoare triple {24633#false} assume !(0 != start_simulation_~tmp___0~1#1); {24633#false} is VALID [2022-02-21 04:23:01,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:01,617 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:01,618 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480995874] [2022-02-21 04:23:01,618 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480995874] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:01,618 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:01,618 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:01,618 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052613338] [2022-02-21 04:23:01,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:01,619 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:01,619 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:01,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:01,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:01,620 INFO L87 Difference]: Start difference. First operand 1170 states and 1738 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,540 INFO L93 Difference]: Finished difference Result 1170 states and 1737 transitions. [2022-02-21 04:23:02,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:02,540 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,636 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:02,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:02,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1737 transitions. [2022-02-21 04:23:02,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:23:02,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:23:02,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:02,737 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2022-02-21 04:23:02,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:23:02,753 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:02,755 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1737 transitions. Second operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,757 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1737 transitions. Second operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,758 INFO L87 Difference]: Start difference. First operand 1170 states and 1737 transitions. Second operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,799 INFO L93 Difference]: Finished difference Result 1170 states and 1737 transitions. [2022-02-21 04:23:02,800 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,802 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:02,802 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:02,804 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,806 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,855 INFO L93 Difference]: Finished difference Result 1170 states and 1737 transitions. [2022-02-21 04:23:02,855 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,857 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:02,857 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:02,858 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:02,858 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:02,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1737 transitions. [2022-02-21 04:23:02,907 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2022-02-21 04:23:02,907 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2022-02-21 04:23:02,907 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:02,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1737 transitions. [2022-02-21 04:23:02,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:02,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:02,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:02,914 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,914 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,915 INFO L791 eck$LassoCheckResult]: Stem: 26677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 26678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 26627#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26628#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26846#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 26513#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26514#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26823#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26322#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26323#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26749#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26750#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25821#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25822#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26025#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26413#L939 assume !(0 == ~M_E~0); 26657#L939-2 assume !(0 == ~T1_E~0); 26658#L944-1 assume !(0 == ~T2_E~0); 26442#L949-1 assume !(0 == ~T3_E~0); 26440#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26441#L959-1 assume !(0 == ~T5_E~0); 26860#L964-1 assume !(0 == ~T6_E~0); 26173#L969-1 assume !(0 == ~T7_E~0); 26174#L974-1 assume !(0 == ~T8_E~0); 26811#L979-1 assume !(0 == ~T9_E~0); 26812#L984-1 assume !(0 == ~E_M~0); 26334#L989-1 assume !(0 == ~E_1~0); 26335#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 26223#L999-1 assume !(0 == ~E_3~0); 26224#L1004-1 assume !(0 == ~E_4~0); 25889#L1009-1 assume !(0 == ~E_5~0); 25890#L1014-1 assume !(0 == ~E_6~0); 26215#L1019-1 assume !(0 == ~E_7~0); 26756#L1024-1 assume !(0 == ~E_8~0); 26146#L1029-1 assume !(0 == ~E_9~0); 26147#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26237#L460 assume 1 == ~m_pc~0; 25805#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25806#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26722#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26961#L1167 assume !(0 != activate_threads_~tmp~1#1); 26430#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26431#L479 assume 1 == ~t1_pc~0; 26414#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26415#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26918#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26158#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 26159#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26007#L498 assume !(1 == ~t2_pc~0); 26008#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26411#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26412#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26789#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26712#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26713#L517 assume 1 == ~t3_pc~0; 26920#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26921#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26485#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26191#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 26192#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26765#L536 assume !(1 == ~t4_pc~0); 26475#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26474#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26851#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26467#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 26468#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26685#L555 assume 1 == ~t5_pc~0; 26686#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26757#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25920#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25921#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 26028#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25928#L574 assume !(1 == ~t6_pc~0); 25929#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26560#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26033#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26034#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 26783#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26945#L593 assume 1 == ~t7_pc~0; 26946#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26165#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26863#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26966#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 26926#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26329#L612 assume !(1 == ~t8_pc~0); 26330#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26739#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26597#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26598#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 26562#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26563#L631 assume 1 == ~t9_pc~0; 26581#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25919#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25887#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25888#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 26417#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26768#L1047 assume !(1 == ~M_E~0); 25857#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25858#L1052-1 assume !(1 == ~T2_E~0); 25840#L1057-1 assume !(1 == ~T3_E~0); 25841#L1062-1 assume !(1 == ~T4_E~0); 26130#L1067-1 assume !(1 == ~T5_E~0); 26433#L1072-1 assume !(1 == ~T6_E~0); 26434#L1077-1 assume !(1 == ~T7_E~0); 26021#L1082-1 assume !(1 == ~T8_E~0); 26022#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25813#L1092-1 assume !(1 == ~E_M~0); 25814#L1097-1 assume !(1 == ~E_1~0); 25842#L1102-1 assume !(1 == ~E_2~0); 26623#L1107-1 assume !(1 == ~E_3~0); 26558#L1112-1 assume !(1 == ~E_4~0); 26559#L1117-1 assume !(1 == ~E_5~0); 26599#L1122-1 assume !(1 == ~E_6~0); 26486#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26240#L1132-1 assume !(1 == ~E_8~0); 26241#L1137-1 assume !(1 == ~E_9~0); 26129#L1142-1 assume { :end_inline_reset_delta_events } true; 25989#L1428-2 [2022-02-21 04:23:02,915 INFO L793 eck$LassoCheckResult]: Loop: 25989#L1428-2 assume !false; 25990#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26064#L914 assume !false; 26554#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26555#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 25826#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 25827#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26786#L783 assume !(0 != eval_~tmp~0#1); 26226#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26227#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26622#L939-3 assume !(0 == ~M_E~0); 26045#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26046#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25811#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25812#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26448#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25891#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25892#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26098#L974-3 assume !(0 == ~T8_E~0); 26099#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26529#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26530#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26152#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26153#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26664#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25975#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25976#L1014-3 assume !(0 == ~E_6~0); 26515#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26516#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26497#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26449#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26450#L460-33 assume 1 == ~m_pc~0; 26487#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26488#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26244#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25819#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25820#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26180#L479-33 assume !(1 == ~t1_pc~0); 26181#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 26148#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26149#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26733#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 26906#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26189#L498-33 assume 1 == ~t2_pc~0; 26190#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25935#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26069#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26070#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26047#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26048#L517-33 assume !(1 == ~t3_pc~0); 26954#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 26837#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26838#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26650#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26651#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26276#L536-33 assume 1 == ~t4_pc~0; 26277#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26346#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26347#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26537#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26816#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25866#L555-33 assume !(1 == ~t5_pc~0); 25867#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 26592#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26139#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26140#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26619#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25837#L574-33 assume 1 == ~t6_pc~0; 25838#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26828#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26154#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26155#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26408#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25913#L593-33 assume !(1 == ~t7_pc~0); 25914#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 26369#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26019#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26020#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26679#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26806#L612-33 assume 1 == ~t8_pc~0; 26933#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26897#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26898#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26740#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26017#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26018#L631-33 assume !(1 == ~t9_pc~0); 26626#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 25959#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25960#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26214#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26071#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26072#L1047-3 assume !(1 == ~M_E~0); 26245#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26859#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26791#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26792#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25970#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25971#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26353#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26198#L1082-3 assume !(1 == ~T8_E~0); 26199#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26272#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26553#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26483#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26484#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26829#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26193#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26194#L1122-3 assume !(1 == ~E_6~0); 26246#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26247#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26636#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26613#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26076#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 25954#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26614#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 26371#L1447 assume !(0 == start_simulation_~tmp~3#1); 26372#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26810#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26112#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26637#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 26222#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25979#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25980#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 26435#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 25989#L1428-2 [2022-02-21 04:23:02,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,916 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2022-02-21 04:23:02,916 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,916 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114834987] [2022-02-21 04:23:02,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:02,953 INFO L290 TraceCheckUtils]: 0: Hoare triple {29318#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {29318#true} is VALID [2022-02-21 04:23:02,953 INFO L290 TraceCheckUtils]: 1: Hoare triple {29318#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,954 INFO L290 TraceCheckUtils]: 2: Hoare triple {29320#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,954 INFO L290 TraceCheckUtils]: 3: Hoare triple {29320#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,954 INFO L290 TraceCheckUtils]: 4: Hoare triple {29320#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,955 INFO L290 TraceCheckUtils]: 5: Hoare triple {29320#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,955 INFO L290 TraceCheckUtils]: 6: Hoare triple {29320#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,955 INFO L290 TraceCheckUtils]: 7: Hoare triple {29320#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,956 INFO L290 TraceCheckUtils]: 8: Hoare triple {29320#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,956 INFO L290 TraceCheckUtils]: 9: Hoare triple {29320#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,956 INFO L290 TraceCheckUtils]: 10: Hoare triple {29320#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {29320#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:02,957 INFO L290 TraceCheckUtils]: 11: Hoare triple {29320#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {29319#false} is VALID [2022-02-21 04:23:02,957 INFO L290 TraceCheckUtils]: 12: Hoare triple {29319#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {29319#false} is VALID [2022-02-21 04:23:02,957 INFO L290 TraceCheckUtils]: 13: Hoare triple {29319#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {29319#false} is VALID [2022-02-21 04:23:02,957 INFO L290 TraceCheckUtils]: 14: Hoare triple {29319#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {29319#false} is VALID [2022-02-21 04:23:02,957 INFO L290 TraceCheckUtils]: 15: Hoare triple {29319#false} assume !(0 == ~M_E~0); {29319#false} is VALID [2022-02-21 04:23:02,957 INFO L290 TraceCheckUtils]: 16: Hoare triple {29319#false} assume !(0 == ~T1_E~0); {29319#false} is VALID [2022-02-21 04:23:02,957 INFO L290 TraceCheckUtils]: 17: Hoare triple {29319#false} assume !(0 == ~T2_E~0); {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 18: Hoare triple {29319#false} assume !(0 == ~T3_E~0); {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 19: Hoare triple {29319#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 20: Hoare triple {29319#false} assume !(0 == ~T5_E~0); {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 21: Hoare triple {29319#false} assume !(0 == ~T6_E~0); {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 22: Hoare triple {29319#false} assume !(0 == ~T7_E~0); {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 23: Hoare triple {29319#false} assume !(0 == ~T8_E~0); {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 24: Hoare triple {29319#false} assume !(0 == ~T9_E~0); {29319#false} is VALID [2022-02-21 04:23:02,958 INFO L290 TraceCheckUtils]: 25: Hoare triple {29319#false} assume !(0 == ~E_M~0); {29319#false} is VALID [2022-02-21 04:23:02,959 INFO L290 TraceCheckUtils]: 26: Hoare triple {29319#false} assume !(0 == ~E_1~0); {29319#false} is VALID [2022-02-21 04:23:02,959 INFO L290 TraceCheckUtils]: 27: Hoare triple {29319#false} assume 0 == ~E_2~0;~E_2~0 := 1; {29319#false} is VALID [2022-02-21 04:23:02,959 INFO L290 TraceCheckUtils]: 28: Hoare triple {29319#false} assume !(0 == ~E_3~0); {29319#false} is VALID [2022-02-21 04:23:02,959 INFO L290 TraceCheckUtils]: 29: Hoare triple {29319#false} assume !(0 == ~E_4~0); {29319#false} is VALID [2022-02-21 04:23:02,959 INFO L290 TraceCheckUtils]: 30: Hoare triple {29319#false} assume !(0 == ~E_5~0); {29319#false} is VALID [2022-02-21 04:23:02,959 INFO L290 TraceCheckUtils]: 31: Hoare triple {29319#false} assume !(0 == ~E_6~0); {29319#false} is VALID [2022-02-21 04:23:02,959 INFO L290 TraceCheckUtils]: 32: Hoare triple {29319#false} assume !(0 == ~E_7~0); {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 33: Hoare triple {29319#false} assume !(0 == ~E_8~0); {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 34: Hoare triple {29319#false} assume !(0 == ~E_9~0); {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 35: Hoare triple {29319#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 36: Hoare triple {29319#false} assume 1 == ~m_pc~0; {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 37: Hoare triple {29319#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 38: Hoare triple {29319#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 39: Hoare triple {29319#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {29319#false} is VALID [2022-02-21 04:23:02,960 INFO L290 TraceCheckUtils]: 40: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp~1#1); {29319#false} is VALID [2022-02-21 04:23:02,961 INFO L290 TraceCheckUtils]: 41: Hoare triple {29319#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {29319#false} is VALID [2022-02-21 04:23:02,961 INFO L290 TraceCheckUtils]: 42: Hoare triple {29319#false} assume 1 == ~t1_pc~0; {29319#false} is VALID [2022-02-21 04:23:02,961 INFO L290 TraceCheckUtils]: 43: Hoare triple {29319#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {29319#false} is VALID [2022-02-21 04:23:02,961 INFO L290 TraceCheckUtils]: 44: Hoare triple {29319#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {29319#false} is VALID [2022-02-21 04:23:02,961 INFO L290 TraceCheckUtils]: 45: Hoare triple {29319#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {29319#false} is VALID [2022-02-21 04:23:02,961 INFO L290 TraceCheckUtils]: 46: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___0~0#1); {29319#false} is VALID [2022-02-21 04:23:02,961 INFO L290 TraceCheckUtils]: 47: Hoare triple {29319#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 48: Hoare triple {29319#false} assume !(1 == ~t2_pc~0); {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 49: Hoare triple {29319#false} is_transmit2_triggered_~__retres1~2#1 := 0; {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 50: Hoare triple {29319#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 51: Hoare triple {29319#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 52: Hoare triple {29319#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 53: Hoare triple {29319#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 54: Hoare triple {29319#false} assume 1 == ~t3_pc~0; {29319#false} is VALID [2022-02-21 04:23:02,962 INFO L290 TraceCheckUtils]: 55: Hoare triple {29319#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {29319#false} is VALID [2022-02-21 04:23:02,963 INFO L290 TraceCheckUtils]: 56: Hoare triple {29319#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {29319#false} is VALID [2022-02-21 04:23:02,963 INFO L290 TraceCheckUtils]: 57: Hoare triple {29319#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {29319#false} is VALID [2022-02-21 04:23:02,963 INFO L290 TraceCheckUtils]: 58: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___2~0#1); {29319#false} is VALID [2022-02-21 04:23:02,963 INFO L290 TraceCheckUtils]: 59: Hoare triple {29319#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {29319#false} is VALID [2022-02-21 04:23:02,963 INFO L290 TraceCheckUtils]: 60: Hoare triple {29319#false} assume !(1 == ~t4_pc~0); {29319#false} is VALID [2022-02-21 04:23:02,963 INFO L290 TraceCheckUtils]: 61: Hoare triple {29319#false} is_transmit4_triggered_~__retres1~4#1 := 0; {29319#false} is VALID [2022-02-21 04:23:02,963 INFO L290 TraceCheckUtils]: 62: Hoare triple {29319#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 63: Hoare triple {29319#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 64: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___3~0#1); {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 65: Hoare triple {29319#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 66: Hoare triple {29319#false} assume 1 == ~t5_pc~0; {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 67: Hoare triple {29319#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 68: Hoare triple {29319#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 69: Hoare triple {29319#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {29319#false} is VALID [2022-02-21 04:23:02,964 INFO L290 TraceCheckUtils]: 70: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___4~0#1); {29319#false} is VALID [2022-02-21 04:23:02,965 INFO L290 TraceCheckUtils]: 71: Hoare triple {29319#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {29319#false} is VALID [2022-02-21 04:23:02,965 INFO L290 TraceCheckUtils]: 72: Hoare triple {29319#false} assume !(1 == ~t6_pc~0); {29319#false} is VALID [2022-02-21 04:23:02,965 INFO L290 TraceCheckUtils]: 73: Hoare triple {29319#false} is_transmit6_triggered_~__retres1~6#1 := 0; {29319#false} is VALID [2022-02-21 04:23:02,965 INFO L290 TraceCheckUtils]: 74: Hoare triple {29319#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {29319#false} is VALID [2022-02-21 04:23:02,965 INFO L290 TraceCheckUtils]: 75: Hoare triple {29319#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {29319#false} is VALID [2022-02-21 04:23:02,965 INFO L290 TraceCheckUtils]: 76: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___5~0#1); {29319#false} is VALID [2022-02-21 04:23:02,965 INFO L290 TraceCheckUtils]: 77: Hoare triple {29319#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 78: Hoare triple {29319#false} assume 1 == ~t7_pc~0; {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 79: Hoare triple {29319#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 80: Hoare triple {29319#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 81: Hoare triple {29319#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 82: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___6~0#1); {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 83: Hoare triple {29319#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 84: Hoare triple {29319#false} assume !(1 == ~t8_pc~0); {29319#false} is VALID [2022-02-21 04:23:02,966 INFO L290 TraceCheckUtils]: 85: Hoare triple {29319#false} is_transmit8_triggered_~__retres1~8#1 := 0; {29319#false} is VALID [2022-02-21 04:23:02,967 INFO L290 TraceCheckUtils]: 86: Hoare triple {29319#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {29319#false} is VALID [2022-02-21 04:23:02,967 INFO L290 TraceCheckUtils]: 87: Hoare triple {29319#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {29319#false} is VALID [2022-02-21 04:23:02,967 INFO L290 TraceCheckUtils]: 88: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___7~0#1); {29319#false} is VALID [2022-02-21 04:23:02,967 INFO L290 TraceCheckUtils]: 89: Hoare triple {29319#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {29319#false} is VALID [2022-02-21 04:23:02,967 INFO L290 TraceCheckUtils]: 90: Hoare triple {29319#false} assume 1 == ~t9_pc~0; {29319#false} is VALID [2022-02-21 04:23:02,967 INFO L290 TraceCheckUtils]: 91: Hoare triple {29319#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {29319#false} is VALID [2022-02-21 04:23:02,967 INFO L290 TraceCheckUtils]: 92: Hoare triple {29319#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 93: Hoare triple {29319#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 94: Hoare triple {29319#false} assume !(0 != activate_threads_~tmp___8~0#1); {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 95: Hoare triple {29319#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 96: Hoare triple {29319#false} assume !(1 == ~M_E~0); {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 97: Hoare triple {29319#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 98: Hoare triple {29319#false} assume !(1 == ~T2_E~0); {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 99: Hoare triple {29319#false} assume !(1 == ~T3_E~0); {29319#false} is VALID [2022-02-21 04:23:02,968 INFO L290 TraceCheckUtils]: 100: Hoare triple {29319#false} assume !(1 == ~T4_E~0); {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 101: Hoare triple {29319#false} assume !(1 == ~T5_E~0); {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 102: Hoare triple {29319#false} assume !(1 == ~T6_E~0); {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 103: Hoare triple {29319#false} assume !(1 == ~T7_E~0); {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 104: Hoare triple {29319#false} assume !(1 == ~T8_E~0); {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 105: Hoare triple {29319#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 106: Hoare triple {29319#false} assume !(1 == ~E_M~0); {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 107: Hoare triple {29319#false} assume !(1 == ~E_1~0); {29319#false} is VALID [2022-02-21 04:23:02,969 INFO L290 TraceCheckUtils]: 108: Hoare triple {29319#false} assume !(1 == ~E_2~0); {29319#false} is VALID [2022-02-21 04:23:02,970 INFO L290 TraceCheckUtils]: 109: Hoare triple {29319#false} assume !(1 == ~E_3~0); {29319#false} is VALID [2022-02-21 04:23:02,970 INFO L290 TraceCheckUtils]: 110: Hoare triple {29319#false} assume !(1 == ~E_4~0); {29319#false} is VALID [2022-02-21 04:23:02,970 INFO L290 TraceCheckUtils]: 111: Hoare triple {29319#false} assume !(1 == ~E_5~0); {29319#false} is VALID [2022-02-21 04:23:02,970 INFO L290 TraceCheckUtils]: 112: Hoare triple {29319#false} assume !(1 == ~E_6~0); {29319#false} is VALID [2022-02-21 04:23:02,970 INFO L290 TraceCheckUtils]: 113: Hoare triple {29319#false} assume 1 == ~E_7~0;~E_7~0 := 2; {29319#false} is VALID [2022-02-21 04:23:02,970 INFO L290 TraceCheckUtils]: 114: Hoare triple {29319#false} assume !(1 == ~E_8~0); {29319#false} is VALID [2022-02-21 04:23:02,970 INFO L290 TraceCheckUtils]: 115: Hoare triple {29319#false} assume !(1 == ~E_9~0); {29319#false} is VALID [2022-02-21 04:23:02,971 INFO L290 TraceCheckUtils]: 116: Hoare triple {29319#false} assume { :end_inline_reset_delta_events } true; {29319#false} is VALID [2022-02-21 04:23:02,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:02,971 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:02,971 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114834987] [2022-02-21 04:23:02,971 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114834987] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:02,972 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:02,972 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:02,972 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [807914939] [2022-02-21 04:23:02,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:02,972 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:02,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,973 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 3 times [2022-02-21 04:23:02,973 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,973 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431652899] [2022-02-21 04:23:02,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:03,012 INFO L290 TraceCheckUtils]: 0: Hoare triple {29321#true} assume !false; {29321#true} is VALID [2022-02-21 04:23:03,012 INFO L290 TraceCheckUtils]: 1: Hoare triple {29321#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {29321#true} is VALID [2022-02-21 04:23:03,012 INFO L290 TraceCheckUtils]: 2: Hoare triple {29321#true} assume !false; {29321#true} is VALID [2022-02-21 04:23:03,013 INFO L290 TraceCheckUtils]: 3: Hoare triple {29321#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {29321#true} is VALID [2022-02-21 04:23:03,013 INFO L290 TraceCheckUtils]: 4: Hoare triple {29321#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {29321#true} is VALID [2022-02-21 04:23:03,013 INFO L290 TraceCheckUtils]: 5: Hoare triple {29321#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {29321#true} is VALID [2022-02-21 04:23:03,013 INFO L290 TraceCheckUtils]: 6: Hoare triple {29321#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {29321#true} is VALID [2022-02-21 04:23:03,013 INFO L290 TraceCheckUtils]: 7: Hoare triple {29321#true} assume !(0 != eval_~tmp~0#1); {29321#true} is VALID [2022-02-21 04:23:03,013 INFO L290 TraceCheckUtils]: 8: Hoare triple {29321#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {29321#true} is VALID [2022-02-21 04:23:03,013 INFO L290 TraceCheckUtils]: 9: Hoare triple {29321#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 10: Hoare triple {29321#true} assume !(0 == ~M_E~0); {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 11: Hoare triple {29321#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 12: Hoare triple {29321#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 13: Hoare triple {29321#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 14: Hoare triple {29321#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 15: Hoare triple {29321#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 16: Hoare triple {29321#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,014 INFO L290 TraceCheckUtils]: 17: Hoare triple {29321#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,015 INFO L290 TraceCheckUtils]: 18: Hoare triple {29321#true} assume !(0 == ~T8_E~0); {29321#true} is VALID [2022-02-21 04:23:03,015 INFO L290 TraceCheckUtils]: 19: Hoare triple {29321#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,015 INFO L290 TraceCheckUtils]: 20: Hoare triple {29321#true} assume 0 == ~E_M~0;~E_M~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,015 INFO L290 TraceCheckUtils]: 21: Hoare triple {29321#true} assume 0 == ~E_1~0;~E_1~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,015 INFO L290 TraceCheckUtils]: 22: Hoare triple {29321#true} assume 0 == ~E_2~0;~E_2~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,015 INFO L290 TraceCheckUtils]: 23: Hoare triple {29321#true} assume 0 == ~E_3~0;~E_3~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,015 INFO L290 TraceCheckUtils]: 24: Hoare triple {29321#true} assume 0 == ~E_4~0;~E_4~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 25: Hoare triple {29321#true} assume 0 == ~E_5~0;~E_5~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 26: Hoare triple {29321#true} assume !(0 == ~E_6~0); {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 27: Hoare triple {29321#true} assume 0 == ~E_7~0;~E_7~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 28: Hoare triple {29321#true} assume 0 == ~E_8~0;~E_8~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 29: Hoare triple {29321#true} assume 0 == ~E_9~0;~E_9~0 := 1; {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 30: Hoare triple {29321#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 31: Hoare triple {29321#true} assume 1 == ~m_pc~0; {29321#true} is VALID [2022-02-21 04:23:03,016 INFO L290 TraceCheckUtils]: 32: Hoare triple {29321#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {29321#true} is VALID [2022-02-21 04:23:03,017 INFO L290 TraceCheckUtils]: 33: Hoare triple {29321#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {29321#true} is VALID [2022-02-21 04:23:03,017 INFO L290 TraceCheckUtils]: 34: Hoare triple {29321#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {29321#true} is VALID [2022-02-21 04:23:03,017 INFO L290 TraceCheckUtils]: 35: Hoare triple {29321#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {29321#true} is VALID [2022-02-21 04:23:03,017 INFO L290 TraceCheckUtils]: 36: Hoare triple {29321#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {29321#true} is VALID [2022-02-21 04:23:03,017 INFO L290 TraceCheckUtils]: 37: Hoare triple {29321#true} assume !(1 == ~t1_pc~0); {29321#true} is VALID [2022-02-21 04:23:03,017 INFO L290 TraceCheckUtils]: 38: Hoare triple {29321#true} is_transmit1_triggered_~__retres1~1#1 := 0; {29321#true} is VALID [2022-02-21 04:23:03,017 INFO L290 TraceCheckUtils]: 39: Hoare triple {29321#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 40: Hoare triple {29321#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 41: Hoare triple {29321#true} assume !(0 != activate_threads_~tmp___0~0#1); {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 42: Hoare triple {29321#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 43: Hoare triple {29321#true} assume 1 == ~t2_pc~0; {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 44: Hoare triple {29321#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 45: Hoare triple {29321#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 46: Hoare triple {29321#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {29321#true} is VALID [2022-02-21 04:23:03,018 INFO L290 TraceCheckUtils]: 47: Hoare triple {29321#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 48: Hoare triple {29321#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 49: Hoare triple {29321#true} assume !(1 == ~t3_pc~0); {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 50: Hoare triple {29321#true} is_transmit3_triggered_~__retres1~3#1 := 0; {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 51: Hoare triple {29321#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 52: Hoare triple {29321#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 53: Hoare triple {29321#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 54: Hoare triple {29321#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {29321#true} is VALID [2022-02-21 04:23:03,019 INFO L290 TraceCheckUtils]: 55: Hoare triple {29321#true} assume 1 == ~t4_pc~0; {29321#true} is VALID [2022-02-21 04:23:03,020 INFO L290 TraceCheckUtils]: 56: Hoare triple {29321#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {29321#true} is VALID [2022-02-21 04:23:03,020 INFO L290 TraceCheckUtils]: 57: Hoare triple {29321#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {29321#true} is VALID [2022-02-21 04:23:03,020 INFO L290 TraceCheckUtils]: 58: Hoare triple {29321#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {29321#true} is VALID [2022-02-21 04:23:03,020 INFO L290 TraceCheckUtils]: 59: Hoare triple {29321#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {29321#true} is VALID [2022-02-21 04:23:03,020 INFO L290 TraceCheckUtils]: 60: Hoare triple {29321#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {29321#true} is VALID [2022-02-21 04:23:03,020 INFO L290 TraceCheckUtils]: 61: Hoare triple {29321#true} assume !(1 == ~t5_pc~0); {29321#true} is VALID [2022-02-21 04:23:03,020 INFO L290 TraceCheckUtils]: 62: Hoare triple {29321#true} is_transmit5_triggered_~__retres1~5#1 := 0; {29321#true} is VALID [2022-02-21 04:23:03,021 INFO L290 TraceCheckUtils]: 63: Hoare triple {29321#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {29321#true} is VALID [2022-02-21 04:23:03,021 INFO L290 TraceCheckUtils]: 64: Hoare triple {29321#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {29321#true} is VALID [2022-02-21 04:23:03,021 INFO L290 TraceCheckUtils]: 65: Hoare triple {29321#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {29321#true} is VALID [2022-02-21 04:23:03,021 INFO L290 TraceCheckUtils]: 66: Hoare triple {29321#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {29321#true} is VALID [2022-02-21 04:23:03,021 INFO L290 TraceCheckUtils]: 67: Hoare triple {29321#true} assume 1 == ~t6_pc~0; {29321#true} is VALID [2022-02-21 04:23:03,022 INFO L290 TraceCheckUtils]: 68: Hoare triple {29321#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,022 INFO L290 TraceCheckUtils]: 69: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,022 INFO L290 TraceCheckUtils]: 70: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,023 INFO L290 TraceCheckUtils]: 71: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,023 INFO L290 TraceCheckUtils]: 72: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,023 INFO L290 TraceCheckUtils]: 73: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,024 INFO L290 TraceCheckUtils]: 74: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,024 INFO L290 TraceCheckUtils]: 75: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,024 INFO L290 TraceCheckUtils]: 76: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,025 INFO L290 TraceCheckUtils]: 77: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,025 INFO L290 TraceCheckUtils]: 78: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,025 INFO L290 TraceCheckUtils]: 79: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,026 INFO L290 TraceCheckUtils]: 80: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,026 INFO L290 TraceCheckUtils]: 81: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,026 INFO L290 TraceCheckUtils]: 82: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,027 INFO L290 TraceCheckUtils]: 83: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,027 INFO L290 TraceCheckUtils]: 84: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,027 INFO L290 TraceCheckUtils]: 85: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t9_pc~0); {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,028 INFO L290 TraceCheckUtils]: 86: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,028 INFO L290 TraceCheckUtils]: 87: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,028 INFO L290 TraceCheckUtils]: 88: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,029 INFO L290 TraceCheckUtils]: 89: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,029 INFO L290 TraceCheckUtils]: 90: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,029 INFO L290 TraceCheckUtils]: 91: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,030 INFO L290 TraceCheckUtils]: 92: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,030 INFO L290 TraceCheckUtils]: 93: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,030 INFO L290 TraceCheckUtils]: 94: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,031 INFO L290 TraceCheckUtils]: 95: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,031 INFO L290 TraceCheckUtils]: 96: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,031 INFO L290 TraceCheckUtils]: 97: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,032 INFO L290 TraceCheckUtils]: 98: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,032 INFO L290 TraceCheckUtils]: 99: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,032 INFO L290 TraceCheckUtils]: 100: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,032 INFO L290 TraceCheckUtils]: 101: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,033 INFO L290 TraceCheckUtils]: 102: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,033 INFO L290 TraceCheckUtils]: 103: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,033 INFO L290 TraceCheckUtils]: 104: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,034 INFO L290 TraceCheckUtils]: 105: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,034 INFO L290 TraceCheckUtils]: 106: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {29323#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 107: Hoare triple {29323#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {29322#false} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 108: Hoare triple {29322#false} assume 1 == ~E_7~0;~E_7~0 := 2; {29322#false} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 109: Hoare triple {29322#false} assume 1 == ~E_8~0;~E_8~0 := 2; {29322#false} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 110: Hoare triple {29322#false} assume 1 == ~E_9~0;~E_9~0 := 2; {29322#false} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 111: Hoare triple {29322#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {29322#false} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 112: Hoare triple {29322#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {29322#false} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 113: Hoare triple {29322#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {29322#false} is VALID [2022-02-21 04:23:03,035 INFO L290 TraceCheckUtils]: 114: Hoare triple {29322#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {29322#false} is VALID [2022-02-21 04:23:03,036 INFO L290 TraceCheckUtils]: 115: Hoare triple {29322#false} assume !(0 == start_simulation_~tmp~3#1); {29322#false} is VALID [2022-02-21 04:23:03,036 INFO L290 TraceCheckUtils]: 116: Hoare triple {29322#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {29322#false} is VALID [2022-02-21 04:23:03,036 INFO L290 TraceCheckUtils]: 117: Hoare triple {29322#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {29322#false} is VALID [2022-02-21 04:23:03,036 INFO L290 TraceCheckUtils]: 118: Hoare triple {29322#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {29322#false} is VALID [2022-02-21 04:23:03,036 INFO L290 TraceCheckUtils]: 119: Hoare triple {29322#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {29322#false} is VALID [2022-02-21 04:23:03,036 INFO L290 TraceCheckUtils]: 120: Hoare triple {29322#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {29322#false} is VALID [2022-02-21 04:23:03,036 INFO L290 TraceCheckUtils]: 121: Hoare triple {29322#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {29322#false} is VALID [2022-02-21 04:23:03,037 INFO L290 TraceCheckUtils]: 122: Hoare triple {29322#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {29322#false} is VALID [2022-02-21 04:23:03,037 INFO L290 TraceCheckUtils]: 123: Hoare triple {29322#false} assume !(0 != start_simulation_~tmp___0~1#1); {29322#false} is VALID [2022-02-21 04:23:03,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:03,037 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:03,037 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431652899] [2022-02-21 04:23:03,038 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431652899] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:03,038 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:03,038 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:03,038 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445675148] [2022-02-21 04:23:03,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:03,038 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:03,039 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:03,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:03,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:03,040 INFO L87 Difference]: Start difference. First operand 1170 states and 1737 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:03,988 INFO L93 Difference]: Finished difference Result 1170 states and 1736 transitions. [2022-02-21 04:23:03,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:03,988 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,079 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:04,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,131 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:04,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1736 transitions. [2022-02-21 04:23:04,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:23:04,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:23:04,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:04,183 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2022-02-21 04:23:04,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:23:04,198 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:04,200 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1736 transitions. Second operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,201 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1736 transitions. Second operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,203 INFO L87 Difference]: Start difference. First operand 1170 states and 1736 transitions. Second operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,249 INFO L93 Difference]: Finished difference Result 1170 states and 1736 transitions. [2022-02-21 04:23:04,249 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,251 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,251 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,253 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,255 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,304 INFO L93 Difference]: Finished difference Result 1170 states and 1736 transitions. [2022-02-21 04:23:04,304 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,306 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,306 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,306 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:04,306 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:04,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1736 transitions. [2022-02-21 04:23:04,357 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2022-02-21 04:23:04,357 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2022-02-21 04:23:04,357 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:04,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1736 transitions. [2022-02-21 04:23:04,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:04,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:04,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:04,363 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,363 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,364 INFO L791 eck$LassoCheckResult]: Stem: 31366#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 31367#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 31316#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31317#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31535#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 31202#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31203#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31512#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31011#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31012#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31438#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31439#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30510#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30511#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30714#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31102#L939 assume !(0 == ~M_E~0); 31346#L939-2 assume !(0 == ~T1_E~0); 31347#L944-1 assume !(0 == ~T2_E~0); 31131#L949-1 assume !(0 == ~T3_E~0); 31129#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31130#L959-1 assume !(0 == ~T5_E~0); 31549#L964-1 assume !(0 == ~T6_E~0); 30862#L969-1 assume !(0 == ~T7_E~0); 30863#L974-1 assume !(0 == ~T8_E~0); 31500#L979-1 assume !(0 == ~T9_E~0); 31501#L984-1 assume !(0 == ~E_M~0); 31023#L989-1 assume !(0 == ~E_1~0); 31024#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 30912#L999-1 assume !(0 == ~E_3~0); 30913#L1004-1 assume !(0 == ~E_4~0); 30578#L1009-1 assume !(0 == ~E_5~0); 30579#L1014-1 assume !(0 == ~E_6~0); 30904#L1019-1 assume !(0 == ~E_7~0); 31445#L1024-1 assume !(0 == ~E_8~0); 30835#L1029-1 assume !(0 == ~E_9~0); 30836#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30926#L460 assume 1 == ~m_pc~0; 30494#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30495#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31411#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31650#L1167 assume !(0 != activate_threads_~tmp~1#1); 31119#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31120#L479 assume 1 == ~t1_pc~0; 31103#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31104#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31607#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30847#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 30848#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30696#L498 assume !(1 == ~t2_pc~0); 30697#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31100#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31101#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31478#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31401#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31402#L517 assume 1 == ~t3_pc~0; 31609#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31610#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31174#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30880#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 30881#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31454#L536 assume !(1 == ~t4_pc~0); 31164#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31163#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31540#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31156#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 31157#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31374#L555 assume 1 == ~t5_pc~0; 31375#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31446#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30609#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30610#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 30717#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30617#L574 assume !(1 == ~t6_pc~0); 30618#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31249#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30722#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30723#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 31472#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31634#L593 assume 1 == ~t7_pc~0; 31635#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30854#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31552#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31655#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 31615#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31018#L612 assume !(1 == ~t8_pc~0); 31019#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31428#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31286#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31287#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 31251#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31252#L631 assume 1 == ~t9_pc~0; 31270#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30608#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30576#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30577#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 31106#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31457#L1047 assume !(1 == ~M_E~0); 30546#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30547#L1052-1 assume !(1 == ~T2_E~0); 30529#L1057-1 assume !(1 == ~T3_E~0); 30530#L1062-1 assume !(1 == ~T4_E~0); 30819#L1067-1 assume !(1 == ~T5_E~0); 31122#L1072-1 assume !(1 == ~T6_E~0); 31123#L1077-1 assume !(1 == ~T7_E~0); 30710#L1082-1 assume !(1 == ~T8_E~0); 30711#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30502#L1092-1 assume !(1 == ~E_M~0); 30503#L1097-1 assume !(1 == ~E_1~0); 30531#L1102-1 assume !(1 == ~E_2~0); 31312#L1107-1 assume !(1 == ~E_3~0); 31247#L1112-1 assume !(1 == ~E_4~0); 31248#L1117-1 assume !(1 == ~E_5~0); 31288#L1122-1 assume !(1 == ~E_6~0); 31175#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30929#L1132-1 assume !(1 == ~E_8~0); 30930#L1137-1 assume !(1 == ~E_9~0); 30818#L1142-1 assume { :end_inline_reset_delta_events } true; 30678#L1428-2 [2022-02-21 04:23:04,365 INFO L793 eck$LassoCheckResult]: Loop: 30678#L1428-2 assume !false; 30679#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30753#L914 assume !false; 31243#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 31244#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 30515#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 30516#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31475#L783 assume !(0 != eval_~tmp~0#1); 30915#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30916#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31311#L939-3 assume !(0 == ~M_E~0); 30734#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30735#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30500#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30501#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31137#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30580#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30581#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30787#L974-3 assume !(0 == ~T8_E~0); 30788#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31218#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31219#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30841#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30842#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31353#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30664#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30665#L1014-3 assume !(0 == ~E_6~0); 31204#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31205#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31186#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31138#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31139#L460-33 assume 1 == ~m_pc~0; 31176#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31177#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30933#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30508#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30509#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30869#L479-33 assume !(1 == ~t1_pc~0); 30870#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 30837#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30838#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31422#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 31595#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30878#L498-33 assume 1 == ~t2_pc~0; 30879#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30624#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30758#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30759#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30736#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30737#L517-33 assume !(1 == ~t3_pc~0); 31643#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 31526#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31527#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31339#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31340#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30965#L536-33 assume 1 == ~t4_pc~0; 30966#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31035#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31036#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31226#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31505#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30555#L555-33 assume !(1 == ~t5_pc~0); 30556#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 31281#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30828#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30829#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31308#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30526#L574-33 assume !(1 == ~t6_pc~0); 30528#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 31517#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30843#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30844#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31097#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30602#L593-33 assume !(1 == ~t7_pc~0); 30603#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 31058#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30708#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30709#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31368#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31495#L612-33 assume 1 == ~t8_pc~0; 31622#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31586#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31587#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31429#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30706#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30707#L631-33 assume !(1 == ~t9_pc~0); 31315#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 30648#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30649#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30903#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30760#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30761#L1047-3 assume !(1 == ~M_E~0); 30934#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31548#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31480#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31481#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30659#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30660#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31042#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30887#L1082-3 assume !(1 == ~T8_E~0); 30888#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30961#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31242#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31172#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31173#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31518#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30882#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30883#L1122-3 assume !(1 == ~E_6~0); 30935#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30936#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31325#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31302#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 30765#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 30643#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 31303#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 31060#L1447 assume !(0 == start_simulation_~tmp~3#1); 31061#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 31499#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 30801#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 31326#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 30911#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 30668#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30669#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 31124#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 30678#L1428-2 [2022-02-21 04:23:04,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,365 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2022-02-21 04:23:04,365 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,366 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327022233] [2022-02-21 04:23:04,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,392 INFO L290 TraceCheckUtils]: 0: Hoare triple {34007#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {34007#true} is VALID [2022-02-21 04:23:04,392 INFO L290 TraceCheckUtils]: 1: Hoare triple {34007#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,392 INFO L290 TraceCheckUtils]: 2: Hoare triple {34009#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,393 INFO L290 TraceCheckUtils]: 3: Hoare triple {34009#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,393 INFO L290 TraceCheckUtils]: 4: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,393 INFO L290 TraceCheckUtils]: 5: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,394 INFO L290 TraceCheckUtils]: 6: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,394 INFO L290 TraceCheckUtils]: 7: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,394 INFO L290 TraceCheckUtils]: 8: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,395 INFO L290 TraceCheckUtils]: 9: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,395 INFO L290 TraceCheckUtils]: 10: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,395 INFO L290 TraceCheckUtils]: 11: Hoare triple {34009#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {34009#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:04,396 INFO L290 TraceCheckUtils]: 12: Hoare triple {34009#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {34008#false} is VALID [2022-02-21 04:23:04,396 INFO L290 TraceCheckUtils]: 13: Hoare triple {34008#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {34008#false} is VALID [2022-02-21 04:23:04,396 INFO L290 TraceCheckUtils]: 14: Hoare triple {34008#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34008#false} is VALID [2022-02-21 04:23:04,396 INFO L290 TraceCheckUtils]: 15: Hoare triple {34008#false} assume !(0 == ~M_E~0); {34008#false} is VALID [2022-02-21 04:23:04,396 INFO L290 TraceCheckUtils]: 16: Hoare triple {34008#false} assume !(0 == ~T1_E~0); {34008#false} is VALID [2022-02-21 04:23:04,396 INFO L290 TraceCheckUtils]: 17: Hoare triple {34008#false} assume !(0 == ~T2_E~0); {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 18: Hoare triple {34008#false} assume !(0 == ~T3_E~0); {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 19: Hoare triple {34008#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 20: Hoare triple {34008#false} assume !(0 == ~T5_E~0); {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 21: Hoare triple {34008#false} assume !(0 == ~T6_E~0); {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 22: Hoare triple {34008#false} assume !(0 == ~T7_E~0); {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 23: Hoare triple {34008#false} assume !(0 == ~T8_E~0); {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 24: Hoare triple {34008#false} assume !(0 == ~T9_E~0); {34008#false} is VALID [2022-02-21 04:23:04,397 INFO L290 TraceCheckUtils]: 25: Hoare triple {34008#false} assume !(0 == ~E_M~0); {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 26: Hoare triple {34008#false} assume !(0 == ~E_1~0); {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 27: Hoare triple {34008#false} assume 0 == ~E_2~0;~E_2~0 := 1; {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 28: Hoare triple {34008#false} assume !(0 == ~E_3~0); {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 29: Hoare triple {34008#false} assume !(0 == ~E_4~0); {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 30: Hoare triple {34008#false} assume !(0 == ~E_5~0); {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 31: Hoare triple {34008#false} assume !(0 == ~E_6~0); {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 32: Hoare triple {34008#false} assume !(0 == ~E_7~0); {34008#false} is VALID [2022-02-21 04:23:04,398 INFO L290 TraceCheckUtils]: 33: Hoare triple {34008#false} assume !(0 == ~E_8~0); {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 34: Hoare triple {34008#false} assume !(0 == ~E_9~0); {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 35: Hoare triple {34008#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 36: Hoare triple {34008#false} assume 1 == ~m_pc~0; {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 37: Hoare triple {34008#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 38: Hoare triple {34008#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 39: Hoare triple {34008#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 40: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp~1#1); {34008#false} is VALID [2022-02-21 04:23:04,399 INFO L290 TraceCheckUtils]: 41: Hoare triple {34008#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34008#false} is VALID [2022-02-21 04:23:04,400 INFO L290 TraceCheckUtils]: 42: Hoare triple {34008#false} assume 1 == ~t1_pc~0; {34008#false} is VALID [2022-02-21 04:23:04,400 INFO L290 TraceCheckUtils]: 43: Hoare triple {34008#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34008#false} is VALID [2022-02-21 04:23:04,400 INFO L290 TraceCheckUtils]: 44: Hoare triple {34008#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34008#false} is VALID [2022-02-21 04:23:04,400 INFO L290 TraceCheckUtils]: 45: Hoare triple {34008#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34008#false} is VALID [2022-02-21 04:23:04,400 INFO L290 TraceCheckUtils]: 46: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___0~0#1); {34008#false} is VALID [2022-02-21 04:23:04,400 INFO L290 TraceCheckUtils]: 47: Hoare triple {34008#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34008#false} is VALID [2022-02-21 04:23:04,400 INFO L290 TraceCheckUtils]: 48: Hoare triple {34008#false} assume !(1 == ~t2_pc~0); {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 49: Hoare triple {34008#false} is_transmit2_triggered_~__retres1~2#1 := 0; {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 50: Hoare triple {34008#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 51: Hoare triple {34008#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 52: Hoare triple {34008#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 53: Hoare triple {34008#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 54: Hoare triple {34008#false} assume 1 == ~t3_pc~0; {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 55: Hoare triple {34008#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34008#false} is VALID [2022-02-21 04:23:04,401 INFO L290 TraceCheckUtils]: 56: Hoare triple {34008#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34008#false} is VALID [2022-02-21 04:23:04,402 INFO L290 TraceCheckUtils]: 57: Hoare triple {34008#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34008#false} is VALID [2022-02-21 04:23:04,402 INFO L290 TraceCheckUtils]: 58: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___2~0#1); {34008#false} is VALID [2022-02-21 04:23:04,402 INFO L290 TraceCheckUtils]: 59: Hoare triple {34008#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34008#false} is VALID [2022-02-21 04:23:04,402 INFO L290 TraceCheckUtils]: 60: Hoare triple {34008#false} assume !(1 == ~t4_pc~0); {34008#false} is VALID [2022-02-21 04:23:04,402 INFO L290 TraceCheckUtils]: 61: Hoare triple {34008#false} is_transmit4_triggered_~__retres1~4#1 := 0; {34008#false} is VALID [2022-02-21 04:23:04,402 INFO L290 TraceCheckUtils]: 62: Hoare triple {34008#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34008#false} is VALID [2022-02-21 04:23:04,402 INFO L290 TraceCheckUtils]: 63: Hoare triple {34008#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 64: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___3~0#1); {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 65: Hoare triple {34008#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 66: Hoare triple {34008#false} assume 1 == ~t5_pc~0; {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 67: Hoare triple {34008#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 68: Hoare triple {34008#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 69: Hoare triple {34008#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 70: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___4~0#1); {34008#false} is VALID [2022-02-21 04:23:04,403 INFO L290 TraceCheckUtils]: 71: Hoare triple {34008#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 72: Hoare triple {34008#false} assume !(1 == ~t6_pc~0); {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 73: Hoare triple {34008#false} is_transmit6_triggered_~__retres1~6#1 := 0; {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 74: Hoare triple {34008#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 75: Hoare triple {34008#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 76: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___5~0#1); {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 77: Hoare triple {34008#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 78: Hoare triple {34008#false} assume 1 == ~t7_pc~0; {34008#false} is VALID [2022-02-21 04:23:04,404 INFO L290 TraceCheckUtils]: 79: Hoare triple {34008#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 80: Hoare triple {34008#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 81: Hoare triple {34008#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 82: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___6~0#1); {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 83: Hoare triple {34008#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 84: Hoare triple {34008#false} assume !(1 == ~t8_pc~0); {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 85: Hoare triple {34008#false} is_transmit8_triggered_~__retres1~8#1 := 0; {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 86: Hoare triple {34008#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34008#false} is VALID [2022-02-21 04:23:04,405 INFO L290 TraceCheckUtils]: 87: Hoare triple {34008#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 88: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___7~0#1); {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 89: Hoare triple {34008#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 90: Hoare triple {34008#false} assume 1 == ~t9_pc~0; {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 91: Hoare triple {34008#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 92: Hoare triple {34008#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 93: Hoare triple {34008#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 94: Hoare triple {34008#false} assume !(0 != activate_threads_~tmp___8~0#1); {34008#false} is VALID [2022-02-21 04:23:04,406 INFO L290 TraceCheckUtils]: 95: Hoare triple {34008#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34008#false} is VALID [2022-02-21 04:23:04,407 INFO L290 TraceCheckUtils]: 96: Hoare triple {34008#false} assume !(1 == ~M_E~0); {34008#false} is VALID [2022-02-21 04:23:04,407 INFO L290 TraceCheckUtils]: 97: Hoare triple {34008#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34008#false} is VALID [2022-02-21 04:23:04,407 INFO L290 TraceCheckUtils]: 98: Hoare triple {34008#false} assume !(1 == ~T2_E~0); {34008#false} is VALID [2022-02-21 04:23:04,407 INFO L290 TraceCheckUtils]: 99: Hoare triple {34008#false} assume !(1 == ~T3_E~0); {34008#false} is VALID [2022-02-21 04:23:04,407 INFO L290 TraceCheckUtils]: 100: Hoare triple {34008#false} assume !(1 == ~T4_E~0); {34008#false} is VALID [2022-02-21 04:23:04,407 INFO L290 TraceCheckUtils]: 101: Hoare triple {34008#false} assume !(1 == ~T5_E~0); {34008#false} is VALID [2022-02-21 04:23:04,407 INFO L290 TraceCheckUtils]: 102: Hoare triple {34008#false} assume !(1 == ~T6_E~0); {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 103: Hoare triple {34008#false} assume !(1 == ~T7_E~0); {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 104: Hoare triple {34008#false} assume !(1 == ~T8_E~0); {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 105: Hoare triple {34008#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 106: Hoare triple {34008#false} assume !(1 == ~E_M~0); {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 107: Hoare triple {34008#false} assume !(1 == ~E_1~0); {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 108: Hoare triple {34008#false} assume !(1 == ~E_2~0); {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 109: Hoare triple {34008#false} assume !(1 == ~E_3~0); {34008#false} is VALID [2022-02-21 04:23:04,408 INFO L290 TraceCheckUtils]: 110: Hoare triple {34008#false} assume !(1 == ~E_4~0); {34008#false} is VALID [2022-02-21 04:23:04,409 INFO L290 TraceCheckUtils]: 111: Hoare triple {34008#false} assume !(1 == ~E_5~0); {34008#false} is VALID [2022-02-21 04:23:04,409 INFO L290 TraceCheckUtils]: 112: Hoare triple {34008#false} assume !(1 == ~E_6~0); {34008#false} is VALID [2022-02-21 04:23:04,409 INFO L290 TraceCheckUtils]: 113: Hoare triple {34008#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34008#false} is VALID [2022-02-21 04:23:04,409 INFO L290 TraceCheckUtils]: 114: Hoare triple {34008#false} assume !(1 == ~E_8~0); {34008#false} is VALID [2022-02-21 04:23:04,409 INFO L290 TraceCheckUtils]: 115: Hoare triple {34008#false} assume !(1 == ~E_9~0); {34008#false} is VALID [2022-02-21 04:23:04,409 INFO L290 TraceCheckUtils]: 116: Hoare triple {34008#false} assume { :end_inline_reset_delta_events } true; {34008#false} is VALID [2022-02-21 04:23:04,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,410 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,410 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327022233] [2022-02-21 04:23:04,410 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327022233] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,411 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,411 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:04,412 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424270465] [2022-02-21 04:23:04,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,412 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:04,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,413 INFO L85 PathProgramCache]: Analyzing trace with hash -466631152, now seen corresponding path program 1 times [2022-02-21 04:23:04,413 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,413 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58153910] [2022-02-21 04:23:04,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,458 INFO L290 TraceCheckUtils]: 0: Hoare triple {34010#true} assume !false; {34010#true} is VALID [2022-02-21 04:23:04,459 INFO L290 TraceCheckUtils]: 1: Hoare triple {34010#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34010#true} is VALID [2022-02-21 04:23:04,459 INFO L290 TraceCheckUtils]: 2: Hoare triple {34010#true} assume !false; {34010#true} is VALID [2022-02-21 04:23:04,459 INFO L290 TraceCheckUtils]: 3: Hoare triple {34010#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {34010#true} is VALID [2022-02-21 04:23:04,460 INFO L290 TraceCheckUtils]: 4: Hoare triple {34010#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {34012#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} is VALID [2022-02-21 04:23:04,460 INFO L290 TraceCheckUtils]: 5: Hoare triple {34012#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {34013#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:23:04,461 INFO L290 TraceCheckUtils]: 6: Hoare triple {34013#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {34014#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:23:04,461 INFO L290 TraceCheckUtils]: 7: Hoare triple {34014#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {34011#false} is VALID [2022-02-21 04:23:04,461 INFO L290 TraceCheckUtils]: 8: Hoare triple {34011#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34011#false} is VALID [2022-02-21 04:23:04,461 INFO L290 TraceCheckUtils]: 9: Hoare triple {34011#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34011#false} is VALID [2022-02-21 04:23:04,461 INFO L290 TraceCheckUtils]: 10: Hoare triple {34011#false} assume !(0 == ~M_E~0); {34011#false} is VALID [2022-02-21 04:23:04,461 INFO L290 TraceCheckUtils]: 11: Hoare triple {34011#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,462 INFO L290 TraceCheckUtils]: 12: Hoare triple {34011#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,462 INFO L290 TraceCheckUtils]: 13: Hoare triple {34011#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,462 INFO L290 TraceCheckUtils]: 14: Hoare triple {34011#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,462 INFO L290 TraceCheckUtils]: 15: Hoare triple {34011#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,462 INFO L290 TraceCheckUtils]: 16: Hoare triple {34011#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,462 INFO L290 TraceCheckUtils]: 17: Hoare triple {34011#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,462 INFO L290 TraceCheckUtils]: 18: Hoare triple {34011#false} assume !(0 == ~T8_E~0); {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 19: Hoare triple {34011#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 20: Hoare triple {34011#false} assume 0 == ~E_M~0;~E_M~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 21: Hoare triple {34011#false} assume 0 == ~E_1~0;~E_1~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 22: Hoare triple {34011#false} assume 0 == ~E_2~0;~E_2~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 23: Hoare triple {34011#false} assume 0 == ~E_3~0;~E_3~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 24: Hoare triple {34011#false} assume 0 == ~E_4~0;~E_4~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 25: Hoare triple {34011#false} assume 0 == ~E_5~0;~E_5~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,463 INFO L290 TraceCheckUtils]: 26: Hoare triple {34011#false} assume !(0 == ~E_6~0); {34011#false} is VALID [2022-02-21 04:23:04,464 INFO L290 TraceCheckUtils]: 27: Hoare triple {34011#false} assume 0 == ~E_7~0;~E_7~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,464 INFO L290 TraceCheckUtils]: 28: Hoare triple {34011#false} assume 0 == ~E_8~0;~E_8~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,464 INFO L290 TraceCheckUtils]: 29: Hoare triple {34011#false} assume 0 == ~E_9~0;~E_9~0 := 1; {34011#false} is VALID [2022-02-21 04:23:04,464 INFO L290 TraceCheckUtils]: 30: Hoare triple {34011#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34011#false} is VALID [2022-02-21 04:23:04,464 INFO L290 TraceCheckUtils]: 31: Hoare triple {34011#false} assume 1 == ~m_pc~0; {34011#false} is VALID [2022-02-21 04:23:04,464 INFO L290 TraceCheckUtils]: 32: Hoare triple {34011#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34011#false} is VALID [2022-02-21 04:23:04,464 INFO L290 TraceCheckUtils]: 33: Hoare triple {34011#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 34: Hoare triple {34011#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 35: Hoare triple {34011#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 36: Hoare triple {34011#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 37: Hoare triple {34011#false} assume !(1 == ~t1_pc~0); {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 38: Hoare triple {34011#false} is_transmit1_triggered_~__retres1~1#1 := 0; {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 39: Hoare triple {34011#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 40: Hoare triple {34011#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34011#false} is VALID [2022-02-21 04:23:04,465 INFO L290 TraceCheckUtils]: 41: Hoare triple {34011#false} assume !(0 != activate_threads_~tmp___0~0#1); {34011#false} is VALID [2022-02-21 04:23:04,466 INFO L290 TraceCheckUtils]: 42: Hoare triple {34011#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34011#false} is VALID [2022-02-21 04:23:04,466 INFO L290 TraceCheckUtils]: 43: Hoare triple {34011#false} assume 1 == ~t2_pc~0; {34011#false} is VALID [2022-02-21 04:23:04,466 INFO L290 TraceCheckUtils]: 44: Hoare triple {34011#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34011#false} is VALID [2022-02-21 04:23:04,466 INFO L290 TraceCheckUtils]: 45: Hoare triple {34011#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34011#false} is VALID [2022-02-21 04:23:04,466 INFO L290 TraceCheckUtils]: 46: Hoare triple {34011#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34011#false} is VALID [2022-02-21 04:23:04,466 INFO L290 TraceCheckUtils]: 47: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,466 INFO L290 TraceCheckUtils]: 48: Hoare triple {34011#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 49: Hoare triple {34011#false} assume !(1 == ~t3_pc~0); {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 50: Hoare triple {34011#false} is_transmit3_triggered_~__retres1~3#1 := 0; {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 51: Hoare triple {34011#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 52: Hoare triple {34011#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 53: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 54: Hoare triple {34011#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 55: Hoare triple {34011#false} assume 1 == ~t4_pc~0; {34011#false} is VALID [2022-02-21 04:23:04,467 INFO L290 TraceCheckUtils]: 56: Hoare triple {34011#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34011#false} is VALID [2022-02-21 04:23:04,468 INFO L290 TraceCheckUtils]: 57: Hoare triple {34011#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34011#false} is VALID [2022-02-21 04:23:04,468 INFO L290 TraceCheckUtils]: 58: Hoare triple {34011#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34011#false} is VALID [2022-02-21 04:23:04,468 INFO L290 TraceCheckUtils]: 59: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,468 INFO L290 TraceCheckUtils]: 60: Hoare triple {34011#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34011#false} is VALID [2022-02-21 04:23:04,468 INFO L290 TraceCheckUtils]: 61: Hoare triple {34011#false} assume !(1 == ~t5_pc~0); {34011#false} is VALID [2022-02-21 04:23:04,468 INFO L290 TraceCheckUtils]: 62: Hoare triple {34011#false} is_transmit5_triggered_~__retres1~5#1 := 0; {34011#false} is VALID [2022-02-21 04:23:04,468 INFO L290 TraceCheckUtils]: 63: Hoare triple {34011#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 64: Hoare triple {34011#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 65: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 66: Hoare triple {34011#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 67: Hoare triple {34011#false} assume !(1 == ~t6_pc~0); {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 68: Hoare triple {34011#false} is_transmit6_triggered_~__retres1~6#1 := 0; {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 69: Hoare triple {34011#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 70: Hoare triple {34011#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34011#false} is VALID [2022-02-21 04:23:04,469 INFO L290 TraceCheckUtils]: 71: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,470 INFO L290 TraceCheckUtils]: 72: Hoare triple {34011#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34011#false} is VALID [2022-02-21 04:23:04,470 INFO L290 TraceCheckUtils]: 73: Hoare triple {34011#false} assume !(1 == ~t7_pc~0); {34011#false} is VALID [2022-02-21 04:23:04,470 INFO L290 TraceCheckUtils]: 74: Hoare triple {34011#false} is_transmit7_triggered_~__retres1~7#1 := 0; {34011#false} is VALID [2022-02-21 04:23:04,470 INFO L290 TraceCheckUtils]: 75: Hoare triple {34011#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34011#false} is VALID [2022-02-21 04:23:04,470 INFO L290 TraceCheckUtils]: 76: Hoare triple {34011#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34011#false} is VALID [2022-02-21 04:23:04,470 INFO L290 TraceCheckUtils]: 77: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,470 INFO L290 TraceCheckUtils]: 78: Hoare triple {34011#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 79: Hoare triple {34011#false} assume 1 == ~t8_pc~0; {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 80: Hoare triple {34011#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 81: Hoare triple {34011#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 82: Hoare triple {34011#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 83: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 84: Hoare triple {34011#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 85: Hoare triple {34011#false} assume !(1 == ~t9_pc~0); {34011#false} is VALID [2022-02-21 04:23:04,471 INFO L290 TraceCheckUtils]: 86: Hoare triple {34011#false} is_transmit9_triggered_~__retres1~9#1 := 0; {34011#false} is VALID [2022-02-21 04:23:04,472 INFO L290 TraceCheckUtils]: 87: Hoare triple {34011#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34011#false} is VALID [2022-02-21 04:23:04,472 INFO L290 TraceCheckUtils]: 88: Hoare triple {34011#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34011#false} is VALID [2022-02-21 04:23:04,472 INFO L290 TraceCheckUtils]: 89: Hoare triple {34011#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {34011#false} is VALID [2022-02-21 04:23:04,472 INFO L290 TraceCheckUtils]: 90: Hoare triple {34011#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34011#false} is VALID [2022-02-21 04:23:04,472 INFO L290 TraceCheckUtils]: 91: Hoare triple {34011#false} assume !(1 == ~M_E~0); {34011#false} is VALID [2022-02-21 04:23:04,472 INFO L290 TraceCheckUtils]: 92: Hoare triple {34011#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,472 INFO L290 TraceCheckUtils]: 93: Hoare triple {34011#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 94: Hoare triple {34011#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 95: Hoare triple {34011#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 96: Hoare triple {34011#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 97: Hoare triple {34011#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 98: Hoare triple {34011#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 99: Hoare triple {34011#false} assume !(1 == ~T8_E~0); {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 100: Hoare triple {34011#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,473 INFO L290 TraceCheckUtils]: 101: Hoare triple {34011#false} assume 1 == ~E_M~0;~E_M~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 102: Hoare triple {34011#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 103: Hoare triple {34011#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 104: Hoare triple {34011#false} assume 1 == ~E_3~0;~E_3~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 105: Hoare triple {34011#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 106: Hoare triple {34011#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 107: Hoare triple {34011#false} assume !(1 == ~E_6~0); {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 108: Hoare triple {34011#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,474 INFO L290 TraceCheckUtils]: 109: Hoare triple {34011#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,475 INFO L290 TraceCheckUtils]: 110: Hoare triple {34011#false} assume 1 == ~E_9~0;~E_9~0 := 2; {34011#false} is VALID [2022-02-21 04:23:04,475 INFO L290 TraceCheckUtils]: 111: Hoare triple {34011#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {34011#false} is VALID [2022-02-21 04:23:04,475 INFO L290 TraceCheckUtils]: 112: Hoare triple {34011#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {34011#false} is VALID [2022-02-21 04:23:04,475 INFO L290 TraceCheckUtils]: 113: Hoare triple {34011#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {34011#false} is VALID [2022-02-21 04:23:04,475 INFO L290 TraceCheckUtils]: 114: Hoare triple {34011#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {34011#false} is VALID [2022-02-21 04:23:04,475 INFO L290 TraceCheckUtils]: 115: Hoare triple {34011#false} assume !(0 == start_simulation_~tmp~3#1); {34011#false} is VALID [2022-02-21 04:23:04,475 INFO L290 TraceCheckUtils]: 116: Hoare triple {34011#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {34011#false} is VALID [2022-02-21 04:23:04,476 INFO L290 TraceCheckUtils]: 117: Hoare triple {34011#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {34011#false} is VALID [2022-02-21 04:23:04,476 INFO L290 TraceCheckUtils]: 118: Hoare triple {34011#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {34011#false} is VALID [2022-02-21 04:23:04,476 INFO L290 TraceCheckUtils]: 119: Hoare triple {34011#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {34011#false} is VALID [2022-02-21 04:23:04,476 INFO L290 TraceCheckUtils]: 120: Hoare triple {34011#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {34011#false} is VALID [2022-02-21 04:23:04,476 INFO L290 TraceCheckUtils]: 121: Hoare triple {34011#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34011#false} is VALID [2022-02-21 04:23:04,476 INFO L290 TraceCheckUtils]: 122: Hoare triple {34011#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {34011#false} is VALID [2022-02-21 04:23:04,476 INFO L290 TraceCheckUtils]: 123: Hoare triple {34011#false} assume !(0 != start_simulation_~tmp___0~1#1); {34011#false} is VALID [2022-02-21 04:23:04,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,477 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,479 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58153910] [2022-02-21 04:23:04,481 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58153910] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,481 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,481 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:23:04,481 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038991387] [2022-02-21 04:23:04,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,482 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:04,482 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:04,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:04,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:04,483 INFO L87 Difference]: Start difference. First operand 1170 states and 1736 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,502 INFO L93 Difference]: Finished difference Result 1170 states and 1735 transitions. [2022-02-21 04:23:05,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:05,503 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,587 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:05,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:05,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1735 transitions. [2022-02-21 04:23:05,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2022-02-21 04:23:05,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2022-02-21 04:23:05,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:05,691 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2022-02-21 04:23:05,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2022-02-21 04:23:05,706 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:05,708 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1170 states and 1735 transitions. Second operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,709 INFO L74 IsIncluded]: Start isIncluded. First operand 1170 states and 1735 transitions. Second operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,711 INFO L87 Difference]: Start difference. First operand 1170 states and 1735 transitions. Second operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,758 INFO L93 Difference]: Finished difference Result 1170 states and 1735 transitions. [2022-02-21 04:23:05,758 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,759 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:05,760 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:05,762 INFO L74 IsIncluded]: Start isIncluded. First operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,763 INFO L87 Difference]: Start difference. First operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,811 INFO L93 Difference]: Finished difference Result 1170 states and 1735 transitions. [2022-02-21 04:23:05,811 INFO L276 IsEmpty]: Start isEmpty. Operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,813 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:05,813 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:05,813 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:05,813 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:05,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1735 transitions. [2022-02-21 04:23:05,865 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2022-02-21 04:23:05,865 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2022-02-21 04:23:05,865 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:05,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1735 transitions. [2022-02-21 04:23:05,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2022-02-21 04:23:05,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:05,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:05,870 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,870 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,870 INFO L791 eck$LassoCheckResult]: Stem: 36057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 36058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 36007#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36008#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36226#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 35893#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35894#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36203#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35702#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35703#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36131#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36132#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35201#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35202#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35405#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35793#L939 assume !(0 == ~M_E~0); 36037#L939-2 assume !(0 == ~T1_E~0); 36038#L944-1 assume !(0 == ~T2_E~0); 35822#L949-1 assume !(0 == ~T3_E~0); 35820#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35821#L959-1 assume !(0 == ~T5_E~0); 36240#L964-1 assume !(0 == ~T6_E~0); 35553#L969-1 assume !(0 == ~T7_E~0); 35554#L974-1 assume !(0 == ~T8_E~0); 36191#L979-1 assume !(0 == ~T9_E~0); 36192#L984-1 assume !(0 == ~E_M~0); 35714#L989-1 assume !(0 == ~E_1~0); 35715#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 35603#L999-1 assume !(0 == ~E_3~0); 35604#L1004-1 assume !(0 == ~E_4~0); 35269#L1009-1 assume !(0 == ~E_5~0); 35270#L1014-1 assume !(0 == ~E_6~0); 35597#L1019-1 assume !(0 == ~E_7~0); 36136#L1024-1 assume !(0 == ~E_8~0); 35526#L1029-1 assume !(0 == ~E_9~0); 35527#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35617#L460 assume 1 == ~m_pc~0; 35185#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35186#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36102#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36341#L1167 assume !(0 != activate_threads_~tmp~1#1); 35810#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35811#L479 assume 1 == ~t1_pc~0; 35794#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35795#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36298#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35538#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 35539#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35387#L498 assume !(1 == ~t2_pc~0); 35388#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35791#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35792#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36169#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36093#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36094#L517 assume 1 == ~t3_pc~0; 36302#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36303#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35865#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35571#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 35572#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36147#L536 assume !(1 == ~t4_pc~0); 35855#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35854#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36231#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35847#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 35848#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36067#L555 assume 1 == ~t5_pc~0; 36068#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36137#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35300#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35301#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 35408#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35308#L574 assume !(1 == ~t6_pc~0); 35309#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35940#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35413#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35414#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 36165#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36325#L593 assume 1 == ~t7_pc~0; 36326#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35545#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36243#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36346#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 36306#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35709#L612 assume !(1 == ~t8_pc~0); 35710#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36119#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35977#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35978#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 35944#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35945#L631 assume 1 == ~t9_pc~0; 35961#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35299#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35267#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35268#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 35797#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36148#L1047 assume !(1 == ~M_E~0); 35237#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35238#L1052-1 assume !(1 == ~T2_E~0); 35220#L1057-1 assume !(1 == ~T3_E~0); 35221#L1062-1 assume !(1 == ~T4_E~0); 35510#L1067-1 assume !(1 == ~T5_E~0); 35813#L1072-1 assume !(1 == ~T6_E~0); 35814#L1077-1 assume !(1 == ~T7_E~0); 35401#L1082-1 assume !(1 == ~T8_E~0); 35402#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35195#L1092-1 assume !(1 == ~E_M~0); 35196#L1097-1 assume !(1 == ~E_1~0); 35222#L1102-1 assume !(1 == ~E_2~0); 36003#L1107-1 assume !(1 == ~E_3~0); 35938#L1112-1 assume !(1 == ~E_4~0); 35939#L1117-1 assume !(1 == ~E_5~0); 35979#L1122-1 assume !(1 == ~E_6~0); 35866#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 35622#L1132-1 assume !(1 == ~E_8~0); 35623#L1137-1 assume !(1 == ~E_9~0); 35509#L1142-1 assume { :end_inline_reset_delta_events } true; 35369#L1428-2 [2022-02-21 04:23:05,871 INFO L793 eck$LassoCheckResult]: Loop: 35369#L1428-2 assume !false; 35370#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35444#L914 assume !false; 35934#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 35935#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35206#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 35207#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 36166#L783 assume !(0 != eval_~tmp~0#1); 35606#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35607#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36002#L939-3 assume !(0 == ~M_E~0); 35425#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35426#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35191#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35192#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35828#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35271#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35272#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35478#L974-3 assume !(0 == ~T8_E~0); 35479#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35909#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35910#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35532#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35533#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36044#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35355#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35356#L1014-3 assume !(0 == ~E_6~0); 35895#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35896#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35877#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35829#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35830#L460-33 assume 1 == ~m_pc~0; 35867#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35868#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35624#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35199#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35200#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35561#L479-33 assume !(1 == ~t1_pc~0); 35562#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 35528#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35529#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36113#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 36286#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35569#L498-33 assume 1 == ~t2_pc~0; 35570#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35315#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35451#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35452#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35427#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35428#L517-33 assume !(1 == ~t3_pc~0); 36334#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 36217#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36218#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36030#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36031#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35656#L536-33 assume 1 == ~t4_pc~0; 35657#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35726#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35727#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35917#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36196#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35246#L555-33 assume 1 == ~t5_pc~0; 35248#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35972#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35519#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35520#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35999#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35212#L574-33 assume 1 == ~t6_pc~0; 35213#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36208#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35534#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35535#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35788#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35288#L593-33 assume !(1 == ~t7_pc~0); 35289#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 35744#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35399#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35400#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36059#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36186#L612-33 assume 1 == ~t8_pc~0; 36313#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36277#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36278#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36120#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35395#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35396#L631-33 assume !(1 == ~t9_pc~0); 36006#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 35339#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35340#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35592#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35449#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35450#L1047-3 assume !(1 == ~M_E~0); 35625#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36239#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36171#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36172#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35350#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35351#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35733#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35578#L1082-3 assume !(1 == ~T8_E~0); 35579#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35652#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35933#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35863#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35864#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36209#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35573#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35574#L1122-3 assume !(1 == ~E_6~0); 35626#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35627#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36016#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35993#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 35453#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35331#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 35994#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 35751#L1447 assume !(0 == start_simulation_~tmp~3#1); 35752#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 36190#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35492#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 36017#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 35602#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 35359#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35360#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 35815#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 35369#L1428-2 [2022-02-21 04:23:05,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:05,871 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2022-02-21 04:23:05,871 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:05,872 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502378142] [2022-02-21 04:23:05,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:05,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:05,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 0: Hoare triple {38698#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 1: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 2: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 3: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 4: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,910 INFO L290 TraceCheckUtils]: 5: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,910 INFO L290 TraceCheckUtils]: 6: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,910 INFO L290 TraceCheckUtils]: 7: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,911 INFO L290 TraceCheckUtils]: 8: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,911 INFO L290 TraceCheckUtils]: 9: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,911 INFO L290 TraceCheckUtils]: 10: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,912 INFO L290 TraceCheckUtils]: 11: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,912 INFO L290 TraceCheckUtils]: 12: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,912 INFO L290 TraceCheckUtils]: 13: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,913 INFO L290 TraceCheckUtils]: 14: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {38700#(= ~T4_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:05,913 INFO L290 TraceCheckUtils]: 15: Hoare triple {38700#(= ~T4_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {38701#(not (= ~T4_E~0 0))} is VALID [2022-02-21 04:23:05,913 INFO L290 TraceCheckUtils]: 16: Hoare triple {38701#(not (= ~T4_E~0 0))} assume !(0 == ~T1_E~0); {38701#(not (= ~T4_E~0 0))} is VALID [2022-02-21 04:23:05,914 INFO L290 TraceCheckUtils]: 17: Hoare triple {38701#(not (= ~T4_E~0 0))} assume !(0 == ~T2_E~0); {38701#(not (= ~T4_E~0 0))} is VALID [2022-02-21 04:23:05,914 INFO L290 TraceCheckUtils]: 18: Hoare triple {38701#(not (= ~T4_E~0 0))} assume !(0 == ~T3_E~0); {38701#(not (= ~T4_E~0 0))} is VALID [2022-02-21 04:23:05,914 INFO L290 TraceCheckUtils]: 19: Hoare triple {38701#(not (= ~T4_E~0 0))} assume 0 == ~T4_E~0;~T4_E~0 := 1; {38699#false} is VALID [2022-02-21 04:23:05,915 INFO L290 TraceCheckUtils]: 20: Hoare triple {38699#false} assume !(0 == ~T5_E~0); {38699#false} is VALID [2022-02-21 04:23:05,915 INFO L290 TraceCheckUtils]: 21: Hoare triple {38699#false} assume !(0 == ~T6_E~0); {38699#false} is VALID [2022-02-21 04:23:05,915 INFO L290 TraceCheckUtils]: 22: Hoare triple {38699#false} assume !(0 == ~T7_E~0); {38699#false} is VALID [2022-02-21 04:23:05,915 INFO L290 TraceCheckUtils]: 23: Hoare triple {38699#false} assume !(0 == ~T8_E~0); {38699#false} is VALID [2022-02-21 04:23:05,915 INFO L290 TraceCheckUtils]: 24: Hoare triple {38699#false} assume !(0 == ~T9_E~0); {38699#false} is VALID [2022-02-21 04:23:05,915 INFO L290 TraceCheckUtils]: 25: Hoare triple {38699#false} assume !(0 == ~E_M~0); {38699#false} is VALID [2022-02-21 04:23:05,915 INFO L290 TraceCheckUtils]: 26: Hoare triple {38699#false} assume !(0 == ~E_1~0); {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 27: Hoare triple {38699#false} assume 0 == ~E_2~0;~E_2~0 := 1; {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 28: Hoare triple {38699#false} assume !(0 == ~E_3~0); {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 29: Hoare triple {38699#false} assume !(0 == ~E_4~0); {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 30: Hoare triple {38699#false} assume !(0 == ~E_5~0); {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 31: Hoare triple {38699#false} assume !(0 == ~E_6~0); {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 32: Hoare triple {38699#false} assume !(0 == ~E_7~0); {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 33: Hoare triple {38699#false} assume !(0 == ~E_8~0); {38699#false} is VALID [2022-02-21 04:23:05,916 INFO L290 TraceCheckUtils]: 34: Hoare triple {38699#false} assume !(0 == ~E_9~0); {38699#false} is VALID [2022-02-21 04:23:05,917 INFO L290 TraceCheckUtils]: 35: Hoare triple {38699#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {38699#false} is VALID [2022-02-21 04:23:05,917 INFO L290 TraceCheckUtils]: 36: Hoare triple {38699#false} assume 1 == ~m_pc~0; {38699#false} is VALID [2022-02-21 04:23:05,917 INFO L290 TraceCheckUtils]: 37: Hoare triple {38699#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {38699#false} is VALID [2022-02-21 04:23:05,917 INFO L290 TraceCheckUtils]: 38: Hoare triple {38699#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {38699#false} is VALID [2022-02-21 04:23:05,917 INFO L290 TraceCheckUtils]: 39: Hoare triple {38699#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {38699#false} is VALID [2022-02-21 04:23:05,917 INFO L290 TraceCheckUtils]: 40: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp~1#1); {38699#false} is VALID [2022-02-21 04:23:05,917 INFO L290 TraceCheckUtils]: 41: Hoare triple {38699#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 42: Hoare triple {38699#false} assume 1 == ~t1_pc~0; {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 43: Hoare triple {38699#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 44: Hoare triple {38699#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 45: Hoare triple {38699#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 46: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___0~0#1); {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 47: Hoare triple {38699#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 48: Hoare triple {38699#false} assume !(1 == ~t2_pc~0); {38699#false} is VALID [2022-02-21 04:23:05,918 INFO L290 TraceCheckUtils]: 49: Hoare triple {38699#false} is_transmit2_triggered_~__retres1~2#1 := 0; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 50: Hoare triple {38699#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 51: Hoare triple {38699#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 52: Hoare triple {38699#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 53: Hoare triple {38699#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 54: Hoare triple {38699#false} assume 1 == ~t3_pc~0; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 55: Hoare triple {38699#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 56: Hoare triple {38699#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {38699#false} is VALID [2022-02-21 04:23:05,919 INFO L290 TraceCheckUtils]: 57: Hoare triple {38699#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 58: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___2~0#1); {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 59: Hoare triple {38699#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 60: Hoare triple {38699#false} assume !(1 == ~t4_pc~0); {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 61: Hoare triple {38699#false} is_transmit4_triggered_~__retres1~4#1 := 0; {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 62: Hoare triple {38699#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 63: Hoare triple {38699#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 64: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___3~0#1); {38699#false} is VALID [2022-02-21 04:23:05,920 INFO L290 TraceCheckUtils]: 65: Hoare triple {38699#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 66: Hoare triple {38699#false} assume 1 == ~t5_pc~0; {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 67: Hoare triple {38699#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 68: Hoare triple {38699#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 69: Hoare triple {38699#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 70: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___4~0#1); {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 71: Hoare triple {38699#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 72: Hoare triple {38699#false} assume !(1 == ~t6_pc~0); {38699#false} is VALID [2022-02-21 04:23:05,921 INFO L290 TraceCheckUtils]: 73: Hoare triple {38699#false} is_transmit6_triggered_~__retres1~6#1 := 0; {38699#false} is VALID [2022-02-21 04:23:05,922 INFO L290 TraceCheckUtils]: 74: Hoare triple {38699#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {38699#false} is VALID [2022-02-21 04:23:05,922 INFO L290 TraceCheckUtils]: 75: Hoare triple {38699#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {38699#false} is VALID [2022-02-21 04:23:05,922 INFO L290 TraceCheckUtils]: 76: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___5~0#1); {38699#false} is VALID [2022-02-21 04:23:05,922 INFO L290 TraceCheckUtils]: 77: Hoare triple {38699#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {38699#false} is VALID [2022-02-21 04:23:05,922 INFO L290 TraceCheckUtils]: 78: Hoare triple {38699#false} assume 1 == ~t7_pc~0; {38699#false} is VALID [2022-02-21 04:23:05,922 INFO L290 TraceCheckUtils]: 79: Hoare triple {38699#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {38699#false} is VALID [2022-02-21 04:23:05,922 INFO L290 TraceCheckUtils]: 80: Hoare triple {38699#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 81: Hoare triple {38699#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 82: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___6~0#1); {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 83: Hoare triple {38699#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 84: Hoare triple {38699#false} assume !(1 == ~t8_pc~0); {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 85: Hoare triple {38699#false} is_transmit8_triggered_~__retres1~8#1 := 0; {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 86: Hoare triple {38699#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 87: Hoare triple {38699#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {38699#false} is VALID [2022-02-21 04:23:05,923 INFO L290 TraceCheckUtils]: 88: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___7~0#1); {38699#false} is VALID [2022-02-21 04:23:05,924 INFO L290 TraceCheckUtils]: 89: Hoare triple {38699#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {38699#false} is VALID [2022-02-21 04:23:05,924 INFO L290 TraceCheckUtils]: 90: Hoare triple {38699#false} assume 1 == ~t9_pc~0; {38699#false} is VALID [2022-02-21 04:23:05,924 INFO L290 TraceCheckUtils]: 91: Hoare triple {38699#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {38699#false} is VALID [2022-02-21 04:23:05,924 INFO L290 TraceCheckUtils]: 92: Hoare triple {38699#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {38699#false} is VALID [2022-02-21 04:23:05,924 INFO L290 TraceCheckUtils]: 93: Hoare triple {38699#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {38699#false} is VALID [2022-02-21 04:23:05,924 INFO L290 TraceCheckUtils]: 94: Hoare triple {38699#false} assume !(0 != activate_threads_~tmp___8~0#1); {38699#false} is VALID [2022-02-21 04:23:05,924 INFO L290 TraceCheckUtils]: 95: Hoare triple {38699#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 96: Hoare triple {38699#false} assume !(1 == ~M_E~0); {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 97: Hoare triple {38699#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 98: Hoare triple {38699#false} assume !(1 == ~T2_E~0); {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 99: Hoare triple {38699#false} assume !(1 == ~T3_E~0); {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 100: Hoare triple {38699#false} assume !(1 == ~T4_E~0); {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 101: Hoare triple {38699#false} assume !(1 == ~T5_E~0); {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 102: Hoare triple {38699#false} assume !(1 == ~T6_E~0); {38699#false} is VALID [2022-02-21 04:23:05,925 INFO L290 TraceCheckUtils]: 103: Hoare triple {38699#false} assume !(1 == ~T7_E~0); {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 104: Hoare triple {38699#false} assume !(1 == ~T8_E~0); {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 105: Hoare triple {38699#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 106: Hoare triple {38699#false} assume !(1 == ~E_M~0); {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 107: Hoare triple {38699#false} assume !(1 == ~E_1~0); {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 108: Hoare triple {38699#false} assume !(1 == ~E_2~0); {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 109: Hoare triple {38699#false} assume !(1 == ~E_3~0); {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 110: Hoare triple {38699#false} assume !(1 == ~E_4~0); {38699#false} is VALID [2022-02-21 04:23:05,926 INFO L290 TraceCheckUtils]: 111: Hoare triple {38699#false} assume !(1 == ~E_5~0); {38699#false} is VALID [2022-02-21 04:23:05,927 INFO L290 TraceCheckUtils]: 112: Hoare triple {38699#false} assume !(1 == ~E_6~0); {38699#false} is VALID [2022-02-21 04:23:05,927 INFO L290 TraceCheckUtils]: 113: Hoare triple {38699#false} assume 1 == ~E_7~0;~E_7~0 := 2; {38699#false} is VALID [2022-02-21 04:23:05,927 INFO L290 TraceCheckUtils]: 114: Hoare triple {38699#false} assume !(1 == ~E_8~0); {38699#false} is VALID [2022-02-21 04:23:05,927 INFO L290 TraceCheckUtils]: 115: Hoare triple {38699#false} assume !(1 == ~E_9~0); {38699#false} is VALID [2022-02-21 04:23:05,927 INFO L290 TraceCheckUtils]: 116: Hoare triple {38699#false} assume { :end_inline_reset_delta_events } true; {38699#false} is VALID [2022-02-21 04:23:05,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:05,928 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:05,928 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502378142] [2022-02-21 04:23:05,928 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502378142] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:05,928 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:05,928 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:05,928 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845984528] [2022-02-21 04:23:05,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:05,929 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:05,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:05,930 INFO L85 PathProgramCache]: Analyzing trace with hash -1283827122, now seen corresponding path program 1 times [2022-02-21 04:23:05,930 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:05,930 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347298104] [2022-02-21 04:23:05,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:05,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:05,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,965 INFO L290 TraceCheckUtils]: 0: Hoare triple {38702#true} assume !false; {38702#true} is VALID [2022-02-21 04:23:05,965 INFO L290 TraceCheckUtils]: 1: Hoare triple {38702#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {38702#true} is VALID [2022-02-21 04:23:05,965 INFO L290 TraceCheckUtils]: 2: Hoare triple {38702#true} assume !false; {38702#true} is VALID [2022-02-21 04:23:05,965 INFO L290 TraceCheckUtils]: 3: Hoare triple {38702#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 4: Hoare triple {38702#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 5: Hoare triple {38702#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 6: Hoare triple {38702#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 7: Hoare triple {38702#true} assume !(0 != eval_~tmp~0#1); {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 8: Hoare triple {38702#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 9: Hoare triple {38702#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 10: Hoare triple {38702#true} assume !(0 == ~M_E~0); {38702#true} is VALID [2022-02-21 04:23:05,966 INFO L290 TraceCheckUtils]: 11: Hoare triple {38702#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,967 INFO L290 TraceCheckUtils]: 12: Hoare triple {38702#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,967 INFO L290 TraceCheckUtils]: 13: Hoare triple {38702#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,967 INFO L290 TraceCheckUtils]: 14: Hoare triple {38702#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,967 INFO L290 TraceCheckUtils]: 15: Hoare triple {38702#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,967 INFO L290 TraceCheckUtils]: 16: Hoare triple {38702#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,967 INFO L290 TraceCheckUtils]: 17: Hoare triple {38702#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,967 INFO L290 TraceCheckUtils]: 18: Hoare triple {38702#true} assume !(0 == ~T8_E~0); {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 19: Hoare triple {38702#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 20: Hoare triple {38702#true} assume 0 == ~E_M~0;~E_M~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 21: Hoare triple {38702#true} assume 0 == ~E_1~0;~E_1~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 22: Hoare triple {38702#true} assume 0 == ~E_2~0;~E_2~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 23: Hoare triple {38702#true} assume 0 == ~E_3~0;~E_3~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 24: Hoare triple {38702#true} assume 0 == ~E_4~0;~E_4~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 25: Hoare triple {38702#true} assume 0 == ~E_5~0;~E_5~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,968 INFO L290 TraceCheckUtils]: 26: Hoare triple {38702#true} assume !(0 == ~E_6~0); {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 27: Hoare triple {38702#true} assume 0 == ~E_7~0;~E_7~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 28: Hoare triple {38702#true} assume 0 == ~E_8~0;~E_8~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 29: Hoare triple {38702#true} assume 0 == ~E_9~0;~E_9~0 := 1; {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 30: Hoare triple {38702#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 31: Hoare triple {38702#true} assume 1 == ~m_pc~0; {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 32: Hoare triple {38702#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 33: Hoare triple {38702#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {38702#true} is VALID [2022-02-21 04:23:05,969 INFO L290 TraceCheckUtils]: 34: Hoare triple {38702#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {38702#true} is VALID [2022-02-21 04:23:05,970 INFO L290 TraceCheckUtils]: 35: Hoare triple {38702#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {38702#true} is VALID [2022-02-21 04:23:05,970 INFO L290 TraceCheckUtils]: 36: Hoare triple {38702#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {38702#true} is VALID [2022-02-21 04:23:05,970 INFO L290 TraceCheckUtils]: 37: Hoare triple {38702#true} assume !(1 == ~t1_pc~0); {38702#true} is VALID [2022-02-21 04:23:05,970 INFO L290 TraceCheckUtils]: 38: Hoare triple {38702#true} is_transmit1_triggered_~__retres1~1#1 := 0; {38702#true} is VALID [2022-02-21 04:23:05,970 INFO L290 TraceCheckUtils]: 39: Hoare triple {38702#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {38702#true} is VALID [2022-02-21 04:23:05,970 INFO L290 TraceCheckUtils]: 40: Hoare triple {38702#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {38702#true} is VALID [2022-02-21 04:23:05,970 INFO L290 TraceCheckUtils]: 41: Hoare triple {38702#true} assume !(0 != activate_threads_~tmp___0~0#1); {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 42: Hoare triple {38702#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 43: Hoare triple {38702#true} assume 1 == ~t2_pc~0; {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 44: Hoare triple {38702#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 45: Hoare triple {38702#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 46: Hoare triple {38702#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 47: Hoare triple {38702#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 48: Hoare triple {38702#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {38702#true} is VALID [2022-02-21 04:23:05,971 INFO L290 TraceCheckUtils]: 49: Hoare triple {38702#true} assume !(1 == ~t3_pc~0); {38702#true} is VALID [2022-02-21 04:23:05,972 INFO L290 TraceCheckUtils]: 50: Hoare triple {38702#true} is_transmit3_triggered_~__retres1~3#1 := 0; {38702#true} is VALID [2022-02-21 04:23:05,972 INFO L290 TraceCheckUtils]: 51: Hoare triple {38702#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {38702#true} is VALID [2022-02-21 04:23:05,972 INFO L290 TraceCheckUtils]: 52: Hoare triple {38702#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {38702#true} is VALID [2022-02-21 04:23:05,972 INFO L290 TraceCheckUtils]: 53: Hoare triple {38702#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {38702#true} is VALID [2022-02-21 04:23:05,972 INFO L290 TraceCheckUtils]: 54: Hoare triple {38702#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {38702#true} is VALID [2022-02-21 04:23:05,972 INFO L290 TraceCheckUtils]: 55: Hoare triple {38702#true} assume 1 == ~t4_pc~0; {38702#true} is VALID [2022-02-21 04:23:05,972 INFO L290 TraceCheckUtils]: 56: Hoare triple {38702#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 57: Hoare triple {38702#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 58: Hoare triple {38702#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 59: Hoare triple {38702#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 60: Hoare triple {38702#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 61: Hoare triple {38702#true} assume 1 == ~t5_pc~0; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 62: Hoare triple {38702#true} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 63: Hoare triple {38702#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {38702#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 64: Hoare triple {38702#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {38702#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 65: Hoare triple {38702#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {38702#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 66: Hoare triple {38702#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {38702#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 67: Hoare triple {38702#true} assume 1 == ~t6_pc~0; {38702#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 68: Hoare triple {38702#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,975 INFO L290 TraceCheckUtils]: 69: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,975 INFO L290 TraceCheckUtils]: 70: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,975 INFO L290 TraceCheckUtils]: 71: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,976 INFO L290 TraceCheckUtils]: 72: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,976 INFO L290 TraceCheckUtils]: 73: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,976 INFO L290 TraceCheckUtils]: 74: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,977 INFO L290 TraceCheckUtils]: 75: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,977 INFO L290 TraceCheckUtils]: 76: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,977 INFO L290 TraceCheckUtils]: 77: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 78: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 79: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 80: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 81: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,979 INFO L290 TraceCheckUtils]: 82: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,979 INFO L290 TraceCheckUtils]: 83: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,979 INFO L290 TraceCheckUtils]: 84: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,980 INFO L290 TraceCheckUtils]: 85: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t9_pc~0); {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,980 INFO L290 TraceCheckUtils]: 86: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,980 INFO L290 TraceCheckUtils]: 87: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,981 INFO L290 TraceCheckUtils]: 88: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,981 INFO L290 TraceCheckUtils]: 89: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,981 INFO L290 TraceCheckUtils]: 90: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,982 INFO L290 TraceCheckUtils]: 91: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,982 INFO L290 TraceCheckUtils]: 92: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,982 INFO L290 TraceCheckUtils]: 93: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,983 INFO L290 TraceCheckUtils]: 94: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,983 INFO L290 TraceCheckUtils]: 95: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,983 INFO L290 TraceCheckUtils]: 96: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,984 INFO L290 TraceCheckUtils]: 97: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,984 INFO L290 TraceCheckUtils]: 98: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,984 INFO L290 TraceCheckUtils]: 99: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,985 INFO L290 TraceCheckUtils]: 100: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,985 INFO L290 TraceCheckUtils]: 101: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,985 INFO L290 TraceCheckUtils]: 102: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,986 INFO L290 TraceCheckUtils]: 103: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,986 INFO L290 TraceCheckUtils]: 104: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,986 INFO L290 TraceCheckUtils]: 105: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 106: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {38704#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 107: Hoare triple {38704#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {38703#false} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 108: Hoare triple {38703#false} assume 1 == ~E_7~0;~E_7~0 := 2; {38703#false} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 109: Hoare triple {38703#false} assume 1 == ~E_8~0;~E_8~0 := 2; {38703#false} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 110: Hoare triple {38703#false} assume 1 == ~E_9~0;~E_9~0 := 2; {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 111: Hoare triple {38703#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 112: Hoare triple {38703#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 113: Hoare triple {38703#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 114: Hoare triple {38703#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 115: Hoare triple {38703#false} assume !(0 == start_simulation_~tmp~3#1); {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 116: Hoare triple {38703#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 117: Hoare triple {38703#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {38703#false} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 118: Hoare triple {38703#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {38703#false} is VALID [2022-02-21 04:23:05,989 INFO L290 TraceCheckUtils]: 119: Hoare triple {38703#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {38703#false} is VALID [2022-02-21 04:23:05,989 INFO L290 TraceCheckUtils]: 120: Hoare triple {38703#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {38703#false} is VALID [2022-02-21 04:23:05,989 INFO L290 TraceCheckUtils]: 121: Hoare triple {38703#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {38703#false} is VALID [2022-02-21 04:23:05,989 INFO L290 TraceCheckUtils]: 122: Hoare triple {38703#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {38703#false} is VALID [2022-02-21 04:23:05,989 INFO L290 TraceCheckUtils]: 123: Hoare triple {38703#false} assume !(0 != start_simulation_~tmp___0~1#1); {38703#false} is VALID [2022-02-21 04:23:05,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:05,990 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:05,990 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347298104] [2022-02-21 04:23:05,990 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347298104] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:05,990 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:05,990 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:05,990 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125014325] [2022-02-21 04:23:05,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:05,991 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:05,991 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:05,992 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:05,992 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:05,992 INFO L87 Difference]: Start difference. First operand 1170 states and 1735 transitions. cyclomatic complexity: 566 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,466 INFO L93 Difference]: Finished difference Result 2141 states and 3163 transitions. [2022-02-21 04:23:08,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:08,466 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,546 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:08,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2141 states and 3163 transitions. [2022-02-21 04:23:08,705 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-02-21 04:23:08,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2141 states to 2141 states and 3163 transitions. [2022-02-21 04:23:08,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2141 [2022-02-21 04:23:08,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2141 [2022-02-21 04:23:08,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2141 states and 3163 transitions. [2022-02-21 04:23:08,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:08,824 INFO L681 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2022-02-21 04:23:08,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states and 3163 transitions. [2022-02-21 04:23:08,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 2141. [2022-02-21 04:23:08,856 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:08,860 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2141 states and 3163 transitions. Second operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,862 INFO L74 IsIncluded]: Start isIncluded. First operand 2141 states and 3163 transitions. Second operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,865 INFO L87 Difference]: Start difference. First operand 2141 states and 3163 transitions. Second operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,988 INFO L93 Difference]: Finished difference Result 2141 states and 3163 transitions. [2022-02-21 04:23:08,988 INFO L276 IsEmpty]: Start isEmpty. Operand 2141 states and 3163 transitions. [2022-02-21 04:23:08,991 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:08,991 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:08,996 INFO L74 IsIncluded]: Start isIncluded. First operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2141 states and 3163 transitions. [2022-02-21 04:23:09,000 INFO L87 Difference]: Start difference. First operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2141 states and 3163 transitions. [2022-02-21 04:23:09,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:09,152 INFO L93 Difference]: Finished difference Result 2141 states and 3163 transitions. [2022-02-21 04:23:09,152 INFO L276 IsEmpty]: Start isEmpty. Operand 2141 states and 3163 transitions. [2022-02-21 04:23:09,154 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:09,155 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:09,155 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:09,155 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:09,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2141 states to 2141 states and 3163 transitions. [2022-02-21 04:23:09,288 INFO L704 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2022-02-21 04:23:09,288 INFO L587 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2022-02-21 04:23:09,288 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:09,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2141 states and 3163 transitions. [2022-02-21 04:23:09,294 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-02-21 04:23:09,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:09,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:09,296 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,296 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,296 INFO L791 eck$LassoCheckResult]: Stem: 41766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 41767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 41709#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41710#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41977#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 41578#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41579#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41944#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41378#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41379#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41851#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41852#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40864#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40865#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41071#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41472#L939 assume !(0 == ~M_E~0); 41744#L939-2 assume !(0 == ~T1_E~0); 41745#L944-1 assume !(0 == ~T2_E~0); 41502#L949-1 assume !(0 == ~T3_E~0); 41500#L954-1 assume !(0 == ~T4_E~0); 41501#L959-1 assume !(0 == ~T5_E~0); 41997#L964-1 assume !(0 == ~T6_E~0); 41223#L969-1 assume !(0 == ~T7_E~0); 41224#L974-1 assume !(0 == ~T8_E~0); 41929#L979-1 assume !(0 == ~T9_E~0); 41930#L984-1 assume !(0 == ~E_M~0); 41391#L989-1 assume !(0 == ~E_1~0); 41392#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41274#L999-1 assume !(0 == ~E_3~0); 41275#L1004-1 assume !(0 == ~E_4~0); 40933#L1009-1 assume !(0 == ~E_5~0); 40934#L1014-1 assume !(0 == ~E_6~0); 41266#L1019-1 assume !(0 == ~E_7~0); 41858#L1024-1 assume !(0 == ~E_8~0); 41194#L1029-1 assume !(0 == ~E_9~0); 41195#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41288#L460 assume 1 == ~m_pc~0; 40848#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40849#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41821#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42142#L1167 assume !(0 != activate_threads_~tmp~1#1); 41489#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41490#L479 assume 1 == ~t1_pc~0; 41473#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41474#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42070#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41206#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 41207#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41053#L498 assume !(1 == ~t2_pc~0); 41054#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41470#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41471#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41901#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41810#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41811#L517 assume 1 == ~t3_pc~0; 42073#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42074#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41549#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41241#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 41242#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41867#L536 assume !(1 == ~t4_pc~0); 41539#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41538#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41985#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41531#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 41532#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41777#L555 assume 1 == ~t5_pc~0; 41778#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41859#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40965#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40966#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 41074#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40973#L574 assume !(1 == ~t6_pc~0); 40974#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41631#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41079#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41080#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 41892#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42116#L593 assume 1 == ~t7_pc~0; 42117#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41213#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42000#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42153#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 42079#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41386#L612 assume !(1 == ~t8_pc~0); 41387#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41839#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41674#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41675#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 41633#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41634#L631 assume 1 == ~t9_pc~0; 41653#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40964#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40931#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40932#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 41476#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41871#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 41872#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42927#L1052-1 assume !(1 == ~T2_E~0); 42926#L1057-1 assume !(1 == ~T3_E~0); 42925#L1062-1 assume !(1 == ~T4_E~0); 41177#L1067-1 assume !(1 == ~T5_E~0); 42924#L1072-1 assume !(1 == ~T6_E~0); 42923#L1077-1 assume !(1 == ~T7_E~0); 42922#L1082-1 assume !(1 == ~T8_E~0); 42921#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42920#L1092-1 assume !(1 == ~E_M~0); 42919#L1097-1 assume !(1 == ~E_1~0); 42918#L1102-1 assume !(1 == ~E_2~0); 42917#L1107-1 assume !(1 == ~E_3~0); 42916#L1112-1 assume !(1 == ~E_4~0); 42915#L1117-1 assume !(1 == ~E_5~0); 42914#L1122-1 assume !(1 == ~E_6~0); 42913#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42912#L1132-1 assume !(1 == ~E_8~0); 42911#L1137-1 assume !(1 == ~E_9~0); 42211#L1142-1 assume { :end_inline_reset_delta_events } true; 42209#L1428-2 [2022-02-21 04:23:09,297 INFO L793 eck$LassoCheckResult]: Loop: 42209#L1428-2 assume !false; 41626#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41110#L914 assume !false; 41624#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 41625#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40869#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40870#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41897#L783 assume !(0 != eval_~tmp~0#1); 41898#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41702#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41703#L939-3 assume !(0 == ~M_E~0); 42187#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42324#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42323#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41946#L954-3 assume !(0 == ~T4_E~0); 41947#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42321#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42319#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42317#L974-3 assume !(0 == ~T8_E~0); 42316#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42315#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42314#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42313#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42312#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42311#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42310#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42309#L1014-3 assume !(0 == ~E_6~0); 42308#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42307#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41561#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41562#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42096#L460-33 assume !(1 == ~m_pc~0); 41553#L460-35 is_master_triggered_~__retres1~0#1 := 0; 41552#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41769#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40862#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40863#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41230#L479-33 assume 1 == ~t1_pc~0; 41232#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41196#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41197#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42056#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 42057#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41239#L498-33 assume !(1 == ~t2_pc~0); 40979#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 40980#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41115#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41116#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41093#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41094#L517-33 assume !(1 == ~t3_pc~0); 42133#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 41965#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41966#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41737#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41738#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41332#L536-33 assume 1 == ~t4_pc~0; 41333#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41403#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41404#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41605#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41935#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40910#L555-33 assume 1 == ~t5_pc~0; 40912#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42281#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42280#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42279#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42278#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42277#L574-33 assume 1 == ~t6_pc~0; 42275#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42274#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42273#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42272#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42271#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42266#L593-33 assume !(1 == ~t7_pc~0); 42264#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 42109#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41065#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41066#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41768#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42161#L612-33 assume 1 == ~t8_pc~0; 42162#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42043#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42044#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42156#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41063#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41064#L631-33 assume 1 == ~t9_pc~0; 41995#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41708#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41583#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41584#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41117#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41118#L1047-3 assume !(1 == ~M_E~0); 41299#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41996#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41906#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41907#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42181#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42253#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41410#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41248#L1082-3 assume !(1 == ~T8_E~0); 41249#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42251#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 42250#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41547#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41548#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41954#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41955#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41962#L1122-3 assume !(1 == ~E_6~0); 41300#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41301#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41722#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42155#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 42237#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 41700#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 41701#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 41429#L1447 assume !(0 == start_simulation_~tmp~3#1); 41430#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 42227#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 42216#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 42215#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 42214#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 42213#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42212#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 42210#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 42209#L1428-2 [2022-02-21 04:23:09,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,297 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2022-02-21 04:23:09,298 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,298 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418466894] [2022-02-21 04:23:09,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,333 INFO L290 TraceCheckUtils]: 0: Hoare triple {47274#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,333 INFO L290 TraceCheckUtils]: 1: Hoare triple {47276#(<= 2 ~E_2~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,334 INFO L290 TraceCheckUtils]: 2: Hoare triple {47276#(<= 2 ~E_2~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,334 INFO L290 TraceCheckUtils]: 3: Hoare triple {47276#(<= 2 ~E_2~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,334 INFO L290 TraceCheckUtils]: 4: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,335 INFO L290 TraceCheckUtils]: 5: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,335 INFO L290 TraceCheckUtils]: 6: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,335 INFO L290 TraceCheckUtils]: 7: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,336 INFO L290 TraceCheckUtils]: 8: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,336 INFO L290 TraceCheckUtils]: 9: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,336 INFO L290 TraceCheckUtils]: 10: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,337 INFO L290 TraceCheckUtils]: 11: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,337 INFO L290 TraceCheckUtils]: 12: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,337 INFO L290 TraceCheckUtils]: 13: Hoare triple {47276#(<= 2 ~E_2~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,338 INFO L290 TraceCheckUtils]: 14: Hoare triple {47276#(<= 2 ~E_2~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,338 INFO L290 TraceCheckUtils]: 15: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~M_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,338 INFO L290 TraceCheckUtils]: 16: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T1_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,339 INFO L290 TraceCheckUtils]: 17: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T2_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,339 INFO L290 TraceCheckUtils]: 18: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T3_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,339 INFO L290 TraceCheckUtils]: 19: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T4_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,340 INFO L290 TraceCheckUtils]: 20: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T5_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,340 INFO L290 TraceCheckUtils]: 21: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T6_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,340 INFO L290 TraceCheckUtils]: 22: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T7_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,341 INFO L290 TraceCheckUtils]: 23: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T8_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,341 INFO L290 TraceCheckUtils]: 24: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~T9_E~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,341 INFO L290 TraceCheckUtils]: 25: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~E_M~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,342 INFO L290 TraceCheckUtils]: 26: Hoare triple {47276#(<= 2 ~E_2~0)} assume !(0 == ~E_1~0); {47276#(<= 2 ~E_2~0)} is VALID [2022-02-21 04:23:09,342 INFO L290 TraceCheckUtils]: 27: Hoare triple {47276#(<= 2 ~E_2~0)} assume 0 == ~E_2~0;~E_2~0 := 1; {47275#false} is VALID [2022-02-21 04:23:09,342 INFO L290 TraceCheckUtils]: 28: Hoare triple {47275#false} assume !(0 == ~E_3~0); {47275#false} is VALID [2022-02-21 04:23:09,342 INFO L290 TraceCheckUtils]: 29: Hoare triple {47275#false} assume !(0 == ~E_4~0); {47275#false} is VALID [2022-02-21 04:23:09,342 INFO L290 TraceCheckUtils]: 30: Hoare triple {47275#false} assume !(0 == ~E_5~0); {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 31: Hoare triple {47275#false} assume !(0 == ~E_6~0); {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 32: Hoare triple {47275#false} assume !(0 == ~E_7~0); {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 33: Hoare triple {47275#false} assume !(0 == ~E_8~0); {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 34: Hoare triple {47275#false} assume !(0 == ~E_9~0); {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 35: Hoare triple {47275#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 36: Hoare triple {47275#false} assume 1 == ~m_pc~0; {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 37: Hoare triple {47275#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {47275#false} is VALID [2022-02-21 04:23:09,343 INFO L290 TraceCheckUtils]: 38: Hoare triple {47275#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47275#false} is VALID [2022-02-21 04:23:09,344 INFO L290 TraceCheckUtils]: 39: Hoare triple {47275#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {47275#false} is VALID [2022-02-21 04:23:09,344 INFO L290 TraceCheckUtils]: 40: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp~1#1); {47275#false} is VALID [2022-02-21 04:23:09,344 INFO L290 TraceCheckUtils]: 41: Hoare triple {47275#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47275#false} is VALID [2022-02-21 04:23:09,344 INFO L290 TraceCheckUtils]: 42: Hoare triple {47275#false} assume 1 == ~t1_pc~0; {47275#false} is VALID [2022-02-21 04:23:09,344 INFO L290 TraceCheckUtils]: 43: Hoare triple {47275#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {47275#false} is VALID [2022-02-21 04:23:09,344 INFO L290 TraceCheckUtils]: 44: Hoare triple {47275#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47275#false} is VALID [2022-02-21 04:23:09,344 INFO L290 TraceCheckUtils]: 45: Hoare triple {47275#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 46: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___0~0#1); {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 47: Hoare triple {47275#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 48: Hoare triple {47275#false} assume !(1 == ~t2_pc~0); {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 49: Hoare triple {47275#false} is_transmit2_triggered_~__retres1~2#1 := 0; {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 50: Hoare triple {47275#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 51: Hoare triple {47275#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 52: Hoare triple {47275#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {47275#false} is VALID [2022-02-21 04:23:09,345 INFO L290 TraceCheckUtils]: 53: Hoare triple {47275#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47275#false} is VALID [2022-02-21 04:23:09,346 INFO L290 TraceCheckUtils]: 54: Hoare triple {47275#false} assume 1 == ~t3_pc~0; {47275#false} is VALID [2022-02-21 04:23:09,346 INFO L290 TraceCheckUtils]: 55: Hoare triple {47275#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {47275#false} is VALID [2022-02-21 04:23:09,346 INFO L290 TraceCheckUtils]: 56: Hoare triple {47275#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47275#false} is VALID [2022-02-21 04:23:09,346 INFO L290 TraceCheckUtils]: 57: Hoare triple {47275#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47275#false} is VALID [2022-02-21 04:23:09,346 INFO L290 TraceCheckUtils]: 58: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___2~0#1); {47275#false} is VALID [2022-02-21 04:23:09,346 INFO L290 TraceCheckUtils]: 59: Hoare triple {47275#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47275#false} is VALID [2022-02-21 04:23:09,346 INFO L290 TraceCheckUtils]: 60: Hoare triple {47275#false} assume !(1 == ~t4_pc~0); {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 61: Hoare triple {47275#false} is_transmit4_triggered_~__retres1~4#1 := 0; {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 62: Hoare triple {47275#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 63: Hoare triple {47275#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 64: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___3~0#1); {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 65: Hoare triple {47275#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 66: Hoare triple {47275#false} assume 1 == ~t5_pc~0; {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 67: Hoare triple {47275#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47275#false} is VALID [2022-02-21 04:23:09,347 INFO L290 TraceCheckUtils]: 68: Hoare triple {47275#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 69: Hoare triple {47275#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 70: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___4~0#1); {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 71: Hoare triple {47275#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 72: Hoare triple {47275#false} assume !(1 == ~t6_pc~0); {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 73: Hoare triple {47275#false} is_transmit6_triggered_~__retres1~6#1 := 0; {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 74: Hoare triple {47275#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 75: Hoare triple {47275#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47275#false} is VALID [2022-02-21 04:23:09,348 INFO L290 TraceCheckUtils]: 76: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___5~0#1); {47275#false} is VALID [2022-02-21 04:23:09,349 INFO L290 TraceCheckUtils]: 77: Hoare triple {47275#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47275#false} is VALID [2022-02-21 04:23:09,349 INFO L290 TraceCheckUtils]: 78: Hoare triple {47275#false} assume 1 == ~t7_pc~0; {47275#false} is VALID [2022-02-21 04:23:09,349 INFO L290 TraceCheckUtils]: 79: Hoare triple {47275#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {47275#false} is VALID [2022-02-21 04:23:09,349 INFO L290 TraceCheckUtils]: 80: Hoare triple {47275#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47275#false} is VALID [2022-02-21 04:23:09,349 INFO L290 TraceCheckUtils]: 81: Hoare triple {47275#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47275#false} is VALID [2022-02-21 04:23:09,349 INFO L290 TraceCheckUtils]: 82: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___6~0#1); {47275#false} is VALID [2022-02-21 04:23:09,349 INFO L290 TraceCheckUtils]: 83: Hoare triple {47275#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 84: Hoare triple {47275#false} assume !(1 == ~t8_pc~0); {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 85: Hoare triple {47275#false} is_transmit8_triggered_~__retres1~8#1 := 0; {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 86: Hoare triple {47275#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 87: Hoare triple {47275#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 88: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___7~0#1); {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 89: Hoare triple {47275#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 90: Hoare triple {47275#false} assume 1 == ~t9_pc~0; {47275#false} is VALID [2022-02-21 04:23:09,350 INFO L290 TraceCheckUtils]: 91: Hoare triple {47275#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 92: Hoare triple {47275#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 93: Hoare triple {47275#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 94: Hoare triple {47275#false} assume !(0 != activate_threads_~tmp___8~0#1); {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 95: Hoare triple {47275#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 96: Hoare triple {47275#false} assume 1 == ~M_E~0;~M_E~0 := 2; {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 97: Hoare triple {47275#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 98: Hoare triple {47275#false} assume !(1 == ~T2_E~0); {47275#false} is VALID [2022-02-21 04:23:09,351 INFO L290 TraceCheckUtils]: 99: Hoare triple {47275#false} assume !(1 == ~T3_E~0); {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 100: Hoare triple {47275#false} assume !(1 == ~T4_E~0); {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 101: Hoare triple {47275#false} assume !(1 == ~T5_E~0); {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 102: Hoare triple {47275#false} assume !(1 == ~T6_E~0); {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 103: Hoare triple {47275#false} assume !(1 == ~T7_E~0); {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 104: Hoare triple {47275#false} assume !(1 == ~T8_E~0); {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 105: Hoare triple {47275#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 106: Hoare triple {47275#false} assume !(1 == ~E_M~0); {47275#false} is VALID [2022-02-21 04:23:09,352 INFO L290 TraceCheckUtils]: 107: Hoare triple {47275#false} assume !(1 == ~E_1~0); {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 108: Hoare triple {47275#false} assume !(1 == ~E_2~0); {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 109: Hoare triple {47275#false} assume !(1 == ~E_3~0); {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 110: Hoare triple {47275#false} assume !(1 == ~E_4~0); {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 111: Hoare triple {47275#false} assume !(1 == ~E_5~0); {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 112: Hoare triple {47275#false} assume !(1 == ~E_6~0); {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 113: Hoare triple {47275#false} assume 1 == ~E_7~0;~E_7~0 := 2; {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 114: Hoare triple {47275#false} assume !(1 == ~E_8~0); {47275#false} is VALID [2022-02-21 04:23:09,353 INFO L290 TraceCheckUtils]: 115: Hoare triple {47275#false} assume !(1 == ~E_9~0); {47275#false} is VALID [2022-02-21 04:23:09,354 INFO L290 TraceCheckUtils]: 116: Hoare triple {47275#false} assume { :end_inline_reset_delta_events } true; {47275#false} is VALID [2022-02-21 04:23:09,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,354 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,354 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418466894] [2022-02-21 04:23:09,354 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [418466894] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,355 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,355 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:09,355 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158687403] [2022-02-21 04:23:09,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,355 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:09,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,356 INFO L85 PathProgramCache]: Analyzing trace with hash 1604169612, now seen corresponding path program 1 times [2022-02-21 04:23:09,356 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,356 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872334754] [2022-02-21 04:23:09,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,385 INFO L290 TraceCheckUtils]: 0: Hoare triple {47277#true} assume !false; {47277#true} is VALID [2022-02-21 04:23:09,386 INFO L290 TraceCheckUtils]: 1: Hoare triple {47277#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {47277#true} is VALID [2022-02-21 04:23:09,386 INFO L290 TraceCheckUtils]: 2: Hoare triple {47277#true} assume !false; {47277#true} is VALID [2022-02-21 04:23:09,386 INFO L290 TraceCheckUtils]: 3: Hoare triple {47277#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {47277#true} is VALID [2022-02-21 04:23:09,386 INFO L290 TraceCheckUtils]: 4: Hoare triple {47277#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {47277#true} is VALID [2022-02-21 04:23:09,386 INFO L290 TraceCheckUtils]: 5: Hoare triple {47277#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {47277#true} is VALID [2022-02-21 04:23:09,386 INFO L290 TraceCheckUtils]: 6: Hoare triple {47277#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {47277#true} is VALID [2022-02-21 04:23:09,387 INFO L290 TraceCheckUtils]: 7: Hoare triple {47277#true} assume !(0 != eval_~tmp~0#1); {47277#true} is VALID [2022-02-21 04:23:09,387 INFO L290 TraceCheckUtils]: 8: Hoare triple {47277#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {47277#true} is VALID [2022-02-21 04:23:09,387 INFO L290 TraceCheckUtils]: 9: Hoare triple {47277#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {47277#true} is VALID [2022-02-21 04:23:09,387 INFO L290 TraceCheckUtils]: 10: Hoare triple {47277#true} assume !(0 == ~M_E~0); {47277#true} is VALID [2022-02-21 04:23:09,387 INFO L290 TraceCheckUtils]: 11: Hoare triple {47277#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,387 INFO L290 TraceCheckUtils]: 12: Hoare triple {47277#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,387 INFO L290 TraceCheckUtils]: 13: Hoare triple {47277#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 14: Hoare triple {47277#true} assume !(0 == ~T4_E~0); {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 15: Hoare triple {47277#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 16: Hoare triple {47277#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 17: Hoare triple {47277#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 18: Hoare triple {47277#true} assume !(0 == ~T8_E~0); {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 19: Hoare triple {47277#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 20: Hoare triple {47277#true} assume 0 == ~E_M~0;~E_M~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,388 INFO L290 TraceCheckUtils]: 21: Hoare triple {47277#true} assume 0 == ~E_1~0;~E_1~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 22: Hoare triple {47277#true} assume 0 == ~E_2~0;~E_2~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 23: Hoare triple {47277#true} assume 0 == ~E_3~0;~E_3~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 24: Hoare triple {47277#true} assume 0 == ~E_4~0;~E_4~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 25: Hoare triple {47277#true} assume 0 == ~E_5~0;~E_5~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 26: Hoare triple {47277#true} assume !(0 == ~E_6~0); {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 27: Hoare triple {47277#true} assume 0 == ~E_7~0;~E_7~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 28: Hoare triple {47277#true} assume 0 == ~E_8~0;~E_8~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,389 INFO L290 TraceCheckUtils]: 29: Hoare triple {47277#true} assume 0 == ~E_9~0;~E_9~0 := 1; {47277#true} is VALID [2022-02-21 04:23:09,390 INFO L290 TraceCheckUtils]: 30: Hoare triple {47277#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47277#true} is VALID [2022-02-21 04:23:09,390 INFO L290 TraceCheckUtils]: 31: Hoare triple {47277#true} assume !(1 == ~m_pc~0); {47277#true} is VALID [2022-02-21 04:23:09,390 INFO L290 TraceCheckUtils]: 32: Hoare triple {47277#true} is_master_triggered_~__retres1~0#1 := 0; {47277#true} is VALID [2022-02-21 04:23:09,390 INFO L290 TraceCheckUtils]: 33: Hoare triple {47277#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47277#true} is VALID [2022-02-21 04:23:09,390 INFO L290 TraceCheckUtils]: 34: Hoare triple {47277#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {47277#true} is VALID [2022-02-21 04:23:09,390 INFO L290 TraceCheckUtils]: 35: Hoare triple {47277#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {47277#true} is VALID [2022-02-21 04:23:09,390 INFO L290 TraceCheckUtils]: 36: Hoare triple {47277#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 37: Hoare triple {47277#true} assume 1 == ~t1_pc~0; {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 38: Hoare triple {47277#true} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 39: Hoare triple {47277#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 40: Hoare triple {47277#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 41: Hoare triple {47277#true} assume !(0 != activate_threads_~tmp___0~0#1); {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 42: Hoare triple {47277#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 43: Hoare triple {47277#true} assume !(1 == ~t2_pc~0); {47277#true} is VALID [2022-02-21 04:23:09,391 INFO L290 TraceCheckUtils]: 44: Hoare triple {47277#true} is_transmit2_triggered_~__retres1~2#1 := 0; {47277#true} is VALID [2022-02-21 04:23:09,392 INFO L290 TraceCheckUtils]: 45: Hoare triple {47277#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47277#true} is VALID [2022-02-21 04:23:09,392 INFO L290 TraceCheckUtils]: 46: Hoare triple {47277#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {47277#true} is VALID [2022-02-21 04:23:09,392 INFO L290 TraceCheckUtils]: 47: Hoare triple {47277#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {47277#true} is VALID [2022-02-21 04:23:09,392 INFO L290 TraceCheckUtils]: 48: Hoare triple {47277#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47277#true} is VALID [2022-02-21 04:23:09,392 INFO L290 TraceCheckUtils]: 49: Hoare triple {47277#true} assume !(1 == ~t3_pc~0); {47277#true} is VALID [2022-02-21 04:23:09,392 INFO L290 TraceCheckUtils]: 50: Hoare triple {47277#true} is_transmit3_triggered_~__retres1~3#1 := 0; {47277#true} is VALID [2022-02-21 04:23:09,392 INFO L290 TraceCheckUtils]: 51: Hoare triple {47277#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47277#true} is VALID [2022-02-21 04:23:09,393 INFO L290 TraceCheckUtils]: 52: Hoare triple {47277#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47277#true} is VALID [2022-02-21 04:23:09,393 INFO L290 TraceCheckUtils]: 53: Hoare triple {47277#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {47277#true} is VALID [2022-02-21 04:23:09,393 INFO L290 TraceCheckUtils]: 54: Hoare triple {47277#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47277#true} is VALID [2022-02-21 04:23:09,393 INFO L290 TraceCheckUtils]: 55: Hoare triple {47277#true} assume 1 == ~t4_pc~0; {47277#true} is VALID [2022-02-21 04:23:09,393 INFO L290 TraceCheckUtils]: 56: Hoare triple {47277#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {47277#true} is VALID [2022-02-21 04:23:09,393 INFO L290 TraceCheckUtils]: 57: Hoare triple {47277#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47277#true} is VALID [2022-02-21 04:23:09,393 INFO L290 TraceCheckUtils]: 58: Hoare triple {47277#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 59: Hoare triple {47277#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 60: Hoare triple {47277#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 61: Hoare triple {47277#true} assume 1 == ~t5_pc~0; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 62: Hoare triple {47277#true} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 63: Hoare triple {47277#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 64: Hoare triple {47277#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 65: Hoare triple {47277#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {47277#true} is VALID [2022-02-21 04:23:09,394 INFO L290 TraceCheckUtils]: 66: Hoare triple {47277#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47277#true} is VALID [2022-02-21 04:23:09,395 INFO L290 TraceCheckUtils]: 67: Hoare triple {47277#true} assume 1 == ~t6_pc~0; {47277#true} is VALID [2022-02-21 04:23:09,395 INFO L290 TraceCheckUtils]: 68: Hoare triple {47277#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,395 INFO L290 TraceCheckUtils]: 69: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,396 INFO L290 TraceCheckUtils]: 70: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,396 INFO L290 TraceCheckUtils]: 71: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,396 INFO L290 TraceCheckUtils]: 72: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,397 INFO L290 TraceCheckUtils]: 73: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,397 INFO L290 TraceCheckUtils]: 74: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,397 INFO L290 TraceCheckUtils]: 75: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,398 INFO L290 TraceCheckUtils]: 76: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,398 INFO L290 TraceCheckUtils]: 77: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,398 INFO L290 TraceCheckUtils]: 78: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,399 INFO L290 TraceCheckUtils]: 79: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,399 INFO L290 TraceCheckUtils]: 80: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,399 INFO L290 TraceCheckUtils]: 81: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,400 INFO L290 TraceCheckUtils]: 82: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,400 INFO L290 TraceCheckUtils]: 83: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,400 INFO L290 TraceCheckUtils]: 84: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,401 INFO L290 TraceCheckUtils]: 85: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t9_pc~0; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,401 INFO L290 TraceCheckUtils]: 86: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,401 INFO L290 TraceCheckUtils]: 87: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,402 INFO L290 TraceCheckUtils]: 88: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,402 INFO L290 TraceCheckUtils]: 89: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,402 INFO L290 TraceCheckUtils]: 90: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,403 INFO L290 TraceCheckUtils]: 91: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,403 INFO L290 TraceCheckUtils]: 92: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,403 INFO L290 TraceCheckUtils]: 93: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,404 INFO L290 TraceCheckUtils]: 94: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,404 INFO L290 TraceCheckUtils]: 95: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,404 INFO L290 TraceCheckUtils]: 96: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,405 INFO L290 TraceCheckUtils]: 97: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,405 INFO L290 TraceCheckUtils]: 98: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,405 INFO L290 TraceCheckUtils]: 99: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,406 INFO L290 TraceCheckUtils]: 100: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,406 INFO L290 TraceCheckUtils]: 101: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,406 INFO L290 TraceCheckUtils]: 102: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,407 INFO L290 TraceCheckUtils]: 103: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,407 INFO L290 TraceCheckUtils]: 104: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,407 INFO L290 TraceCheckUtils]: 105: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,408 INFO L290 TraceCheckUtils]: 106: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {47279#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:09,408 INFO L290 TraceCheckUtils]: 107: Hoare triple {47279#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {47278#false} is VALID [2022-02-21 04:23:09,408 INFO L290 TraceCheckUtils]: 108: Hoare triple {47278#false} assume 1 == ~E_7~0;~E_7~0 := 2; {47278#false} is VALID [2022-02-21 04:23:09,408 INFO L290 TraceCheckUtils]: 109: Hoare triple {47278#false} assume 1 == ~E_8~0;~E_8~0 := 2; {47278#false} is VALID [2022-02-21 04:23:09,409 INFO L290 TraceCheckUtils]: 110: Hoare triple {47278#false} assume 1 == ~E_9~0;~E_9~0 := 2; {47278#false} is VALID [2022-02-21 04:23:09,409 INFO L290 TraceCheckUtils]: 111: Hoare triple {47278#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {47278#false} is VALID [2022-02-21 04:23:09,409 INFO L290 TraceCheckUtils]: 112: Hoare triple {47278#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {47278#false} is VALID [2022-02-21 04:23:09,409 INFO L290 TraceCheckUtils]: 113: Hoare triple {47278#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {47278#false} is VALID [2022-02-21 04:23:09,409 INFO L290 TraceCheckUtils]: 114: Hoare triple {47278#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {47278#false} is VALID [2022-02-21 04:23:09,409 INFO L290 TraceCheckUtils]: 115: Hoare triple {47278#false} assume !(0 == start_simulation_~tmp~3#1); {47278#false} is VALID [2022-02-21 04:23:09,409 INFO L290 TraceCheckUtils]: 116: Hoare triple {47278#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {47278#false} is VALID [2022-02-21 04:23:09,410 INFO L290 TraceCheckUtils]: 117: Hoare triple {47278#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {47278#false} is VALID [2022-02-21 04:23:09,410 INFO L290 TraceCheckUtils]: 118: Hoare triple {47278#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {47278#false} is VALID [2022-02-21 04:23:09,410 INFO L290 TraceCheckUtils]: 119: Hoare triple {47278#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {47278#false} is VALID [2022-02-21 04:23:09,410 INFO L290 TraceCheckUtils]: 120: Hoare triple {47278#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {47278#false} is VALID [2022-02-21 04:23:09,410 INFO L290 TraceCheckUtils]: 121: Hoare triple {47278#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {47278#false} is VALID [2022-02-21 04:23:09,410 INFO L290 TraceCheckUtils]: 122: Hoare triple {47278#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {47278#false} is VALID [2022-02-21 04:23:09,410 INFO L290 TraceCheckUtils]: 123: Hoare triple {47278#false} assume !(0 != start_simulation_~tmp___0~1#1); {47278#false} is VALID [2022-02-21 04:23:09,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,411 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,411 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872334754] [2022-02-21 04:23:09,411 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1872334754] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,411 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,411 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,412 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375181796] [2022-02-21 04:23:09,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:09,412 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:09,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:09,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:09,413 INFO L87 Difference]: Start difference. First operand 2141 states and 3163 transitions. cyclomatic complexity: 1024 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,367 INFO L93 Difference]: Finished difference Result 2141 states and 3133 transitions. [2022-02-21 04:23:10,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:10,367 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,445 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:10,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2141 states and 3133 transitions. [2022-02-21 04:23:10,545 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-02-21 04:23:10,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2141 states to 2141 states and 3133 transitions. [2022-02-21 04:23:10,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2141 [2022-02-21 04:23:10,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2141 [2022-02-21 04:23:10,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2141 states and 3133 transitions. [2022-02-21 04:23:10,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:10,656 INFO L681 BuchiCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2022-02-21 04:23:10,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states and 3133 transitions. [2022-02-21 04:23:10,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 2141. [2022-02-21 04:23:10,687 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:10,691 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2141 states and 3133 transitions. Second operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,694 INFO L74 IsIncluded]: Start isIncluded. First operand 2141 states and 3133 transitions. Second operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,698 INFO L87 Difference]: Start difference. First operand 2141 states and 3133 transitions. Second operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,828 INFO L93 Difference]: Finished difference Result 2141 states and 3133 transitions. [2022-02-21 04:23:10,828 INFO L276 IsEmpty]: Start isEmpty. Operand 2141 states and 3133 transitions. [2022-02-21 04:23:10,830 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,831 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,834 INFO L74 IsIncluded]: Start isIncluded. First operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2141 states and 3133 transitions. [2022-02-21 04:23:10,837 INFO L87 Difference]: Start difference. First operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2141 states and 3133 transitions. [2022-02-21 04:23:10,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,938 INFO L93 Difference]: Finished difference Result 2141 states and 3133 transitions. [2022-02-21 04:23:10,938 INFO L276 IsEmpty]: Start isEmpty. Operand 2141 states and 3133 transitions. [2022-02-21 04:23:10,940 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,940 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,940 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:10,940 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:10,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2141 states to 2141 states and 3133 transitions. [2022-02-21 04:23:11,052 INFO L704 BuchiCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2022-02-21 04:23:11,052 INFO L587 BuchiCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2022-02-21 04:23:11,052 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:11,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2141 states and 3133 transitions. [2022-02-21 04:23:11,055 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2022-02-21 04:23:11,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:11,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:11,057 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,057 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,058 INFO L791 eck$LassoCheckResult]: Stem: 50332#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 50333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 50275#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50276#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50528#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 50144#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50145#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50498#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49950#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49951#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50415#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50416#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49437#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49438#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49642#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50042#L939 assume !(0 == ~M_E~0); 50308#L939-2 assume !(0 == ~T1_E~0); 50309#L944-1 assume !(0 == ~T2_E~0); 50071#L949-1 assume !(0 == ~T3_E~0); 50069#L954-1 assume !(0 == ~T4_E~0); 50070#L959-1 assume !(0 == ~T5_E~0); 50547#L964-1 assume !(0 == ~T6_E~0); 49796#L969-1 assume !(0 == ~T7_E~0); 49797#L974-1 assume !(0 == ~T8_E~0); 50485#L979-1 assume !(0 == ~T9_E~0); 50486#L984-1 assume !(0 == ~E_M~0); 49962#L989-1 assume !(0 == ~E_1~0); 49963#L994-1 assume !(0 == ~E_2~0); 49847#L999-1 assume !(0 == ~E_3~0); 49848#L1004-1 assume !(0 == ~E_4~0); 49506#L1009-1 assume !(0 == ~E_5~0); 49507#L1014-1 assume !(0 == ~E_6~0); 49839#L1019-1 assume !(0 == ~E_7~0); 50420#L1024-1 assume !(0 == ~E_8~0); 49768#L1029-1 assume !(0 == ~E_9~0); 49769#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49861#L460 assume 1 == ~m_pc~0; 49421#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49422#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50382#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50698#L1167 assume !(0 != activate_threads_~tmp~1#1); 50059#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50060#L479 assume 1 == ~t1_pc~0; 50043#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50044#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50628#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49780#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 49781#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49624#L498 assume !(1 == ~t2_pc~0); 49625#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50040#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50041#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50461#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50371#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50372#L517 assume 1 == ~t3_pc~0; 50633#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50634#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50113#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49814#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 49815#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50430#L536 assume !(1 == ~t4_pc~0); 50103#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50102#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50534#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50095#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 50096#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50344#L555 assume 1 == ~t5_pc~0; 50345#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50421#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49537#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49538#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 49645#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49545#L574 assume !(1 == ~t6_pc~0); 49546#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50200#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49650#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49651#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 50454#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50672#L593 assume 1 == ~t7_pc~0; 50673#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49788#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50552#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50705#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 50637#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49957#L612 assume !(1 == ~t8_pc~0); 49958#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50399#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50241#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50242#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 50202#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50203#L631 assume 1 == ~t9_pc~0; 50221#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49536#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49504#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49505#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 50046#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50434#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 49473#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49474#L1052-1 assume !(1 == ~T2_E~0); 49456#L1057-1 assume !(1 == ~T3_E~0); 49457#L1062-1 assume !(1 == ~T4_E~0); 49750#L1067-1 assume !(1 == ~T5_E~0); 50548#L1072-1 assume !(1 == ~T6_E~0); 50401#L1077-1 assume !(1 == ~T7_E~0); 49638#L1082-1 assume !(1 == ~T8_E~0); 49639#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49429#L1092-1 assume !(1 == ~E_M~0); 49430#L1097-1 assume !(1 == ~E_1~0); 49458#L1102-1 assume !(1 == ~E_2~0); 50268#L1107-1 assume !(1 == ~E_3~0); 50269#L1112-1 assume !(1 == ~E_4~0); 50769#L1117-1 assume !(1 == ~E_5~0); 50767#L1122-1 assume !(1 == ~E_6~0); 50114#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49864#L1132-1 assume !(1 == ~E_8~0); 49865#L1137-1 assume !(1 == ~E_9~0); 50740#L1142-1 assume { :end_inline_reset_delta_events } true; 50739#L1428-2 [2022-02-21 04:23:11,058 INFO L793 eck$LassoCheckResult]: Loop: 50739#L1428-2 assume !false; 50193#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49682#L914 assume !false; 50191#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 50192#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 49442#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 49443#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50457#L783 assume !(0 != eval_~tmp~0#1); 50458#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50266#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50267#L939-3 assume !(0 == ~M_E~0); 50725#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51495#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51494#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51493#L954-3 assume !(0 == ~T4_E~0); 51492#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51491#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51490#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51489#L974-3 assume !(0 == ~T8_E~0); 51488#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51487#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 51486#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51485#L994-3 assume !(0 == ~E_2~0); 51484#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51483#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51482#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51481#L1014-3 assume !(0 == ~E_6~0); 51480#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51479#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51478#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51477#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51476#L460-33 assume !(1 == ~m_pc~0); 51474#L460-35 is_master_triggered_~__retres1~0#1 := 0; 51473#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51472#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51471#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51470#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51469#L479-33 assume 1 == ~t1_pc~0; 50656#L480-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49770#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49771#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50393#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 50611#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49812#L498-33 assume !(1 == ~t2_pc~0); 49550#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 49551#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49690#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49691#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49664#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49665#L517-33 assume !(1 == ~t3_pc~0); 50688#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 50519#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50520#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50301#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50302#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49902#L536-33 assume !(1 == ~t4_pc~0); 49904#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 49975#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49976#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50170#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50491#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49483#L555-33 assume !(1 == ~t5_pc~0); 49484#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 50235#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49761#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49762#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50263#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49453#L574-33 assume 1 == ~t6_pc~0; 49454#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50506#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49776#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49777#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50037#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49530#L593-33 assume !(1 == ~t7_pc~0); 49531#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 49999#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49636#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49637#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50334#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50480#L612-33 assume 1 == ~t8_pc~0; 50649#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50596#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50597#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50400#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49629#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49630#L631-33 assume 1 == ~t9_pc~0; 50545#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49573#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49574#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49836#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49688#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49689#L1047-3 assume !(1 == ~M_E~0); 49869#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50546#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50464#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50465#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49587#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49588#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49982#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49821#L1082-3 assume !(1 == ~T8_E~0); 49822#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49897#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50190#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50724#L1102-3 assume !(1 == ~E_2~0); 50665#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50666#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49816#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49817#L1122-3 assume !(1 == ~E_6~0); 49870#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49871#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50284#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50257#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 49692#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 49567#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50258#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 50000#L1447 assume !(0 == start_simulation_~tmp~3#1); 50001#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 50484#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 49731#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50285#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 49846#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 49596#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49597#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 50310#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 50739#L1428-2 [2022-02-21 04:23:11,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,059 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2022-02-21 04:23:11,059 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,059 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36634964] [2022-02-21 04:23:11,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,086 INFO L290 TraceCheckUtils]: 0: Hoare triple {55847#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,087 INFO L290 TraceCheckUtils]: 1: Hoare triple {55849#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,087 INFO L290 TraceCheckUtils]: 2: Hoare triple {55849#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,087 INFO L290 TraceCheckUtils]: 3: Hoare triple {55849#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,088 INFO L290 TraceCheckUtils]: 4: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,088 INFO L290 TraceCheckUtils]: 5: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,088 INFO L290 TraceCheckUtils]: 6: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,089 INFO L290 TraceCheckUtils]: 7: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,089 INFO L290 TraceCheckUtils]: 8: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,089 INFO L290 TraceCheckUtils]: 9: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,090 INFO L290 TraceCheckUtils]: 10: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,090 INFO L290 TraceCheckUtils]: 11: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,090 INFO L290 TraceCheckUtils]: 12: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,091 INFO L290 TraceCheckUtils]: 13: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,091 INFO L290 TraceCheckUtils]: 14: Hoare triple {55849#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,091 INFO L290 TraceCheckUtils]: 15: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,092 INFO L290 TraceCheckUtils]: 16: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,092 INFO L290 TraceCheckUtils]: 17: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,092 INFO L290 TraceCheckUtils]: 18: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,092 INFO L290 TraceCheckUtils]: 19: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,093 INFO L290 TraceCheckUtils]: 20: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,093 INFO L290 TraceCheckUtils]: 21: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,093 INFO L290 TraceCheckUtils]: 22: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T7_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,094 INFO L290 TraceCheckUtils]: 23: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T8_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,094 INFO L290 TraceCheckUtils]: 24: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~T9_E~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,094 INFO L290 TraceCheckUtils]: 25: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,095 INFO L290 TraceCheckUtils]: 26: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,095 INFO L290 TraceCheckUtils]: 27: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,095 INFO L290 TraceCheckUtils]: 28: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,096 INFO L290 TraceCheckUtils]: 29: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,096 INFO L290 TraceCheckUtils]: 30: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,096 INFO L290 TraceCheckUtils]: 31: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,097 INFO L290 TraceCheckUtils]: 32: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_7~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,097 INFO L290 TraceCheckUtils]: 33: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_8~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,097 INFO L290 TraceCheckUtils]: 34: Hoare triple {55849#(= ~m_pc~0 0)} assume !(0 == ~E_9~0); {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,098 INFO L290 TraceCheckUtils]: 35: Hoare triple {55849#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55849#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:11,098 INFO L290 TraceCheckUtils]: 36: Hoare triple {55849#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {55848#false} is VALID [2022-02-21 04:23:11,098 INFO L290 TraceCheckUtils]: 37: Hoare triple {55848#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {55848#false} is VALID [2022-02-21 04:23:11,098 INFO L290 TraceCheckUtils]: 38: Hoare triple {55848#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55848#false} is VALID [2022-02-21 04:23:11,098 INFO L290 TraceCheckUtils]: 39: Hoare triple {55848#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {55848#false} is VALID [2022-02-21 04:23:11,098 INFO L290 TraceCheckUtils]: 40: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp~1#1); {55848#false} is VALID [2022-02-21 04:23:11,099 INFO L290 TraceCheckUtils]: 41: Hoare triple {55848#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55848#false} is VALID [2022-02-21 04:23:11,099 INFO L290 TraceCheckUtils]: 42: Hoare triple {55848#false} assume 1 == ~t1_pc~0; {55848#false} is VALID [2022-02-21 04:23:11,099 INFO L290 TraceCheckUtils]: 43: Hoare triple {55848#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {55848#false} is VALID [2022-02-21 04:23:11,099 INFO L290 TraceCheckUtils]: 44: Hoare triple {55848#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55848#false} is VALID [2022-02-21 04:23:11,099 INFO L290 TraceCheckUtils]: 45: Hoare triple {55848#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {55848#false} is VALID [2022-02-21 04:23:11,099 INFO L290 TraceCheckUtils]: 46: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___0~0#1); {55848#false} is VALID [2022-02-21 04:23:11,099 INFO L290 TraceCheckUtils]: 47: Hoare triple {55848#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 48: Hoare triple {55848#false} assume !(1 == ~t2_pc~0); {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 49: Hoare triple {55848#false} is_transmit2_triggered_~__retres1~2#1 := 0; {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 50: Hoare triple {55848#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 51: Hoare triple {55848#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 52: Hoare triple {55848#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 53: Hoare triple {55848#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 54: Hoare triple {55848#false} assume 1 == ~t3_pc~0; {55848#false} is VALID [2022-02-21 04:23:11,100 INFO L290 TraceCheckUtils]: 55: Hoare triple {55848#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {55848#false} is VALID [2022-02-21 04:23:11,101 INFO L290 TraceCheckUtils]: 56: Hoare triple {55848#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55848#false} is VALID [2022-02-21 04:23:11,101 INFO L290 TraceCheckUtils]: 57: Hoare triple {55848#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55848#false} is VALID [2022-02-21 04:23:11,101 INFO L290 TraceCheckUtils]: 58: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___2~0#1); {55848#false} is VALID [2022-02-21 04:23:11,101 INFO L290 TraceCheckUtils]: 59: Hoare triple {55848#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55848#false} is VALID [2022-02-21 04:23:11,101 INFO L290 TraceCheckUtils]: 60: Hoare triple {55848#false} assume !(1 == ~t4_pc~0); {55848#false} is VALID [2022-02-21 04:23:11,101 INFO L290 TraceCheckUtils]: 61: Hoare triple {55848#false} is_transmit4_triggered_~__retres1~4#1 := 0; {55848#false} is VALID [2022-02-21 04:23:11,101 INFO L290 TraceCheckUtils]: 62: Hoare triple {55848#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55848#false} is VALID [2022-02-21 04:23:11,102 INFO L290 TraceCheckUtils]: 63: Hoare triple {55848#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55848#false} is VALID [2022-02-21 04:23:11,102 INFO L290 TraceCheckUtils]: 64: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___3~0#1); {55848#false} is VALID [2022-02-21 04:23:11,102 INFO L290 TraceCheckUtils]: 65: Hoare triple {55848#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55848#false} is VALID [2022-02-21 04:23:11,102 INFO L290 TraceCheckUtils]: 66: Hoare triple {55848#false} assume 1 == ~t5_pc~0; {55848#false} is VALID [2022-02-21 04:23:11,102 INFO L290 TraceCheckUtils]: 67: Hoare triple {55848#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {55848#false} is VALID [2022-02-21 04:23:11,102 INFO L290 TraceCheckUtils]: 68: Hoare triple {55848#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55848#false} is VALID [2022-02-21 04:23:11,102 INFO L290 TraceCheckUtils]: 69: Hoare triple {55848#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 70: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___4~0#1); {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 71: Hoare triple {55848#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 72: Hoare triple {55848#false} assume !(1 == ~t6_pc~0); {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 73: Hoare triple {55848#false} is_transmit6_triggered_~__retres1~6#1 := 0; {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 74: Hoare triple {55848#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 75: Hoare triple {55848#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 76: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___5~0#1); {55848#false} is VALID [2022-02-21 04:23:11,103 INFO L290 TraceCheckUtils]: 77: Hoare triple {55848#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55848#false} is VALID [2022-02-21 04:23:11,104 INFO L290 TraceCheckUtils]: 78: Hoare triple {55848#false} assume 1 == ~t7_pc~0; {55848#false} is VALID [2022-02-21 04:23:11,104 INFO L290 TraceCheckUtils]: 79: Hoare triple {55848#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {55848#false} is VALID [2022-02-21 04:23:11,104 INFO L290 TraceCheckUtils]: 80: Hoare triple {55848#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55848#false} is VALID [2022-02-21 04:23:11,104 INFO L290 TraceCheckUtils]: 81: Hoare triple {55848#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55848#false} is VALID [2022-02-21 04:23:11,104 INFO L290 TraceCheckUtils]: 82: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___6~0#1); {55848#false} is VALID [2022-02-21 04:23:11,104 INFO L290 TraceCheckUtils]: 83: Hoare triple {55848#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55848#false} is VALID [2022-02-21 04:23:11,104 INFO L290 TraceCheckUtils]: 84: Hoare triple {55848#false} assume !(1 == ~t8_pc~0); {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 85: Hoare triple {55848#false} is_transmit8_triggered_~__retres1~8#1 := 0; {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 86: Hoare triple {55848#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 87: Hoare triple {55848#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 88: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___7~0#1); {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 89: Hoare triple {55848#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 90: Hoare triple {55848#false} assume 1 == ~t9_pc~0; {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 91: Hoare triple {55848#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55848#false} is VALID [2022-02-21 04:23:11,105 INFO L290 TraceCheckUtils]: 92: Hoare triple {55848#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 93: Hoare triple {55848#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 94: Hoare triple {55848#false} assume !(0 != activate_threads_~tmp___8~0#1); {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 95: Hoare triple {55848#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 96: Hoare triple {55848#false} assume 1 == ~M_E~0;~M_E~0 := 2; {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 97: Hoare triple {55848#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 98: Hoare triple {55848#false} assume !(1 == ~T2_E~0); {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 99: Hoare triple {55848#false} assume !(1 == ~T3_E~0); {55848#false} is VALID [2022-02-21 04:23:11,106 INFO L290 TraceCheckUtils]: 100: Hoare triple {55848#false} assume !(1 == ~T4_E~0); {55848#false} is VALID [2022-02-21 04:23:11,107 INFO L290 TraceCheckUtils]: 101: Hoare triple {55848#false} assume !(1 == ~T5_E~0); {55848#false} is VALID [2022-02-21 04:23:11,107 INFO L290 TraceCheckUtils]: 102: Hoare triple {55848#false} assume !(1 == ~T6_E~0); {55848#false} is VALID [2022-02-21 04:23:11,107 INFO L290 TraceCheckUtils]: 103: Hoare triple {55848#false} assume !(1 == ~T7_E~0); {55848#false} is VALID [2022-02-21 04:23:11,107 INFO L290 TraceCheckUtils]: 104: Hoare triple {55848#false} assume !(1 == ~T8_E~0); {55848#false} is VALID [2022-02-21 04:23:11,107 INFO L290 TraceCheckUtils]: 105: Hoare triple {55848#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {55848#false} is VALID [2022-02-21 04:23:11,107 INFO L290 TraceCheckUtils]: 106: Hoare triple {55848#false} assume !(1 == ~E_M~0); {55848#false} is VALID [2022-02-21 04:23:11,107 INFO L290 TraceCheckUtils]: 107: Hoare triple {55848#false} assume !(1 == ~E_1~0); {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 108: Hoare triple {55848#false} assume !(1 == ~E_2~0); {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 109: Hoare triple {55848#false} assume !(1 == ~E_3~0); {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 110: Hoare triple {55848#false} assume !(1 == ~E_4~0); {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 111: Hoare triple {55848#false} assume !(1 == ~E_5~0); {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 112: Hoare triple {55848#false} assume !(1 == ~E_6~0); {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 113: Hoare triple {55848#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 114: Hoare triple {55848#false} assume !(1 == ~E_8~0); {55848#false} is VALID [2022-02-21 04:23:11,108 INFO L290 TraceCheckUtils]: 115: Hoare triple {55848#false} assume !(1 == ~E_9~0); {55848#false} is VALID [2022-02-21 04:23:11,109 INFO L290 TraceCheckUtils]: 116: Hoare triple {55848#false} assume { :end_inline_reset_delta_events } true; {55848#false} is VALID [2022-02-21 04:23:11,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,109 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,109 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36634964] [2022-02-21 04:23:11,109 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36634964] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,110 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,110 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:11,110 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350732677] [2022-02-21 04:23:11,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:11,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1874720270, now seen corresponding path program 1 times [2022-02-21 04:23:11,111 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,111 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017472590] [2022-02-21 04:23:11,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,150 INFO L290 TraceCheckUtils]: 0: Hoare triple {55850#true} assume !false; {55850#true} is VALID [2022-02-21 04:23:11,151 INFO L290 TraceCheckUtils]: 1: Hoare triple {55850#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {55850#true} is VALID [2022-02-21 04:23:11,151 INFO L290 TraceCheckUtils]: 2: Hoare triple {55850#true} assume !false; {55850#true} is VALID [2022-02-21 04:23:11,151 INFO L290 TraceCheckUtils]: 3: Hoare triple {55850#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {55850#true} is VALID [2022-02-21 04:23:11,151 INFO L290 TraceCheckUtils]: 4: Hoare triple {55850#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {55850#true} is VALID [2022-02-21 04:23:11,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {55850#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {55850#true} is VALID [2022-02-21 04:23:11,151 INFO L290 TraceCheckUtils]: 6: Hoare triple {55850#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 7: Hoare triple {55850#true} assume !(0 != eval_~tmp~0#1); {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 8: Hoare triple {55850#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 9: Hoare triple {55850#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 10: Hoare triple {55850#true} assume !(0 == ~M_E~0); {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {55850#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 12: Hoare triple {55850#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 13: Hoare triple {55850#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,152 INFO L290 TraceCheckUtils]: 14: Hoare triple {55850#true} assume !(0 == ~T4_E~0); {55850#true} is VALID [2022-02-21 04:23:11,153 INFO L290 TraceCheckUtils]: 15: Hoare triple {55850#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,153 INFO L290 TraceCheckUtils]: 16: Hoare triple {55850#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,153 INFO L290 TraceCheckUtils]: 17: Hoare triple {55850#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,153 INFO L290 TraceCheckUtils]: 18: Hoare triple {55850#true} assume !(0 == ~T8_E~0); {55850#true} is VALID [2022-02-21 04:23:11,153 INFO L290 TraceCheckUtils]: 19: Hoare triple {55850#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,153 INFO L290 TraceCheckUtils]: 20: Hoare triple {55850#true} assume 0 == ~E_M~0;~E_M~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,153 INFO L290 TraceCheckUtils]: 21: Hoare triple {55850#true} assume 0 == ~E_1~0;~E_1~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 22: Hoare triple {55850#true} assume !(0 == ~E_2~0); {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 23: Hoare triple {55850#true} assume 0 == ~E_3~0;~E_3~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 24: Hoare triple {55850#true} assume 0 == ~E_4~0;~E_4~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 25: Hoare triple {55850#true} assume 0 == ~E_5~0;~E_5~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 26: Hoare triple {55850#true} assume !(0 == ~E_6~0); {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 27: Hoare triple {55850#true} assume 0 == ~E_7~0;~E_7~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 28: Hoare triple {55850#true} assume 0 == ~E_8~0;~E_8~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,154 INFO L290 TraceCheckUtils]: 29: Hoare triple {55850#true} assume 0 == ~E_9~0;~E_9~0 := 1; {55850#true} is VALID [2022-02-21 04:23:11,155 INFO L290 TraceCheckUtils]: 30: Hoare triple {55850#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55850#true} is VALID [2022-02-21 04:23:11,155 INFO L290 TraceCheckUtils]: 31: Hoare triple {55850#true} assume !(1 == ~m_pc~0); {55850#true} is VALID [2022-02-21 04:23:11,155 INFO L290 TraceCheckUtils]: 32: Hoare triple {55850#true} is_master_triggered_~__retres1~0#1 := 0; {55850#true} is VALID [2022-02-21 04:23:11,155 INFO L290 TraceCheckUtils]: 33: Hoare triple {55850#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55850#true} is VALID [2022-02-21 04:23:11,155 INFO L290 TraceCheckUtils]: 34: Hoare triple {55850#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {55850#true} is VALID [2022-02-21 04:23:11,155 INFO L290 TraceCheckUtils]: 35: Hoare triple {55850#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {55850#true} is VALID [2022-02-21 04:23:11,155 INFO L290 TraceCheckUtils]: 36: Hoare triple {55850#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 37: Hoare triple {55850#true} assume 1 == ~t1_pc~0; {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 38: Hoare triple {55850#true} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 39: Hoare triple {55850#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 40: Hoare triple {55850#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 41: Hoare triple {55850#true} assume !(0 != activate_threads_~tmp___0~0#1); {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 42: Hoare triple {55850#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 43: Hoare triple {55850#true} assume !(1 == ~t2_pc~0); {55850#true} is VALID [2022-02-21 04:23:11,156 INFO L290 TraceCheckUtils]: 44: Hoare triple {55850#true} is_transmit2_triggered_~__retres1~2#1 := 0; {55850#true} is VALID [2022-02-21 04:23:11,157 INFO L290 TraceCheckUtils]: 45: Hoare triple {55850#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55850#true} is VALID [2022-02-21 04:23:11,157 INFO L290 TraceCheckUtils]: 46: Hoare triple {55850#true} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {55850#true} is VALID [2022-02-21 04:23:11,157 INFO L290 TraceCheckUtils]: 47: Hoare triple {55850#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {55850#true} is VALID [2022-02-21 04:23:11,157 INFO L290 TraceCheckUtils]: 48: Hoare triple {55850#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55850#true} is VALID [2022-02-21 04:23:11,157 INFO L290 TraceCheckUtils]: 49: Hoare triple {55850#true} assume !(1 == ~t3_pc~0); {55850#true} is VALID [2022-02-21 04:23:11,157 INFO L290 TraceCheckUtils]: 50: Hoare triple {55850#true} is_transmit3_triggered_~__retres1~3#1 := 0; {55850#true} is VALID [2022-02-21 04:23:11,157 INFO L290 TraceCheckUtils]: 51: Hoare triple {55850#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 52: Hoare triple {55850#true} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 53: Hoare triple {55850#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 54: Hoare triple {55850#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 55: Hoare triple {55850#true} assume !(1 == ~t4_pc~0); {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 56: Hoare triple {55850#true} is_transmit4_triggered_~__retres1~4#1 := 0; {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 57: Hoare triple {55850#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 58: Hoare triple {55850#true} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55850#true} is VALID [2022-02-21 04:23:11,158 INFO L290 TraceCheckUtils]: 59: Hoare triple {55850#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {55850#true} is VALID [2022-02-21 04:23:11,159 INFO L290 TraceCheckUtils]: 60: Hoare triple {55850#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55850#true} is VALID [2022-02-21 04:23:11,159 INFO L290 TraceCheckUtils]: 61: Hoare triple {55850#true} assume !(1 == ~t5_pc~0); {55850#true} is VALID [2022-02-21 04:23:11,159 INFO L290 TraceCheckUtils]: 62: Hoare triple {55850#true} is_transmit5_triggered_~__retres1~5#1 := 0; {55850#true} is VALID [2022-02-21 04:23:11,159 INFO L290 TraceCheckUtils]: 63: Hoare triple {55850#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55850#true} is VALID [2022-02-21 04:23:11,159 INFO L290 TraceCheckUtils]: 64: Hoare triple {55850#true} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55850#true} is VALID [2022-02-21 04:23:11,159 INFO L290 TraceCheckUtils]: 65: Hoare triple {55850#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {55850#true} is VALID [2022-02-21 04:23:11,159 INFO L290 TraceCheckUtils]: 66: Hoare triple {55850#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55850#true} is VALID [2022-02-21 04:23:11,160 INFO L290 TraceCheckUtils]: 67: Hoare triple {55850#true} assume 1 == ~t6_pc~0; {55850#true} is VALID [2022-02-21 04:23:11,160 INFO L290 TraceCheckUtils]: 68: Hoare triple {55850#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,160 INFO L290 TraceCheckUtils]: 69: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,161 INFO L290 TraceCheckUtils]: 70: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,161 INFO L290 TraceCheckUtils]: 71: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,161 INFO L290 TraceCheckUtils]: 72: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,162 INFO L290 TraceCheckUtils]: 73: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,162 INFO L290 TraceCheckUtils]: 74: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,163 INFO L290 TraceCheckUtils]: 75: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,163 INFO L290 TraceCheckUtils]: 76: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,163 INFO L290 TraceCheckUtils]: 77: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,164 INFO L290 TraceCheckUtils]: 78: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,164 INFO L290 TraceCheckUtils]: 79: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,164 INFO L290 TraceCheckUtils]: 80: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,165 INFO L290 TraceCheckUtils]: 81: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,165 INFO L290 TraceCheckUtils]: 82: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,165 INFO L290 TraceCheckUtils]: 83: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,166 INFO L290 TraceCheckUtils]: 84: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,166 INFO L290 TraceCheckUtils]: 85: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t9_pc~0; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,166 INFO L290 TraceCheckUtils]: 86: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,167 INFO L290 TraceCheckUtils]: 87: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,167 INFO L290 TraceCheckUtils]: 88: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,167 INFO L290 TraceCheckUtils]: 89: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,168 INFO L290 TraceCheckUtils]: 90: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,168 INFO L290 TraceCheckUtils]: 91: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~M_E~0); {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,169 INFO L290 TraceCheckUtils]: 92: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,169 INFO L290 TraceCheckUtils]: 93: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,169 INFO L290 TraceCheckUtils]: 94: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,170 INFO L290 TraceCheckUtils]: 95: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,170 INFO L290 TraceCheckUtils]: 96: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,170 INFO L290 TraceCheckUtils]: 97: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,171 INFO L290 TraceCheckUtils]: 98: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,171 INFO L290 TraceCheckUtils]: 99: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T8_E~0); {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,171 INFO L290 TraceCheckUtils]: 100: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,172 INFO L290 TraceCheckUtils]: 101: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,172 INFO L290 TraceCheckUtils]: 102: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,172 INFO L290 TraceCheckUtils]: 103: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_2~0); {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,173 INFO L290 TraceCheckUtils]: 104: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,173 INFO L290 TraceCheckUtils]: 105: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,173 INFO L290 TraceCheckUtils]: 106: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {55852#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:11,174 INFO L290 TraceCheckUtils]: 107: Hoare triple {55852#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {55851#false} is VALID [2022-02-21 04:23:11,174 INFO L290 TraceCheckUtils]: 108: Hoare triple {55851#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55851#false} is VALID [2022-02-21 04:23:11,174 INFO L290 TraceCheckUtils]: 109: Hoare triple {55851#false} assume 1 == ~E_8~0;~E_8~0 := 2; {55851#false} is VALID [2022-02-21 04:23:11,174 INFO L290 TraceCheckUtils]: 110: Hoare triple {55851#false} assume 1 == ~E_9~0;~E_9~0 := 2; {55851#false} is VALID [2022-02-21 04:23:11,174 INFO L290 TraceCheckUtils]: 111: Hoare triple {55851#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {55851#false} is VALID [2022-02-21 04:23:11,174 INFO L290 TraceCheckUtils]: 112: Hoare triple {55851#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {55851#false} is VALID [2022-02-21 04:23:11,175 INFO L290 TraceCheckUtils]: 113: Hoare triple {55851#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {55851#false} is VALID [2022-02-21 04:23:11,175 INFO L290 TraceCheckUtils]: 114: Hoare triple {55851#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {55851#false} is VALID [2022-02-21 04:23:11,175 INFO L290 TraceCheckUtils]: 115: Hoare triple {55851#false} assume !(0 == start_simulation_~tmp~3#1); {55851#false} is VALID [2022-02-21 04:23:11,175 INFO L290 TraceCheckUtils]: 116: Hoare triple {55851#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {55851#false} is VALID [2022-02-21 04:23:11,175 INFO L290 TraceCheckUtils]: 117: Hoare triple {55851#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {55851#false} is VALID [2022-02-21 04:23:11,175 INFO L290 TraceCheckUtils]: 118: Hoare triple {55851#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {55851#false} is VALID [2022-02-21 04:23:11,175 INFO L290 TraceCheckUtils]: 119: Hoare triple {55851#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {55851#false} is VALID [2022-02-21 04:23:11,176 INFO L290 TraceCheckUtils]: 120: Hoare triple {55851#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {55851#false} is VALID [2022-02-21 04:23:11,176 INFO L290 TraceCheckUtils]: 121: Hoare triple {55851#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {55851#false} is VALID [2022-02-21 04:23:11,176 INFO L290 TraceCheckUtils]: 122: Hoare triple {55851#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {55851#false} is VALID [2022-02-21 04:23:11,176 INFO L290 TraceCheckUtils]: 123: Hoare triple {55851#false} assume !(0 != start_simulation_~tmp___0~1#1); {55851#false} is VALID [2022-02-21 04:23:11,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,177 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,177 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017472590] [2022-02-21 04:23:11,177 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017472590] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,177 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,177 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,177 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869579697] [2022-02-21 04:23:11,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,178 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:11,178 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:11,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:11,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:11,179 INFO L87 Difference]: Start difference. First operand 2141 states and 3133 transitions. cyclomatic complexity: 994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,024 INFO L93 Difference]: Finished difference Result 4105 states and 5952 transitions. [2022-02-21 04:23:13,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:13,025 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,095 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:13,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4105 states and 5952 transitions. [2022-02-21 04:23:13,540 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3957 [2022-02-21 04:23:13,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4105 states to 4105 states and 5952 transitions. [2022-02-21 04:23:13,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4105 [2022-02-21 04:23:13,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4105 [2022-02-21 04:23:13,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4105 states and 5952 transitions. [2022-02-21 04:23:13,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:13,995 INFO L681 BuchiCegarLoop]: Abstraction has 4105 states and 5952 transitions. [2022-02-21 04:23:13,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4105 states and 5952 transitions. [2022-02-21 04:23:14,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4105 to 3967. [2022-02-21 04:23:14,058 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:14,063 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4105 states and 5952 transitions. Second operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,069 INFO L74 IsIncluded]: Start isIncluded. First operand 4105 states and 5952 transitions. Second operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,074 INFO L87 Difference]: Start difference. First operand 4105 states and 5952 transitions. Second operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,469 INFO L93 Difference]: Finished difference Result 4105 states and 5952 transitions. [2022-02-21 04:23:14,469 INFO L276 IsEmpty]: Start isEmpty. Operand 4105 states and 5952 transitions. [2022-02-21 04:23:14,472 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,472 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,477 INFO L74 IsIncluded]: Start isIncluded. First operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4105 states and 5952 transitions. [2022-02-21 04:23:14,482 INFO L87 Difference]: Start difference. First operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4105 states and 5952 transitions. [2022-02-21 04:23:14,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,851 INFO L93 Difference]: Finished difference Result 4105 states and 5952 transitions. [2022-02-21 04:23:14,851 INFO L276 IsEmpty]: Start isEmpty. Operand 4105 states and 5952 transitions. [2022-02-21 04:23:14,855 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,855 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,855 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:14,855 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:14,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3967 states to 3967 states and 5760 transitions. [2022-02-21 04:23:15,212 INFO L704 BuchiCegarLoop]: Abstraction has 3967 states and 5760 transitions. [2022-02-21 04:23:15,212 INFO L587 BuchiCegarLoop]: Abstraction has 3967 states and 5760 transitions. [2022-02-21 04:23:15,212 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:15,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3967 states and 5760 transitions. [2022-02-21 04:23:15,222 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3819 [2022-02-21 04:23:15,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:15,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:15,224 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,224 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,225 INFO L791 eck$LassoCheckResult]: Stem: 60869#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 60870#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 60812#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60813#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61080#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 60683#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60684#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61048#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60485#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60486#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60964#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60965#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59971#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59972#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60175#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60578#L939 assume !(0 == ~M_E~0); 60848#L939-2 assume !(0 == ~T1_E~0); 60849#L944-1 assume !(0 == ~T2_E~0); 60608#L949-1 assume !(0 == ~T3_E~0); 60606#L954-1 assume !(0 == ~T4_E~0); 60607#L959-1 assume !(0 == ~T5_E~0); 61097#L964-1 assume !(0 == ~T6_E~0); 60328#L969-1 assume !(0 == ~T7_E~0); 60329#L974-1 assume !(0 == ~T8_E~0); 61036#L979-1 assume !(0 == ~T9_E~0); 61037#L984-1 assume !(0 == ~E_M~0); 60497#L989-1 assume !(0 == ~E_1~0); 60498#L994-1 assume !(0 == ~E_2~0); 60377#L999-1 assume !(0 == ~E_3~0); 60378#L1004-1 assume !(0 == ~E_4~0); 60039#L1009-1 assume !(0 == ~E_5~0); 60040#L1014-1 assume !(0 == ~E_6~0); 60373#L1019-1 assume !(0 == ~E_7~0); 60969#L1024-1 assume !(0 == ~E_8~0); 60299#L1029-1 assume !(0 == ~E_9~0); 60300#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60393#L460 assume !(1 == ~m_pc~0); 61221#L460-2 is_master_triggered_~__retres1~0#1 := 0; 60929#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60930#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 61258#L1167 assume !(0 != activate_threads_~tmp~1#1); 60595#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60596#L479 assume 1 == ~t1_pc~0; 60579#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60580#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61179#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 60313#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 60314#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60157#L498 assume !(1 == ~t2_pc~0); 60158#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60576#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60577#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61007#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60919#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60920#L517 assume 1 == ~t3_pc~0; 61187#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 61188#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60651#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60346#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 60347#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60981#L536 assume !(1 == ~t4_pc~0); 60641#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 60640#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61087#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60633#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 60634#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60883#L555 assume 1 == ~t5_pc~0; 60884#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60970#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60073#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60074#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 60180#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60079#L574 assume !(1 == ~t6_pc~0); 60080#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 60732#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60183#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60184#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 61002#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61226#L593 assume 1 == ~t7_pc~0; 61227#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60320#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61102#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61274#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 61190#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60490#L612 assume !(1 == ~t8_pc~0); 60491#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 60948#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60777#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60778#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 60737#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60738#L631 assume 1 == ~t9_pc~0; 60756#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60070#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60037#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60038#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 60582#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60982#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 60009#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60010#L1052-1 assume !(1 == ~T2_E~0); 59990#L1057-1 assume !(1 == ~T3_E~0); 59991#L1062-1 assume !(1 == ~T4_E~0); 60282#L1067-1 assume !(1 == ~T5_E~0); 60599#L1072-1 assume !(1 == ~T6_E~0); 60600#L1077-1 assume !(1 == ~T7_E~0); 60171#L1082-1 assume !(1 == ~T8_E~0); 60172#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 59967#L1092-1 assume !(1 == ~E_M~0); 59968#L1097-1 assume !(1 == ~E_1~0); 59992#L1102-1 assume !(1 == ~E_2~0); 60808#L1107-1 assume !(1 == ~E_3~0); 60730#L1112-1 assume !(1 == ~E_4~0); 60731#L1117-1 assume !(1 == ~E_5~0); 60779#L1122-1 assume !(1 == ~E_6~0); 60652#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60396#L1132-1 assume !(1 == ~E_8~0); 60397#L1137-1 assume !(1 == ~E_9~0); 61216#L1142-1 assume { :end_inline_reset_delta_events } true; 63108#L1428-2 [2022-02-21 04:23:15,225 INFO L793 eck$LassoCheckResult]: Loop: 63108#L1428-2 assume !false; 60727#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60214#L914 assume !false; 60725#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 60726#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 63042#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 61214#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 61215#L783 assume !(0 != eval_~tmp~0#1); 60380#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60381#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62196#L939-3 assume !(0 == ~M_E~0); 63031#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62190#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62191#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62186#L954-3 assume !(0 == ~T4_E~0); 62187#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62170#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62171#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62166#L974-3 assume !(0 == ~T8_E~0); 62167#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62162#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62163#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62158#L994-3 assume !(0 == ~E_2~0); 62159#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62154#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62155#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62150#L1014-3 assume !(0 == ~E_6~0); 62151#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61291#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61292#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 60619#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60620#L460-33 assume !(1 == ~m_pc~0); 60898#L460-35 is_master_triggered_~__retres1~0#1 := 0; 60899#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63875#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59969#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59970#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60335#L479-33 assume !(1 == ~t1_pc~0); 60336#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 60301#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60302#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61158#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 61159#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60344#L498-33 assume !(1 == ~t2_pc~0); 60084#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 60085#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63872#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60719#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60197#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60198#L517-33 assume !(1 == ~t3_pc~0); 61246#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 61069#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61070#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60841#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60842#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60436#L536-33 assume 1 == ~t4_pc~0; 60437#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60508#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60509#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60705#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61041#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60016#L555-33 assume !(1 == ~t5_pc~0); 60017#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 61081#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60292#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60293#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60801#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59982#L574-33 assume !(1 == ~t6_pc~0); 59984#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 61054#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60307#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60308#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60573#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60058#L593-33 assume !(1 == ~t7_pc~0); 60059#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 60526#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60169#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60170#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60871#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61026#L612-33 assume 1 == ~t8_pc~0; 61202#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61147#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61148#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60949#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60167#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60168#L631-33 assume 1 == ~t9_pc~0; 61095#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60108#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60109#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60368#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60219#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60220#L1047-3 assume !(1 == ~M_E~0); 60400#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61096#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61011#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61012#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60120#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60121#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60515#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60353#L1082-3 assume !(1 == ~T8_E~0); 60354#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60432#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 60724#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60649#L1102-3 assume !(1 == ~E_2~0); 60650#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61056#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61057#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61065#L1122-3 assume !(1 == ~E_6~0); 61066#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60825#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60826#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60793#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 60794#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 60804#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 60805#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 60534#L1447 assume !(0 == start_simulation_~tmp~3#1); 60535#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 61300#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 60263#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 60827#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 60376#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 60129#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60130#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 60852#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 63108#L1428-2 [2022-02-21 04:23:15,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,226 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2022-02-21 04:23:15,226 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,226 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893077772] [2022-02-21 04:23:15,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,256 INFO L290 TraceCheckUtils]: 0: Hoare triple {72138#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,257 INFO L290 TraceCheckUtils]: 1: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,257 INFO L290 TraceCheckUtils]: 2: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,257 INFO L290 TraceCheckUtils]: 3: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,258 INFO L290 TraceCheckUtils]: 4: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,258 INFO L290 TraceCheckUtils]: 5: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,259 INFO L290 TraceCheckUtils]: 6: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,259 INFO L290 TraceCheckUtils]: 7: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,259 INFO L290 TraceCheckUtils]: 8: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,260 INFO L290 TraceCheckUtils]: 9: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,260 INFO L290 TraceCheckUtils]: 10: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,260 INFO L290 TraceCheckUtils]: 11: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,261 INFO L290 TraceCheckUtils]: 12: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,261 INFO L290 TraceCheckUtils]: 13: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,261 INFO L290 TraceCheckUtils]: 14: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,262 INFO L290 TraceCheckUtils]: 15: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,262 INFO L290 TraceCheckUtils]: 16: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,262 INFO L290 TraceCheckUtils]: 17: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,263 INFO L290 TraceCheckUtils]: 18: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,263 INFO L290 TraceCheckUtils]: 19: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,264 INFO L290 TraceCheckUtils]: 20: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,264 INFO L290 TraceCheckUtils]: 21: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,264 INFO L290 TraceCheckUtils]: 22: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,265 INFO L290 TraceCheckUtils]: 23: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,265 INFO L290 TraceCheckUtils]: 24: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T9_E~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,265 INFO L290 TraceCheckUtils]: 25: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 26: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 27: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 28: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 29: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 30: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 31: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 32: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 33: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 34: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_9~0); {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 35: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {72140#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 36: Hoare triple {72140#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {72141#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 37: Hoare triple {72141#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {72141#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 38: Hoare triple {72141#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {72141#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 39: Hoare triple {72141#(not (= ~t1_pc~0 1))} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {72141#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 40: Hoare triple {72141#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {72141#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 41: Hoare triple {72141#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {72141#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 42: Hoare triple {72141#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {72139#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 43: Hoare triple {72139#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {72139#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 44: Hoare triple {72139#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {72139#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 45: Hoare triple {72139#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 46: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___0~0#1); {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 47: Hoare triple {72139#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 48: Hoare triple {72139#false} assume !(1 == ~t2_pc~0); {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 49: Hoare triple {72139#false} is_transmit2_triggered_~__retres1~2#1 := 0; {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 50: Hoare triple {72139#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 51: Hoare triple {72139#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 52: Hoare triple {72139#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {72139#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 53: Hoare triple {72139#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {72139#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 54: Hoare triple {72139#false} assume 1 == ~t3_pc~0; {72139#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 55: Hoare triple {72139#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {72139#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 56: Hoare triple {72139#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {72139#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 57: Hoare triple {72139#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {72139#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 58: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___2~0#1); {72139#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 59: Hoare triple {72139#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {72139#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 60: Hoare triple {72139#false} assume !(1 == ~t4_pc~0); {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 61: Hoare triple {72139#false} is_transmit4_triggered_~__retres1~4#1 := 0; {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 62: Hoare triple {72139#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 63: Hoare triple {72139#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 64: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___3~0#1); {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 65: Hoare triple {72139#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 66: Hoare triple {72139#false} assume 1 == ~t5_pc~0; {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 67: Hoare triple {72139#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {72139#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 68: Hoare triple {72139#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 69: Hoare triple {72139#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 70: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___4~0#1); {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 71: Hoare triple {72139#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 72: Hoare triple {72139#false} assume !(1 == ~t6_pc~0); {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 73: Hoare triple {72139#false} is_transmit6_triggered_~__retres1~6#1 := 0; {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 74: Hoare triple {72139#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 75: Hoare triple {72139#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {72139#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 76: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___5~0#1); {72139#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 77: Hoare triple {72139#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {72139#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 78: Hoare triple {72139#false} assume 1 == ~t7_pc~0; {72139#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 79: Hoare triple {72139#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {72139#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 80: Hoare triple {72139#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {72139#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 81: Hoare triple {72139#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {72139#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 82: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___6~0#1); {72139#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 83: Hoare triple {72139#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 84: Hoare triple {72139#false} assume !(1 == ~t8_pc~0); {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 85: Hoare triple {72139#false} is_transmit8_triggered_~__retres1~8#1 := 0; {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 86: Hoare triple {72139#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 87: Hoare triple {72139#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 88: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___7~0#1); {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 89: Hoare triple {72139#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 90: Hoare triple {72139#false} assume 1 == ~t9_pc~0; {72139#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 91: Hoare triple {72139#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 92: Hoare triple {72139#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 93: Hoare triple {72139#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 94: Hoare triple {72139#false} assume !(0 != activate_threads_~tmp___8~0#1); {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 95: Hoare triple {72139#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 96: Hoare triple {72139#false} assume 1 == ~M_E~0;~M_E~0 := 2; {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 97: Hoare triple {72139#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 98: Hoare triple {72139#false} assume !(1 == ~T2_E~0); {72139#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 99: Hoare triple {72139#false} assume !(1 == ~T3_E~0); {72139#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 100: Hoare triple {72139#false} assume !(1 == ~T4_E~0); {72139#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 101: Hoare triple {72139#false} assume !(1 == ~T5_E~0); {72139#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 102: Hoare triple {72139#false} assume !(1 == ~T6_E~0); {72139#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 103: Hoare triple {72139#false} assume !(1 == ~T7_E~0); {72139#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 104: Hoare triple {72139#false} assume !(1 == ~T8_E~0); {72139#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 105: Hoare triple {72139#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {72139#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 106: Hoare triple {72139#false} assume !(1 == ~E_M~0); {72139#false} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 107: Hoare triple {72139#false} assume !(1 == ~E_1~0); {72139#false} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 108: Hoare triple {72139#false} assume !(1 == ~E_2~0); {72139#false} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 109: Hoare triple {72139#false} assume !(1 == ~E_3~0); {72139#false} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 110: Hoare triple {72139#false} assume !(1 == ~E_4~0); {72139#false} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 111: Hoare triple {72139#false} assume !(1 == ~E_5~0); {72139#false} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 112: Hoare triple {72139#false} assume !(1 == ~E_6~0); {72139#false} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 113: Hoare triple {72139#false} assume 1 == ~E_7~0;~E_7~0 := 2; {72139#false} is VALID [2022-02-21 04:23:15,281 INFO L290 TraceCheckUtils]: 114: Hoare triple {72139#false} assume !(1 == ~E_8~0); {72139#false} is VALID [2022-02-21 04:23:15,281 INFO L290 TraceCheckUtils]: 115: Hoare triple {72139#false} assume !(1 == ~E_9~0); {72139#false} is VALID [2022-02-21 04:23:15,281 INFO L290 TraceCheckUtils]: 116: Hoare triple {72139#false} assume { :end_inline_reset_delta_events } true; {72139#false} is VALID [2022-02-21 04:23:15,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,281 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,281 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893077772] [2022-02-21 04:23:15,282 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893077772] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,282 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,282 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,282 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552679929] [2022-02-21 04:23:15,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,283 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:15,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,283 INFO L85 PathProgramCache]: Analyzing trace with hash -507881457, now seen corresponding path program 1 times [2022-02-21 04:23:15,283 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,283 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87846053] [2022-02-21 04:23:15,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,315 INFO L290 TraceCheckUtils]: 0: Hoare triple {72142#true} assume !false; {72142#true} is VALID [2022-02-21 04:23:15,315 INFO L290 TraceCheckUtils]: 1: Hoare triple {72142#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {72142#true} is VALID [2022-02-21 04:23:15,316 INFO L290 TraceCheckUtils]: 2: Hoare triple {72142#true} assume !false; {72142#true} is VALID [2022-02-21 04:23:15,316 INFO L290 TraceCheckUtils]: 3: Hoare triple {72142#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {72142#true} is VALID [2022-02-21 04:23:15,316 INFO L290 TraceCheckUtils]: 4: Hoare triple {72142#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {72144#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} is VALID [2022-02-21 04:23:15,317 INFO L290 TraceCheckUtils]: 5: Hoare triple {72144#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {72145#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:23:15,317 INFO L290 TraceCheckUtils]: 6: Hoare triple {72145#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {72146#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 7: Hoare triple {72146#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {72143#false} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 8: Hoare triple {72143#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {72143#false} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 9: Hoare triple {72143#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {72143#false} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 10: Hoare triple {72143#false} assume !(0 == ~M_E~0); {72143#false} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 11: Hoare triple {72143#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 12: Hoare triple {72143#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 13: Hoare triple {72143#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 14: Hoare triple {72143#false} assume !(0 == ~T4_E~0); {72143#false} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 15: Hoare triple {72143#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 16: Hoare triple {72143#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 17: Hoare triple {72143#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 18: Hoare triple {72143#false} assume !(0 == ~T8_E~0); {72143#false} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 19: Hoare triple {72143#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 20: Hoare triple {72143#false} assume 0 == ~E_M~0;~E_M~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 21: Hoare triple {72143#false} assume 0 == ~E_1~0;~E_1~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 22: Hoare triple {72143#false} assume !(0 == ~E_2~0); {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 23: Hoare triple {72143#false} assume 0 == ~E_3~0;~E_3~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 24: Hoare triple {72143#false} assume 0 == ~E_4~0;~E_4~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 25: Hoare triple {72143#false} assume 0 == ~E_5~0;~E_5~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 26: Hoare triple {72143#false} assume !(0 == ~E_6~0); {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 27: Hoare triple {72143#false} assume 0 == ~E_7~0;~E_7~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 28: Hoare triple {72143#false} assume 0 == ~E_8~0;~E_8~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 29: Hoare triple {72143#false} assume 0 == ~E_9~0;~E_9~0 := 1; {72143#false} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 30: Hoare triple {72143#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {72143#false} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 31: Hoare triple {72143#false} assume !(1 == ~m_pc~0); {72143#false} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 32: Hoare triple {72143#false} is_master_triggered_~__retres1~0#1 := 0; {72143#false} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 33: Hoare triple {72143#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {72143#false} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 34: Hoare triple {72143#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {72143#false} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 35: Hoare triple {72143#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 36: Hoare triple {72143#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 37: Hoare triple {72143#false} assume !(1 == ~t1_pc~0); {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 38: Hoare triple {72143#false} is_transmit1_triggered_~__retres1~1#1 := 0; {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 39: Hoare triple {72143#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 40: Hoare triple {72143#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 41: Hoare triple {72143#false} assume !(0 != activate_threads_~tmp___0~0#1); {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 42: Hoare triple {72143#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {72143#false} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 43: Hoare triple {72143#false} assume !(1 == ~t2_pc~0); {72143#false} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 44: Hoare triple {72143#false} is_transmit2_triggered_~__retres1~2#1 := 0; {72143#false} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 45: Hoare triple {72143#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {72143#false} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 46: Hoare triple {72143#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {72143#false} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 47: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 48: Hoare triple {72143#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {72143#false} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 49: Hoare triple {72143#false} assume !(1 == ~t3_pc~0); {72143#false} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 50: Hoare triple {72143#false} is_transmit3_triggered_~__retres1~3#1 := 0; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 51: Hoare triple {72143#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 52: Hoare triple {72143#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 53: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 54: Hoare triple {72143#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 55: Hoare triple {72143#false} assume 1 == ~t4_pc~0; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 56: Hoare triple {72143#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 57: Hoare triple {72143#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {72143#false} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 58: Hoare triple {72143#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {72143#false} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 59: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 60: Hoare triple {72143#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {72143#false} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 61: Hoare triple {72143#false} assume !(1 == ~t5_pc~0); {72143#false} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 62: Hoare triple {72143#false} is_transmit5_triggered_~__retres1~5#1 := 0; {72143#false} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 63: Hoare triple {72143#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {72143#false} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 64: Hoare triple {72143#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {72143#false} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 65: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 66: Hoare triple {72143#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 67: Hoare triple {72143#false} assume !(1 == ~t6_pc~0); {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 68: Hoare triple {72143#false} is_transmit6_triggered_~__retres1~6#1 := 0; {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 69: Hoare triple {72143#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 70: Hoare triple {72143#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 71: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 72: Hoare triple {72143#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {72143#false} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 73: Hoare triple {72143#false} assume !(1 == ~t7_pc~0); {72143#false} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 74: Hoare triple {72143#false} is_transmit7_triggered_~__retres1~7#1 := 0; {72143#false} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 75: Hoare triple {72143#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {72143#false} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 76: Hoare triple {72143#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {72143#false} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 77: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 78: Hoare triple {72143#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {72143#false} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 79: Hoare triple {72143#false} assume 1 == ~t8_pc~0; {72143#false} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 80: Hoare triple {72143#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 81: Hoare triple {72143#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 82: Hoare triple {72143#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 83: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 84: Hoare triple {72143#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 85: Hoare triple {72143#false} assume 1 == ~t9_pc~0; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 86: Hoare triple {72143#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 87: Hoare triple {72143#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {72143#false} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 88: Hoare triple {72143#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 89: Hoare triple {72143#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 90: Hoare triple {72143#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 91: Hoare triple {72143#false} assume !(1 == ~M_E~0); {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 92: Hoare triple {72143#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 93: Hoare triple {72143#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 94: Hoare triple {72143#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 95: Hoare triple {72143#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 96: Hoare triple {72143#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 97: Hoare triple {72143#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 98: Hoare triple {72143#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 99: Hoare triple {72143#false} assume !(1 == ~T8_E~0); {72143#false} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 100: Hoare triple {72143#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 101: Hoare triple {72143#false} assume 1 == ~E_M~0;~E_M~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 102: Hoare triple {72143#false} assume 1 == ~E_1~0;~E_1~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 103: Hoare triple {72143#false} assume !(1 == ~E_2~0); {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 104: Hoare triple {72143#false} assume 1 == ~E_3~0;~E_3~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 105: Hoare triple {72143#false} assume 1 == ~E_4~0;~E_4~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 106: Hoare triple {72143#false} assume 1 == ~E_5~0;~E_5~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 107: Hoare triple {72143#false} assume !(1 == ~E_6~0); {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 108: Hoare triple {72143#false} assume 1 == ~E_7~0;~E_7~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 109: Hoare triple {72143#false} assume 1 == ~E_8~0;~E_8~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 110: Hoare triple {72143#false} assume 1 == ~E_9~0;~E_9~0 := 2; {72143#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 111: Hoare triple {72143#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {72143#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 112: Hoare triple {72143#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {72143#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 113: Hoare triple {72143#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {72143#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 114: Hoare triple {72143#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {72143#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 115: Hoare triple {72143#false} assume !(0 == start_simulation_~tmp~3#1); {72143#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 116: Hoare triple {72143#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {72143#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 117: Hoare triple {72143#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {72143#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 118: Hoare triple {72143#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {72143#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 119: Hoare triple {72143#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {72143#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 120: Hoare triple {72143#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {72143#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 121: Hoare triple {72143#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {72143#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 122: Hoare triple {72143#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {72143#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 123: Hoare triple {72143#false} assume !(0 != start_simulation_~tmp___0~1#1); {72143#false} is VALID [2022-02-21 04:23:15,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,334 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,334 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [87846053] [2022-02-21 04:23:15,334 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [87846053] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,334 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,334 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:23:15,334 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288411151] [2022-02-21 04:23:15,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,335 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:15,335 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:15,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:15,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:15,336 INFO L87 Difference]: Start difference. First operand 3967 states and 5760 transitions. cyclomatic complexity: 1797 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,237 INFO L93 Difference]: Finished difference Result 9505 states and 13663 transitions. [2022-02-21 04:23:20,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:20,237 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,309 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:20,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9505 states and 13663 transitions. [2022-02-21 04:23:22,303 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9204 [2022-02-21 04:23:24,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9505 states to 9505 states and 13663 transitions. [2022-02-21 04:23:24,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9505 [2022-02-21 04:23:24,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9505 [2022-02-21 04:23:24,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9505 states and 13663 transitions. [2022-02-21 04:23:24,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:24,346 INFO L681 BuchiCegarLoop]: Abstraction has 9505 states and 13663 transitions. [2022-02-21 04:23:24,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9505 states and 13663 transitions. [2022-02-21 04:23:24,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9505 to 7449. [2022-02-21 04:23:24,469 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:24,479 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9505 states and 13663 transitions. Second operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,490 INFO L74 IsIncluded]: Start isIncluded. First operand 9505 states and 13663 transitions. Second operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,502 INFO L87 Difference]: Start difference. First operand 9505 states and 13663 transitions. Second operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,411 INFO L93 Difference]: Finished difference Result 9505 states and 13663 transitions. [2022-02-21 04:23:26,411 INFO L276 IsEmpty]: Start isEmpty. Operand 9505 states and 13663 transitions. [2022-02-21 04:23:26,420 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,420 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,428 INFO L74 IsIncluded]: Start isIncluded. First operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9505 states and 13663 transitions. [2022-02-21 04:23:26,434 INFO L87 Difference]: Start difference. First operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9505 states and 13663 transitions. [2022-02-21 04:23:28,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,419 INFO L93 Difference]: Finished difference Result 9505 states and 13663 transitions. [2022-02-21 04:23:28,419 INFO L276 IsEmpty]: Start isEmpty. Operand 9505 states and 13663 transitions. [2022-02-21 04:23:28,429 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:28,429 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:28,429 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:28,429 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:28,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7449 states to 7449 states and 10750 transitions. [2022-02-21 04:23:29,582 INFO L704 BuchiCegarLoop]: Abstraction has 7449 states and 10750 transitions. [2022-02-21 04:23:29,582 INFO L587 BuchiCegarLoop]: Abstraction has 7449 states and 10750 transitions. [2022-02-21 04:23:29,582 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:29,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7449 states and 10750 transitions. [2022-02-21 04:23:29,592 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7300 [2022-02-21 04:23:29,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:29,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:29,594 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,594 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,594 INFO L791 eck$LassoCheckResult]: Stem: 82541#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 82542#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 82488#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82489#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82726#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 82358#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82359#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82702#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82170#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82171#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82624#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82625#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81667#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81668#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81870#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82263#L939 assume !(0 == ~M_E~0); 82520#L939-2 assume !(0 == ~T1_E~0); 82521#L944-1 assume !(0 == ~T2_E~0); 82289#L949-1 assume !(0 == ~T3_E~0); 82287#L954-1 assume !(0 == ~T4_E~0); 82288#L959-1 assume !(0 == ~T5_E~0); 82743#L964-1 assume !(0 == ~T6_E~0); 82021#L969-1 assume !(0 == ~T7_E~0); 82022#L974-1 assume !(0 == ~T8_E~0); 82688#L979-1 assume !(0 == ~T9_E~0); 82689#L984-1 assume !(0 == ~E_M~0); 82182#L989-1 assume !(0 == ~E_1~0); 82183#L994-1 assume !(0 == ~E_2~0); 82068#L999-1 assume !(0 == ~E_3~0); 82069#L1004-1 assume !(0 == ~E_4~0); 81736#L1009-1 assume !(0 == ~E_5~0); 81737#L1014-1 assume !(0 == ~E_6~0); 82060#L1019-1 assume !(0 == ~E_7~0); 82631#L1024-1 assume !(0 == ~E_8~0); 81993#L1029-1 assume !(0 == ~E_9~0); 81994#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82082#L460 assume !(1 == ~m_pc~0); 82862#L460-2 is_master_triggered_~__retres1~0#1 := 0; 82594#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82595#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82885#L1167 assume !(0 != activate_threads_~tmp~1#1); 82276#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82277#L479 assume !(1 == ~t1_pc~0); 82435#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82436#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82819#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82005#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 82006#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81852#L498 assume !(1 == ~t2_pc~0); 81853#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82261#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82262#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82666#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82581#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82582#L517 assume 1 == ~t3_pc~0; 82824#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 82825#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82331#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82038#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 82039#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82640#L536 assume !(1 == ~t4_pc~0); 82321#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82320#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82731#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82313#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 82314#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82550#L555 assume 1 == ~t5_pc~0; 82551#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82632#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81767#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81768#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 81873#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81775#L574 assume !(1 == ~t6_pc~0); 81776#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 82411#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81878#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81879#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 82659#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82867#L593 assume 1 == ~t7_pc~0; 82868#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82013#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82748#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82899#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 82830#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82177#L612 assume !(1 == ~t8_pc~0); 82178#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82612#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82455#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82456#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 82413#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82414#L631 assume 1 == ~t9_pc~0; 82433#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81766#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81734#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81735#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 82264#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82643#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 81704#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81705#L1052-1 assume !(1 == ~T2_E~0); 81686#L1057-1 assume !(1 == ~T3_E~0); 81687#L1062-1 assume !(1 == ~T4_E~0); 81976#L1067-1 assume !(1 == ~T5_E~0); 82744#L1072-1 assume !(1 == ~T6_E~0); 82614#L1077-1 assume !(1 == ~T7_E~0); 82615#L1082-1 assume !(1 == ~T8_E~0); 82385#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 82386#L1092-1 assume !(1 == ~E_M~0); 81688#L1097-1 assume !(1 == ~E_1~0); 81689#L1102-1 assume !(1 == ~E_2~0); 82483#L1107-1 assume !(1 == ~E_3~0); 82484#L1112-1 assume !(1 == ~E_4~0); 82457#L1117-1 assume !(1 == ~E_5~0); 82458#L1122-1 assume !(1 == ~E_6~0); 82332#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 82333#L1132-1 assume !(1 == ~E_8~0); 82856#L1137-1 assume !(1 == ~E_9~0); 82857#L1142-1 assume { :end_inline_reset_delta_events } true; 88319#L1428-2 [2022-02-21 04:23:29,594 INFO L793 eck$LassoCheckResult]: Loop: 88319#L1428-2 assume !false; 88313#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88309#L914 assume !false; 88308#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 88306#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 88297#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 88296#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 88295#L783 assume !(0 != eval_~tmp~0#1); 82071#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82072#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82482#L939-3 assume !(0 == ~M_E~0); 81890#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 81891#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 81657#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 81658#L954-3 assume !(0 == ~T4_E~0); 82295#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81738#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81739#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81943#L974-3 assume !(0 == ~T8_E~0); 81944#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82376#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 82377#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 81999#L994-3 assume !(0 == ~E_2~0); 82000#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 82527#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81820#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81821#L1014-3 assume !(0 == ~E_6~0); 82360#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 82361#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 82344#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 82296#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82297#L460-33 assume !(1 == ~m_pc~0); 82565#L460-35 is_master_triggered_~__retres1~0#1 := 0; 82544#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82089#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81665#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81666#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82025#L479-33 assume !(1 == ~t1_pc~0); 82026#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 81995#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81996#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82606#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 82800#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82033#L498-33 assume !(1 == ~t2_pc~0); 81780#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 81781#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81914#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81915#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81892#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81893#L517-33 assume !(1 == ~t3_pc~0); 82877#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 88973#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88971#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88969#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88966#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88964#L536-33 assume 1 == ~t4_pc~0; 88961#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 88959#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88957#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88955#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88953#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88950#L555-33 assume !(1 == ~t5_pc~0); 88947#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 88946#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88945#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88944#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88943#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88942#L574-33 assume !(1 == ~t6_pc~0); 88941#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 88939#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88938#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88937#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88936#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88935#L593-33 assume 1 == ~t7_pc~0; 88933#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88931#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88930#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88928#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 88925#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88923#L612-33 assume 1 == ~t8_pc~0; 82839#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82791#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82792#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82613#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81862#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81863#L631-33 assume 1 == ~t9_pc~0; 82741#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81804#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81805#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88901#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 88899#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88897#L1047-3 assume !(1 == ~M_E~0); 82091#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88894#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88891#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88889#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82920#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88887#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88886#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88851#L1082-3 assume !(1 == ~T8_E~0); 88850#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 88849#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88575#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 88574#L1102-3 assume !(1 == ~E_2~0); 88573#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88572#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88571#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88570#L1122-3 assume !(1 == ~E_6~0); 88569#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 88568#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 88567#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 88566#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 88564#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 88555#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 88554#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 88553#L1447 assume !(0 == start_simulation_~tmp~3#1); 82373#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 88549#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 88539#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 88537#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 88535#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 88355#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88334#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 88326#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 88319#L1428-2 [2022-02-21 04:23:29,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,595 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2022-02-21 04:23:29,595 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,595 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553934954] [2022-02-21 04:23:29,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,629 INFO L290 TraceCheckUtils]: 0: Hoare triple {108116#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,629 INFO L290 TraceCheckUtils]: 1: Hoare triple {108116#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {108116#true} is VALID [2022-02-21 04:23:29,630 INFO L290 TraceCheckUtils]: 2: Hoare triple {108116#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {108116#true} is VALID [2022-02-21 04:23:29,630 INFO L290 TraceCheckUtils]: 3: Hoare triple {108116#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {108116#true} is VALID [2022-02-21 04:23:29,630 INFO L290 TraceCheckUtils]: 4: Hoare triple {108116#true} assume 1 == ~m_i~0;~m_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,630 INFO L290 TraceCheckUtils]: 5: Hoare triple {108116#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,630 INFO L290 TraceCheckUtils]: 6: Hoare triple {108116#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,630 INFO L290 TraceCheckUtils]: 7: Hoare triple {108116#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,630 INFO L290 TraceCheckUtils]: 8: Hoare triple {108116#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 9: Hoare triple {108116#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 10: Hoare triple {108116#true} assume 1 == ~t6_i~0;~t6_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 11: Hoare triple {108116#true} assume 1 == ~t7_i~0;~t7_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 12: Hoare triple {108116#true} assume 1 == ~t8_i~0;~t8_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 13: Hoare triple {108116#true} assume 1 == ~t9_i~0;~t9_st~0 := 0; {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 14: Hoare triple {108116#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 15: Hoare triple {108116#true} assume !(0 == ~M_E~0); {108116#true} is VALID [2022-02-21 04:23:29,631 INFO L290 TraceCheckUtils]: 16: Hoare triple {108116#true} assume !(0 == ~T1_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 17: Hoare triple {108116#true} assume !(0 == ~T2_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 18: Hoare triple {108116#true} assume !(0 == ~T3_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 19: Hoare triple {108116#true} assume !(0 == ~T4_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 20: Hoare triple {108116#true} assume !(0 == ~T5_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 21: Hoare triple {108116#true} assume !(0 == ~T6_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 22: Hoare triple {108116#true} assume !(0 == ~T7_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 23: Hoare triple {108116#true} assume !(0 == ~T8_E~0); {108116#true} is VALID [2022-02-21 04:23:29,632 INFO L290 TraceCheckUtils]: 24: Hoare triple {108116#true} assume !(0 == ~T9_E~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 25: Hoare triple {108116#true} assume !(0 == ~E_M~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 26: Hoare triple {108116#true} assume !(0 == ~E_1~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 27: Hoare triple {108116#true} assume !(0 == ~E_2~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 28: Hoare triple {108116#true} assume !(0 == ~E_3~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 29: Hoare triple {108116#true} assume !(0 == ~E_4~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 30: Hoare triple {108116#true} assume !(0 == ~E_5~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 31: Hoare triple {108116#true} assume !(0 == ~E_6~0); {108116#true} is VALID [2022-02-21 04:23:29,633 INFO L290 TraceCheckUtils]: 32: Hoare triple {108116#true} assume !(0 == ~E_7~0); {108116#true} is VALID [2022-02-21 04:23:29,634 INFO L290 TraceCheckUtils]: 33: Hoare triple {108116#true} assume !(0 == ~E_8~0); {108116#true} is VALID [2022-02-21 04:23:29,634 INFO L290 TraceCheckUtils]: 34: Hoare triple {108116#true} assume !(0 == ~E_9~0); {108116#true} is VALID [2022-02-21 04:23:29,634 INFO L290 TraceCheckUtils]: 35: Hoare triple {108116#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108116#true} is VALID [2022-02-21 04:23:29,634 INFO L290 TraceCheckUtils]: 36: Hoare triple {108116#true} assume !(1 == ~m_pc~0); {108116#true} is VALID [2022-02-21 04:23:29,634 INFO L290 TraceCheckUtils]: 37: Hoare triple {108116#true} is_master_triggered_~__retres1~0#1 := 0; {108116#true} is VALID [2022-02-21 04:23:29,634 INFO L290 TraceCheckUtils]: 38: Hoare triple {108116#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108116#true} is VALID [2022-02-21 04:23:29,634 INFO L290 TraceCheckUtils]: 39: Hoare triple {108116#true} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 40: Hoare triple {108116#true} assume !(0 != activate_threads_~tmp~1#1); {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 41: Hoare triple {108116#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 42: Hoare triple {108116#true} assume !(1 == ~t1_pc~0); {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 43: Hoare triple {108116#true} is_transmit1_triggered_~__retres1~1#1 := 0; {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 44: Hoare triple {108116#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 45: Hoare triple {108116#true} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 46: Hoare triple {108116#true} assume !(0 != activate_threads_~tmp___0~0#1); {108116#true} is VALID [2022-02-21 04:23:29,635 INFO L290 TraceCheckUtils]: 47: Hoare triple {108116#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108116#true} is VALID [2022-02-21 04:23:29,636 INFO L290 TraceCheckUtils]: 48: Hoare triple {108116#true} assume !(1 == ~t2_pc~0); {108116#true} is VALID [2022-02-21 04:23:29,636 INFO L290 TraceCheckUtils]: 49: Hoare triple {108116#true} is_transmit2_triggered_~__retres1~2#1 := 0; {108118#(= |ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1| 0)} is VALID [2022-02-21 04:23:29,636 INFO L290 TraceCheckUtils]: 50: Hoare triple {108118#(= |ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1| 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108119#(= |ULTIMATE.start_is_transmit2_triggered_#res#1| 0)} is VALID [2022-02-21 04:23:29,637 INFO L290 TraceCheckUtils]: 51: Hoare triple {108119#(= |ULTIMATE.start_is_transmit2_triggered_#res#1| 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {108120#(= |ULTIMATE.start_activate_threads_~tmp___1~0#1| 0)} is VALID [2022-02-21 04:23:29,637 INFO L290 TraceCheckUtils]: 52: Hoare triple {108120#(= |ULTIMATE.start_activate_threads_~tmp___1~0#1| 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {108117#false} is VALID [2022-02-21 04:23:29,637 INFO L290 TraceCheckUtils]: 53: Hoare triple {108117#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108117#false} is VALID [2022-02-21 04:23:29,637 INFO L290 TraceCheckUtils]: 54: Hoare triple {108117#false} assume 1 == ~t3_pc~0; {108117#false} is VALID [2022-02-21 04:23:29,637 INFO L290 TraceCheckUtils]: 55: Hoare triple {108117#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {108117#false} is VALID [2022-02-21 04:23:29,637 INFO L290 TraceCheckUtils]: 56: Hoare triple {108117#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 57: Hoare triple {108117#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 58: Hoare triple {108117#false} assume !(0 != activate_threads_~tmp___2~0#1); {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 59: Hoare triple {108117#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 60: Hoare triple {108117#false} assume !(1 == ~t4_pc~0); {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 61: Hoare triple {108117#false} is_transmit4_triggered_~__retres1~4#1 := 0; {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 62: Hoare triple {108117#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 63: Hoare triple {108117#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108117#false} is VALID [2022-02-21 04:23:29,638 INFO L290 TraceCheckUtils]: 64: Hoare triple {108117#false} assume !(0 != activate_threads_~tmp___3~0#1); {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 65: Hoare triple {108117#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 66: Hoare triple {108117#false} assume 1 == ~t5_pc~0; {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 67: Hoare triple {108117#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 68: Hoare triple {108117#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 69: Hoare triple {108117#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 70: Hoare triple {108117#false} assume !(0 != activate_threads_~tmp___4~0#1); {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 71: Hoare triple {108117#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108117#false} is VALID [2022-02-21 04:23:29,639 INFO L290 TraceCheckUtils]: 72: Hoare triple {108117#false} assume !(1 == ~t6_pc~0); {108117#false} is VALID [2022-02-21 04:23:29,640 INFO L290 TraceCheckUtils]: 73: Hoare triple {108117#false} is_transmit6_triggered_~__retres1~6#1 := 0; {108117#false} is VALID [2022-02-21 04:23:29,640 INFO L290 TraceCheckUtils]: 74: Hoare triple {108117#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108117#false} is VALID [2022-02-21 04:23:29,640 INFO L290 TraceCheckUtils]: 75: Hoare triple {108117#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108117#false} is VALID [2022-02-21 04:23:29,640 INFO L290 TraceCheckUtils]: 76: Hoare triple {108117#false} assume !(0 != activate_threads_~tmp___5~0#1); {108117#false} is VALID [2022-02-21 04:23:29,640 INFO L290 TraceCheckUtils]: 77: Hoare triple {108117#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108117#false} is VALID [2022-02-21 04:23:29,640 INFO L290 TraceCheckUtils]: 78: Hoare triple {108117#false} assume 1 == ~t7_pc~0; {108117#false} is VALID [2022-02-21 04:23:29,640 INFO L290 TraceCheckUtils]: 79: Hoare triple {108117#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 80: Hoare triple {108117#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 81: Hoare triple {108117#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 82: Hoare triple {108117#false} assume !(0 != activate_threads_~tmp___6~0#1); {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 83: Hoare triple {108117#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 84: Hoare triple {108117#false} assume !(1 == ~t8_pc~0); {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 85: Hoare triple {108117#false} is_transmit8_triggered_~__retres1~8#1 := 0; {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 86: Hoare triple {108117#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108117#false} is VALID [2022-02-21 04:23:29,641 INFO L290 TraceCheckUtils]: 87: Hoare triple {108117#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 88: Hoare triple {108117#false} assume !(0 != activate_threads_~tmp___7~0#1); {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 89: Hoare triple {108117#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 90: Hoare triple {108117#false} assume 1 == ~t9_pc~0; {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 91: Hoare triple {108117#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 92: Hoare triple {108117#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 93: Hoare triple {108117#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 94: Hoare triple {108117#false} assume !(0 != activate_threads_~tmp___8~0#1); {108117#false} is VALID [2022-02-21 04:23:29,642 INFO L290 TraceCheckUtils]: 95: Hoare triple {108117#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 96: Hoare triple {108117#false} assume 1 == ~M_E~0;~M_E~0 := 2; {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 97: Hoare triple {108117#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 98: Hoare triple {108117#false} assume !(1 == ~T2_E~0); {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 99: Hoare triple {108117#false} assume !(1 == ~T3_E~0); {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 100: Hoare triple {108117#false} assume !(1 == ~T4_E~0); {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 101: Hoare triple {108117#false} assume !(1 == ~T5_E~0); {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 102: Hoare triple {108117#false} assume !(1 == ~T6_E~0); {108117#false} is VALID [2022-02-21 04:23:29,643 INFO L290 TraceCheckUtils]: 103: Hoare triple {108117#false} assume !(1 == ~T7_E~0); {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 104: Hoare triple {108117#false} assume !(1 == ~T8_E~0); {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 105: Hoare triple {108117#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 106: Hoare triple {108117#false} assume !(1 == ~E_M~0); {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 107: Hoare triple {108117#false} assume !(1 == ~E_1~0); {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 108: Hoare triple {108117#false} assume !(1 == ~E_2~0); {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 109: Hoare triple {108117#false} assume !(1 == ~E_3~0); {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 110: Hoare triple {108117#false} assume !(1 == ~E_4~0); {108117#false} is VALID [2022-02-21 04:23:29,644 INFO L290 TraceCheckUtils]: 111: Hoare triple {108117#false} assume !(1 == ~E_5~0); {108117#false} is VALID [2022-02-21 04:23:29,645 INFO L290 TraceCheckUtils]: 112: Hoare triple {108117#false} assume !(1 == ~E_6~0); {108117#false} is VALID [2022-02-21 04:23:29,645 INFO L290 TraceCheckUtils]: 113: Hoare triple {108117#false} assume 1 == ~E_7~0;~E_7~0 := 2; {108117#false} is VALID [2022-02-21 04:23:29,645 INFO L290 TraceCheckUtils]: 114: Hoare triple {108117#false} assume !(1 == ~E_8~0); {108117#false} is VALID [2022-02-21 04:23:29,645 INFO L290 TraceCheckUtils]: 115: Hoare triple {108117#false} assume !(1 == ~E_9~0); {108117#false} is VALID [2022-02-21 04:23:29,645 INFO L290 TraceCheckUtils]: 116: Hoare triple {108117#false} assume { :end_inline_reset_delta_events } true; {108117#false} is VALID [2022-02-21 04:23:29,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,646 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,646 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553934954] [2022-02-21 04:23:29,646 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553934954] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,646 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,646 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:23:29,646 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95621092] [2022-02-21 04:23:29,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,647 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:29,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,647 INFO L85 PathProgramCache]: Analyzing trace with hash 1592959758, now seen corresponding path program 1 times [2022-02-21 04:23:29,647 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,648 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768732134] [2022-02-21 04:23:29,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:29,680 INFO L290 TraceCheckUtils]: 0: Hoare triple {108121#true} assume !false; {108121#true} is VALID [2022-02-21 04:23:29,680 INFO L290 TraceCheckUtils]: 1: Hoare triple {108121#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {108121#true} is VALID [2022-02-21 04:23:29,680 INFO L290 TraceCheckUtils]: 2: Hoare triple {108121#true} assume !false; {108121#true} is VALID [2022-02-21 04:23:29,680 INFO L290 TraceCheckUtils]: 3: Hoare triple {108121#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {108121#true} is VALID [2022-02-21 04:23:29,681 INFO L290 TraceCheckUtils]: 4: Hoare triple {108121#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {108123#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} is VALID [2022-02-21 04:23:29,681 INFO L290 TraceCheckUtils]: 5: Hoare triple {108123#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {108124#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:23:29,681 INFO L290 TraceCheckUtils]: 6: Hoare triple {108124#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {108125#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:23:29,682 INFO L290 TraceCheckUtils]: 7: Hoare triple {108125#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {108122#false} is VALID [2022-02-21 04:23:29,682 INFO L290 TraceCheckUtils]: 8: Hoare triple {108122#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {108122#false} is VALID [2022-02-21 04:23:29,682 INFO L290 TraceCheckUtils]: 9: Hoare triple {108122#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {108122#false} is VALID [2022-02-21 04:23:29,682 INFO L290 TraceCheckUtils]: 10: Hoare triple {108122#false} assume !(0 == ~M_E~0); {108122#false} is VALID [2022-02-21 04:23:29,682 INFO L290 TraceCheckUtils]: 11: Hoare triple {108122#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,682 INFO L290 TraceCheckUtils]: 12: Hoare triple {108122#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,682 INFO L290 TraceCheckUtils]: 13: Hoare triple {108122#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 14: Hoare triple {108122#false} assume !(0 == ~T4_E~0); {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 15: Hoare triple {108122#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 16: Hoare triple {108122#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 17: Hoare triple {108122#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 18: Hoare triple {108122#false} assume !(0 == ~T8_E~0); {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 19: Hoare triple {108122#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 20: Hoare triple {108122#false} assume 0 == ~E_M~0;~E_M~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,683 INFO L290 TraceCheckUtils]: 21: Hoare triple {108122#false} assume 0 == ~E_1~0;~E_1~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 22: Hoare triple {108122#false} assume !(0 == ~E_2~0); {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 23: Hoare triple {108122#false} assume 0 == ~E_3~0;~E_3~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 24: Hoare triple {108122#false} assume 0 == ~E_4~0;~E_4~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 25: Hoare triple {108122#false} assume 0 == ~E_5~0;~E_5~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 26: Hoare triple {108122#false} assume !(0 == ~E_6~0); {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 27: Hoare triple {108122#false} assume 0 == ~E_7~0;~E_7~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 28: Hoare triple {108122#false} assume 0 == ~E_8~0;~E_8~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,684 INFO L290 TraceCheckUtils]: 29: Hoare triple {108122#false} assume 0 == ~E_9~0;~E_9~0 := 1; {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 30: Hoare triple {108122#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 31: Hoare triple {108122#false} assume !(1 == ~m_pc~0); {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 32: Hoare triple {108122#false} is_master_triggered_~__retres1~0#1 := 0; {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 33: Hoare triple {108122#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 34: Hoare triple {108122#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 35: Hoare triple {108122#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 36: Hoare triple {108122#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108122#false} is VALID [2022-02-21 04:23:29,685 INFO L290 TraceCheckUtils]: 37: Hoare triple {108122#false} assume !(1 == ~t1_pc~0); {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 38: Hoare triple {108122#false} is_transmit1_triggered_~__retres1~1#1 := 0; {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 39: Hoare triple {108122#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 40: Hoare triple {108122#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 41: Hoare triple {108122#false} assume !(0 != activate_threads_~tmp___0~0#1); {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 42: Hoare triple {108122#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 43: Hoare triple {108122#false} assume !(1 == ~t2_pc~0); {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 44: Hoare triple {108122#false} is_transmit2_triggered_~__retres1~2#1 := 0; {108122#false} is VALID [2022-02-21 04:23:29,686 INFO L290 TraceCheckUtils]: 45: Hoare triple {108122#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 46: Hoare triple {108122#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 47: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 48: Hoare triple {108122#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 49: Hoare triple {108122#false} assume !(1 == ~t3_pc~0); {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 50: Hoare triple {108122#false} is_transmit3_triggered_~__retres1~3#1 := 0; {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 51: Hoare triple {108122#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 52: Hoare triple {108122#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {108122#false} is VALID [2022-02-21 04:23:29,687 INFO L290 TraceCheckUtils]: 53: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,688 INFO L290 TraceCheckUtils]: 54: Hoare triple {108122#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108122#false} is VALID [2022-02-21 04:23:29,688 INFO L290 TraceCheckUtils]: 55: Hoare triple {108122#false} assume 1 == ~t4_pc~0; {108122#false} is VALID [2022-02-21 04:23:29,688 INFO L290 TraceCheckUtils]: 56: Hoare triple {108122#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {108122#false} is VALID [2022-02-21 04:23:29,688 INFO L290 TraceCheckUtils]: 57: Hoare triple {108122#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108122#false} is VALID [2022-02-21 04:23:29,688 INFO L290 TraceCheckUtils]: 58: Hoare triple {108122#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108122#false} is VALID [2022-02-21 04:23:29,688 INFO L290 TraceCheckUtils]: 59: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,688 INFO L290 TraceCheckUtils]: 60: Hoare triple {108122#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 61: Hoare triple {108122#false} assume !(1 == ~t5_pc~0); {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 62: Hoare triple {108122#false} is_transmit5_triggered_~__retres1~5#1 := 0; {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 63: Hoare triple {108122#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 64: Hoare triple {108122#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 65: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 66: Hoare triple {108122#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 67: Hoare triple {108122#false} assume !(1 == ~t6_pc~0); {108122#false} is VALID [2022-02-21 04:23:29,689 INFO L290 TraceCheckUtils]: 68: Hoare triple {108122#false} is_transmit6_triggered_~__retres1~6#1 := 0; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 69: Hoare triple {108122#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 70: Hoare triple {108122#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 71: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 72: Hoare triple {108122#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 73: Hoare triple {108122#false} assume 1 == ~t7_pc~0; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 74: Hoare triple {108122#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 75: Hoare triple {108122#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108122#false} is VALID [2022-02-21 04:23:29,690 INFO L290 TraceCheckUtils]: 76: Hoare triple {108122#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 77: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 78: Hoare triple {108122#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 79: Hoare triple {108122#false} assume 1 == ~t8_pc~0; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 80: Hoare triple {108122#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 81: Hoare triple {108122#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 82: Hoare triple {108122#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 83: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,691 INFO L290 TraceCheckUtils]: 84: Hoare triple {108122#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 85: Hoare triple {108122#false} assume 1 == ~t9_pc~0; {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 86: Hoare triple {108122#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 87: Hoare triple {108122#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 88: Hoare triple {108122#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 89: Hoare triple {108122#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 90: Hoare triple {108122#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 91: Hoare triple {108122#false} assume !(1 == ~M_E~0); {108122#false} is VALID [2022-02-21 04:23:29,692 INFO L290 TraceCheckUtils]: 92: Hoare triple {108122#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 93: Hoare triple {108122#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 94: Hoare triple {108122#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 95: Hoare triple {108122#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 96: Hoare triple {108122#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 97: Hoare triple {108122#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 98: Hoare triple {108122#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 99: Hoare triple {108122#false} assume !(1 == ~T8_E~0); {108122#false} is VALID [2022-02-21 04:23:29,693 INFO L290 TraceCheckUtils]: 100: Hoare triple {108122#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 101: Hoare triple {108122#false} assume 1 == ~E_M~0;~E_M~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 102: Hoare triple {108122#false} assume 1 == ~E_1~0;~E_1~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 103: Hoare triple {108122#false} assume !(1 == ~E_2~0); {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 104: Hoare triple {108122#false} assume 1 == ~E_3~0;~E_3~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 105: Hoare triple {108122#false} assume 1 == ~E_4~0;~E_4~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 106: Hoare triple {108122#false} assume 1 == ~E_5~0;~E_5~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 107: Hoare triple {108122#false} assume !(1 == ~E_6~0); {108122#false} is VALID [2022-02-21 04:23:29,694 INFO L290 TraceCheckUtils]: 108: Hoare triple {108122#false} assume 1 == ~E_7~0;~E_7~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,695 INFO L290 TraceCheckUtils]: 109: Hoare triple {108122#false} assume 1 == ~E_8~0;~E_8~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,695 INFO L290 TraceCheckUtils]: 110: Hoare triple {108122#false} assume 1 == ~E_9~0;~E_9~0 := 2; {108122#false} is VALID [2022-02-21 04:23:29,695 INFO L290 TraceCheckUtils]: 111: Hoare triple {108122#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {108122#false} is VALID [2022-02-21 04:23:29,695 INFO L290 TraceCheckUtils]: 112: Hoare triple {108122#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {108122#false} is VALID [2022-02-21 04:23:29,695 INFO L290 TraceCheckUtils]: 113: Hoare triple {108122#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {108122#false} is VALID [2022-02-21 04:23:29,695 INFO L290 TraceCheckUtils]: 114: Hoare triple {108122#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {108122#false} is VALID [2022-02-21 04:23:29,695 INFO L290 TraceCheckUtils]: 115: Hoare triple {108122#false} assume !(0 == start_simulation_~tmp~3#1); {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 116: Hoare triple {108122#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 117: Hoare triple {108122#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 118: Hoare triple {108122#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 119: Hoare triple {108122#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 120: Hoare triple {108122#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 121: Hoare triple {108122#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 122: Hoare triple {108122#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {108122#false} is VALID [2022-02-21 04:23:29,696 INFO L290 TraceCheckUtils]: 123: Hoare triple {108122#false} assume !(0 != start_simulation_~tmp___0~1#1); {108122#false} is VALID [2022-02-21 04:23:29,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:29,697 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:29,697 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768732134] [2022-02-21 04:23:29,697 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768732134] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:29,697 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:29,697 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:23:29,698 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809183512] [2022-02-21 04:23:29,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:29,698 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:29,698 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:29,699 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:23:29,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:23:29,699 INFO L87 Difference]: Start difference. First operand 7449 states and 10750 transitions. cyclomatic complexity: 3305 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,859 INFO L93 Difference]: Finished difference Result 9557 states and 13735 transitions. [2022-02-21 04:23:33,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:23:33,860 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,927 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:33,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9557 states and 13735 transitions. [2022-02-21 04:23:35,692 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9404 [2022-02-21 04:23:37,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9557 states to 9557 states and 13735 transitions. [2022-02-21 04:23:37,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9557 [2022-02-21 04:23:37,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9557 [2022-02-21 04:23:37,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9557 states and 13735 transitions. [2022-02-21 04:23:37,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:37,518 INFO L681 BuchiCegarLoop]: Abstraction has 9557 states and 13735 transitions. [2022-02-21 04:23:37,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9557 states and 13735 transitions. [2022-02-21 04:23:37,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9557 to 7461. [2022-02-21 04:23:37,616 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:37,625 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9557 states and 13735 transitions. Second operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,635 INFO L74 IsIncluded]: Start isIncluded. First operand 9557 states and 13735 transitions. Second operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,686 INFO L87 Difference]: Start difference. First operand 9557 states and 13735 transitions. Second operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:39,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:39,633 INFO L93 Difference]: Finished difference Result 9557 states and 13735 transitions. [2022-02-21 04:23:39,634 INFO L276 IsEmpty]: Start isEmpty. Operand 9557 states and 13735 transitions. [2022-02-21 04:23:39,643 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:39,643 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:39,649 INFO L74 IsIncluded]: Start isIncluded. First operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9557 states and 13735 transitions. [2022-02-21 04:23:39,653 INFO L87 Difference]: Start difference. First operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9557 states and 13735 transitions. [2022-02-21 04:23:41,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:41,592 INFO L93 Difference]: Finished difference Result 9557 states and 13735 transitions. [2022-02-21 04:23:41,593 INFO L276 IsEmpty]: Start isEmpty. Operand 9557 states and 13735 transitions. [2022-02-21 04:23:41,599 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:41,599 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:41,599 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:41,599 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:41,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7461 states to 7461 states and 10681 transitions. [2022-02-21 04:23:42,719 INFO L704 BuchiCegarLoop]: Abstraction has 7461 states and 10681 transitions. [2022-02-21 04:23:42,719 INFO L587 BuchiCegarLoop]: Abstraction has 7461 states and 10681 transitions. [2022-02-21 04:23:42,719 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:23:42,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7461 states and 10681 transitions. [2022-02-21 04:23:42,730 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7312 [2022-02-21 04:23:42,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:42,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:42,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:42,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:42,731 INFO L791 eck$LassoCheckResult]: Stem: 118667#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 118668#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 118591#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118592#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118944#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 118443#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118444#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118897#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118232#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118233#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118779#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 118780#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 117700#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 117701#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 117905#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118331#L939 assume !(0 == ~M_E~0); 118638#L939-2 assume !(0 == ~T1_E~0); 118639#L944-1 assume !(0 == ~T2_E~0); 118361#L949-1 assume !(0 == ~T3_E~0); 118359#L954-1 assume !(0 == ~T4_E~0); 118360#L959-1 assume !(0 == ~T5_E~0); 118966#L964-1 assume !(0 == ~T6_E~0); 118064#L969-1 assume !(0 == ~T7_E~0); 118065#L974-1 assume !(0 == ~T8_E~0); 118879#L979-1 assume !(0 == ~T9_E~0); 118880#L984-1 assume !(0 == ~E_M~0); 118242#L989-1 assume !(0 == ~E_1~0); 118243#L994-1 assume !(0 == ~E_2~0); 118117#L999-1 assume !(0 == ~E_3~0); 118118#L1004-1 assume !(0 == ~E_4~0); 117768#L1009-1 assume !(0 == ~E_5~0); 117769#L1014-1 assume !(0 == ~E_6~0); 118113#L1019-1 assume !(0 == ~E_7~0); 118786#L1024-1 assume !(0 == ~E_8~0); 118034#L1029-1 assume !(0 == ~E_9~0); 118035#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118133#L460 assume !(1 == ~m_pc~0); 119150#L460-2 is_master_triggered_~__retres1~0#1 := 0; 118739#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118740#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119213#L1167 assume !(0 != activate_threads_~tmp~1#1); 118346#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118347#L479 assume !(1 == ~t1_pc~0); 118525#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118526#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119089#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118047#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 118048#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117886#L498 assume !(1 == ~t2_pc~0); 117887#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118329#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118330#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 118840#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 118725#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118726#L517 assume 1 == ~t3_pc~0; 119096#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 119097#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118407#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 118082#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 118083#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118805#L536 assume !(1 == ~t4_pc~0); 118397#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118396#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118954#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 118389#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 118390#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118688#L555 assume 1 == ~t5_pc~0; 118689#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 118787#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117799#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117800#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 117910#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117808#L574 assume !(1 == ~t6_pc~0); 117809#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 118498#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117913#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117914#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 118835#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119166#L593 assume 1 == ~t7_pc~0; 119167#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 118055#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118973#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 119256#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 119100#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118237#L612 assume !(1 == ~t8_pc~0); 118238#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 118763#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 118548#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118549#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 118503#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 118504#L631 assume 1 == ~t9_pc~0; 118522#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 117798#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117766#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117767#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 118332#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118806#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 117738#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117739#L1052-1 assume !(1 == ~T2_E~0); 117719#L1057-1 assume !(1 == ~T3_E~0); 117720#L1062-1 assume !(1 == ~T4_E~0); 118017#L1067-1 assume !(1 == ~T5_E~0); 118350#L1072-1 assume !(1 == ~T6_E~0); 118351#L1077-1 assume !(1 == ~T7_E~0); 117900#L1082-1 assume !(1 == ~T8_E~0); 117901#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 117696#L1092-1 assume !(1 == ~E_M~0); 117697#L1097-1 assume !(1 == ~E_1~0); 117721#L1102-1 assume !(1 == ~E_2~0); 118585#L1107-1 assume !(1 == ~E_3~0); 118586#L1112-1 assume !(1 == ~E_4~0); 121885#L1117-1 assume !(1 == ~E_5~0); 121883#L1122-1 assume !(1 == ~E_6~0); 121881#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 118138#L1132-1 assume !(1 == ~E_8~0); 118139#L1137-1 assume !(1 == ~E_9~0); 119144#L1142-1 assume { :end_inline_reset_delta_events } true; 121768#L1428-2 [2022-02-21 04:23:42,732 INFO L793 eck$LassoCheckResult]: Loop: 121768#L1428-2 assume !false; 119915#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119912#L914 assume !false; 119904#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 119905#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 119871#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 119872#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 119863#L783 assume !(0 != eval_~tmp~0#1); 119864#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121754#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121751#L939-3 assume !(0 == ~M_E~0); 121752#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 121746#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 121747#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121742#L954-3 assume !(0 == ~T4_E~0); 121743#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 121738#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 121739#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 121734#L974-3 assume !(0 == ~T8_E~0); 121735#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 121730#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 121731#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121726#L994-3 assume !(0 == ~E_2~0); 121727#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 121722#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 121723#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121718#L1014-3 assume !(0 == ~E_6~0); 121719#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 121714#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 121715#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 121710#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121711#L460-33 assume !(1 == ~m_pc~0); 121706#L460-35 is_master_triggered_~__retres1~0#1 := 0; 121707#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121702#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121703#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 121646#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121647#L479-33 assume !(1 == ~t1_pc~0); 121537#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 121538#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121529#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121530#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 119781#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119782#L498-33 assume !(1 == ~t2_pc~0); 121980#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 121979#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121978#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121977#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 121976#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121975#L517-33 assume 1 == ~t3_pc~0; 121973#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 121972#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121971#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121970#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 121969#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 121968#L536-33 assume !(1 == ~t4_pc~0); 121967#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 121965#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121964#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 121963#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 121962#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121961#L555-33 assume !(1 == ~t5_pc~0); 121959#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 121958#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 121957#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 121956#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 121955#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121954#L574-33 assume !(1 == ~t6_pc~0); 121953#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 121951#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121950#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 121949#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 121948#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 121947#L593-33 assume !(1 == ~t7_pc~0); 121945#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 121944#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121943#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 121942#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 121941#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121940#L612-33 assume !(1 == ~t8_pc~0); 121939#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 121937#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 121936#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 121935#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 121934#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121933#L631-33 assume !(1 == ~t9_pc~0); 121931#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 121930#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 121929#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121928#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 121927#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121926#L1047-3 assume !(1 == ~M_E~0); 119500#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 121925#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121924#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121923#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119479#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121922#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 121921#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 121920#L1082-3 assume !(1 == ~T8_E~0); 121919#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 121918#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 121917#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 121916#L1102-3 assume !(1 == ~E_2~0); 121915#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 121914#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 121913#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 121912#L1122-3 assume !(1 == ~E_6~0); 121911#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 121910#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 121909#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 121908#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 121894#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 119379#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 119375#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 119372#L1447 assume !(0 == start_simulation_~tmp~3#1); 119373#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 120134#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 120124#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 120121#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 120119#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 120120#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 120110#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 120111#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 121768#L1428-2 [2022-02-21 04:23:42,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:42,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2022-02-21 04:23:42,733 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:42,733 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864468526] [2022-02-21 04:23:42,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:42,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:42,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:42,797 INFO L290 TraceCheckUtils]: 0: Hoare triple {144265#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,798 INFO L290 TraceCheckUtils]: 1: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,798 INFO L290 TraceCheckUtils]: 2: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,798 INFO L290 TraceCheckUtils]: 3: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,799 INFO L290 TraceCheckUtils]: 4: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,799 INFO L290 TraceCheckUtils]: 5: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,799 INFO L290 TraceCheckUtils]: 6: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,800 INFO L290 TraceCheckUtils]: 7: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,800 INFO L290 TraceCheckUtils]: 8: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,801 INFO L290 TraceCheckUtils]: 9: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,801 INFO L290 TraceCheckUtils]: 10: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,801 INFO L290 TraceCheckUtils]: 11: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,802 INFO L290 TraceCheckUtils]: 12: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,802 INFO L290 TraceCheckUtils]: 13: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,802 INFO L290 TraceCheckUtils]: 14: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,803 INFO L290 TraceCheckUtils]: 15: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,803 INFO L290 TraceCheckUtils]: 16: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,803 INFO L290 TraceCheckUtils]: 17: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,804 INFO L290 TraceCheckUtils]: 18: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,804 INFO L290 TraceCheckUtils]: 19: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,804 INFO L290 TraceCheckUtils]: 20: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,805 INFO L290 TraceCheckUtils]: 21: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T6_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,805 INFO L290 TraceCheckUtils]: 22: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T7_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,805 INFO L290 TraceCheckUtils]: 23: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T8_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,806 INFO L290 TraceCheckUtils]: 24: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T9_E~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,806 INFO L290 TraceCheckUtils]: 25: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_M~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,806 INFO L290 TraceCheckUtils]: 26: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,807 INFO L290 TraceCheckUtils]: 27: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,807 INFO L290 TraceCheckUtils]: 28: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,807 INFO L290 TraceCheckUtils]: 29: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,808 INFO L290 TraceCheckUtils]: 30: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,808 INFO L290 TraceCheckUtils]: 31: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_6~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,808 INFO L290 TraceCheckUtils]: 32: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_7~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,809 INFO L290 TraceCheckUtils]: 33: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_8~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,809 INFO L290 TraceCheckUtils]: 34: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_9~0); {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,809 INFO L290 TraceCheckUtils]: 35: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {144267#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:23:42,810 INFO L290 TraceCheckUtils]: 36: Hoare triple {144267#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,810 INFO L290 TraceCheckUtils]: 37: Hoare triple {144268#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,810 INFO L290 TraceCheckUtils]: 38: Hoare triple {144268#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,811 INFO L290 TraceCheckUtils]: 39: Hoare triple {144268#(not (= ~t3_pc~0 1))} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,811 INFO L290 TraceCheckUtils]: 40: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,811 INFO L290 TraceCheckUtils]: 41: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,811 INFO L290 TraceCheckUtils]: 42: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,812 INFO L290 TraceCheckUtils]: 43: Hoare triple {144268#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,812 INFO L290 TraceCheckUtils]: 44: Hoare triple {144268#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,812 INFO L290 TraceCheckUtils]: 45: Hoare triple {144268#(not (= ~t3_pc~0 1))} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,813 INFO L290 TraceCheckUtils]: 46: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,813 INFO L290 TraceCheckUtils]: 47: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,813 INFO L290 TraceCheckUtils]: 48: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,814 INFO L290 TraceCheckUtils]: 49: Hoare triple {144268#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,814 INFO L290 TraceCheckUtils]: 50: Hoare triple {144268#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,814 INFO L290 TraceCheckUtils]: 51: Hoare triple {144268#(not (= ~t3_pc~0 1))} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,814 INFO L290 TraceCheckUtils]: 52: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,815 INFO L290 TraceCheckUtils]: 53: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {144268#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:23:42,815 INFO L290 TraceCheckUtils]: 54: Hoare triple {144268#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {144266#false} is VALID [2022-02-21 04:23:42,815 INFO L290 TraceCheckUtils]: 55: Hoare triple {144266#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {144266#false} is VALID [2022-02-21 04:23:42,815 INFO L290 TraceCheckUtils]: 56: Hoare triple {144266#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {144266#false} is VALID [2022-02-21 04:23:42,815 INFO L290 TraceCheckUtils]: 57: Hoare triple {144266#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 58: Hoare triple {144266#false} assume !(0 != activate_threads_~tmp___2~0#1); {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 59: Hoare triple {144266#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 60: Hoare triple {144266#false} assume !(1 == ~t4_pc~0); {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 61: Hoare triple {144266#false} is_transmit4_triggered_~__retres1~4#1 := 0; {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 62: Hoare triple {144266#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 63: Hoare triple {144266#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 64: Hoare triple {144266#false} assume !(0 != activate_threads_~tmp___3~0#1); {144266#false} is VALID [2022-02-21 04:23:42,816 INFO L290 TraceCheckUtils]: 65: Hoare triple {144266#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 66: Hoare triple {144266#false} assume 1 == ~t5_pc~0; {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 67: Hoare triple {144266#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 68: Hoare triple {144266#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 69: Hoare triple {144266#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 70: Hoare triple {144266#false} assume !(0 != activate_threads_~tmp___4~0#1); {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 71: Hoare triple {144266#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 72: Hoare triple {144266#false} assume !(1 == ~t6_pc~0); {144266#false} is VALID [2022-02-21 04:23:42,817 INFO L290 TraceCheckUtils]: 73: Hoare triple {144266#false} is_transmit6_triggered_~__retres1~6#1 := 0; {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 74: Hoare triple {144266#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 75: Hoare triple {144266#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 76: Hoare triple {144266#false} assume !(0 != activate_threads_~tmp___5~0#1); {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 77: Hoare triple {144266#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 78: Hoare triple {144266#false} assume 1 == ~t7_pc~0; {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 79: Hoare triple {144266#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 80: Hoare triple {144266#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {144266#false} is VALID [2022-02-21 04:23:42,818 INFO L290 TraceCheckUtils]: 81: Hoare triple {144266#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 82: Hoare triple {144266#false} assume !(0 != activate_threads_~tmp___6~0#1); {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 83: Hoare triple {144266#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 84: Hoare triple {144266#false} assume !(1 == ~t8_pc~0); {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 85: Hoare triple {144266#false} is_transmit8_triggered_~__retres1~8#1 := 0; {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 86: Hoare triple {144266#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 87: Hoare triple {144266#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 88: Hoare triple {144266#false} assume !(0 != activate_threads_~tmp___7~0#1); {144266#false} is VALID [2022-02-21 04:23:42,819 INFO L290 TraceCheckUtils]: 89: Hoare triple {144266#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 90: Hoare triple {144266#false} assume 1 == ~t9_pc~0; {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 91: Hoare triple {144266#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 92: Hoare triple {144266#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 93: Hoare triple {144266#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 94: Hoare triple {144266#false} assume !(0 != activate_threads_~tmp___8~0#1); {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 95: Hoare triple {144266#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 96: Hoare triple {144266#false} assume 1 == ~M_E~0;~M_E~0 := 2; {144266#false} is VALID [2022-02-21 04:23:42,820 INFO L290 TraceCheckUtils]: 97: Hoare triple {144266#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 98: Hoare triple {144266#false} assume !(1 == ~T2_E~0); {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 99: Hoare triple {144266#false} assume !(1 == ~T3_E~0); {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 100: Hoare triple {144266#false} assume !(1 == ~T4_E~0); {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 101: Hoare triple {144266#false} assume !(1 == ~T5_E~0); {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 102: Hoare triple {144266#false} assume !(1 == ~T6_E~0); {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 103: Hoare triple {144266#false} assume !(1 == ~T7_E~0); {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 104: Hoare triple {144266#false} assume !(1 == ~T8_E~0); {144266#false} is VALID [2022-02-21 04:23:42,821 INFO L290 TraceCheckUtils]: 105: Hoare triple {144266#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 106: Hoare triple {144266#false} assume !(1 == ~E_M~0); {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 107: Hoare triple {144266#false} assume !(1 == ~E_1~0); {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 108: Hoare triple {144266#false} assume !(1 == ~E_2~0); {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 109: Hoare triple {144266#false} assume !(1 == ~E_3~0); {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 110: Hoare triple {144266#false} assume !(1 == ~E_4~0); {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 111: Hoare triple {144266#false} assume !(1 == ~E_5~0); {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 112: Hoare triple {144266#false} assume !(1 == ~E_6~0); {144266#false} is VALID [2022-02-21 04:23:42,822 INFO L290 TraceCheckUtils]: 113: Hoare triple {144266#false} assume 1 == ~E_7~0;~E_7~0 := 2; {144266#false} is VALID [2022-02-21 04:23:42,823 INFO L290 TraceCheckUtils]: 114: Hoare triple {144266#false} assume !(1 == ~E_8~0); {144266#false} is VALID [2022-02-21 04:23:42,823 INFO L290 TraceCheckUtils]: 115: Hoare triple {144266#false} assume !(1 == ~E_9~0); {144266#false} is VALID [2022-02-21 04:23:42,823 INFO L290 TraceCheckUtils]: 116: Hoare triple {144266#false} assume { :end_inline_reset_delta_events } true; {144266#false} is VALID [2022-02-21 04:23:42,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:42,823 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:42,824 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864468526] [2022-02-21 04:23:42,824 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864468526] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:42,824 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:42,824 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:42,824 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709018237] [2022-02-21 04:23:42,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:42,826 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:42,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:42,826 INFO L85 PathProgramCache]: Analyzing trace with hash -1314692589, now seen corresponding path program 1 times [2022-02-21 04:23:42,826 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:42,827 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498131703] [2022-02-21 04:23:42,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:42,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:42,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:42,861 INFO L290 TraceCheckUtils]: 0: Hoare triple {144269#true} assume !false; {144269#true} is VALID [2022-02-21 04:23:42,861 INFO L290 TraceCheckUtils]: 1: Hoare triple {144269#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {144269#true} is VALID [2022-02-21 04:23:42,861 INFO L290 TraceCheckUtils]: 2: Hoare triple {144269#true} assume !false; {144269#true} is VALID [2022-02-21 04:23:42,861 INFO L290 TraceCheckUtils]: 3: Hoare triple {144269#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {144269#true} is VALID [2022-02-21 04:23:42,862 INFO L290 TraceCheckUtils]: 4: Hoare triple {144269#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {144271#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} is VALID [2022-02-21 04:23:42,862 INFO L290 TraceCheckUtils]: 5: Hoare triple {144271#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~10#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {144272#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:23:42,862 INFO L290 TraceCheckUtils]: 6: Hoare triple {144272#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {144273#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:23:42,863 INFO L290 TraceCheckUtils]: 7: Hoare triple {144273#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {144270#false} is VALID [2022-02-21 04:23:42,863 INFO L290 TraceCheckUtils]: 8: Hoare triple {144270#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {144270#false} is VALID [2022-02-21 04:23:42,863 INFO L290 TraceCheckUtils]: 9: Hoare triple {144270#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {144270#false} is VALID [2022-02-21 04:23:42,863 INFO L290 TraceCheckUtils]: 10: Hoare triple {144270#false} assume !(0 == ~M_E~0); {144270#false} is VALID [2022-02-21 04:23:42,863 INFO L290 TraceCheckUtils]: 11: Hoare triple {144270#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,863 INFO L290 TraceCheckUtils]: 12: Hoare triple {144270#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 13: Hoare triple {144270#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 14: Hoare triple {144270#false} assume !(0 == ~T4_E~0); {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 15: Hoare triple {144270#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 16: Hoare triple {144270#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 17: Hoare triple {144270#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 18: Hoare triple {144270#false} assume !(0 == ~T8_E~0); {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 19: Hoare triple {144270#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 20: Hoare triple {144270#false} assume 0 == ~E_M~0;~E_M~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,864 INFO L290 TraceCheckUtils]: 21: Hoare triple {144270#false} assume 0 == ~E_1~0;~E_1~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,865 INFO L290 TraceCheckUtils]: 22: Hoare triple {144270#false} assume !(0 == ~E_2~0); {144270#false} is VALID [2022-02-21 04:23:42,865 INFO L290 TraceCheckUtils]: 23: Hoare triple {144270#false} assume 0 == ~E_3~0;~E_3~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,865 INFO L290 TraceCheckUtils]: 24: Hoare triple {144270#false} assume 0 == ~E_4~0;~E_4~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,865 INFO L290 TraceCheckUtils]: 25: Hoare triple {144270#false} assume 0 == ~E_5~0;~E_5~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,865 INFO L290 TraceCheckUtils]: 26: Hoare triple {144270#false} assume !(0 == ~E_6~0); {144270#false} is VALID [2022-02-21 04:23:42,865 INFO L290 TraceCheckUtils]: 27: Hoare triple {144270#false} assume 0 == ~E_7~0;~E_7~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,865 INFO L290 TraceCheckUtils]: 28: Hoare triple {144270#false} assume 0 == ~E_8~0;~E_8~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 29: Hoare triple {144270#false} assume 0 == ~E_9~0;~E_9~0 := 1; {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 30: Hoare triple {144270#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 31: Hoare triple {144270#false} assume !(1 == ~m_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 32: Hoare triple {144270#false} is_master_triggered_~__retres1~0#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 33: Hoare triple {144270#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 34: Hoare triple {144270#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 35: Hoare triple {144270#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,866 INFO L290 TraceCheckUtils]: 36: Hoare triple {144270#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {144270#false} is VALID [2022-02-21 04:23:42,867 INFO L290 TraceCheckUtils]: 37: Hoare triple {144270#false} assume !(1 == ~t1_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,867 INFO L290 TraceCheckUtils]: 38: Hoare triple {144270#false} is_transmit1_triggered_~__retres1~1#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,867 INFO L290 TraceCheckUtils]: 39: Hoare triple {144270#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {144270#false} is VALID [2022-02-21 04:23:42,874 INFO L290 TraceCheckUtils]: 40: Hoare triple {144270#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {144270#false} is VALID [2022-02-21 04:23:42,875 INFO L290 TraceCheckUtils]: 41: Hoare triple {144270#false} assume !(0 != activate_threads_~tmp___0~0#1); {144270#false} is VALID [2022-02-21 04:23:42,875 INFO L290 TraceCheckUtils]: 42: Hoare triple {144270#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {144270#false} is VALID [2022-02-21 04:23:42,875 INFO L290 TraceCheckUtils]: 43: Hoare triple {144270#false} assume !(1 == ~t2_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,875 INFO L290 TraceCheckUtils]: 44: Hoare triple {144270#false} is_transmit2_triggered_~__retres1~2#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,875 INFO L290 TraceCheckUtils]: 45: Hoare triple {144270#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {144270#false} is VALID [2022-02-21 04:23:42,875 INFO L290 TraceCheckUtils]: 46: Hoare triple {144270#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {144270#false} is VALID [2022-02-21 04:23:42,875 INFO L290 TraceCheckUtils]: 47: Hoare triple {144270#false} assume !(0 != activate_threads_~tmp___1~0#1); {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 48: Hoare triple {144270#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 49: Hoare triple {144270#false} assume 1 == ~t3_pc~0; {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 50: Hoare triple {144270#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 51: Hoare triple {144270#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 52: Hoare triple {144270#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 53: Hoare triple {144270#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 54: Hoare triple {144270#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {144270#false} is VALID [2022-02-21 04:23:42,876 INFO L290 TraceCheckUtils]: 55: Hoare triple {144270#false} assume !(1 == ~t4_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 56: Hoare triple {144270#false} is_transmit4_triggered_~__retres1~4#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 57: Hoare triple {144270#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 58: Hoare triple {144270#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 59: Hoare triple {144270#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 60: Hoare triple {144270#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 61: Hoare triple {144270#false} assume !(1 == ~t5_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 62: Hoare triple {144270#false} is_transmit5_triggered_~__retres1~5#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,877 INFO L290 TraceCheckUtils]: 63: Hoare triple {144270#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 64: Hoare triple {144270#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 65: Hoare triple {144270#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 66: Hoare triple {144270#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 67: Hoare triple {144270#false} assume !(1 == ~t6_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 68: Hoare triple {144270#false} is_transmit6_triggered_~__retres1~6#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 69: Hoare triple {144270#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 70: Hoare triple {144270#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {144270#false} is VALID [2022-02-21 04:23:42,878 INFO L290 TraceCheckUtils]: 71: Hoare triple {144270#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 72: Hoare triple {144270#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 73: Hoare triple {144270#false} assume !(1 == ~t7_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 74: Hoare triple {144270#false} is_transmit7_triggered_~__retres1~7#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 75: Hoare triple {144270#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 76: Hoare triple {144270#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 77: Hoare triple {144270#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 78: Hoare triple {144270#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {144270#false} is VALID [2022-02-21 04:23:42,879 INFO L290 TraceCheckUtils]: 79: Hoare triple {144270#false} assume !(1 == ~t8_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 80: Hoare triple {144270#false} is_transmit8_triggered_~__retres1~8#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 81: Hoare triple {144270#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 82: Hoare triple {144270#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 83: Hoare triple {144270#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 84: Hoare triple {144270#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 85: Hoare triple {144270#false} assume !(1 == ~t9_pc~0); {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 86: Hoare triple {144270#false} is_transmit9_triggered_~__retres1~9#1 := 0; {144270#false} is VALID [2022-02-21 04:23:42,880 INFO L290 TraceCheckUtils]: 87: Hoare triple {144270#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 88: Hoare triple {144270#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 89: Hoare triple {144270#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 90: Hoare triple {144270#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 91: Hoare triple {144270#false} assume !(1 == ~M_E~0); {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 92: Hoare triple {144270#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 93: Hoare triple {144270#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 94: Hoare triple {144270#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,881 INFO L290 TraceCheckUtils]: 95: Hoare triple {144270#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,882 INFO L290 TraceCheckUtils]: 96: Hoare triple {144270#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,882 INFO L290 TraceCheckUtils]: 97: Hoare triple {144270#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,882 INFO L290 TraceCheckUtils]: 98: Hoare triple {144270#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,882 INFO L290 TraceCheckUtils]: 99: Hoare triple {144270#false} assume !(1 == ~T8_E~0); {144270#false} is VALID [2022-02-21 04:23:42,882 INFO L290 TraceCheckUtils]: 100: Hoare triple {144270#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,882 INFO L290 TraceCheckUtils]: 101: Hoare triple {144270#false} assume 1 == ~E_M~0;~E_M~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,882 INFO L290 TraceCheckUtils]: 102: Hoare triple {144270#false} assume 1 == ~E_1~0;~E_1~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 103: Hoare triple {144270#false} assume !(1 == ~E_2~0); {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 104: Hoare triple {144270#false} assume 1 == ~E_3~0;~E_3~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 105: Hoare triple {144270#false} assume 1 == ~E_4~0;~E_4~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 106: Hoare triple {144270#false} assume 1 == ~E_5~0;~E_5~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 107: Hoare triple {144270#false} assume !(1 == ~E_6~0); {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 108: Hoare triple {144270#false} assume 1 == ~E_7~0;~E_7~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 109: Hoare triple {144270#false} assume 1 == ~E_8~0;~E_8~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,883 INFO L290 TraceCheckUtils]: 110: Hoare triple {144270#false} assume 1 == ~E_9~0;~E_9~0 := 2; {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 111: Hoare triple {144270#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 112: Hoare triple {144270#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 113: Hoare triple {144270#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 114: Hoare triple {144270#false} start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 115: Hoare triple {144270#false} assume !(0 == start_simulation_~tmp~3#1); {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 116: Hoare triple {144270#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 117: Hoare triple {144270#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {144270#false} is VALID [2022-02-21 04:23:42,884 INFO L290 TraceCheckUtils]: 118: Hoare triple {144270#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {144270#false} is VALID [2022-02-21 04:23:42,885 INFO L290 TraceCheckUtils]: 119: Hoare triple {144270#false} stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; {144270#false} is VALID [2022-02-21 04:23:42,885 INFO L290 TraceCheckUtils]: 120: Hoare triple {144270#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {144270#false} is VALID [2022-02-21 04:23:42,885 INFO L290 TraceCheckUtils]: 121: Hoare triple {144270#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {144270#false} is VALID [2022-02-21 04:23:42,885 INFO L290 TraceCheckUtils]: 122: Hoare triple {144270#false} start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {144270#false} is VALID [2022-02-21 04:23:42,885 INFO L290 TraceCheckUtils]: 123: Hoare triple {144270#false} assume !(0 != start_simulation_~tmp___0~1#1); {144270#false} is VALID [2022-02-21 04:23:42,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:42,886 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:42,886 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498131703] [2022-02-21 04:23:42,886 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498131703] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:42,886 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:42,886 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:23:42,886 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62451759] [2022-02-21 04:23:42,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:42,887 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:42,887 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:42,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:42,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:42,888 INFO L87 Difference]: Start difference. First operand 7461 states and 10681 transitions. cyclomatic complexity: 3224 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)