./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:22:53,580 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:22:53,581 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:22:53,608 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:22:53,609 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:22:53,610 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:22:53,611 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:22:53,613 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:22:53,614 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:22:53,615 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:22:53,616 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:22:53,617 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:22:53,617 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:22:53,618 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:22:53,619 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:22:53,620 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:22:53,622 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:22:53,625 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:22:53,627 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:22:53,631 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:22:53,639 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:22:53,640 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:22:53,641 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:22:53,642 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:22:53,644 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:22:53,644 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:22:53,651 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:22:53,652 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:22:53,652 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:22:53,653 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:22:53,653 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:22:53,654 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:22:53,654 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:22:53,655 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:22:53,656 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:22:53,656 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:22:53,657 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:22:53,657 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:22:53,657 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:22:53,658 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:22:53,659 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:22:53,662 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:22:53,684 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:22:53,686 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:22:53,687 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:22:53,687 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:22:53,688 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:22:53,689 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:22:53,689 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:22:53,689 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:22:53,690 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:22:53,690 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:22:53,691 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:22:53,691 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:22:53,691 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:22:53,691 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:22:53,692 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:22:53,692 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:22:53,692 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:22:53,692 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:22:53,692 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:22:53,693 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:22:53,693 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:22:53,693 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:22:53,693 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:22:53,693 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:22:53,694 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:22:53,694 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:22:53,694 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:22:53,694 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:22:53,694 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:22:53,695 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:22:53,695 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:22:53,696 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:22:53,696 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2022-02-21 04:22:53,926 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:22:53,944 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:22:53,946 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:22:53,947 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:22:53,948 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:22:53,950 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2022-02-21 04:22:54,004 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/889031420/59ff02fcbd5f46e081b0550083ae4e87/FLAGef55b8760 [2022-02-21 04:22:54,389 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:22:54,389 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2022-02-21 04:22:54,403 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/889031420/59ff02fcbd5f46e081b0550083ae4e87/FLAGef55b8760 [2022-02-21 04:22:54,795 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/889031420/59ff02fcbd5f46e081b0550083ae4e87 [2022-02-21 04:22:54,797 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:22:54,798 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:22:54,800 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:54,801 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:22:54,803 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:22:54,804 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:54" (1/1) ... [2022-02-21 04:22:54,806 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@222b34d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:54, skipping insertion in model container [2022-02-21 04:22:54,806 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:54" (1/1) ... [2022-02-21 04:22:54,811 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:22:54,848 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:22:54,974 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2022-02-21 04:22:55,084 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:55,095 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:22:55,105 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2022-02-21 04:22:55,161 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:55,176 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:22:55,177 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55 WrapperNode [2022-02-21 04:22:55,177 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:55,178 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:55,179 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:22:55,179 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:22:55,186 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,212 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,294 INFO L137 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3198 [2022-02-21 04:22:55,295 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:55,296 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:22:55,296 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:22:55,296 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:22:55,303 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,304 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,311 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,311 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,341 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,377 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,381 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,388 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:22:55,389 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:22:55,389 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:22:55,389 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:22:55,390 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,395 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:22:55,402 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:22:55,412 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:22:55,436 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:22:55,443 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:22:55,444 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:22:55,444 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:22:55,444 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:22:55,592 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:22:55,593 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:22:57,029 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:22:57,042 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:22:57,042 INFO L299 CfgBuilder]: Removed 13 assume(true) statements. [2022-02-21 04:22:57,044 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:57 BoogieIcfgContainer [2022-02-21 04:22:57,044 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:22:57,045 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:22:57,045 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:22:57,047 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:22:57,048 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:57,048 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:22:54" (1/3) ... [2022-02-21 04:22:57,049 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@707fc49a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:57, skipping insertion in model container [2022-02-21 04:22:57,049 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:57,049 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55" (2/3) ... [2022-02-21 04:22:57,049 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@707fc49a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:57, skipping insertion in model container [2022-02-21 04:22:57,049 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:57,050 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:57" (3/3) ... [2022-02-21 04:22:57,051 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2022-02-21 04:22:57,078 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:22:57,078 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:22:57,078 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:22:57,078 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:22:57,079 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:22:57,079 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:22:57,079 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:22:57,079 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:22:57,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:57,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2022-02-21 04:22:57,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:57,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:57,315 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:57,315 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:57,315 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:22:57,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:57,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2022-02-21 04:22:57,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:57,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:57,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:57,442 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:57,450 INFO L791 eck$LassoCheckResult]: Stem: 667#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1260#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 970#L1528true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24#L724true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1154#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1022#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 933#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 999#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1316#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 174#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 232#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 833#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 339#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 175#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58#L1036true assume !(0 == ~M_E~0); 1028#L1036-2true assume !(0 == ~T1_E~0); 609#L1041-1true assume !(0 == ~T2_E~0); 971#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 197#L1051-1true assume !(0 == ~T4_E~0); 748#L1056-1true assume !(0 == ~T5_E~0); 797#L1061-1true assume !(0 == ~T6_E~0); 143#L1066-1true assume !(0 == ~T7_E~0); 1149#L1071-1true assume !(0 == ~T8_E~0); 729#L1076-1true assume !(0 == ~T9_E~0); 91#L1081-1true assume !(0 == ~T10_E~0); 309#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1169#L1091-1true assume !(0 == ~E_1~0); 1030#L1096-1true assume !(0 == ~E_2~0); 1265#L1101-1true assume !(0 == ~E_3~0); 350#L1106-1true assume !(0 == ~E_4~0); 548#L1111-1true assume !(0 == ~E_5~0); 459#L1116-1true assume !(0 == ~E_6~0); 1087#L1121-1true assume !(0 == ~E_7~0); 345#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 530#L1131-1true assume !(0 == ~E_9~0); 619#L1136-1true assume !(0 == ~E_10~0); 899#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 785#L514true assume 1 == ~m_pc~0; 738#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 356#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 302#L526true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1101#L1285true assume !(0 != activate_threads_~tmp~1#1); 1187#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151#L533true assume !(1 == ~t1_pc~0); 1042#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 499#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 380#L545true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 911#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 643#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902#L552true assume 1 == ~t2_pc~0; 276#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 934#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 714#L564true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 976#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 365#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 511#L571true assume 1 == ~t3_pc~0; 496#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 684#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111#L583true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 653#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 462#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50#L590true assume !(1 == ~t4_pc~0); 510#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1286#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 709#L602true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1112#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 668#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 460#L609true assume 1 == ~t5_pc~0; 1276#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1098#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69#L621true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1376#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 455#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1275#L628true assume !(1 == ~t6_pc~0); 531#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1254#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1061#L640true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1178#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 707#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 842#L647true assume 1 == ~t7_pc~0; 351#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 888#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 556#L659true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 352#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1248#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1218#L666true assume !(1 == ~t8_pc~0); 783#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 364#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 815#L678true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 477#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 307#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1131#L685true assume 1 == ~t9_pc~0; 1296#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 913#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 893#L697true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 323#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1008#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 587#L704true assume !(1 == ~t10_pc~0); 1083#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1036#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 746#L716true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 202#L1365-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 696#L1154true assume !(1 == ~M_E~0); 1175#L1154-2true assume !(1 == ~T1_E~0); 186#L1159-1true assume !(1 == ~T2_E~0); 1306#L1164-1true assume !(1 == ~T3_E~0); 475#L1169-1true assume !(1 == ~T4_E~0); 383#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 257#L1179-1true assume !(1 == ~T6_E~0); 179#L1184-1true assume !(1 == ~T7_E~0); 221#L1189-1true assume !(1 == ~T8_E~0); 299#L1194-1true assume !(1 == ~T9_E~0); 1356#L1199-1true assume !(1 == ~T10_E~0); 268#L1204-1true assume !(1 == ~E_M~0); 1212#L1209-1true assume !(1 == ~E_1~0); 663#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1304#L1219-1true assume !(1 == ~E_3~0); 1183#L1224-1true assume !(1 == ~E_4~0); 493#L1229-1true assume !(1 == ~E_5~0); 122#L1234-1true assume !(1 == ~E_6~0); 773#L1239-1true assume !(1 == ~E_7~0); 149#L1244-1true assume !(1 == ~E_8~0); 820#L1249-1true assume !(1 == ~E_9~0); 735#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 74#L1259-1true assume { :end_inline_reset_delta_events } true; 1164#L1565-2true [2022-02-21 04:22:57,452 INFO L793 eck$LassoCheckResult]: Loop: 1164#L1565-2true assume !false; 672#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279#L1011true assume false; 1307#L1026true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 581#L724-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 743#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1062#L1036-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1302#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 827#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1184#L1051-3true assume !(0 == ~T4_E~0); 744#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 195#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 196#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1321#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1065#L1076-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 71#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1238#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 96#L1091-3true assume !(0 == ~E_1~0); 1141#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1002#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1060#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1118#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 986#L1116-3true assume 0 == ~E_6~0;~E_6~0 := 1; 595#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 936#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 853#L1131-3true assume !(0 == ~E_9~0); 1297#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1272#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 599#L514-36true assume !(1 == ~m_pc~0); 394#L514-38true is_master_triggered_~__retres1~0#1 := 0; 291#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1012#L526-12true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 641#L1285-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 226#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L533-36true assume 1 == ~t1_pc~0; 466#L534-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 958#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 737#L545-12true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 683#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 509#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1366#L552-36true assume 1 == ~t2_pc~0; 223#L553-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 547#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131#L564-12true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1173#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 208#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 830#L571-36true assume 1 == ~t3_pc~0; 452#L572-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 258#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 334#L583-12true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 826#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 873#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242#L590-36true assume !(1 == ~t4_pc~0); 879#L590-38true is_transmit4_triggered_~__retres1~4#1 := 0; 1015#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 355#L602-12true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1311#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 791#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1053#L609-36true assume !(1 == ~t5_pc~0); 1327#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 513#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 377#L621-12true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 859#L1325-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 570#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432#L628-36true assume 1 == ~t6_pc~0; 336#L629-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1132#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 673#L640-12true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 749#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 601#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1093#L647-36true assume 1 == ~t7_pc~0; 543#L648-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104#L659-12true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93#L1341-36true assume !(0 != activate_threads_~tmp___6~0#1); 698#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 768#L666-36true assume 1 == ~t8_pc~0; 185#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1193#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 994#L678-12true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1210#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 275#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 583#L685-36true assume !(1 == ~t9_pc~0); 136#L685-38true is_transmit9_triggered_~__retres1~9#1 := 0; 874#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 443#L697-12true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1264#L1357-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 362#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 369#L704-36true assume !(1 == ~t10_pc~0); 271#L704-38true is_transmit10_triggered_~__retres1~10#1 := 0; 1146#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 644#L716-12true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 724#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 145#L1365-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1349#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 969#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 758#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1323#L1164-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1090#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 317#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1180#L1179-3true assume !(1 == ~T6_E~0); 916#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 85#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 921#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 282#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1360#L1204-3true assume 1 == ~E_M~0;~E_M~0 := 2; 489#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 20#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1013#L1219-3true assume !(1 == ~E_3~0); 652#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1370#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 671#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 150#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 526#L1244-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1069#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 987#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 655#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 752#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1282#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 503#L852-1true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 607#L1584true assume !(0 == start_simulation_~tmp~3#1); 636#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 156#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 935#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 234#L852-2true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 348#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 977#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 326#L1547true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1158#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1164#L1565-2true [2022-02-21 04:22:57,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:57,458 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2022-02-21 04:22:57,466 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:57,467 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438485384] [2022-02-21 04:22:57,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:57,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:57,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:57,666 INFO L290 TraceCheckUtils]: 0: Hoare triple {1378#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {1378#true} is VALID [2022-02-21 04:22:57,667 INFO L290 TraceCheckUtils]: 1: Hoare triple {1378#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {1380#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:57,667 INFO L290 TraceCheckUtils]: 2: Hoare triple {1380#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1380#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:57,669 INFO L290 TraceCheckUtils]: 3: Hoare triple {1380#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1380#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:57,669 INFO L290 TraceCheckUtils]: 4: Hoare triple {1380#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,669 INFO L290 TraceCheckUtils]: 5: Hoare triple {1379#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1379#false} is VALID [2022-02-21 04:22:57,669 INFO L290 TraceCheckUtils]: 6: Hoare triple {1379#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,670 INFO L290 TraceCheckUtils]: 7: Hoare triple {1379#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,670 INFO L290 TraceCheckUtils]: 8: Hoare triple {1379#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,670 INFO L290 TraceCheckUtils]: 9: Hoare triple {1379#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,670 INFO L290 TraceCheckUtils]: 10: Hoare triple {1379#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,671 INFO L290 TraceCheckUtils]: 11: Hoare triple {1379#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,671 INFO L290 TraceCheckUtils]: 12: Hoare triple {1379#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,671 INFO L290 TraceCheckUtils]: 13: Hoare triple {1379#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1379#false} is VALID [2022-02-21 04:22:57,671 INFO L290 TraceCheckUtils]: 14: Hoare triple {1379#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,671 INFO L290 TraceCheckUtils]: 15: Hoare triple {1379#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1379#false} is VALID [2022-02-21 04:22:57,672 INFO L290 TraceCheckUtils]: 16: Hoare triple {1379#false} assume !(0 == ~M_E~0); {1379#false} is VALID [2022-02-21 04:22:57,672 INFO L290 TraceCheckUtils]: 17: Hoare triple {1379#false} assume !(0 == ~T1_E~0); {1379#false} is VALID [2022-02-21 04:22:57,672 INFO L290 TraceCheckUtils]: 18: Hoare triple {1379#false} assume !(0 == ~T2_E~0); {1379#false} is VALID [2022-02-21 04:22:57,672 INFO L290 TraceCheckUtils]: 19: Hoare triple {1379#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1379#false} is VALID [2022-02-21 04:22:57,673 INFO L290 TraceCheckUtils]: 20: Hoare triple {1379#false} assume !(0 == ~T4_E~0); {1379#false} is VALID [2022-02-21 04:22:57,673 INFO L290 TraceCheckUtils]: 21: Hoare triple {1379#false} assume !(0 == ~T5_E~0); {1379#false} is VALID [2022-02-21 04:22:57,673 INFO L290 TraceCheckUtils]: 22: Hoare triple {1379#false} assume !(0 == ~T6_E~0); {1379#false} is VALID [2022-02-21 04:22:57,673 INFO L290 TraceCheckUtils]: 23: Hoare triple {1379#false} assume !(0 == ~T7_E~0); {1379#false} is VALID [2022-02-21 04:22:57,673 INFO L290 TraceCheckUtils]: 24: Hoare triple {1379#false} assume !(0 == ~T8_E~0); {1379#false} is VALID [2022-02-21 04:22:57,674 INFO L290 TraceCheckUtils]: 25: Hoare triple {1379#false} assume !(0 == ~T9_E~0); {1379#false} is VALID [2022-02-21 04:22:57,674 INFO L290 TraceCheckUtils]: 26: Hoare triple {1379#false} assume !(0 == ~T10_E~0); {1379#false} is VALID [2022-02-21 04:22:57,674 INFO L290 TraceCheckUtils]: 27: Hoare triple {1379#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1379#false} is VALID [2022-02-21 04:22:57,674 INFO L290 TraceCheckUtils]: 28: Hoare triple {1379#false} assume !(0 == ~E_1~0); {1379#false} is VALID [2022-02-21 04:22:57,674 INFO L290 TraceCheckUtils]: 29: Hoare triple {1379#false} assume !(0 == ~E_2~0); {1379#false} is VALID [2022-02-21 04:22:57,675 INFO L290 TraceCheckUtils]: 30: Hoare triple {1379#false} assume !(0 == ~E_3~0); {1379#false} is VALID [2022-02-21 04:22:57,675 INFO L290 TraceCheckUtils]: 31: Hoare triple {1379#false} assume !(0 == ~E_4~0); {1379#false} is VALID [2022-02-21 04:22:57,675 INFO L290 TraceCheckUtils]: 32: Hoare triple {1379#false} assume !(0 == ~E_5~0); {1379#false} is VALID [2022-02-21 04:22:57,675 INFO L290 TraceCheckUtils]: 33: Hoare triple {1379#false} assume !(0 == ~E_6~0); {1379#false} is VALID [2022-02-21 04:22:57,676 INFO L290 TraceCheckUtils]: 34: Hoare triple {1379#false} assume !(0 == ~E_7~0); {1379#false} is VALID [2022-02-21 04:22:57,676 INFO L290 TraceCheckUtils]: 35: Hoare triple {1379#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1379#false} is VALID [2022-02-21 04:22:57,676 INFO L290 TraceCheckUtils]: 36: Hoare triple {1379#false} assume !(0 == ~E_9~0); {1379#false} is VALID [2022-02-21 04:22:57,676 INFO L290 TraceCheckUtils]: 37: Hoare triple {1379#false} assume !(0 == ~E_10~0); {1379#false} is VALID [2022-02-21 04:22:57,676 INFO L290 TraceCheckUtils]: 38: Hoare triple {1379#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1379#false} is VALID [2022-02-21 04:22:57,677 INFO L290 TraceCheckUtils]: 39: Hoare triple {1379#false} assume 1 == ~m_pc~0; {1379#false} is VALID [2022-02-21 04:22:57,677 INFO L290 TraceCheckUtils]: 40: Hoare triple {1379#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1379#false} is VALID [2022-02-21 04:22:57,677 INFO L290 TraceCheckUtils]: 41: Hoare triple {1379#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1379#false} is VALID [2022-02-21 04:22:57,677 INFO L290 TraceCheckUtils]: 42: Hoare triple {1379#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1379#false} is VALID [2022-02-21 04:22:57,678 INFO L290 TraceCheckUtils]: 43: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp~1#1); {1379#false} is VALID [2022-02-21 04:22:57,678 INFO L290 TraceCheckUtils]: 44: Hoare triple {1379#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1379#false} is VALID [2022-02-21 04:22:57,678 INFO L290 TraceCheckUtils]: 45: Hoare triple {1379#false} assume !(1 == ~t1_pc~0); {1379#false} is VALID [2022-02-21 04:22:57,678 INFO L290 TraceCheckUtils]: 46: Hoare triple {1379#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1379#false} is VALID [2022-02-21 04:22:57,678 INFO L290 TraceCheckUtils]: 47: Hoare triple {1379#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1379#false} is VALID [2022-02-21 04:22:57,679 INFO L290 TraceCheckUtils]: 48: Hoare triple {1379#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1379#false} is VALID [2022-02-21 04:22:57,679 INFO L290 TraceCheckUtils]: 49: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___0~0#1); {1379#false} is VALID [2022-02-21 04:22:57,679 INFO L290 TraceCheckUtils]: 50: Hoare triple {1379#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1379#false} is VALID [2022-02-21 04:22:57,679 INFO L290 TraceCheckUtils]: 51: Hoare triple {1379#false} assume 1 == ~t2_pc~0; {1379#false} is VALID [2022-02-21 04:22:57,680 INFO L290 TraceCheckUtils]: 52: Hoare triple {1379#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1379#false} is VALID [2022-02-21 04:22:57,680 INFO L290 TraceCheckUtils]: 53: Hoare triple {1379#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1379#false} is VALID [2022-02-21 04:22:57,680 INFO L290 TraceCheckUtils]: 54: Hoare triple {1379#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1379#false} is VALID [2022-02-21 04:22:57,680 INFO L290 TraceCheckUtils]: 55: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___1~0#1); {1379#false} is VALID [2022-02-21 04:22:57,680 INFO L290 TraceCheckUtils]: 56: Hoare triple {1379#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1379#false} is VALID [2022-02-21 04:22:57,681 INFO L290 TraceCheckUtils]: 57: Hoare triple {1379#false} assume 1 == ~t3_pc~0; {1379#false} is VALID [2022-02-21 04:22:57,681 INFO L290 TraceCheckUtils]: 58: Hoare triple {1379#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1379#false} is VALID [2022-02-21 04:22:57,681 INFO L290 TraceCheckUtils]: 59: Hoare triple {1379#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1379#false} is VALID [2022-02-21 04:22:57,681 INFO L290 TraceCheckUtils]: 60: Hoare triple {1379#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1379#false} is VALID [2022-02-21 04:22:57,681 INFO L290 TraceCheckUtils]: 61: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___2~0#1); {1379#false} is VALID [2022-02-21 04:22:57,682 INFO L290 TraceCheckUtils]: 62: Hoare triple {1379#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1379#false} is VALID [2022-02-21 04:22:57,682 INFO L290 TraceCheckUtils]: 63: Hoare triple {1379#false} assume !(1 == ~t4_pc~0); {1379#false} is VALID [2022-02-21 04:22:57,682 INFO L290 TraceCheckUtils]: 64: Hoare triple {1379#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1379#false} is VALID [2022-02-21 04:22:57,682 INFO L290 TraceCheckUtils]: 65: Hoare triple {1379#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1379#false} is VALID [2022-02-21 04:22:57,683 INFO L290 TraceCheckUtils]: 66: Hoare triple {1379#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1379#false} is VALID [2022-02-21 04:22:57,683 INFO L290 TraceCheckUtils]: 67: Hoare triple {1379#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1379#false} is VALID [2022-02-21 04:22:57,683 INFO L290 TraceCheckUtils]: 68: Hoare triple {1379#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1379#false} is VALID [2022-02-21 04:22:57,683 INFO L290 TraceCheckUtils]: 69: Hoare triple {1379#false} assume 1 == ~t5_pc~0; {1379#false} is VALID [2022-02-21 04:22:57,683 INFO L290 TraceCheckUtils]: 70: Hoare triple {1379#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1379#false} is VALID [2022-02-21 04:22:57,684 INFO L290 TraceCheckUtils]: 71: Hoare triple {1379#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1379#false} is VALID [2022-02-21 04:22:57,684 INFO L290 TraceCheckUtils]: 72: Hoare triple {1379#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1379#false} is VALID [2022-02-21 04:22:57,684 INFO L290 TraceCheckUtils]: 73: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___4~0#1); {1379#false} is VALID [2022-02-21 04:22:57,684 INFO L290 TraceCheckUtils]: 74: Hoare triple {1379#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1379#false} is VALID [2022-02-21 04:22:57,685 INFO L290 TraceCheckUtils]: 75: Hoare triple {1379#false} assume !(1 == ~t6_pc~0); {1379#false} is VALID [2022-02-21 04:22:57,685 INFO L290 TraceCheckUtils]: 76: Hoare triple {1379#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1379#false} is VALID [2022-02-21 04:22:57,685 INFO L290 TraceCheckUtils]: 77: Hoare triple {1379#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1379#false} is VALID [2022-02-21 04:22:57,685 INFO L290 TraceCheckUtils]: 78: Hoare triple {1379#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1379#false} is VALID [2022-02-21 04:22:57,685 INFO L290 TraceCheckUtils]: 79: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___5~0#1); {1379#false} is VALID [2022-02-21 04:22:57,686 INFO L290 TraceCheckUtils]: 80: Hoare triple {1379#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1379#false} is VALID [2022-02-21 04:22:57,686 INFO L290 TraceCheckUtils]: 81: Hoare triple {1379#false} assume 1 == ~t7_pc~0; {1379#false} is VALID [2022-02-21 04:22:57,686 INFO L290 TraceCheckUtils]: 82: Hoare triple {1379#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1379#false} is VALID [2022-02-21 04:22:57,686 INFO L290 TraceCheckUtils]: 83: Hoare triple {1379#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1379#false} is VALID [2022-02-21 04:22:57,686 INFO L290 TraceCheckUtils]: 84: Hoare triple {1379#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1379#false} is VALID [2022-02-21 04:22:57,687 INFO L290 TraceCheckUtils]: 85: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___6~0#1); {1379#false} is VALID [2022-02-21 04:22:57,687 INFO L290 TraceCheckUtils]: 86: Hoare triple {1379#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1379#false} is VALID [2022-02-21 04:22:57,687 INFO L290 TraceCheckUtils]: 87: Hoare triple {1379#false} assume !(1 == ~t8_pc~0); {1379#false} is VALID [2022-02-21 04:22:57,687 INFO L290 TraceCheckUtils]: 88: Hoare triple {1379#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1379#false} is VALID [2022-02-21 04:22:57,688 INFO L290 TraceCheckUtils]: 89: Hoare triple {1379#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1379#false} is VALID [2022-02-21 04:22:57,688 INFO L290 TraceCheckUtils]: 90: Hoare triple {1379#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1379#false} is VALID [2022-02-21 04:22:57,688 INFO L290 TraceCheckUtils]: 91: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___7~0#1); {1379#false} is VALID [2022-02-21 04:22:57,688 INFO L290 TraceCheckUtils]: 92: Hoare triple {1379#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1379#false} is VALID [2022-02-21 04:22:57,688 INFO L290 TraceCheckUtils]: 93: Hoare triple {1379#false} assume 1 == ~t9_pc~0; {1379#false} is VALID [2022-02-21 04:22:57,689 INFO L290 TraceCheckUtils]: 94: Hoare triple {1379#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1379#false} is VALID [2022-02-21 04:22:57,689 INFO L290 TraceCheckUtils]: 95: Hoare triple {1379#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1379#false} is VALID [2022-02-21 04:22:57,689 INFO L290 TraceCheckUtils]: 96: Hoare triple {1379#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1379#false} is VALID [2022-02-21 04:22:57,689 INFO L290 TraceCheckUtils]: 97: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___8~0#1); {1379#false} is VALID [2022-02-21 04:22:57,689 INFO L290 TraceCheckUtils]: 98: Hoare triple {1379#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1379#false} is VALID [2022-02-21 04:22:57,690 INFO L290 TraceCheckUtils]: 99: Hoare triple {1379#false} assume !(1 == ~t10_pc~0); {1379#false} is VALID [2022-02-21 04:22:57,690 INFO L290 TraceCheckUtils]: 100: Hoare triple {1379#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1379#false} is VALID [2022-02-21 04:22:57,690 INFO L290 TraceCheckUtils]: 101: Hoare triple {1379#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1379#false} is VALID [2022-02-21 04:22:57,690 INFO L290 TraceCheckUtils]: 102: Hoare triple {1379#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1379#false} is VALID [2022-02-21 04:22:57,690 INFO L290 TraceCheckUtils]: 103: Hoare triple {1379#false} assume !(0 != activate_threads_~tmp___9~0#1); {1379#false} is VALID [2022-02-21 04:22:57,691 INFO L290 TraceCheckUtils]: 104: Hoare triple {1379#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1379#false} is VALID [2022-02-21 04:22:57,691 INFO L290 TraceCheckUtils]: 105: Hoare triple {1379#false} assume !(1 == ~M_E~0); {1379#false} is VALID [2022-02-21 04:22:57,691 INFO L290 TraceCheckUtils]: 106: Hoare triple {1379#false} assume !(1 == ~T1_E~0); {1379#false} is VALID [2022-02-21 04:22:57,691 INFO L290 TraceCheckUtils]: 107: Hoare triple {1379#false} assume !(1 == ~T2_E~0); {1379#false} is VALID [2022-02-21 04:22:57,692 INFO L290 TraceCheckUtils]: 108: Hoare triple {1379#false} assume !(1 == ~T3_E~0); {1379#false} is VALID [2022-02-21 04:22:57,692 INFO L290 TraceCheckUtils]: 109: Hoare triple {1379#false} assume !(1 == ~T4_E~0); {1379#false} is VALID [2022-02-21 04:22:57,692 INFO L290 TraceCheckUtils]: 110: Hoare triple {1379#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,692 INFO L290 TraceCheckUtils]: 111: Hoare triple {1379#false} assume !(1 == ~T6_E~0); {1379#false} is VALID [2022-02-21 04:22:57,692 INFO L290 TraceCheckUtils]: 112: Hoare triple {1379#false} assume !(1 == ~T7_E~0); {1379#false} is VALID [2022-02-21 04:22:57,693 INFO L290 TraceCheckUtils]: 113: Hoare triple {1379#false} assume !(1 == ~T8_E~0); {1379#false} is VALID [2022-02-21 04:22:57,693 INFO L290 TraceCheckUtils]: 114: Hoare triple {1379#false} assume !(1 == ~T9_E~0); {1379#false} is VALID [2022-02-21 04:22:57,693 INFO L290 TraceCheckUtils]: 115: Hoare triple {1379#false} assume !(1 == ~T10_E~0); {1379#false} is VALID [2022-02-21 04:22:57,693 INFO L290 TraceCheckUtils]: 116: Hoare triple {1379#false} assume !(1 == ~E_M~0); {1379#false} is VALID [2022-02-21 04:22:57,693 INFO L290 TraceCheckUtils]: 117: Hoare triple {1379#false} assume !(1 == ~E_1~0); {1379#false} is VALID [2022-02-21 04:22:57,694 INFO L290 TraceCheckUtils]: 118: Hoare triple {1379#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,694 INFO L290 TraceCheckUtils]: 119: Hoare triple {1379#false} assume !(1 == ~E_3~0); {1379#false} is VALID [2022-02-21 04:22:57,694 INFO L290 TraceCheckUtils]: 120: Hoare triple {1379#false} assume !(1 == ~E_4~0); {1379#false} is VALID [2022-02-21 04:22:57,694 INFO L290 TraceCheckUtils]: 121: Hoare triple {1379#false} assume !(1 == ~E_5~0); {1379#false} is VALID [2022-02-21 04:22:57,694 INFO L290 TraceCheckUtils]: 122: Hoare triple {1379#false} assume !(1 == ~E_6~0); {1379#false} is VALID [2022-02-21 04:22:57,695 INFO L290 TraceCheckUtils]: 123: Hoare triple {1379#false} assume !(1 == ~E_7~0); {1379#false} is VALID [2022-02-21 04:22:57,695 INFO L290 TraceCheckUtils]: 124: Hoare triple {1379#false} assume !(1 == ~E_8~0); {1379#false} is VALID [2022-02-21 04:22:57,695 INFO L290 TraceCheckUtils]: 125: Hoare triple {1379#false} assume !(1 == ~E_9~0); {1379#false} is VALID [2022-02-21 04:22:57,695 INFO L290 TraceCheckUtils]: 126: Hoare triple {1379#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1379#false} is VALID [2022-02-21 04:22:57,695 INFO L290 TraceCheckUtils]: 127: Hoare triple {1379#false} assume { :end_inline_reset_delta_events } true; {1379#false} is VALID [2022-02-21 04:22:57,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:57,697 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:57,697 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438485384] [2022-02-21 04:22:57,698 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438485384] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:57,698 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:57,698 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:57,700 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799838545] [2022-02-21 04:22:57,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:57,704 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:57,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:57,705 INFO L85 PathProgramCache]: Analyzing trace with hash 1515191513, now seen corresponding path program 1 times [2022-02-21 04:22:57,705 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:57,705 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550377972] [2022-02-21 04:22:57,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:57,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:57,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:57,742 INFO L290 TraceCheckUtils]: 0: Hoare triple {1381#true} assume !false; {1381#true} is VALID [2022-02-21 04:22:57,743 INFO L290 TraceCheckUtils]: 1: Hoare triple {1381#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1381#true} is VALID [2022-02-21 04:22:57,743 INFO L290 TraceCheckUtils]: 2: Hoare triple {1381#true} assume false; {1382#false} is VALID [2022-02-21 04:22:57,743 INFO L290 TraceCheckUtils]: 3: Hoare triple {1382#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1382#false} is VALID [2022-02-21 04:22:57,743 INFO L290 TraceCheckUtils]: 4: Hoare triple {1382#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1382#false} is VALID [2022-02-21 04:22:57,744 INFO L290 TraceCheckUtils]: 5: Hoare triple {1382#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,744 INFO L290 TraceCheckUtils]: 6: Hoare triple {1382#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,744 INFO L290 TraceCheckUtils]: 7: Hoare triple {1382#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,744 INFO L290 TraceCheckUtils]: 8: Hoare triple {1382#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,744 INFO L290 TraceCheckUtils]: 9: Hoare triple {1382#false} assume !(0 == ~T4_E~0); {1382#false} is VALID [2022-02-21 04:22:57,745 INFO L290 TraceCheckUtils]: 10: Hoare triple {1382#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,745 INFO L290 TraceCheckUtils]: 11: Hoare triple {1382#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,745 INFO L290 TraceCheckUtils]: 12: Hoare triple {1382#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,745 INFO L290 TraceCheckUtils]: 13: Hoare triple {1382#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,745 INFO L290 TraceCheckUtils]: 14: Hoare triple {1382#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,745 INFO L290 TraceCheckUtils]: 15: Hoare triple {1382#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,746 INFO L290 TraceCheckUtils]: 16: Hoare triple {1382#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,746 INFO L290 TraceCheckUtils]: 17: Hoare triple {1382#false} assume !(0 == ~E_1~0); {1382#false} is VALID [2022-02-21 04:22:57,746 INFO L290 TraceCheckUtils]: 18: Hoare triple {1382#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,746 INFO L290 TraceCheckUtils]: 19: Hoare triple {1382#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,746 INFO L290 TraceCheckUtils]: 20: Hoare triple {1382#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,747 INFO L290 TraceCheckUtils]: 21: Hoare triple {1382#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,747 INFO L290 TraceCheckUtils]: 22: Hoare triple {1382#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,747 INFO L290 TraceCheckUtils]: 23: Hoare triple {1382#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,747 INFO L290 TraceCheckUtils]: 24: Hoare triple {1382#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,747 INFO L290 TraceCheckUtils]: 25: Hoare triple {1382#false} assume !(0 == ~E_9~0); {1382#false} is VALID [2022-02-21 04:22:57,748 INFO L290 TraceCheckUtils]: 26: Hoare triple {1382#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1382#false} is VALID [2022-02-21 04:22:57,748 INFO L290 TraceCheckUtils]: 27: Hoare triple {1382#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1382#false} is VALID [2022-02-21 04:22:57,748 INFO L290 TraceCheckUtils]: 28: Hoare triple {1382#false} assume !(1 == ~m_pc~0); {1382#false} is VALID [2022-02-21 04:22:57,748 INFO L290 TraceCheckUtils]: 29: Hoare triple {1382#false} is_master_triggered_~__retres1~0#1 := 0; {1382#false} is VALID [2022-02-21 04:22:57,748 INFO L290 TraceCheckUtils]: 30: Hoare triple {1382#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1382#false} is VALID [2022-02-21 04:22:57,749 INFO L290 TraceCheckUtils]: 31: Hoare triple {1382#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1382#false} is VALID [2022-02-21 04:22:57,749 INFO L290 TraceCheckUtils]: 32: Hoare triple {1382#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,749 INFO L290 TraceCheckUtils]: 33: Hoare triple {1382#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1382#false} is VALID [2022-02-21 04:22:57,749 INFO L290 TraceCheckUtils]: 34: Hoare triple {1382#false} assume 1 == ~t1_pc~0; {1382#false} is VALID [2022-02-21 04:22:57,749 INFO L290 TraceCheckUtils]: 35: Hoare triple {1382#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,749 INFO L290 TraceCheckUtils]: 36: Hoare triple {1382#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1382#false} is VALID [2022-02-21 04:22:57,750 INFO L290 TraceCheckUtils]: 37: Hoare triple {1382#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1382#false} is VALID [2022-02-21 04:22:57,750 INFO L290 TraceCheckUtils]: 38: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,750 INFO L290 TraceCheckUtils]: 39: Hoare triple {1382#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1382#false} is VALID [2022-02-21 04:22:57,750 INFO L290 TraceCheckUtils]: 40: Hoare triple {1382#false} assume 1 == ~t2_pc~0; {1382#false} is VALID [2022-02-21 04:22:57,750 INFO L290 TraceCheckUtils]: 41: Hoare triple {1382#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,751 INFO L290 TraceCheckUtils]: 42: Hoare triple {1382#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1382#false} is VALID [2022-02-21 04:22:57,751 INFO L290 TraceCheckUtils]: 43: Hoare triple {1382#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1382#false} is VALID [2022-02-21 04:22:57,751 INFO L290 TraceCheckUtils]: 44: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,751 INFO L290 TraceCheckUtils]: 45: Hoare triple {1382#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1382#false} is VALID [2022-02-21 04:22:57,751 INFO L290 TraceCheckUtils]: 46: Hoare triple {1382#false} assume 1 == ~t3_pc~0; {1382#false} is VALID [2022-02-21 04:22:57,752 INFO L290 TraceCheckUtils]: 47: Hoare triple {1382#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,752 INFO L290 TraceCheckUtils]: 48: Hoare triple {1382#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1382#false} is VALID [2022-02-21 04:22:57,752 INFO L290 TraceCheckUtils]: 49: Hoare triple {1382#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1382#false} is VALID [2022-02-21 04:22:57,752 INFO L290 TraceCheckUtils]: 50: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,752 INFO L290 TraceCheckUtils]: 51: Hoare triple {1382#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1382#false} is VALID [2022-02-21 04:22:57,753 INFO L290 TraceCheckUtils]: 52: Hoare triple {1382#false} assume !(1 == ~t4_pc~0); {1382#false} is VALID [2022-02-21 04:22:57,753 INFO L290 TraceCheckUtils]: 53: Hoare triple {1382#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1382#false} is VALID [2022-02-21 04:22:57,753 INFO L290 TraceCheckUtils]: 54: Hoare triple {1382#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1382#false} is VALID [2022-02-21 04:22:57,753 INFO L290 TraceCheckUtils]: 55: Hoare triple {1382#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1382#false} is VALID [2022-02-21 04:22:57,753 INFO L290 TraceCheckUtils]: 56: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,754 INFO L290 TraceCheckUtils]: 57: Hoare triple {1382#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1382#false} is VALID [2022-02-21 04:22:57,754 INFO L290 TraceCheckUtils]: 58: Hoare triple {1382#false} assume !(1 == ~t5_pc~0); {1382#false} is VALID [2022-02-21 04:22:57,754 INFO L290 TraceCheckUtils]: 59: Hoare triple {1382#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1382#false} is VALID [2022-02-21 04:22:57,754 INFO L290 TraceCheckUtils]: 60: Hoare triple {1382#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1382#false} is VALID [2022-02-21 04:22:57,754 INFO L290 TraceCheckUtils]: 61: Hoare triple {1382#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1382#false} is VALID [2022-02-21 04:22:57,754 INFO L290 TraceCheckUtils]: 62: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,755 INFO L290 TraceCheckUtils]: 63: Hoare triple {1382#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1382#false} is VALID [2022-02-21 04:22:57,755 INFO L290 TraceCheckUtils]: 64: Hoare triple {1382#false} assume 1 == ~t6_pc~0; {1382#false} is VALID [2022-02-21 04:22:57,755 INFO L290 TraceCheckUtils]: 65: Hoare triple {1382#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,755 INFO L290 TraceCheckUtils]: 66: Hoare triple {1382#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1382#false} is VALID [2022-02-21 04:22:57,755 INFO L290 TraceCheckUtils]: 67: Hoare triple {1382#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1382#false} is VALID [2022-02-21 04:22:57,756 INFO L290 TraceCheckUtils]: 68: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,756 INFO L290 TraceCheckUtils]: 69: Hoare triple {1382#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1382#false} is VALID [2022-02-21 04:22:57,756 INFO L290 TraceCheckUtils]: 70: Hoare triple {1382#false} assume 1 == ~t7_pc~0; {1382#false} is VALID [2022-02-21 04:22:57,756 INFO L290 TraceCheckUtils]: 71: Hoare triple {1382#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,756 INFO L290 TraceCheckUtils]: 72: Hoare triple {1382#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1382#false} is VALID [2022-02-21 04:22:57,757 INFO L290 TraceCheckUtils]: 73: Hoare triple {1382#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1382#false} is VALID [2022-02-21 04:22:57,757 INFO L290 TraceCheckUtils]: 74: Hoare triple {1382#false} assume !(0 != activate_threads_~tmp___6~0#1); {1382#false} is VALID [2022-02-21 04:22:57,757 INFO L290 TraceCheckUtils]: 75: Hoare triple {1382#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1382#false} is VALID [2022-02-21 04:22:57,757 INFO L290 TraceCheckUtils]: 76: Hoare triple {1382#false} assume 1 == ~t8_pc~0; {1382#false} is VALID [2022-02-21 04:22:57,757 INFO L290 TraceCheckUtils]: 77: Hoare triple {1382#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,757 INFO L290 TraceCheckUtils]: 78: Hoare triple {1382#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1382#false} is VALID [2022-02-21 04:22:57,758 INFO L290 TraceCheckUtils]: 79: Hoare triple {1382#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1382#false} is VALID [2022-02-21 04:22:57,758 INFO L290 TraceCheckUtils]: 80: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,758 INFO L290 TraceCheckUtils]: 81: Hoare triple {1382#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1382#false} is VALID [2022-02-21 04:22:57,758 INFO L290 TraceCheckUtils]: 82: Hoare triple {1382#false} assume !(1 == ~t9_pc~0); {1382#false} is VALID [2022-02-21 04:22:57,758 INFO L290 TraceCheckUtils]: 83: Hoare triple {1382#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1382#false} is VALID [2022-02-21 04:22:57,759 INFO L290 TraceCheckUtils]: 84: Hoare triple {1382#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1382#false} is VALID [2022-02-21 04:22:57,759 INFO L290 TraceCheckUtils]: 85: Hoare triple {1382#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1382#false} is VALID [2022-02-21 04:22:57,759 INFO L290 TraceCheckUtils]: 86: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,759 INFO L290 TraceCheckUtils]: 87: Hoare triple {1382#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1382#false} is VALID [2022-02-21 04:22:57,759 INFO L290 TraceCheckUtils]: 88: Hoare triple {1382#false} assume !(1 == ~t10_pc~0); {1382#false} is VALID [2022-02-21 04:22:57,760 INFO L290 TraceCheckUtils]: 89: Hoare triple {1382#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1382#false} is VALID [2022-02-21 04:22:57,760 INFO L290 TraceCheckUtils]: 90: Hoare triple {1382#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1382#false} is VALID [2022-02-21 04:22:57,760 INFO L290 TraceCheckUtils]: 91: Hoare triple {1382#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1382#false} is VALID [2022-02-21 04:22:57,760 INFO L290 TraceCheckUtils]: 92: Hoare triple {1382#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1382#false} is VALID [2022-02-21 04:22:57,760 INFO L290 TraceCheckUtils]: 93: Hoare triple {1382#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1382#false} is VALID [2022-02-21 04:22:57,760 INFO L290 TraceCheckUtils]: 94: Hoare triple {1382#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,761 INFO L290 TraceCheckUtils]: 95: Hoare triple {1382#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,761 INFO L290 TraceCheckUtils]: 96: Hoare triple {1382#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,761 INFO L290 TraceCheckUtils]: 97: Hoare triple {1382#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,761 INFO L290 TraceCheckUtils]: 98: Hoare triple {1382#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,761 INFO L290 TraceCheckUtils]: 99: Hoare triple {1382#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,762 INFO L290 TraceCheckUtils]: 100: Hoare triple {1382#false} assume !(1 == ~T6_E~0); {1382#false} is VALID [2022-02-21 04:22:57,762 INFO L290 TraceCheckUtils]: 101: Hoare triple {1382#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,762 INFO L290 TraceCheckUtils]: 102: Hoare triple {1382#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,762 INFO L290 TraceCheckUtils]: 103: Hoare triple {1382#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,762 INFO L290 TraceCheckUtils]: 104: Hoare triple {1382#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,762 INFO L290 TraceCheckUtils]: 105: Hoare triple {1382#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,763 INFO L290 TraceCheckUtils]: 106: Hoare triple {1382#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,763 INFO L290 TraceCheckUtils]: 107: Hoare triple {1382#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,763 INFO L290 TraceCheckUtils]: 108: Hoare triple {1382#false} assume !(1 == ~E_3~0); {1382#false} is VALID [2022-02-21 04:22:57,763 INFO L290 TraceCheckUtils]: 109: Hoare triple {1382#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,763 INFO L290 TraceCheckUtils]: 110: Hoare triple {1382#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,764 INFO L290 TraceCheckUtils]: 111: Hoare triple {1382#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,764 INFO L290 TraceCheckUtils]: 112: Hoare triple {1382#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,764 INFO L290 TraceCheckUtils]: 113: Hoare triple {1382#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,764 INFO L290 TraceCheckUtils]: 114: Hoare triple {1382#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,764 INFO L290 TraceCheckUtils]: 115: Hoare triple {1382#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1382#false} is VALID [2022-02-21 04:22:57,765 INFO L290 TraceCheckUtils]: 116: Hoare triple {1382#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {1382#false} is VALID [2022-02-21 04:22:57,765 INFO L290 TraceCheckUtils]: 117: Hoare triple {1382#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,765 INFO L290 TraceCheckUtils]: 118: Hoare triple {1382#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {1382#false} is VALID [2022-02-21 04:22:57,765 INFO L290 TraceCheckUtils]: 119: Hoare triple {1382#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {1382#false} is VALID [2022-02-21 04:22:57,765 INFO L290 TraceCheckUtils]: 120: Hoare triple {1382#false} assume !(0 == start_simulation_~tmp~3#1); {1382#false} is VALID [2022-02-21 04:22:57,765 INFO L290 TraceCheckUtils]: 121: Hoare triple {1382#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {1382#false} is VALID [2022-02-21 04:22:57,766 INFO L290 TraceCheckUtils]: 122: Hoare triple {1382#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {1382#false} is VALID [2022-02-21 04:22:57,766 INFO L290 TraceCheckUtils]: 123: Hoare triple {1382#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {1382#false} is VALID [2022-02-21 04:22:57,766 INFO L290 TraceCheckUtils]: 124: Hoare triple {1382#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {1382#false} is VALID [2022-02-21 04:22:57,766 INFO L290 TraceCheckUtils]: 125: Hoare triple {1382#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1382#false} is VALID [2022-02-21 04:22:57,766 INFO L290 TraceCheckUtils]: 126: Hoare triple {1382#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1382#false} is VALID [2022-02-21 04:22:57,767 INFO L290 TraceCheckUtils]: 127: Hoare triple {1382#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {1382#false} is VALID [2022-02-21 04:22:57,767 INFO L290 TraceCheckUtils]: 128: Hoare triple {1382#false} assume !(0 != start_simulation_~tmp___0~1#1); {1382#false} is VALID [2022-02-21 04:22:57,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:57,768 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:57,768 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550377972] [2022-02-21 04:22:57,768 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550377972] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:57,768 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:57,768 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:57,769 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414757101] [2022-02-21 04:22:57,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:57,770 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:57,771 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:57,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:57,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:57,802 INFO L87 Difference]: Start difference. First operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:58,915 INFO L93 Difference]: Finished difference Result 1372 states and 2038 transitions. [2022-02-21 04:22:58,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:58,916 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,998 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:59,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2038 transitions. [2022-02-21 04:22:59,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:22:59,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1366 states and 2032 transitions. [2022-02-21 04:22:59,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:22:59,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:22:59,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2032 transitions. [2022-02-21 04:22:59,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:59,110 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2022-02-21 04:22:59,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2032 transitions. [2022-02-21 04:22:59,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:22:59,170 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:59,175 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2032 transitions. Second operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,178 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2032 transitions. Second operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,182 INFO L87 Difference]: Start difference. First operand 1366 states and 2032 transitions. Second operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:59,239 INFO L93 Difference]: Finished difference Result 1366 states and 2032 transitions. [2022-02-21 04:22:59,239 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2032 transitions. [2022-02-21 04:22:59,246 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:59,246 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:59,249 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2032 transitions. [2022-02-21 04:22:59,252 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2032 transitions. [2022-02-21 04:22:59,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:59,298 INFO L93 Difference]: Finished difference Result 1366 states and 2032 transitions. [2022-02-21 04:22:59,298 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2032 transitions. [2022-02-21 04:22:59,300 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:59,300 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:59,300 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:59,300 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:59,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:59,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2032 transitions. [2022-02-21 04:22:59,347 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2022-02-21 04:22:59,348 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2022-02-21 04:22:59,348 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:22:59,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2032 transitions. [2022-02-21 04:22:59,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:22:59,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:59,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:59,354 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:59,354 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:59,355 INFO L791 eck$LassoCheckResult]: Stem: 3813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4021#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2806#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2807#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4046#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4004#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4005#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4035#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3115#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3116#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3219#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3464#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3395#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3117#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2777#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2778#L1036 assume !(0 == ~M_E~0); 2876#L1036-2 assume !(0 == ~T1_E~0); 3752#L1041-1 assume !(0 == ~T2_E~0); 3753#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3151#L1051-1 assume !(0 == ~T4_E~0); 3152#L1056-1 assume !(0 == ~T5_E~0); 3890#L1061-1 assume !(0 == ~T6_E~0); 3049#L1066-1 assume !(0 == ~T7_E~0); 3050#L1071-1 assume !(0 == ~T8_E~0); 3873#L1076-1 assume !(0 == ~T9_E~0); 2944#L1081-1 assume !(0 == ~T10_E~0); 2945#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3348#L1091-1 assume !(0 == ~E_1~0); 4050#L1096-1 assume !(0 == ~E_2~0); 4051#L1101-1 assume !(0 == ~E_3~0); 3409#L1106-1 assume !(0 == ~E_4~0); 3410#L1111-1 assume !(0 == ~E_5~0); 3566#L1116-1 assume !(0 == ~E_6~0); 3567#L1121-1 assume !(0 == ~E_7~0); 3402#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3403#L1131-1 assume !(0 == ~E_9~0); 3653#L1136-1 assume !(0 == ~E_10~0); 3760#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3917#L514 assume 1 == ~m_pc~0; 3880#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3423#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3342#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3343#L1285 assume !(0 != activate_threads_~tmp~1#1); 4086#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3068#L533 assume !(1 == ~t1_pc~0); 3069#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3582#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3455#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3456#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3782#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3783#L552 assume 1 == ~t2_pc~0; 3294#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3295#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3861#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3862#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3437#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3438#L571 assume 1 == ~t3_pc~0; 3614#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3615#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2984#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2985#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3572#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2860#L590 assume !(1 == ~t4_pc~0); 2861#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3625#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3858#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3859#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3815#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3568#L609 assume 1 == ~t5_pc~0; 3569#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4083#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2895#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2896#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3563#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3564#L628 assume !(1 == ~t6_pc~0); 3497#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3496#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4068#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4069#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3853#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3854#L647 assume 1 == ~t7_pc~0; 3411#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3412#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3690#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3418#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3419#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4115#L666 assume !(1 == ~t8_pc~0); 3198#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3199#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3433#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3590#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3345#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3346#L685 assume 1 == ~t9_pc~0; 4092#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3989#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3981#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3371#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3372#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3724#L704 assume !(1 == ~t10_pc~0); 3363#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3362#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3888#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2916#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2917#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3162#L1154 assume !(1 == ~M_E~0); 3841#L1154-2 assume !(1 == ~T1_E~0); 3134#L1159-1 assume !(1 == ~T2_E~0); 3135#L1164-1 assume !(1 == ~T3_E~0); 3587#L1169-1 assume !(1 == ~T4_E~0); 3459#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3266#L1179-1 assume !(1 == ~T6_E~0); 3120#L1184-1 assume !(1 == ~T7_E~0); 3121#L1189-1 assume !(1 == ~T8_E~0); 3196#L1194-1 assume !(1 == ~T9_E~0); 3335#L1199-1 assume !(1 == ~T10_E~0); 3281#L1204-1 assume !(1 == ~E_M~0); 3282#L1209-1 assume !(1 == ~E_1~0); 3808#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3809#L1219-1 assume !(1 == ~E_3~0); 4108#L1224-1 assume !(1 == ~E_4~0); 3607#L1229-1 assume !(1 == ~E_5~0); 3005#L1234-1 assume !(1 == ~E_6~0); 3006#L1239-1 assume !(1 == ~E_7~0); 3064#L1244-1 assume !(1 == ~E_8~0); 3065#L1249-1 assume !(1 == ~E_9~0); 3878#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2907#L1259-1 assume { :end_inline_reset_delta_events } true; 2908#L1565-2 [2022-02-21 04:22:59,355 INFO L793 eck$LassoCheckResult]: Loop: 2908#L1565-2 assume !false; 3816#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3300#L1011 assume !false; 3301#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3350#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3104#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3969#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3131#L866 assume !(0 != eval_~tmp~0#1); 3133#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3719#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3720#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3884#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4070#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3943#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3944#L1051-3 assume !(0 == ~T4_E~0); 3885#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3148#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3149#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3150#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4071#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2899#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2900#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2958#L1091-3 assume !(0 == ~E_1~0); 2959#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4037#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4038#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4067#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4028#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3735#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3736#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3959#L1131-3 assume !(0 == ~E_9~0); 3960#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4119#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3738#L514-36 assume !(1 == ~m_pc~0); 3475#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3325#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3326#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3781#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3207#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3208#L533-36 assume 1 == ~t1_pc~0; 3483#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3579#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3879#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3827#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3630#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3631#L552-36 assume 1 == ~t2_pc~0; 3200#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3202#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3021#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3022#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3174#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3175#L571-36 assume 1 == ~t3_pc~0; 3559#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3264#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3265#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3386#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3942#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3232#L590-36 assume !(1 == ~t4_pc~0); 3233#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3842#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3420#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3421#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3921#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3922#L609-36 assume 1 == ~t5_pc~0; 3797#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3632#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3450#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3451#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3704#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3530#L628-36 assume 1 == ~t6_pc~0; 3387#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3388#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3817#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3818#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3742#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3743#L647-36 assume 1 == ~t7_pc~0; 3671#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2928#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2929#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2948#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 2949#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3843#L666-36 assume 1 == ~t8_pc~0; 3128#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3129#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4032#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4033#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3291#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3292#L685-36 assume 1 == ~t9_pc~0; 3718#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3033#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3548#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3549#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3430#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3431#L704-36 assume !(1 == ~t10_pc~0); 3025#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3024#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3784#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3785#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3053#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3054#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4020#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3898#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3899#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4079#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3359#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3360#L1179-3 assume !(1 == ~T6_E~0); 3991#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2930#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2931#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3304#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3305#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3603#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2793#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2794#L1219-3 assume !(1 == ~E_3~0); 3792#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3793#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3812#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3066#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3067#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3646#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4029#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3795#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3796#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2874#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3619#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3620#L1584 assume !(0 == start_simulation_~tmp~3#1); 3750#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3080#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2775#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3222#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3223#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3406#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3374#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3375#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2908#L1565-2 [2022-02-21 04:22:59,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:59,356 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2022-02-21 04:22:59,356 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:59,356 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241985532] [2022-02-21 04:22:59,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:59,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:59,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:59,429 INFO L290 TraceCheckUtils]: 0: Hoare triple {6856#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {6856#true} is VALID [2022-02-21 04:22:59,430 INFO L290 TraceCheckUtils]: 1: Hoare triple {6856#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {6858#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:59,430 INFO L290 TraceCheckUtils]: 2: Hoare triple {6858#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6858#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:59,430 INFO L290 TraceCheckUtils]: 3: Hoare triple {6858#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6858#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:59,431 INFO L290 TraceCheckUtils]: 4: Hoare triple {6858#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {6858#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:59,431 INFO L290 TraceCheckUtils]: 5: Hoare triple {6858#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6858#(= ~t2_i~0 1)} is VALID [2022-02-21 04:22:59,431 INFO L290 TraceCheckUtils]: 6: Hoare triple {6858#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,431 INFO L290 TraceCheckUtils]: 7: Hoare triple {6857#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,431 INFO L290 TraceCheckUtils]: 8: Hoare triple {6857#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,431 INFO L290 TraceCheckUtils]: 9: Hoare triple {6857#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 10: Hoare triple {6857#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 11: Hoare triple {6857#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 12: Hoare triple {6857#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 13: Hoare triple {6857#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 14: Hoare triple {6857#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 15: Hoare triple {6857#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 16: Hoare triple {6857#false} assume !(0 == ~M_E~0); {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 17: Hoare triple {6857#false} assume !(0 == ~T1_E~0); {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 18: Hoare triple {6857#false} assume !(0 == ~T2_E~0); {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 19: Hoare triple {6857#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6857#false} is VALID [2022-02-21 04:22:59,432 INFO L290 TraceCheckUtils]: 20: Hoare triple {6857#false} assume !(0 == ~T4_E~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 21: Hoare triple {6857#false} assume !(0 == ~T5_E~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 22: Hoare triple {6857#false} assume !(0 == ~T6_E~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 23: Hoare triple {6857#false} assume !(0 == ~T7_E~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 24: Hoare triple {6857#false} assume !(0 == ~T8_E~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 25: Hoare triple {6857#false} assume !(0 == ~T9_E~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 26: Hoare triple {6857#false} assume !(0 == ~T10_E~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 27: Hoare triple {6857#false} assume 0 == ~E_M~0;~E_M~0 := 1; {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 28: Hoare triple {6857#false} assume !(0 == ~E_1~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 29: Hoare triple {6857#false} assume !(0 == ~E_2~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 30: Hoare triple {6857#false} assume !(0 == ~E_3~0); {6857#false} is VALID [2022-02-21 04:22:59,433 INFO L290 TraceCheckUtils]: 31: Hoare triple {6857#false} assume !(0 == ~E_4~0); {6857#false} is VALID [2022-02-21 04:22:59,434 INFO L290 TraceCheckUtils]: 32: Hoare triple {6857#false} assume !(0 == ~E_5~0); {6857#false} is VALID [2022-02-21 04:22:59,434 INFO L290 TraceCheckUtils]: 33: Hoare triple {6857#false} assume !(0 == ~E_6~0); {6857#false} is VALID [2022-02-21 04:22:59,434 INFO L290 TraceCheckUtils]: 34: Hoare triple {6857#false} assume !(0 == ~E_7~0); {6857#false} is VALID [2022-02-21 04:22:59,437 INFO L290 TraceCheckUtils]: 35: Hoare triple {6857#false} assume 0 == ~E_8~0;~E_8~0 := 1; {6857#false} is VALID [2022-02-21 04:22:59,437 INFO L290 TraceCheckUtils]: 36: Hoare triple {6857#false} assume !(0 == ~E_9~0); {6857#false} is VALID [2022-02-21 04:22:59,437 INFO L290 TraceCheckUtils]: 37: Hoare triple {6857#false} assume !(0 == ~E_10~0); {6857#false} is VALID [2022-02-21 04:22:59,437 INFO L290 TraceCheckUtils]: 38: Hoare triple {6857#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6857#false} is VALID [2022-02-21 04:22:59,437 INFO L290 TraceCheckUtils]: 39: Hoare triple {6857#false} assume 1 == ~m_pc~0; {6857#false} is VALID [2022-02-21 04:22:59,437 INFO L290 TraceCheckUtils]: 40: Hoare triple {6857#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {6857#false} is VALID [2022-02-21 04:22:59,437 INFO L290 TraceCheckUtils]: 41: Hoare triple {6857#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6857#false} is VALID [2022-02-21 04:22:59,438 INFO L290 TraceCheckUtils]: 42: Hoare triple {6857#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6857#false} is VALID [2022-02-21 04:22:59,438 INFO L290 TraceCheckUtils]: 43: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp~1#1); {6857#false} is VALID [2022-02-21 04:22:59,438 INFO L290 TraceCheckUtils]: 44: Hoare triple {6857#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6857#false} is VALID [2022-02-21 04:22:59,438 INFO L290 TraceCheckUtils]: 45: Hoare triple {6857#false} assume !(1 == ~t1_pc~0); {6857#false} is VALID [2022-02-21 04:22:59,438 INFO L290 TraceCheckUtils]: 46: Hoare triple {6857#false} is_transmit1_triggered_~__retres1~1#1 := 0; {6857#false} is VALID [2022-02-21 04:22:59,438 INFO L290 TraceCheckUtils]: 47: Hoare triple {6857#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6857#false} is VALID [2022-02-21 04:22:59,439 INFO L290 TraceCheckUtils]: 48: Hoare triple {6857#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6857#false} is VALID [2022-02-21 04:22:59,439 INFO L290 TraceCheckUtils]: 49: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___0~0#1); {6857#false} is VALID [2022-02-21 04:22:59,439 INFO L290 TraceCheckUtils]: 50: Hoare triple {6857#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6857#false} is VALID [2022-02-21 04:22:59,439 INFO L290 TraceCheckUtils]: 51: Hoare triple {6857#false} assume 1 == ~t2_pc~0; {6857#false} is VALID [2022-02-21 04:22:59,440 INFO L290 TraceCheckUtils]: 52: Hoare triple {6857#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6857#false} is VALID [2022-02-21 04:22:59,440 INFO L290 TraceCheckUtils]: 53: Hoare triple {6857#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6857#false} is VALID [2022-02-21 04:22:59,440 INFO L290 TraceCheckUtils]: 54: Hoare triple {6857#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6857#false} is VALID [2022-02-21 04:22:59,440 INFO L290 TraceCheckUtils]: 55: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___1~0#1); {6857#false} is VALID [2022-02-21 04:22:59,440 INFO L290 TraceCheckUtils]: 56: Hoare triple {6857#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6857#false} is VALID [2022-02-21 04:22:59,441 INFO L290 TraceCheckUtils]: 57: Hoare triple {6857#false} assume 1 == ~t3_pc~0; {6857#false} is VALID [2022-02-21 04:22:59,441 INFO L290 TraceCheckUtils]: 58: Hoare triple {6857#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6857#false} is VALID [2022-02-21 04:22:59,441 INFO L290 TraceCheckUtils]: 59: Hoare triple {6857#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6857#false} is VALID [2022-02-21 04:22:59,441 INFO L290 TraceCheckUtils]: 60: Hoare triple {6857#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {6857#false} is VALID [2022-02-21 04:22:59,441 INFO L290 TraceCheckUtils]: 61: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___2~0#1); {6857#false} is VALID [2022-02-21 04:22:59,441 INFO L290 TraceCheckUtils]: 62: Hoare triple {6857#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6857#false} is VALID [2022-02-21 04:22:59,442 INFO L290 TraceCheckUtils]: 63: Hoare triple {6857#false} assume !(1 == ~t4_pc~0); {6857#false} is VALID [2022-02-21 04:22:59,442 INFO L290 TraceCheckUtils]: 64: Hoare triple {6857#false} is_transmit4_triggered_~__retres1~4#1 := 0; {6857#false} is VALID [2022-02-21 04:22:59,442 INFO L290 TraceCheckUtils]: 65: Hoare triple {6857#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6857#false} is VALID [2022-02-21 04:22:59,442 INFO L290 TraceCheckUtils]: 66: Hoare triple {6857#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {6857#false} is VALID [2022-02-21 04:22:59,442 INFO L290 TraceCheckUtils]: 67: Hoare triple {6857#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6857#false} is VALID [2022-02-21 04:22:59,442 INFO L290 TraceCheckUtils]: 68: Hoare triple {6857#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6857#false} is VALID [2022-02-21 04:22:59,442 INFO L290 TraceCheckUtils]: 69: Hoare triple {6857#false} assume 1 == ~t5_pc~0; {6857#false} is VALID [2022-02-21 04:22:59,443 INFO L290 TraceCheckUtils]: 70: Hoare triple {6857#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {6857#false} is VALID [2022-02-21 04:22:59,443 INFO L290 TraceCheckUtils]: 71: Hoare triple {6857#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6857#false} is VALID [2022-02-21 04:22:59,443 INFO L290 TraceCheckUtils]: 72: Hoare triple {6857#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {6857#false} is VALID [2022-02-21 04:22:59,443 INFO L290 TraceCheckUtils]: 73: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___4~0#1); {6857#false} is VALID [2022-02-21 04:22:59,443 INFO L290 TraceCheckUtils]: 74: Hoare triple {6857#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6857#false} is VALID [2022-02-21 04:22:59,443 INFO L290 TraceCheckUtils]: 75: Hoare triple {6857#false} assume !(1 == ~t6_pc~0); {6857#false} is VALID [2022-02-21 04:22:59,443 INFO L290 TraceCheckUtils]: 76: Hoare triple {6857#false} is_transmit6_triggered_~__retres1~6#1 := 0; {6857#false} is VALID [2022-02-21 04:22:59,444 INFO L290 TraceCheckUtils]: 77: Hoare triple {6857#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6857#false} is VALID [2022-02-21 04:22:59,444 INFO L290 TraceCheckUtils]: 78: Hoare triple {6857#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {6857#false} is VALID [2022-02-21 04:22:59,444 INFO L290 TraceCheckUtils]: 79: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___5~0#1); {6857#false} is VALID [2022-02-21 04:22:59,444 INFO L290 TraceCheckUtils]: 80: Hoare triple {6857#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6857#false} is VALID [2022-02-21 04:22:59,444 INFO L290 TraceCheckUtils]: 81: Hoare triple {6857#false} assume 1 == ~t7_pc~0; {6857#false} is VALID [2022-02-21 04:22:59,444 INFO L290 TraceCheckUtils]: 82: Hoare triple {6857#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {6857#false} is VALID [2022-02-21 04:22:59,445 INFO L290 TraceCheckUtils]: 83: Hoare triple {6857#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6857#false} is VALID [2022-02-21 04:22:59,445 INFO L290 TraceCheckUtils]: 84: Hoare triple {6857#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {6857#false} is VALID [2022-02-21 04:22:59,445 INFO L290 TraceCheckUtils]: 85: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___6~0#1); {6857#false} is VALID [2022-02-21 04:22:59,445 INFO L290 TraceCheckUtils]: 86: Hoare triple {6857#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {6857#false} is VALID [2022-02-21 04:22:59,445 INFO L290 TraceCheckUtils]: 87: Hoare triple {6857#false} assume !(1 == ~t8_pc~0); {6857#false} is VALID [2022-02-21 04:22:59,445 INFO L290 TraceCheckUtils]: 88: Hoare triple {6857#false} is_transmit8_triggered_~__retres1~8#1 := 0; {6857#false} is VALID [2022-02-21 04:22:59,445 INFO L290 TraceCheckUtils]: 89: Hoare triple {6857#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {6857#false} is VALID [2022-02-21 04:22:59,448 INFO L290 TraceCheckUtils]: 90: Hoare triple {6857#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {6857#false} is VALID [2022-02-21 04:22:59,448 INFO L290 TraceCheckUtils]: 91: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___7~0#1); {6857#false} is VALID [2022-02-21 04:22:59,448 INFO L290 TraceCheckUtils]: 92: Hoare triple {6857#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {6857#false} is VALID [2022-02-21 04:22:59,448 INFO L290 TraceCheckUtils]: 93: Hoare triple {6857#false} assume 1 == ~t9_pc~0; {6857#false} is VALID [2022-02-21 04:22:59,448 INFO L290 TraceCheckUtils]: 94: Hoare triple {6857#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {6857#false} is VALID [2022-02-21 04:22:59,449 INFO L290 TraceCheckUtils]: 95: Hoare triple {6857#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {6857#false} is VALID [2022-02-21 04:22:59,449 INFO L290 TraceCheckUtils]: 96: Hoare triple {6857#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {6857#false} is VALID [2022-02-21 04:22:59,449 INFO L290 TraceCheckUtils]: 97: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___8~0#1); {6857#false} is VALID [2022-02-21 04:22:59,449 INFO L290 TraceCheckUtils]: 98: Hoare triple {6857#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {6857#false} is VALID [2022-02-21 04:22:59,449 INFO L290 TraceCheckUtils]: 99: Hoare triple {6857#false} assume !(1 == ~t10_pc~0); {6857#false} is VALID [2022-02-21 04:22:59,449 INFO L290 TraceCheckUtils]: 100: Hoare triple {6857#false} is_transmit10_triggered_~__retres1~10#1 := 0; {6857#false} is VALID [2022-02-21 04:22:59,449 INFO L290 TraceCheckUtils]: 101: Hoare triple {6857#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {6857#false} is VALID [2022-02-21 04:22:59,450 INFO L290 TraceCheckUtils]: 102: Hoare triple {6857#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {6857#false} is VALID [2022-02-21 04:22:59,450 INFO L290 TraceCheckUtils]: 103: Hoare triple {6857#false} assume !(0 != activate_threads_~tmp___9~0#1); {6857#false} is VALID [2022-02-21 04:22:59,450 INFO L290 TraceCheckUtils]: 104: Hoare triple {6857#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6857#false} is VALID [2022-02-21 04:22:59,450 INFO L290 TraceCheckUtils]: 105: Hoare triple {6857#false} assume !(1 == ~M_E~0); {6857#false} is VALID [2022-02-21 04:22:59,450 INFO L290 TraceCheckUtils]: 106: Hoare triple {6857#false} assume !(1 == ~T1_E~0); {6857#false} is VALID [2022-02-21 04:22:59,450 INFO L290 TraceCheckUtils]: 107: Hoare triple {6857#false} assume !(1 == ~T2_E~0); {6857#false} is VALID [2022-02-21 04:22:59,450 INFO L290 TraceCheckUtils]: 108: Hoare triple {6857#false} assume !(1 == ~T3_E~0); {6857#false} is VALID [2022-02-21 04:22:59,451 INFO L290 TraceCheckUtils]: 109: Hoare triple {6857#false} assume !(1 == ~T4_E~0); {6857#false} is VALID [2022-02-21 04:22:59,451 INFO L290 TraceCheckUtils]: 110: Hoare triple {6857#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,451 INFO L290 TraceCheckUtils]: 111: Hoare triple {6857#false} assume !(1 == ~T6_E~0); {6857#false} is VALID [2022-02-21 04:22:59,452 INFO L290 TraceCheckUtils]: 112: Hoare triple {6857#false} assume !(1 == ~T7_E~0); {6857#false} is VALID [2022-02-21 04:22:59,452 INFO L290 TraceCheckUtils]: 113: Hoare triple {6857#false} assume !(1 == ~T8_E~0); {6857#false} is VALID [2022-02-21 04:22:59,453 INFO L290 TraceCheckUtils]: 114: Hoare triple {6857#false} assume !(1 == ~T9_E~0); {6857#false} is VALID [2022-02-21 04:22:59,456 INFO L290 TraceCheckUtils]: 115: Hoare triple {6857#false} assume !(1 == ~T10_E~0); {6857#false} is VALID [2022-02-21 04:22:59,457 INFO L290 TraceCheckUtils]: 116: Hoare triple {6857#false} assume !(1 == ~E_M~0); {6857#false} is VALID [2022-02-21 04:22:59,457 INFO L290 TraceCheckUtils]: 117: Hoare triple {6857#false} assume !(1 == ~E_1~0); {6857#false} is VALID [2022-02-21 04:22:59,458 INFO L290 TraceCheckUtils]: 118: Hoare triple {6857#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,458 INFO L290 TraceCheckUtils]: 119: Hoare triple {6857#false} assume !(1 == ~E_3~0); {6857#false} is VALID [2022-02-21 04:22:59,459 INFO L290 TraceCheckUtils]: 120: Hoare triple {6857#false} assume !(1 == ~E_4~0); {6857#false} is VALID [2022-02-21 04:22:59,459 INFO L290 TraceCheckUtils]: 121: Hoare triple {6857#false} assume !(1 == ~E_5~0); {6857#false} is VALID [2022-02-21 04:22:59,459 INFO L290 TraceCheckUtils]: 122: Hoare triple {6857#false} assume !(1 == ~E_6~0); {6857#false} is VALID [2022-02-21 04:22:59,460 INFO L290 TraceCheckUtils]: 123: Hoare triple {6857#false} assume !(1 == ~E_7~0); {6857#false} is VALID [2022-02-21 04:22:59,460 INFO L290 TraceCheckUtils]: 124: Hoare triple {6857#false} assume !(1 == ~E_8~0); {6857#false} is VALID [2022-02-21 04:22:59,460 INFO L290 TraceCheckUtils]: 125: Hoare triple {6857#false} assume !(1 == ~E_9~0); {6857#false} is VALID [2022-02-21 04:22:59,461 INFO L290 TraceCheckUtils]: 126: Hoare triple {6857#false} assume 1 == ~E_10~0;~E_10~0 := 2; {6857#false} is VALID [2022-02-21 04:22:59,461 INFO L290 TraceCheckUtils]: 127: Hoare triple {6857#false} assume { :end_inline_reset_delta_events } true; {6857#false} is VALID [2022-02-21 04:22:59,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:59,463 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:59,463 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241985532] [2022-02-21 04:22:59,463 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241985532] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:59,463 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:59,463 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:59,464 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438674416] [2022-02-21 04:22:59,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:59,464 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:59,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:59,466 INFO L85 PathProgramCache]: Analyzing trace with hash 2100759252, now seen corresponding path program 1 times [2022-02-21 04:22:59,466 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:59,467 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67241803] [2022-02-21 04:22:59,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:59,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:59,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:59,565 INFO L290 TraceCheckUtils]: 0: Hoare triple {6859#true} assume !false; {6859#true} is VALID [2022-02-21 04:22:59,565 INFO L290 TraceCheckUtils]: 1: Hoare triple {6859#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6859#true} is VALID [2022-02-21 04:22:59,565 INFO L290 TraceCheckUtils]: 2: Hoare triple {6859#true} assume !false; {6859#true} is VALID [2022-02-21 04:22:59,565 INFO L290 TraceCheckUtils]: 3: Hoare triple {6859#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6859#true} is VALID [2022-02-21 04:22:59,565 INFO L290 TraceCheckUtils]: 4: Hoare triple {6859#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 5: Hoare triple {6859#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 6: Hoare triple {6859#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 7: Hoare triple {6859#true} assume !(0 != eval_~tmp~0#1); {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 8: Hoare triple {6859#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 9: Hoare triple {6859#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 10: Hoare triple {6859#true} assume 0 == ~M_E~0;~M_E~0 := 1; {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 11: Hoare triple {6859#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6859#true} is VALID [2022-02-21 04:22:59,566 INFO L290 TraceCheckUtils]: 12: Hoare triple {6859#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {6859#true} is VALID [2022-02-21 04:22:59,567 INFO L290 TraceCheckUtils]: 13: Hoare triple {6859#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6859#true} is VALID [2022-02-21 04:22:59,567 INFO L290 TraceCheckUtils]: 14: Hoare triple {6859#true} assume !(0 == ~T4_E~0); {6859#true} is VALID [2022-02-21 04:22:59,567 INFO L290 TraceCheckUtils]: 15: Hoare triple {6859#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {6859#true} is VALID [2022-02-21 04:22:59,567 INFO L290 TraceCheckUtils]: 16: Hoare triple {6859#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,568 INFO L290 TraceCheckUtils]: 17: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,568 INFO L290 TraceCheckUtils]: 18: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,568 INFO L290 TraceCheckUtils]: 19: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,568 INFO L290 TraceCheckUtils]: 20: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,569 INFO L290 TraceCheckUtils]: 21: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,569 INFO L290 TraceCheckUtils]: 22: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,569 INFO L290 TraceCheckUtils]: 23: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,570 INFO L290 TraceCheckUtils]: 24: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,570 INFO L290 TraceCheckUtils]: 25: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,570 INFO L290 TraceCheckUtils]: 26: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,570 INFO L290 TraceCheckUtils]: 27: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,571 INFO L290 TraceCheckUtils]: 28: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,571 INFO L290 TraceCheckUtils]: 29: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,571 INFO L290 TraceCheckUtils]: 30: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,571 INFO L290 TraceCheckUtils]: 31: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,572 INFO L290 TraceCheckUtils]: 32: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,572 INFO L290 TraceCheckUtils]: 33: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,572 INFO L290 TraceCheckUtils]: 34: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,573 INFO L290 TraceCheckUtils]: 35: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,573 INFO L290 TraceCheckUtils]: 36: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,573 INFO L290 TraceCheckUtils]: 37: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,573 INFO L290 TraceCheckUtils]: 38: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,574 INFO L290 TraceCheckUtils]: 39: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,574 INFO L290 TraceCheckUtils]: 40: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,574 INFO L290 TraceCheckUtils]: 41: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,575 INFO L290 TraceCheckUtils]: 42: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,575 INFO L290 TraceCheckUtils]: 43: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,575 INFO L290 TraceCheckUtils]: 44: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,575 INFO L290 TraceCheckUtils]: 45: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,576 INFO L290 TraceCheckUtils]: 46: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,576 INFO L290 TraceCheckUtils]: 47: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,576 INFO L290 TraceCheckUtils]: 48: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,577 INFO L290 TraceCheckUtils]: 49: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,577 INFO L290 TraceCheckUtils]: 50: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,577 INFO L290 TraceCheckUtils]: 51: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,577 INFO L290 TraceCheckUtils]: 52: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,578 INFO L290 TraceCheckUtils]: 53: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,578 INFO L290 TraceCheckUtils]: 54: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,578 INFO L290 TraceCheckUtils]: 55: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,579 INFO L290 TraceCheckUtils]: 56: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,579 INFO L290 TraceCheckUtils]: 57: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,579 INFO L290 TraceCheckUtils]: 58: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,579 INFO L290 TraceCheckUtils]: 59: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,580 INFO L290 TraceCheckUtils]: 60: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,580 INFO L290 TraceCheckUtils]: 61: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,580 INFO L290 TraceCheckUtils]: 62: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,581 INFO L290 TraceCheckUtils]: 63: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,581 INFO L290 TraceCheckUtils]: 64: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,581 INFO L290 TraceCheckUtils]: 65: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,581 INFO L290 TraceCheckUtils]: 66: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,582 INFO L290 TraceCheckUtils]: 67: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,582 INFO L290 TraceCheckUtils]: 68: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,582 INFO L290 TraceCheckUtils]: 69: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,583 INFO L290 TraceCheckUtils]: 70: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,583 INFO L290 TraceCheckUtils]: 71: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,583 INFO L290 TraceCheckUtils]: 72: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,583 INFO L290 TraceCheckUtils]: 73: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,584 INFO L290 TraceCheckUtils]: 74: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,584 INFO L290 TraceCheckUtils]: 75: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,584 INFO L290 TraceCheckUtils]: 76: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,585 INFO L290 TraceCheckUtils]: 77: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,585 INFO L290 TraceCheckUtils]: 78: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,585 INFO L290 TraceCheckUtils]: 79: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,585 INFO L290 TraceCheckUtils]: 80: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,586 INFO L290 TraceCheckUtils]: 81: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,586 INFO L290 TraceCheckUtils]: 82: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,586 INFO L290 TraceCheckUtils]: 83: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,587 INFO L290 TraceCheckUtils]: 84: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,587 INFO L290 TraceCheckUtils]: 85: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,587 INFO L290 TraceCheckUtils]: 86: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,587 INFO L290 TraceCheckUtils]: 87: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,588 INFO L290 TraceCheckUtils]: 88: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,588 INFO L290 TraceCheckUtils]: 89: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,588 INFO L290 TraceCheckUtils]: 90: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,589 INFO L290 TraceCheckUtils]: 91: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,589 INFO L290 TraceCheckUtils]: 92: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,589 INFO L290 TraceCheckUtils]: 93: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t10_pc~0); {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,589 INFO L290 TraceCheckUtils]: 94: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,590 INFO L290 TraceCheckUtils]: 95: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,590 INFO L290 TraceCheckUtils]: 96: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,590 INFO L290 TraceCheckUtils]: 97: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,591 INFO L290 TraceCheckUtils]: 98: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,591 INFO L290 TraceCheckUtils]: 99: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,591 INFO L290 TraceCheckUtils]: 100: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,591 INFO L290 TraceCheckUtils]: 101: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,592 INFO L290 TraceCheckUtils]: 102: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,592 INFO L290 TraceCheckUtils]: 103: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,592 INFO L290 TraceCheckUtils]: 104: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6861#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:22:59,593 INFO L290 TraceCheckUtils]: 105: Hoare triple {6861#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {6860#false} is VALID [2022-02-21 04:22:59,593 INFO L290 TraceCheckUtils]: 106: Hoare triple {6860#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,593 INFO L290 TraceCheckUtils]: 107: Hoare triple {6860#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,593 INFO L290 TraceCheckUtils]: 108: Hoare triple {6860#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,593 INFO L290 TraceCheckUtils]: 109: Hoare triple {6860#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,593 INFO L290 TraceCheckUtils]: 110: Hoare triple {6860#false} assume 1 == ~E_M~0;~E_M~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,593 INFO L290 TraceCheckUtils]: 111: Hoare triple {6860#false} assume 1 == ~E_1~0;~E_1~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,594 INFO L290 TraceCheckUtils]: 112: Hoare triple {6860#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,594 INFO L290 TraceCheckUtils]: 113: Hoare triple {6860#false} assume !(1 == ~E_3~0); {6860#false} is VALID [2022-02-21 04:22:59,594 INFO L290 TraceCheckUtils]: 114: Hoare triple {6860#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,594 INFO L290 TraceCheckUtils]: 115: Hoare triple {6860#false} assume 1 == ~E_5~0;~E_5~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,594 INFO L290 TraceCheckUtils]: 116: Hoare triple {6860#false} assume 1 == ~E_6~0;~E_6~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,594 INFO L290 TraceCheckUtils]: 117: Hoare triple {6860#false} assume 1 == ~E_7~0;~E_7~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,594 INFO L290 TraceCheckUtils]: 118: Hoare triple {6860#false} assume 1 == ~E_8~0;~E_8~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,595 INFO L290 TraceCheckUtils]: 119: Hoare triple {6860#false} assume 1 == ~E_9~0;~E_9~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,595 INFO L290 TraceCheckUtils]: 120: Hoare triple {6860#false} assume 1 == ~E_10~0;~E_10~0 := 2; {6860#false} is VALID [2022-02-21 04:22:59,595 INFO L290 TraceCheckUtils]: 121: Hoare triple {6860#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6860#false} is VALID [2022-02-21 04:22:59,595 INFO L290 TraceCheckUtils]: 122: Hoare triple {6860#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6860#false} is VALID [2022-02-21 04:22:59,595 INFO L290 TraceCheckUtils]: 123: Hoare triple {6860#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6860#false} is VALID [2022-02-21 04:22:59,595 INFO L290 TraceCheckUtils]: 124: Hoare triple {6860#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {6860#false} is VALID [2022-02-21 04:22:59,595 INFO L290 TraceCheckUtils]: 125: Hoare triple {6860#false} assume !(0 == start_simulation_~tmp~3#1); {6860#false} is VALID [2022-02-21 04:22:59,596 INFO L290 TraceCheckUtils]: 126: Hoare triple {6860#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6860#false} is VALID [2022-02-21 04:22:59,596 INFO L290 TraceCheckUtils]: 127: Hoare triple {6860#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6860#false} is VALID [2022-02-21 04:22:59,596 INFO L290 TraceCheckUtils]: 128: Hoare triple {6860#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6860#false} is VALID [2022-02-21 04:22:59,596 INFO L290 TraceCheckUtils]: 129: Hoare triple {6860#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {6860#false} is VALID [2022-02-21 04:22:59,596 INFO L290 TraceCheckUtils]: 130: Hoare triple {6860#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6860#false} is VALID [2022-02-21 04:22:59,596 INFO L290 TraceCheckUtils]: 131: Hoare triple {6860#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6860#false} is VALID [2022-02-21 04:22:59,596 INFO L290 TraceCheckUtils]: 132: Hoare triple {6860#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {6860#false} is VALID [2022-02-21 04:22:59,597 INFO L290 TraceCheckUtils]: 133: Hoare triple {6860#false} assume !(0 != start_simulation_~tmp___0~1#1); {6860#false} is VALID [2022-02-21 04:22:59,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:59,598 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:59,598 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67241803] [2022-02-21 04:22:59,598 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [67241803] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:59,598 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:59,598 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:59,598 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17997307] [2022-02-21 04:22:59,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:59,599 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:59,599 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:59,600 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:59,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:59,600 INFO L87 Difference]: Start difference. First operand 1366 states and 2032 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:00,537 INFO L93 Difference]: Finished difference Result 1366 states and 2031 transitions. [2022-02-21 04:23:00,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:00,538 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,613 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:00,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:00,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2031 transitions. [2022-02-21 04:23:00,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:00,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:00,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:00,707 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2022-02-21 04:23:00,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:00,729 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:00,732 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2031 transitions. Second operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,734 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2031 transitions. Second operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,736 INFO L87 Difference]: Start difference. First operand 1366 states and 2031 transitions. Second operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:00,780 INFO L93 Difference]: Finished difference Result 1366 states and 2031 transitions. [2022-02-21 04:23:00,780 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,783 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:00,783 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:00,786 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,788 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:00,832 INFO L93 Difference]: Finished difference Result 1366 states and 2031 transitions. [2022-02-21 04:23:00,832 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,834 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:00,834 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:00,834 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:00,834 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:00,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2031 transitions. [2022-02-21 04:23:00,884 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2022-02-21 04:23:00,884 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2022-02-21 04:23:00,884 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:00,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2031 transitions. [2022-02-21 04:23:00,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:00,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:00,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:00,890 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,890 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,890 INFO L791 eck$LassoCheckResult]: Stem: 9285#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 9286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9494#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8277#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8278#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9518#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9477#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9478#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9508#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8586#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8587#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8692#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8937#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8868#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8588#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8250#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8251#L1036 assume !(0 == ~M_E~0); 8349#L1036-2 assume !(0 == ~T1_E~0); 9225#L1041-1 assume !(0 == ~T2_E~0); 9226#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8624#L1051-1 assume !(0 == ~T4_E~0); 8625#L1056-1 assume !(0 == ~T5_E~0); 9363#L1061-1 assume !(0 == ~T6_E~0); 8522#L1066-1 assume !(0 == ~T7_E~0); 8523#L1071-1 assume !(0 == ~T8_E~0); 9346#L1076-1 assume !(0 == ~T9_E~0); 8417#L1081-1 assume !(0 == ~T10_E~0); 8418#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8821#L1091-1 assume !(0 == ~E_1~0); 9522#L1096-1 assume !(0 == ~E_2~0); 9523#L1101-1 assume !(0 == ~E_3~0); 8882#L1106-1 assume !(0 == ~E_4~0); 8883#L1111-1 assume !(0 == ~E_5~0); 9039#L1116-1 assume !(0 == ~E_6~0); 9040#L1121-1 assume !(0 == ~E_7~0); 8875#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8876#L1131-1 assume !(0 == ~E_9~0); 9126#L1136-1 assume !(0 == ~E_10~0); 9233#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9390#L514 assume 1 == ~m_pc~0; 9353#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8895#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8812#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8813#L1285 assume !(0 != activate_threads_~tmp~1#1); 9558#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8541#L533 assume !(1 == ~t1_pc~0); 8542#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9055#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8928#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8929#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9255#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9256#L552 assume 1 == ~t2_pc~0; 8766#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8767#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9334#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9335#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8907#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8908#L571 assume 1 == ~t3_pc~0; 9085#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9086#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8455#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8456#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9045#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8331#L590 assume !(1 == ~t4_pc~0); 8332#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9098#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9330#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9331#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9287#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9041#L609 assume 1 == ~t5_pc~0; 9042#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9556#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8368#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8369#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9036#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9037#L628 assume !(1 == ~t6_pc~0); 8970#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8969#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9541#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9542#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9326#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9327#L647 assume 1 == ~t7_pc~0; 8884#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8885#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9161#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8887#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8888#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9588#L666 assume !(1 == ~t8_pc~0); 8671#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8672#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8906#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9062#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8818#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8819#L685 assume 1 == ~t9_pc~0; 9565#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9462#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9454#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8844#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8845#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9197#L704 assume !(1 == ~t10_pc~0); 8836#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8835#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9361#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8387#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8388#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8635#L1154 assume !(1 == ~M_E~0); 9314#L1154-2 assume !(1 == ~T1_E~0); 8607#L1159-1 assume !(1 == ~T2_E~0); 8608#L1164-1 assume !(1 == ~T3_E~0); 9060#L1169-1 assume !(1 == ~T4_E~0); 8932#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8737#L1179-1 assume !(1 == ~T6_E~0); 8593#L1184-1 assume !(1 == ~T7_E~0); 8594#L1189-1 assume !(1 == ~T8_E~0); 8669#L1194-1 assume !(1 == ~T9_E~0); 8808#L1199-1 assume !(1 == ~T10_E~0); 8752#L1204-1 assume !(1 == ~E_M~0); 8753#L1209-1 assume !(1 == ~E_1~0); 9279#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9280#L1219-1 assume !(1 == ~E_3~0); 9581#L1224-1 assume !(1 == ~E_4~0); 9080#L1229-1 assume !(1 == ~E_5~0); 8478#L1234-1 assume !(1 == ~E_6~0); 8479#L1239-1 assume !(1 == ~E_7~0); 8537#L1244-1 assume !(1 == ~E_8~0); 8538#L1249-1 assume !(1 == ~E_9~0); 9351#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8380#L1259-1 assume { :end_inline_reset_delta_events } true; 8381#L1565-2 [2022-02-21 04:23:00,891 INFO L793 eck$LassoCheckResult]: Loop: 8381#L1565-2 assume !false; 9289#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8773#L1011 assume !false; 8774#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8823#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8577#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9442#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8601#L866 assume !(0 != eval_~tmp~0#1); 8603#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9190#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9191#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9357#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9543#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9416#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9417#L1051-3 assume !(0 == ~T4_E~0); 9358#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8621#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8622#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8623#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9544#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8372#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8373#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8427#L1091-3 assume !(0 == ~E_1~0); 8428#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9510#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9511#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9540#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9501#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9207#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9208#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9432#L1131-3 assume !(0 == ~E_9~0); 9433#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9592#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9211#L514-36 assume !(1 == ~m_pc~0); 8948#L514-38 is_master_triggered_~__retres1~0#1 := 0; 8796#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8797#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9254#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8680#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8681#L533-36 assume 1 == ~t1_pc~0; 8956#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9049#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9352#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9300#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9103#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9104#L552-36 assume 1 == ~t2_pc~0; 8673#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8675#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8494#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8495#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8647#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8648#L571-36 assume 1 == ~t3_pc~0; 9032#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8738#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8739#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8859#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9415#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8708#L590-36 assume !(1 == ~t4_pc~0); 8709#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 9315#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8893#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8894#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9394#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9395#L609-36 assume 1 == ~t5_pc~0; 9270#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9105#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8923#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8924#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9177#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9003#L628-36 assume !(1 == ~t6_pc~0); 8864#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 8863#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9290#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9291#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9215#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9216#L647-36 assume 1 == ~t7_pc~0; 9144#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8401#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8402#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8421#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 8422#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9316#L666-36 assume 1 == ~t8_pc~0; 8604#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8605#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9505#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9506#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8764#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8765#L685-36 assume !(1 == ~t9_pc~0); 8505#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 8506#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9021#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9022#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8903#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8904#L704-36 assume 1 == ~t10_pc~0; 8496#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8497#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9257#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9258#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8526#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8527#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9493#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9371#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9372#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9552#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8832#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8833#L1179-3 assume !(1 == ~T6_E~0); 9464#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8403#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8404#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8779#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8780#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9076#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8266#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8267#L1219-3 assume !(1 == ~E_3~0); 9265#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9266#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9288#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8539#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8540#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9123#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9502#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9268#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9269#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8347#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9094#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9095#L1584 assume !(0 == start_simulation_~tmp~3#1); 9223#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8553#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8248#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8695#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8696#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8880#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8847#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 8848#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8381#L1565-2 [2022-02-21 04:23:00,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:00,891 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2022-02-21 04:23:00,892 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:00,892 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825496488] [2022-02-21 04:23:00,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:00,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:00,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:00,931 INFO L290 TraceCheckUtils]: 0: Hoare triple {12329#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {12329#true} is VALID [2022-02-21 04:23:00,932 INFO L290 TraceCheckUtils]: 1: Hoare triple {12329#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {12331#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:00,932 INFO L290 TraceCheckUtils]: 2: Hoare triple {12331#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {12331#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:00,933 INFO L290 TraceCheckUtils]: 3: Hoare triple {12331#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {12331#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:00,933 INFO L290 TraceCheckUtils]: 4: Hoare triple {12331#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {12331#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:00,933 INFO L290 TraceCheckUtils]: 5: Hoare triple {12331#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {12331#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:00,934 INFO L290 TraceCheckUtils]: 6: Hoare triple {12331#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {12331#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:00,934 INFO L290 TraceCheckUtils]: 7: Hoare triple {12331#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,934 INFO L290 TraceCheckUtils]: 8: Hoare triple {12330#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,934 INFO L290 TraceCheckUtils]: 9: Hoare triple {12330#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,934 INFO L290 TraceCheckUtils]: 10: Hoare triple {12330#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,934 INFO L290 TraceCheckUtils]: 11: Hoare triple {12330#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,934 INFO L290 TraceCheckUtils]: 12: Hoare triple {12330#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,935 INFO L290 TraceCheckUtils]: 13: Hoare triple {12330#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {12330#false} is VALID [2022-02-21 04:23:00,935 INFO L290 TraceCheckUtils]: 14: Hoare triple {12330#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,935 INFO L290 TraceCheckUtils]: 15: Hoare triple {12330#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {12330#false} is VALID [2022-02-21 04:23:00,935 INFO L290 TraceCheckUtils]: 16: Hoare triple {12330#false} assume !(0 == ~M_E~0); {12330#false} is VALID [2022-02-21 04:23:00,935 INFO L290 TraceCheckUtils]: 17: Hoare triple {12330#false} assume !(0 == ~T1_E~0); {12330#false} is VALID [2022-02-21 04:23:00,935 INFO L290 TraceCheckUtils]: 18: Hoare triple {12330#false} assume !(0 == ~T2_E~0); {12330#false} is VALID [2022-02-21 04:23:00,935 INFO L290 TraceCheckUtils]: 19: Hoare triple {12330#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 20: Hoare triple {12330#false} assume !(0 == ~T4_E~0); {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 21: Hoare triple {12330#false} assume !(0 == ~T5_E~0); {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 22: Hoare triple {12330#false} assume !(0 == ~T6_E~0); {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 23: Hoare triple {12330#false} assume !(0 == ~T7_E~0); {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 24: Hoare triple {12330#false} assume !(0 == ~T8_E~0); {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 25: Hoare triple {12330#false} assume !(0 == ~T9_E~0); {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 26: Hoare triple {12330#false} assume !(0 == ~T10_E~0); {12330#false} is VALID [2022-02-21 04:23:00,936 INFO L290 TraceCheckUtils]: 27: Hoare triple {12330#false} assume 0 == ~E_M~0;~E_M~0 := 1; {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 28: Hoare triple {12330#false} assume !(0 == ~E_1~0); {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 29: Hoare triple {12330#false} assume !(0 == ~E_2~0); {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 30: Hoare triple {12330#false} assume !(0 == ~E_3~0); {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 31: Hoare triple {12330#false} assume !(0 == ~E_4~0); {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 32: Hoare triple {12330#false} assume !(0 == ~E_5~0); {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 33: Hoare triple {12330#false} assume !(0 == ~E_6~0); {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 34: Hoare triple {12330#false} assume !(0 == ~E_7~0); {12330#false} is VALID [2022-02-21 04:23:00,937 INFO L290 TraceCheckUtils]: 35: Hoare triple {12330#false} assume 0 == ~E_8~0;~E_8~0 := 1; {12330#false} is VALID [2022-02-21 04:23:00,938 INFO L290 TraceCheckUtils]: 36: Hoare triple {12330#false} assume !(0 == ~E_9~0); {12330#false} is VALID [2022-02-21 04:23:00,938 INFO L290 TraceCheckUtils]: 37: Hoare triple {12330#false} assume !(0 == ~E_10~0); {12330#false} is VALID [2022-02-21 04:23:00,938 INFO L290 TraceCheckUtils]: 38: Hoare triple {12330#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12330#false} is VALID [2022-02-21 04:23:00,938 INFO L290 TraceCheckUtils]: 39: Hoare triple {12330#false} assume 1 == ~m_pc~0; {12330#false} is VALID [2022-02-21 04:23:00,938 INFO L290 TraceCheckUtils]: 40: Hoare triple {12330#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {12330#false} is VALID [2022-02-21 04:23:00,938 INFO L290 TraceCheckUtils]: 41: Hoare triple {12330#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12330#false} is VALID [2022-02-21 04:23:00,938 INFO L290 TraceCheckUtils]: 42: Hoare triple {12330#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 43: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp~1#1); {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 44: Hoare triple {12330#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 45: Hoare triple {12330#false} assume !(1 == ~t1_pc~0); {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 46: Hoare triple {12330#false} is_transmit1_triggered_~__retres1~1#1 := 0; {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 47: Hoare triple {12330#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 48: Hoare triple {12330#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 49: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___0~0#1); {12330#false} is VALID [2022-02-21 04:23:00,939 INFO L290 TraceCheckUtils]: 50: Hoare triple {12330#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 51: Hoare triple {12330#false} assume 1 == ~t2_pc~0; {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 52: Hoare triple {12330#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 53: Hoare triple {12330#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 54: Hoare triple {12330#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 55: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___1~0#1); {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 56: Hoare triple {12330#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 57: Hoare triple {12330#false} assume 1 == ~t3_pc~0; {12330#false} is VALID [2022-02-21 04:23:00,940 INFO L290 TraceCheckUtils]: 58: Hoare triple {12330#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 59: Hoare triple {12330#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 60: Hoare triple {12330#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 61: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___2~0#1); {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 62: Hoare triple {12330#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 63: Hoare triple {12330#false} assume !(1 == ~t4_pc~0); {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 64: Hoare triple {12330#false} is_transmit4_triggered_~__retres1~4#1 := 0; {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 65: Hoare triple {12330#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12330#false} is VALID [2022-02-21 04:23:00,941 INFO L290 TraceCheckUtils]: 66: Hoare triple {12330#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12330#false} is VALID [2022-02-21 04:23:00,942 INFO L290 TraceCheckUtils]: 67: Hoare triple {12330#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {12330#false} is VALID [2022-02-21 04:23:00,942 INFO L290 TraceCheckUtils]: 68: Hoare triple {12330#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12330#false} is VALID [2022-02-21 04:23:00,942 INFO L290 TraceCheckUtils]: 69: Hoare triple {12330#false} assume 1 == ~t5_pc~0; {12330#false} is VALID [2022-02-21 04:23:00,942 INFO L290 TraceCheckUtils]: 70: Hoare triple {12330#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {12330#false} is VALID [2022-02-21 04:23:00,942 INFO L290 TraceCheckUtils]: 71: Hoare triple {12330#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12330#false} is VALID [2022-02-21 04:23:00,942 INFO L290 TraceCheckUtils]: 72: Hoare triple {12330#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {12330#false} is VALID [2022-02-21 04:23:00,942 INFO L290 TraceCheckUtils]: 73: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___4~0#1); {12330#false} is VALID [2022-02-21 04:23:00,943 INFO L290 TraceCheckUtils]: 74: Hoare triple {12330#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12330#false} is VALID [2022-02-21 04:23:00,943 INFO L290 TraceCheckUtils]: 75: Hoare triple {12330#false} assume !(1 == ~t6_pc~0); {12330#false} is VALID [2022-02-21 04:23:00,943 INFO L290 TraceCheckUtils]: 76: Hoare triple {12330#false} is_transmit6_triggered_~__retres1~6#1 := 0; {12330#false} is VALID [2022-02-21 04:23:00,943 INFO L290 TraceCheckUtils]: 77: Hoare triple {12330#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12330#false} is VALID [2022-02-21 04:23:00,943 INFO L290 TraceCheckUtils]: 78: Hoare triple {12330#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {12330#false} is VALID [2022-02-21 04:23:00,944 INFO L290 TraceCheckUtils]: 79: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___5~0#1); {12330#false} is VALID [2022-02-21 04:23:00,945 INFO L290 TraceCheckUtils]: 80: Hoare triple {12330#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12330#false} is VALID [2022-02-21 04:23:00,945 INFO L290 TraceCheckUtils]: 81: Hoare triple {12330#false} assume 1 == ~t7_pc~0; {12330#false} is VALID [2022-02-21 04:23:00,945 INFO L290 TraceCheckUtils]: 82: Hoare triple {12330#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {12330#false} is VALID [2022-02-21 04:23:00,945 INFO L290 TraceCheckUtils]: 83: Hoare triple {12330#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12330#false} is VALID [2022-02-21 04:23:00,945 INFO L290 TraceCheckUtils]: 84: Hoare triple {12330#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {12330#false} is VALID [2022-02-21 04:23:00,945 INFO L290 TraceCheckUtils]: 85: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___6~0#1); {12330#false} is VALID [2022-02-21 04:23:00,945 INFO L290 TraceCheckUtils]: 86: Hoare triple {12330#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 87: Hoare triple {12330#false} assume !(1 == ~t8_pc~0); {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 88: Hoare triple {12330#false} is_transmit8_triggered_~__retres1~8#1 := 0; {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 89: Hoare triple {12330#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 90: Hoare triple {12330#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 91: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___7~0#1); {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 92: Hoare triple {12330#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 93: Hoare triple {12330#false} assume 1 == ~t9_pc~0; {12330#false} is VALID [2022-02-21 04:23:00,946 INFO L290 TraceCheckUtils]: 94: Hoare triple {12330#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {12330#false} is VALID [2022-02-21 04:23:00,947 INFO L290 TraceCheckUtils]: 95: Hoare triple {12330#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {12330#false} is VALID [2022-02-21 04:23:00,947 INFO L290 TraceCheckUtils]: 96: Hoare triple {12330#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {12330#false} is VALID [2022-02-21 04:23:00,947 INFO L290 TraceCheckUtils]: 97: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___8~0#1); {12330#false} is VALID [2022-02-21 04:23:00,947 INFO L290 TraceCheckUtils]: 98: Hoare triple {12330#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {12330#false} is VALID [2022-02-21 04:23:00,947 INFO L290 TraceCheckUtils]: 99: Hoare triple {12330#false} assume !(1 == ~t10_pc~0); {12330#false} is VALID [2022-02-21 04:23:00,947 INFO L290 TraceCheckUtils]: 100: Hoare triple {12330#false} is_transmit10_triggered_~__retres1~10#1 := 0; {12330#false} is VALID [2022-02-21 04:23:00,947 INFO L290 TraceCheckUtils]: 101: Hoare triple {12330#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 102: Hoare triple {12330#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 103: Hoare triple {12330#false} assume !(0 != activate_threads_~tmp___9~0#1); {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 104: Hoare triple {12330#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 105: Hoare triple {12330#false} assume !(1 == ~M_E~0); {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 106: Hoare triple {12330#false} assume !(1 == ~T1_E~0); {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 107: Hoare triple {12330#false} assume !(1 == ~T2_E~0); {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 108: Hoare triple {12330#false} assume !(1 == ~T3_E~0); {12330#false} is VALID [2022-02-21 04:23:00,948 INFO L290 TraceCheckUtils]: 109: Hoare triple {12330#false} assume !(1 == ~T4_E~0); {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 110: Hoare triple {12330#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 111: Hoare triple {12330#false} assume !(1 == ~T6_E~0); {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 112: Hoare triple {12330#false} assume !(1 == ~T7_E~0); {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 113: Hoare triple {12330#false} assume !(1 == ~T8_E~0); {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 114: Hoare triple {12330#false} assume !(1 == ~T9_E~0); {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 115: Hoare triple {12330#false} assume !(1 == ~T10_E~0); {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 116: Hoare triple {12330#false} assume !(1 == ~E_M~0); {12330#false} is VALID [2022-02-21 04:23:00,949 INFO L290 TraceCheckUtils]: 117: Hoare triple {12330#false} assume !(1 == ~E_1~0); {12330#false} is VALID [2022-02-21 04:23:00,950 INFO L290 TraceCheckUtils]: 118: Hoare triple {12330#false} assume 1 == ~E_2~0;~E_2~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,950 INFO L290 TraceCheckUtils]: 119: Hoare triple {12330#false} assume !(1 == ~E_3~0); {12330#false} is VALID [2022-02-21 04:23:00,950 INFO L290 TraceCheckUtils]: 120: Hoare triple {12330#false} assume !(1 == ~E_4~0); {12330#false} is VALID [2022-02-21 04:23:00,950 INFO L290 TraceCheckUtils]: 121: Hoare triple {12330#false} assume !(1 == ~E_5~0); {12330#false} is VALID [2022-02-21 04:23:00,950 INFO L290 TraceCheckUtils]: 122: Hoare triple {12330#false} assume !(1 == ~E_6~0); {12330#false} is VALID [2022-02-21 04:23:00,950 INFO L290 TraceCheckUtils]: 123: Hoare triple {12330#false} assume !(1 == ~E_7~0); {12330#false} is VALID [2022-02-21 04:23:00,950 INFO L290 TraceCheckUtils]: 124: Hoare triple {12330#false} assume !(1 == ~E_8~0); {12330#false} is VALID [2022-02-21 04:23:00,951 INFO L290 TraceCheckUtils]: 125: Hoare triple {12330#false} assume !(1 == ~E_9~0); {12330#false} is VALID [2022-02-21 04:23:00,951 INFO L290 TraceCheckUtils]: 126: Hoare triple {12330#false} assume 1 == ~E_10~0;~E_10~0 := 2; {12330#false} is VALID [2022-02-21 04:23:00,951 INFO L290 TraceCheckUtils]: 127: Hoare triple {12330#false} assume { :end_inline_reset_delta_events } true; {12330#false} is VALID [2022-02-21 04:23:00,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:00,954 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:00,954 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825496488] [2022-02-21 04:23:00,954 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825496488] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:00,954 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:00,954 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:00,954 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654368959] [2022-02-21 04:23:00,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:00,955 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:00,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:00,955 INFO L85 PathProgramCache]: Analyzing trace with hash 1070134613, now seen corresponding path program 1 times [2022-02-21 04:23:00,956 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:00,956 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094411953] [2022-02-21 04:23:00,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:00,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:00,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:01,041 INFO L290 TraceCheckUtils]: 0: Hoare triple {12332#true} assume !false; {12332#true} is VALID [2022-02-21 04:23:01,041 INFO L290 TraceCheckUtils]: 1: Hoare triple {12332#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {12332#true} is VALID [2022-02-21 04:23:01,041 INFO L290 TraceCheckUtils]: 2: Hoare triple {12332#true} assume !false; {12332#true} is VALID [2022-02-21 04:23:01,041 INFO L290 TraceCheckUtils]: 3: Hoare triple {12332#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {12332#true} is VALID [2022-02-21 04:23:01,041 INFO L290 TraceCheckUtils]: 4: Hoare triple {12332#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {12332#true} is VALID [2022-02-21 04:23:01,041 INFO L290 TraceCheckUtils]: 5: Hoare triple {12332#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {12332#true} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 6: Hoare triple {12332#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {12332#true} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 7: Hoare triple {12332#true} assume !(0 != eval_~tmp~0#1); {12332#true} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 8: Hoare triple {12332#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {12332#true} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 9: Hoare triple {12332#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {12332#true} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 10: Hoare triple {12332#true} assume 0 == ~M_E~0;~M_E~0 := 1; {12332#true} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 11: Hoare triple {12332#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {12332#true} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 12: Hoare triple {12332#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {12332#true} is VALID [2022-02-21 04:23:01,043 INFO L290 TraceCheckUtils]: 13: Hoare triple {12332#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {12332#true} is VALID [2022-02-21 04:23:01,043 INFO L290 TraceCheckUtils]: 14: Hoare triple {12332#true} assume !(0 == ~T4_E~0); {12332#true} is VALID [2022-02-21 04:23:01,043 INFO L290 TraceCheckUtils]: 15: Hoare triple {12332#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {12332#true} is VALID [2022-02-21 04:23:01,043 INFO L290 TraceCheckUtils]: 16: Hoare triple {12332#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,044 INFO L290 TraceCheckUtils]: 17: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,044 INFO L290 TraceCheckUtils]: 18: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,044 INFO L290 TraceCheckUtils]: 19: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,044 INFO L290 TraceCheckUtils]: 20: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,045 INFO L290 TraceCheckUtils]: 21: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,045 INFO L290 TraceCheckUtils]: 22: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,045 INFO L290 TraceCheckUtils]: 23: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,046 INFO L290 TraceCheckUtils]: 24: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,046 INFO L290 TraceCheckUtils]: 25: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,046 INFO L290 TraceCheckUtils]: 26: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,047 INFO L290 TraceCheckUtils]: 27: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,047 INFO L290 TraceCheckUtils]: 28: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,047 INFO L290 TraceCheckUtils]: 29: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,047 INFO L290 TraceCheckUtils]: 30: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,048 INFO L290 TraceCheckUtils]: 31: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,048 INFO L290 TraceCheckUtils]: 32: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,048 INFO L290 TraceCheckUtils]: 33: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 34: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 35: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 36: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 37: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 38: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 39: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,053 INFO L290 TraceCheckUtils]: 40: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,053 INFO L290 TraceCheckUtils]: 41: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,053 INFO L290 TraceCheckUtils]: 42: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,054 INFO L290 TraceCheckUtils]: 43: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,054 INFO L290 TraceCheckUtils]: 44: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,054 INFO L290 TraceCheckUtils]: 45: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,055 INFO L290 TraceCheckUtils]: 46: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,055 INFO L290 TraceCheckUtils]: 47: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,055 INFO L290 TraceCheckUtils]: 48: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,055 INFO L290 TraceCheckUtils]: 49: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,056 INFO L290 TraceCheckUtils]: 50: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,056 INFO L290 TraceCheckUtils]: 51: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,056 INFO L290 TraceCheckUtils]: 52: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,057 INFO L290 TraceCheckUtils]: 53: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,057 INFO L290 TraceCheckUtils]: 54: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,057 INFO L290 TraceCheckUtils]: 55: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,057 INFO L290 TraceCheckUtils]: 56: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,058 INFO L290 TraceCheckUtils]: 57: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,058 INFO L290 TraceCheckUtils]: 58: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,058 INFO L290 TraceCheckUtils]: 59: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,059 INFO L290 TraceCheckUtils]: 60: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,059 INFO L290 TraceCheckUtils]: 61: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,059 INFO L290 TraceCheckUtils]: 62: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,072 INFO L290 TraceCheckUtils]: 63: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,083 INFO L290 TraceCheckUtils]: 64: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,084 INFO L290 TraceCheckUtils]: 65: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,084 INFO L290 TraceCheckUtils]: 66: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,084 INFO L290 TraceCheckUtils]: 67: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,085 INFO L290 TraceCheckUtils]: 68: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,085 INFO L290 TraceCheckUtils]: 69: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,085 INFO L290 TraceCheckUtils]: 70: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,086 INFO L290 TraceCheckUtils]: 71: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,086 INFO L290 TraceCheckUtils]: 72: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,086 INFO L290 TraceCheckUtils]: 73: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,087 INFO L290 TraceCheckUtils]: 74: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,087 INFO L290 TraceCheckUtils]: 75: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,087 INFO L290 TraceCheckUtils]: 76: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,087 INFO L290 TraceCheckUtils]: 77: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,088 INFO L290 TraceCheckUtils]: 78: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,088 INFO L290 TraceCheckUtils]: 79: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,088 INFO L290 TraceCheckUtils]: 80: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,089 INFO L290 TraceCheckUtils]: 81: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,089 INFO L290 TraceCheckUtils]: 82: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,089 INFO L290 TraceCheckUtils]: 83: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,089 INFO L290 TraceCheckUtils]: 84: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,090 INFO L290 TraceCheckUtils]: 85: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,090 INFO L290 TraceCheckUtils]: 86: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,090 INFO L290 TraceCheckUtils]: 87: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,091 INFO L290 TraceCheckUtils]: 88: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,091 INFO L290 TraceCheckUtils]: 89: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,091 INFO L290 TraceCheckUtils]: 90: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,091 INFO L290 TraceCheckUtils]: 91: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,092 INFO L290 TraceCheckUtils]: 92: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,092 INFO L290 TraceCheckUtils]: 93: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,092 INFO L290 TraceCheckUtils]: 94: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,093 INFO L290 TraceCheckUtils]: 95: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,093 INFO L290 TraceCheckUtils]: 96: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,093 INFO L290 TraceCheckUtils]: 97: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,094 INFO L290 TraceCheckUtils]: 98: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,094 INFO L290 TraceCheckUtils]: 99: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,094 INFO L290 TraceCheckUtils]: 100: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,095 INFO L290 TraceCheckUtils]: 101: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,095 INFO L290 TraceCheckUtils]: 102: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,095 INFO L290 TraceCheckUtils]: 103: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,095 INFO L290 TraceCheckUtils]: 104: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {12334#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:01,096 INFO L290 TraceCheckUtils]: 105: Hoare triple {12334#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {12333#false} is VALID [2022-02-21 04:23:01,096 INFO L290 TraceCheckUtils]: 106: Hoare triple {12333#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,096 INFO L290 TraceCheckUtils]: 107: Hoare triple {12333#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,096 INFO L290 TraceCheckUtils]: 108: Hoare triple {12333#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,096 INFO L290 TraceCheckUtils]: 109: Hoare triple {12333#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,096 INFO L290 TraceCheckUtils]: 110: Hoare triple {12333#false} assume 1 == ~E_M~0;~E_M~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,097 INFO L290 TraceCheckUtils]: 111: Hoare triple {12333#false} assume 1 == ~E_1~0;~E_1~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,097 INFO L290 TraceCheckUtils]: 112: Hoare triple {12333#false} assume 1 == ~E_2~0;~E_2~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,097 INFO L290 TraceCheckUtils]: 113: Hoare triple {12333#false} assume !(1 == ~E_3~0); {12333#false} is VALID [2022-02-21 04:23:01,097 INFO L290 TraceCheckUtils]: 114: Hoare triple {12333#false} assume 1 == ~E_4~0;~E_4~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,097 INFO L290 TraceCheckUtils]: 115: Hoare triple {12333#false} assume 1 == ~E_5~0;~E_5~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,097 INFO L290 TraceCheckUtils]: 116: Hoare triple {12333#false} assume 1 == ~E_6~0;~E_6~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,097 INFO L290 TraceCheckUtils]: 117: Hoare triple {12333#false} assume 1 == ~E_7~0;~E_7~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 118: Hoare triple {12333#false} assume 1 == ~E_8~0;~E_8~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 119: Hoare triple {12333#false} assume 1 == ~E_9~0;~E_9~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 120: Hoare triple {12333#false} assume 1 == ~E_10~0;~E_10~0 := 2; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 121: Hoare triple {12333#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 122: Hoare triple {12333#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 123: Hoare triple {12333#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 124: Hoare triple {12333#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {12333#false} is VALID [2022-02-21 04:23:01,098 INFO L290 TraceCheckUtils]: 125: Hoare triple {12333#false} assume !(0 == start_simulation_~tmp~3#1); {12333#false} is VALID [2022-02-21 04:23:01,099 INFO L290 TraceCheckUtils]: 126: Hoare triple {12333#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {12333#false} is VALID [2022-02-21 04:23:01,099 INFO L290 TraceCheckUtils]: 127: Hoare triple {12333#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {12333#false} is VALID [2022-02-21 04:23:01,099 INFO L290 TraceCheckUtils]: 128: Hoare triple {12333#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {12333#false} is VALID [2022-02-21 04:23:01,099 INFO L290 TraceCheckUtils]: 129: Hoare triple {12333#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {12333#false} is VALID [2022-02-21 04:23:01,099 INFO L290 TraceCheckUtils]: 130: Hoare triple {12333#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {12333#false} is VALID [2022-02-21 04:23:01,099 INFO L290 TraceCheckUtils]: 131: Hoare triple {12333#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {12333#false} is VALID [2022-02-21 04:23:01,099 INFO L290 TraceCheckUtils]: 132: Hoare triple {12333#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {12333#false} is VALID [2022-02-21 04:23:01,100 INFO L290 TraceCheckUtils]: 133: Hoare triple {12333#false} assume !(0 != start_simulation_~tmp___0~1#1); {12333#false} is VALID [2022-02-21 04:23:01,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:01,101 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:01,101 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094411953] [2022-02-21 04:23:01,101 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094411953] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:01,102 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:01,102 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:01,102 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045613045] [2022-02-21 04:23:01,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:01,102 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:01,103 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:01,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:01,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:01,104 INFO L87 Difference]: Start difference. First operand 1366 states and 2031 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,136 INFO L93 Difference]: Finished difference Result 1366 states and 2030 transitions. [2022-02-21 04:23:02,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:02,137 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,223 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:02,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:02,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2030 transitions. [2022-02-21 04:23:02,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:02,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:02,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:02,343 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2022-02-21 04:23:02,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:02,358 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:02,362 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2030 transitions. Second operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,365 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2030 transitions. Second operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,380 INFO L87 Difference]: Start difference. First operand 1366 states and 2030 transitions. Second operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,451 INFO L93 Difference]: Finished difference Result 1366 states and 2030 transitions. [2022-02-21 04:23:02,451 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,453 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:02,453 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:02,457 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,460 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,528 INFO L93 Difference]: Finished difference Result 1366 states and 2030 transitions. [2022-02-21 04:23:02,528 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,530 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:02,530 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:02,530 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:02,530 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:02,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2030 transitions. [2022-02-21 04:23:02,577 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2022-02-21 04:23:02,577 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2022-02-21 04:23:02,577 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:02,577 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2030 transitions. [2022-02-21 04:23:02,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:02,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:02,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:02,583 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,583 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,583 INFO L791 eck$LassoCheckResult]: Stem: 14758#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14967#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13750#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13751#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 14991#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14950#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14951#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14981#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14059#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14060#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14165#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14410#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14341#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14061#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13723#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13724#L1036 assume !(0 == ~M_E~0); 13822#L1036-2 assume !(0 == ~T1_E~0); 14698#L1041-1 assume !(0 == ~T2_E~0); 14699#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14097#L1051-1 assume !(0 == ~T4_E~0); 14098#L1056-1 assume !(0 == ~T5_E~0); 14836#L1061-1 assume !(0 == ~T6_E~0); 13995#L1066-1 assume !(0 == ~T7_E~0); 13996#L1071-1 assume !(0 == ~T8_E~0); 14819#L1076-1 assume !(0 == ~T9_E~0); 13890#L1081-1 assume !(0 == ~T10_E~0); 13891#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14294#L1091-1 assume !(0 == ~E_1~0); 14995#L1096-1 assume !(0 == ~E_2~0); 14996#L1101-1 assume !(0 == ~E_3~0); 14355#L1106-1 assume !(0 == ~E_4~0); 14356#L1111-1 assume !(0 == ~E_5~0); 14512#L1116-1 assume !(0 == ~E_6~0); 14513#L1121-1 assume !(0 == ~E_7~0); 14348#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14349#L1131-1 assume !(0 == ~E_9~0); 14599#L1136-1 assume !(0 == ~E_10~0); 14706#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14863#L514 assume 1 == ~m_pc~0; 14826#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14368#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14285#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14286#L1285 assume !(0 != activate_threads_~tmp~1#1); 15031#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14014#L533 assume !(1 == ~t1_pc~0); 14015#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14528#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14401#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14402#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14728#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14729#L552 assume 1 == ~t2_pc~0; 14239#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14240#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14807#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14808#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14380#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14381#L571 assume 1 == ~t3_pc~0; 14558#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14559#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13928#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13929#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14518#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13804#L590 assume !(1 == ~t4_pc~0); 13805#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14571#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14803#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14804#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14760#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L609 assume 1 == ~t5_pc~0; 14515#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15029#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13841#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13842#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14509#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14510#L628 assume !(1 == ~t6_pc~0); 14443#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14442#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15014#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15015#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14799#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14800#L647 assume 1 == ~t7_pc~0; 14357#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14358#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14634#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14360#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14361#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15061#L666 assume !(1 == ~t8_pc~0); 14144#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14145#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14379#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14535#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14291#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14292#L685 assume 1 == ~t9_pc~0; 15038#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14935#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14927#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14317#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14318#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14670#L704 assume !(1 == ~t10_pc~0); 14309#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14308#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14834#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13860#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13861#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14108#L1154 assume !(1 == ~M_E~0); 14787#L1154-2 assume !(1 == ~T1_E~0); 14080#L1159-1 assume !(1 == ~T2_E~0); 14081#L1164-1 assume !(1 == ~T3_E~0); 14533#L1169-1 assume !(1 == ~T4_E~0); 14405#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14210#L1179-1 assume !(1 == ~T6_E~0); 14066#L1184-1 assume !(1 == ~T7_E~0); 14067#L1189-1 assume !(1 == ~T8_E~0); 14142#L1194-1 assume !(1 == ~T9_E~0); 14281#L1199-1 assume !(1 == ~T10_E~0); 14225#L1204-1 assume !(1 == ~E_M~0); 14226#L1209-1 assume !(1 == ~E_1~0); 14752#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14753#L1219-1 assume !(1 == ~E_3~0); 15054#L1224-1 assume !(1 == ~E_4~0); 14553#L1229-1 assume !(1 == ~E_5~0); 13951#L1234-1 assume !(1 == ~E_6~0); 13952#L1239-1 assume !(1 == ~E_7~0); 14010#L1244-1 assume !(1 == ~E_8~0); 14011#L1249-1 assume !(1 == ~E_9~0); 14824#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13853#L1259-1 assume { :end_inline_reset_delta_events } true; 13854#L1565-2 [2022-02-21 04:23:02,583 INFO L793 eck$LassoCheckResult]: Loop: 13854#L1565-2 assume !false; 14762#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14246#L1011 assume !false; 14247#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14296#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14050#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14915#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14074#L866 assume !(0 != eval_~tmp~0#1); 14076#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14663#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14664#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14830#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15016#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14889#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14890#L1051-3 assume !(0 == ~T4_E~0); 14831#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14094#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14095#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14096#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15017#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13845#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13846#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13900#L1091-3 assume !(0 == ~E_1~0); 13901#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14983#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14984#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15013#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14974#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14680#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14681#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14905#L1131-3 assume !(0 == ~E_9~0); 14906#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15065#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14684#L514-36 assume !(1 == ~m_pc~0); 14421#L514-38 is_master_triggered_~__retres1~0#1 := 0; 14269#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14270#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14727#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14153#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14154#L533-36 assume 1 == ~t1_pc~0; 14429#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14522#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14825#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14773#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14576#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14577#L552-36 assume 1 == ~t2_pc~0; 14146#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14148#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13967#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13968#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14120#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14121#L571-36 assume 1 == ~t3_pc~0; 14505#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14211#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14212#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14332#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14888#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14181#L590-36 assume !(1 == ~t4_pc~0); 14182#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 14788#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14366#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14367#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14867#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14868#L609-36 assume 1 == ~t5_pc~0; 14743#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14578#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14396#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14397#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14650#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14476#L628-36 assume !(1 == ~t6_pc~0); 14337#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 14336#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14763#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14764#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14688#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14689#L647-36 assume 1 == ~t7_pc~0; 14617#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13874#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13875#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13894#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 13895#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14789#L666-36 assume 1 == ~t8_pc~0; 14077#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14078#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14978#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14979#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14237#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14238#L685-36 assume !(1 == ~t9_pc~0); 13978#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 13979#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14494#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14495#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14376#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14377#L704-36 assume 1 == ~t10_pc~0; 13969#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13970#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14730#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14731#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13999#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14000#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14966#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14844#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14845#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15025#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14305#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14306#L1179-3 assume !(1 == ~T6_E~0); 14937#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13876#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13877#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14252#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14253#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14549#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13739#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13740#L1219-3 assume !(1 == ~E_3~0); 14738#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14739#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14761#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14012#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14013#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14596#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14975#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14741#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14742#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13820#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14567#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14568#L1584 assume !(0 == start_simulation_~tmp~3#1); 14696#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14026#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13721#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14168#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14169#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14353#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14320#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14321#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13854#L1565-2 [2022-02-21 04:23:02,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,585 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2022-02-21 04:23:02,586 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,586 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880498572] [2022-02-21 04:23:02,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:02,633 INFO L290 TraceCheckUtils]: 0: Hoare triple {17802#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {17802#true} is VALID [2022-02-21 04:23:02,634 INFO L290 TraceCheckUtils]: 1: Hoare triple {17802#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {17804#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:02,634 INFO L290 TraceCheckUtils]: 2: Hoare triple {17804#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17804#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:02,634 INFO L290 TraceCheckUtils]: 3: Hoare triple {17804#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17804#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:02,635 INFO L290 TraceCheckUtils]: 4: Hoare triple {17804#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {17804#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:02,635 INFO L290 TraceCheckUtils]: 5: Hoare triple {17804#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17804#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:02,636 INFO L290 TraceCheckUtils]: 6: Hoare triple {17804#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17804#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:02,636 INFO L290 TraceCheckUtils]: 7: Hoare triple {17804#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {17804#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 8: Hoare triple {17804#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 9: Hoare triple {17803#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 10: Hoare triple {17803#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 11: Hoare triple {17803#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 12: Hoare triple {17803#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 13: Hoare triple {17803#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {17803#false} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 14: Hoare triple {17803#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 15: Hoare triple {17803#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17803#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 16: Hoare triple {17803#false} assume !(0 == ~M_E~0); {17803#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 17: Hoare triple {17803#false} assume !(0 == ~T1_E~0); {17803#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 18: Hoare triple {17803#false} assume !(0 == ~T2_E~0); {17803#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 19: Hoare triple {17803#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17803#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 20: Hoare triple {17803#false} assume !(0 == ~T4_E~0); {17803#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 21: Hoare triple {17803#false} assume !(0 == ~T5_E~0); {17803#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 22: Hoare triple {17803#false} assume !(0 == ~T6_E~0); {17803#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 23: Hoare triple {17803#false} assume !(0 == ~T7_E~0); {17803#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 24: Hoare triple {17803#false} assume !(0 == ~T8_E~0); {17803#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 25: Hoare triple {17803#false} assume !(0 == ~T9_E~0); {17803#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 26: Hoare triple {17803#false} assume !(0 == ~T10_E~0); {17803#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 27: Hoare triple {17803#false} assume 0 == ~E_M~0;~E_M~0 := 1; {17803#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 28: Hoare triple {17803#false} assume !(0 == ~E_1~0); {17803#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 29: Hoare triple {17803#false} assume !(0 == ~E_2~0); {17803#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 30: Hoare triple {17803#false} assume !(0 == ~E_3~0); {17803#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 31: Hoare triple {17803#false} assume !(0 == ~E_4~0); {17803#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 32: Hoare triple {17803#false} assume !(0 == ~E_5~0); {17803#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 33: Hoare triple {17803#false} assume !(0 == ~E_6~0); {17803#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 34: Hoare triple {17803#false} assume !(0 == ~E_7~0); {17803#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 35: Hoare triple {17803#false} assume 0 == ~E_8~0;~E_8~0 := 1; {17803#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 36: Hoare triple {17803#false} assume !(0 == ~E_9~0); {17803#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 37: Hoare triple {17803#false} assume !(0 == ~E_10~0); {17803#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 38: Hoare triple {17803#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17803#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 39: Hoare triple {17803#false} assume 1 == ~m_pc~0; {17803#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 40: Hoare triple {17803#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {17803#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 41: Hoare triple {17803#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 42: Hoare triple {17803#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 43: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp~1#1); {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 44: Hoare triple {17803#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 45: Hoare triple {17803#false} assume !(1 == ~t1_pc~0); {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 46: Hoare triple {17803#false} is_transmit1_triggered_~__retres1~1#1 := 0; {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 47: Hoare triple {17803#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 48: Hoare triple {17803#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17803#false} is VALID [2022-02-21 04:23:02,642 INFO L290 TraceCheckUtils]: 49: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___0~0#1); {17803#false} is VALID [2022-02-21 04:23:02,643 INFO L290 TraceCheckUtils]: 50: Hoare triple {17803#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17803#false} is VALID [2022-02-21 04:23:02,643 INFO L290 TraceCheckUtils]: 51: Hoare triple {17803#false} assume 1 == ~t2_pc~0; {17803#false} is VALID [2022-02-21 04:23:02,643 INFO L290 TraceCheckUtils]: 52: Hoare triple {17803#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17803#false} is VALID [2022-02-21 04:23:02,643 INFO L290 TraceCheckUtils]: 53: Hoare triple {17803#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17803#false} is VALID [2022-02-21 04:23:02,643 INFO L290 TraceCheckUtils]: 54: Hoare triple {17803#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17803#false} is VALID [2022-02-21 04:23:02,643 INFO L290 TraceCheckUtils]: 55: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___1~0#1); {17803#false} is VALID [2022-02-21 04:23:02,643 INFO L290 TraceCheckUtils]: 56: Hoare triple {17803#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 57: Hoare triple {17803#false} assume 1 == ~t3_pc~0; {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 58: Hoare triple {17803#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 59: Hoare triple {17803#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 60: Hoare triple {17803#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 61: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___2~0#1); {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 62: Hoare triple {17803#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 63: Hoare triple {17803#false} assume !(1 == ~t4_pc~0); {17803#false} is VALID [2022-02-21 04:23:02,644 INFO L290 TraceCheckUtils]: 64: Hoare triple {17803#false} is_transmit4_triggered_~__retres1~4#1 := 0; {17803#false} is VALID [2022-02-21 04:23:02,645 INFO L290 TraceCheckUtils]: 65: Hoare triple {17803#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17803#false} is VALID [2022-02-21 04:23:02,645 INFO L290 TraceCheckUtils]: 66: Hoare triple {17803#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17803#false} is VALID [2022-02-21 04:23:02,645 INFO L290 TraceCheckUtils]: 67: Hoare triple {17803#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17803#false} is VALID [2022-02-21 04:23:02,645 INFO L290 TraceCheckUtils]: 68: Hoare triple {17803#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17803#false} is VALID [2022-02-21 04:23:02,645 INFO L290 TraceCheckUtils]: 69: Hoare triple {17803#false} assume 1 == ~t5_pc~0; {17803#false} is VALID [2022-02-21 04:23:02,645 INFO L290 TraceCheckUtils]: 70: Hoare triple {17803#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17803#false} is VALID [2022-02-21 04:23:02,646 INFO L290 TraceCheckUtils]: 71: Hoare triple {17803#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17803#false} is VALID [2022-02-21 04:23:02,646 INFO L290 TraceCheckUtils]: 72: Hoare triple {17803#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17803#false} is VALID [2022-02-21 04:23:02,646 INFO L290 TraceCheckUtils]: 73: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___4~0#1); {17803#false} is VALID [2022-02-21 04:23:02,646 INFO L290 TraceCheckUtils]: 74: Hoare triple {17803#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17803#false} is VALID [2022-02-21 04:23:02,646 INFO L290 TraceCheckUtils]: 75: Hoare triple {17803#false} assume !(1 == ~t6_pc~0); {17803#false} is VALID [2022-02-21 04:23:02,646 INFO L290 TraceCheckUtils]: 76: Hoare triple {17803#false} is_transmit6_triggered_~__retres1~6#1 := 0; {17803#false} is VALID [2022-02-21 04:23:02,646 INFO L290 TraceCheckUtils]: 77: Hoare triple {17803#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 78: Hoare triple {17803#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 79: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___5~0#1); {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 80: Hoare triple {17803#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 81: Hoare triple {17803#false} assume 1 == ~t7_pc~0; {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 82: Hoare triple {17803#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 83: Hoare triple {17803#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 84: Hoare triple {17803#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17803#false} is VALID [2022-02-21 04:23:02,647 INFO L290 TraceCheckUtils]: 85: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___6~0#1); {17803#false} is VALID [2022-02-21 04:23:02,648 INFO L290 TraceCheckUtils]: 86: Hoare triple {17803#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17803#false} is VALID [2022-02-21 04:23:02,648 INFO L290 TraceCheckUtils]: 87: Hoare triple {17803#false} assume !(1 == ~t8_pc~0); {17803#false} is VALID [2022-02-21 04:23:02,648 INFO L290 TraceCheckUtils]: 88: Hoare triple {17803#false} is_transmit8_triggered_~__retres1~8#1 := 0; {17803#false} is VALID [2022-02-21 04:23:02,648 INFO L290 TraceCheckUtils]: 89: Hoare triple {17803#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17803#false} is VALID [2022-02-21 04:23:02,648 INFO L290 TraceCheckUtils]: 90: Hoare triple {17803#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17803#false} is VALID [2022-02-21 04:23:02,648 INFO L290 TraceCheckUtils]: 91: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___7~0#1); {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 92: Hoare triple {17803#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 93: Hoare triple {17803#false} assume 1 == ~t9_pc~0; {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 94: Hoare triple {17803#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 95: Hoare triple {17803#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 96: Hoare triple {17803#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 97: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___8~0#1); {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 98: Hoare triple {17803#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17803#false} is VALID [2022-02-21 04:23:02,649 INFO L290 TraceCheckUtils]: 99: Hoare triple {17803#false} assume !(1 == ~t10_pc~0); {17803#false} is VALID [2022-02-21 04:23:02,650 INFO L290 TraceCheckUtils]: 100: Hoare triple {17803#false} is_transmit10_triggered_~__retres1~10#1 := 0; {17803#false} is VALID [2022-02-21 04:23:02,650 INFO L290 TraceCheckUtils]: 101: Hoare triple {17803#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17803#false} is VALID [2022-02-21 04:23:02,650 INFO L290 TraceCheckUtils]: 102: Hoare triple {17803#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {17803#false} is VALID [2022-02-21 04:23:02,650 INFO L290 TraceCheckUtils]: 103: Hoare triple {17803#false} assume !(0 != activate_threads_~tmp___9~0#1); {17803#false} is VALID [2022-02-21 04:23:02,650 INFO L290 TraceCheckUtils]: 104: Hoare triple {17803#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17803#false} is VALID [2022-02-21 04:23:02,650 INFO L290 TraceCheckUtils]: 105: Hoare triple {17803#false} assume !(1 == ~M_E~0); {17803#false} is VALID [2022-02-21 04:23:02,650 INFO L290 TraceCheckUtils]: 106: Hoare triple {17803#false} assume !(1 == ~T1_E~0); {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 107: Hoare triple {17803#false} assume !(1 == ~T2_E~0); {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 108: Hoare triple {17803#false} assume !(1 == ~T3_E~0); {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 109: Hoare triple {17803#false} assume !(1 == ~T4_E~0); {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 110: Hoare triple {17803#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 111: Hoare triple {17803#false} assume !(1 == ~T6_E~0); {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 112: Hoare triple {17803#false} assume !(1 == ~T7_E~0); {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 113: Hoare triple {17803#false} assume !(1 == ~T8_E~0); {17803#false} is VALID [2022-02-21 04:23:02,651 INFO L290 TraceCheckUtils]: 114: Hoare triple {17803#false} assume !(1 == ~T9_E~0); {17803#false} is VALID [2022-02-21 04:23:02,652 INFO L290 TraceCheckUtils]: 115: Hoare triple {17803#false} assume !(1 == ~T10_E~0); {17803#false} is VALID [2022-02-21 04:23:02,652 INFO L290 TraceCheckUtils]: 116: Hoare triple {17803#false} assume !(1 == ~E_M~0); {17803#false} is VALID [2022-02-21 04:23:02,652 INFO L290 TraceCheckUtils]: 117: Hoare triple {17803#false} assume !(1 == ~E_1~0); {17803#false} is VALID [2022-02-21 04:23:02,652 INFO L290 TraceCheckUtils]: 118: Hoare triple {17803#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,652 INFO L290 TraceCheckUtils]: 119: Hoare triple {17803#false} assume !(1 == ~E_3~0); {17803#false} is VALID [2022-02-21 04:23:02,652 INFO L290 TraceCheckUtils]: 120: Hoare triple {17803#false} assume !(1 == ~E_4~0); {17803#false} is VALID [2022-02-21 04:23:02,652 INFO L290 TraceCheckUtils]: 121: Hoare triple {17803#false} assume !(1 == ~E_5~0); {17803#false} is VALID [2022-02-21 04:23:02,653 INFO L290 TraceCheckUtils]: 122: Hoare triple {17803#false} assume !(1 == ~E_6~0); {17803#false} is VALID [2022-02-21 04:23:02,653 INFO L290 TraceCheckUtils]: 123: Hoare triple {17803#false} assume !(1 == ~E_7~0); {17803#false} is VALID [2022-02-21 04:23:02,653 INFO L290 TraceCheckUtils]: 124: Hoare triple {17803#false} assume !(1 == ~E_8~0); {17803#false} is VALID [2022-02-21 04:23:02,653 INFO L290 TraceCheckUtils]: 125: Hoare triple {17803#false} assume !(1 == ~E_9~0); {17803#false} is VALID [2022-02-21 04:23:02,653 INFO L290 TraceCheckUtils]: 126: Hoare triple {17803#false} assume 1 == ~E_10~0;~E_10~0 := 2; {17803#false} is VALID [2022-02-21 04:23:02,653 INFO L290 TraceCheckUtils]: 127: Hoare triple {17803#false} assume { :end_inline_reset_delta_events } true; {17803#false} is VALID [2022-02-21 04:23:02,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:02,654 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:02,654 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880498572] [2022-02-21 04:23:02,655 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880498572] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:02,655 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:02,655 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:02,655 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145518165] [2022-02-21 04:23:02,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:02,656 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:02,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1070134613, now seen corresponding path program 2 times [2022-02-21 04:23:02,656 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,659 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329683168] [2022-02-21 04:23:02,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:02,695 INFO L290 TraceCheckUtils]: 0: Hoare triple {17805#true} assume !false; {17805#true} is VALID [2022-02-21 04:23:02,695 INFO L290 TraceCheckUtils]: 1: Hoare triple {17805#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17805#true} is VALID [2022-02-21 04:23:02,695 INFO L290 TraceCheckUtils]: 2: Hoare triple {17805#true} assume !false; {17805#true} is VALID [2022-02-21 04:23:02,695 INFO L290 TraceCheckUtils]: 3: Hoare triple {17805#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {17805#true} is VALID [2022-02-21 04:23:02,695 INFO L290 TraceCheckUtils]: 4: Hoare triple {17805#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {17805#true} is VALID [2022-02-21 04:23:02,696 INFO L290 TraceCheckUtils]: 5: Hoare triple {17805#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {17805#true} is VALID [2022-02-21 04:23:02,696 INFO L290 TraceCheckUtils]: 6: Hoare triple {17805#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {17805#true} is VALID [2022-02-21 04:23:02,696 INFO L290 TraceCheckUtils]: 7: Hoare triple {17805#true} assume !(0 != eval_~tmp~0#1); {17805#true} is VALID [2022-02-21 04:23:02,696 INFO L290 TraceCheckUtils]: 8: Hoare triple {17805#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17805#true} is VALID [2022-02-21 04:23:02,696 INFO L290 TraceCheckUtils]: 9: Hoare triple {17805#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17805#true} is VALID [2022-02-21 04:23:02,696 INFO L290 TraceCheckUtils]: 10: Hoare triple {17805#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17805#true} is VALID [2022-02-21 04:23:02,696 INFO L290 TraceCheckUtils]: 11: Hoare triple {17805#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {17805#true} is VALID [2022-02-21 04:23:02,697 INFO L290 TraceCheckUtils]: 12: Hoare triple {17805#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17805#true} is VALID [2022-02-21 04:23:02,697 INFO L290 TraceCheckUtils]: 13: Hoare triple {17805#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17805#true} is VALID [2022-02-21 04:23:02,697 INFO L290 TraceCheckUtils]: 14: Hoare triple {17805#true} assume !(0 == ~T4_E~0); {17805#true} is VALID [2022-02-21 04:23:02,697 INFO L290 TraceCheckUtils]: 15: Hoare triple {17805#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17805#true} is VALID [2022-02-21 04:23:02,697 INFO L290 TraceCheckUtils]: 16: Hoare triple {17805#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,698 INFO L290 TraceCheckUtils]: 17: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,698 INFO L290 TraceCheckUtils]: 18: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,698 INFO L290 TraceCheckUtils]: 19: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,698 INFO L290 TraceCheckUtils]: 20: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,699 INFO L290 TraceCheckUtils]: 21: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,699 INFO L290 TraceCheckUtils]: 22: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,699 INFO L290 TraceCheckUtils]: 23: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,700 INFO L290 TraceCheckUtils]: 24: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,700 INFO L290 TraceCheckUtils]: 25: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,700 INFO L290 TraceCheckUtils]: 26: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,700 INFO L290 TraceCheckUtils]: 27: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,701 INFO L290 TraceCheckUtils]: 28: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,701 INFO L290 TraceCheckUtils]: 29: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,701 INFO L290 TraceCheckUtils]: 30: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,702 INFO L290 TraceCheckUtils]: 31: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,702 INFO L290 TraceCheckUtils]: 32: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,702 INFO L290 TraceCheckUtils]: 33: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,702 INFO L290 TraceCheckUtils]: 34: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,703 INFO L290 TraceCheckUtils]: 35: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,703 INFO L290 TraceCheckUtils]: 36: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,703 INFO L290 TraceCheckUtils]: 37: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,704 INFO L290 TraceCheckUtils]: 38: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,704 INFO L290 TraceCheckUtils]: 39: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,704 INFO L290 TraceCheckUtils]: 40: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,705 INFO L290 TraceCheckUtils]: 41: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,705 INFO L290 TraceCheckUtils]: 42: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,705 INFO L290 TraceCheckUtils]: 43: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,705 INFO L290 TraceCheckUtils]: 44: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,706 INFO L290 TraceCheckUtils]: 45: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,706 INFO L290 TraceCheckUtils]: 46: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,706 INFO L290 TraceCheckUtils]: 47: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,707 INFO L290 TraceCheckUtils]: 48: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,707 INFO L290 TraceCheckUtils]: 49: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,707 INFO L290 TraceCheckUtils]: 50: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,707 INFO L290 TraceCheckUtils]: 51: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,708 INFO L290 TraceCheckUtils]: 52: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,708 INFO L290 TraceCheckUtils]: 53: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,708 INFO L290 TraceCheckUtils]: 54: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,709 INFO L290 TraceCheckUtils]: 55: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,709 INFO L290 TraceCheckUtils]: 56: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,709 INFO L290 TraceCheckUtils]: 57: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,709 INFO L290 TraceCheckUtils]: 58: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,710 INFO L290 TraceCheckUtils]: 59: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,710 INFO L290 TraceCheckUtils]: 60: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,710 INFO L290 TraceCheckUtils]: 61: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,711 INFO L290 TraceCheckUtils]: 62: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,711 INFO L290 TraceCheckUtils]: 63: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,711 INFO L290 TraceCheckUtils]: 64: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,711 INFO L290 TraceCheckUtils]: 65: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,712 INFO L290 TraceCheckUtils]: 66: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,712 INFO L290 TraceCheckUtils]: 67: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,712 INFO L290 TraceCheckUtils]: 68: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,713 INFO L290 TraceCheckUtils]: 69: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,713 INFO L290 TraceCheckUtils]: 70: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,713 INFO L290 TraceCheckUtils]: 71: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,713 INFO L290 TraceCheckUtils]: 72: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,714 INFO L290 TraceCheckUtils]: 73: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,714 INFO L290 TraceCheckUtils]: 74: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,714 INFO L290 TraceCheckUtils]: 75: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,715 INFO L290 TraceCheckUtils]: 76: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,715 INFO L290 TraceCheckUtils]: 77: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,715 INFO L290 TraceCheckUtils]: 78: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,715 INFO L290 TraceCheckUtils]: 79: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,716 INFO L290 TraceCheckUtils]: 80: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,716 INFO L290 TraceCheckUtils]: 81: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,716 INFO L290 TraceCheckUtils]: 82: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,717 INFO L290 TraceCheckUtils]: 83: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,717 INFO L290 TraceCheckUtils]: 84: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,717 INFO L290 TraceCheckUtils]: 85: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,717 INFO L290 TraceCheckUtils]: 86: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,718 INFO L290 TraceCheckUtils]: 87: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,718 INFO L290 TraceCheckUtils]: 88: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,718 INFO L290 TraceCheckUtils]: 89: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,719 INFO L290 TraceCheckUtils]: 90: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,719 INFO L290 TraceCheckUtils]: 91: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,719 INFO L290 TraceCheckUtils]: 92: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,719 INFO L290 TraceCheckUtils]: 93: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,720 INFO L290 TraceCheckUtils]: 94: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,720 INFO L290 TraceCheckUtils]: 95: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,720 INFO L290 TraceCheckUtils]: 96: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,721 INFO L290 TraceCheckUtils]: 97: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,721 INFO L290 TraceCheckUtils]: 98: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,721 INFO L290 TraceCheckUtils]: 99: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,722 INFO L290 TraceCheckUtils]: 100: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,722 INFO L290 TraceCheckUtils]: 101: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,722 INFO L290 TraceCheckUtils]: 102: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,722 INFO L290 TraceCheckUtils]: 103: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,723 INFO L290 TraceCheckUtils]: 104: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17807#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,723 INFO L290 TraceCheckUtils]: 105: Hoare triple {17807#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {17806#false} is VALID [2022-02-21 04:23:02,723 INFO L290 TraceCheckUtils]: 106: Hoare triple {17806#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,723 INFO L290 TraceCheckUtils]: 107: Hoare triple {17806#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,723 INFO L290 TraceCheckUtils]: 108: Hoare triple {17806#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,724 INFO L290 TraceCheckUtils]: 109: Hoare triple {17806#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,724 INFO L290 TraceCheckUtils]: 110: Hoare triple {17806#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,724 INFO L290 TraceCheckUtils]: 111: Hoare triple {17806#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,724 INFO L290 TraceCheckUtils]: 112: Hoare triple {17806#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,724 INFO L290 TraceCheckUtils]: 113: Hoare triple {17806#false} assume !(1 == ~E_3~0); {17806#false} is VALID [2022-02-21 04:23:02,724 INFO L290 TraceCheckUtils]: 114: Hoare triple {17806#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,724 INFO L290 TraceCheckUtils]: 115: Hoare triple {17806#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 116: Hoare triple {17806#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 117: Hoare triple {17806#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 118: Hoare triple {17806#false} assume 1 == ~E_8~0;~E_8~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 119: Hoare triple {17806#false} assume 1 == ~E_9~0;~E_9~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 120: Hoare triple {17806#false} assume 1 == ~E_10~0;~E_10~0 := 2; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 121: Hoare triple {17806#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 122: Hoare triple {17806#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {17806#false} is VALID [2022-02-21 04:23:02,725 INFO L290 TraceCheckUtils]: 123: Hoare triple {17806#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {17806#false} is VALID [2022-02-21 04:23:02,726 INFO L290 TraceCheckUtils]: 124: Hoare triple {17806#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {17806#false} is VALID [2022-02-21 04:23:02,726 INFO L290 TraceCheckUtils]: 125: Hoare triple {17806#false} assume !(0 == start_simulation_~tmp~3#1); {17806#false} is VALID [2022-02-21 04:23:02,726 INFO L290 TraceCheckUtils]: 126: Hoare triple {17806#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {17806#false} is VALID [2022-02-21 04:23:02,726 INFO L290 TraceCheckUtils]: 127: Hoare triple {17806#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {17806#false} is VALID [2022-02-21 04:23:02,726 INFO L290 TraceCheckUtils]: 128: Hoare triple {17806#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {17806#false} is VALID [2022-02-21 04:23:02,726 INFO L290 TraceCheckUtils]: 129: Hoare triple {17806#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {17806#false} is VALID [2022-02-21 04:23:02,726 INFO L290 TraceCheckUtils]: 130: Hoare triple {17806#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17806#false} is VALID [2022-02-21 04:23:02,727 INFO L290 TraceCheckUtils]: 131: Hoare triple {17806#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17806#false} is VALID [2022-02-21 04:23:02,727 INFO L290 TraceCheckUtils]: 132: Hoare triple {17806#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {17806#false} is VALID [2022-02-21 04:23:02,727 INFO L290 TraceCheckUtils]: 133: Hoare triple {17806#false} assume !(0 != start_simulation_~tmp___0~1#1); {17806#false} is VALID [2022-02-21 04:23:02,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:02,749 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:02,749 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329683168] [2022-02-21 04:23:02,749 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1329683168] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:02,749 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:02,749 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:02,749 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960142596] [2022-02-21 04:23:02,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:02,750 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:02,750 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:02,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:02,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:02,751 INFO L87 Difference]: Start difference. First operand 1366 states and 2030 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:03,750 INFO L93 Difference]: Finished difference Result 1366 states and 2029 transitions. [2022-02-21 04:23:03,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:03,750 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,824 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:03,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2029 transitions. [2022-02-21 04:23:03,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:03,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2029 transitions. [2022-02-21 04:23:03,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:03,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:03,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2029 transitions. [2022-02-21 04:23:03,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:03,971 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2022-02-21 04:23:03,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2029 transitions. [2022-02-21 04:23:03,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:03,987 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:03,989 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2029 transitions. Second operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,991 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2029 transitions. Second operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,992 INFO L87 Difference]: Start difference. First operand 1366 states and 2029 transitions. Second operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,059 INFO L93 Difference]: Finished difference Result 1366 states and 2029 transitions. [2022-02-21 04:23:04,059 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2029 transitions. [2022-02-21 04:23:04,062 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,062 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,065 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2029 transitions. [2022-02-21 04:23:04,066 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2029 transitions. [2022-02-21 04:23:04,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,129 INFO L93 Difference]: Finished difference Result 1366 states and 2029 transitions. [2022-02-21 04:23:04,129 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2029 transitions. [2022-02-21 04:23:04,131 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,131 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,132 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:04,132 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:04,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2029 transitions. [2022-02-21 04:23:04,204 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2022-02-21 04:23:04,204 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2022-02-21 04:23:04,204 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:04,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2029 transitions. [2022-02-21 04:23:04,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:04,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:04,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:04,212 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,212 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,213 INFO L791 eck$LassoCheckResult]: Stem: 20232#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 20233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20440#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19225#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19226#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20465#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20423#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20424#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20454#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19534#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19535#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19638#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19883#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19814#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19536#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19196#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19197#L1036 assume !(0 == ~M_E~0); 19295#L1036-2 assume !(0 == ~T1_E~0); 20171#L1041-1 assume !(0 == ~T2_E~0); 20172#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19570#L1051-1 assume !(0 == ~T4_E~0); 19571#L1056-1 assume !(0 == ~T5_E~0); 20309#L1061-1 assume !(0 == ~T6_E~0); 19468#L1066-1 assume !(0 == ~T7_E~0); 19469#L1071-1 assume !(0 == ~T8_E~0); 20292#L1076-1 assume !(0 == ~T9_E~0); 19363#L1081-1 assume !(0 == ~T10_E~0); 19364#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19767#L1091-1 assume !(0 == ~E_1~0); 20469#L1096-1 assume !(0 == ~E_2~0); 20470#L1101-1 assume !(0 == ~E_3~0); 19828#L1106-1 assume !(0 == ~E_4~0); 19829#L1111-1 assume !(0 == ~E_5~0); 19985#L1116-1 assume !(0 == ~E_6~0); 19986#L1121-1 assume !(0 == ~E_7~0); 19821#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19822#L1131-1 assume !(0 == ~E_9~0); 20072#L1136-1 assume !(0 == ~E_10~0); 20179#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20336#L514 assume 1 == ~m_pc~0; 20299#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19842#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19761#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19762#L1285 assume !(0 != activate_threads_~tmp~1#1); 20505#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19487#L533 assume !(1 == ~t1_pc~0); 19488#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20001#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19874#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19875#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20201#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20202#L552 assume 1 == ~t2_pc~0; 19713#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19714#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20280#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20281#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 19856#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19857#L571 assume 1 == ~t3_pc~0; 20033#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20034#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19403#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19404#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 19991#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19279#L590 assume !(1 == ~t4_pc~0); 19280#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20044#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20277#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20278#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20234#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19987#L609 assume 1 == ~t5_pc~0; 19988#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20502#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19314#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19315#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 19982#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19983#L628 assume !(1 == ~t6_pc~0); 19916#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19915#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20487#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20488#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20272#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20273#L647 assume 1 == ~t7_pc~0; 19830#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19831#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20109#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19837#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 19838#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20534#L666 assume !(1 == ~t8_pc~0); 19617#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19618#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19852#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20009#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19765#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19766#L685 assume 1 == ~t9_pc~0; 20511#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20408#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20400#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19790#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19791#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20143#L704 assume !(1 == ~t10_pc~0); 19782#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19781#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20307#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19335#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19336#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19581#L1154 assume !(1 == ~M_E~0); 20260#L1154-2 assume !(1 == ~T1_E~0); 19553#L1159-1 assume !(1 == ~T2_E~0); 19554#L1164-1 assume !(1 == ~T3_E~0); 20006#L1169-1 assume !(1 == ~T4_E~0); 19878#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19685#L1179-1 assume !(1 == ~T6_E~0); 19539#L1184-1 assume !(1 == ~T7_E~0); 19540#L1189-1 assume !(1 == ~T8_E~0); 19615#L1194-1 assume !(1 == ~T9_E~0); 19754#L1199-1 assume !(1 == ~T10_E~0); 19700#L1204-1 assume !(1 == ~E_M~0); 19701#L1209-1 assume !(1 == ~E_1~0); 20227#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20228#L1219-1 assume !(1 == ~E_3~0); 20527#L1224-1 assume !(1 == ~E_4~0); 20026#L1229-1 assume !(1 == ~E_5~0); 19424#L1234-1 assume !(1 == ~E_6~0); 19425#L1239-1 assume !(1 == ~E_7~0); 19483#L1244-1 assume !(1 == ~E_8~0); 19484#L1249-1 assume !(1 == ~E_9~0); 20297#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19326#L1259-1 assume { :end_inline_reset_delta_events } true; 19327#L1565-2 [2022-02-21 04:23:04,213 INFO L793 eck$LassoCheckResult]: Loop: 19327#L1565-2 assume !false; 20235#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19719#L1011 assume !false; 19720#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19769#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19523#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20388#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19550#L866 assume !(0 != eval_~tmp~0#1); 19552#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20138#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20139#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20303#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20489#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20362#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20363#L1051-3 assume !(0 == ~T4_E~0); 20304#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19567#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19568#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19569#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20490#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19318#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19319#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19377#L1091-3 assume !(0 == ~E_1~0); 19378#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20456#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20457#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20486#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20447#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20154#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20155#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20378#L1131-3 assume !(0 == ~E_9~0); 20379#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20538#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20157#L514-36 assume !(1 == ~m_pc~0); 19894#L514-38 is_master_triggered_~__retres1~0#1 := 0; 19744#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19745#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20200#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19626#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19627#L533-36 assume 1 == ~t1_pc~0; 19902#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19998#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20298#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20246#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20049#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20050#L552-36 assume 1 == ~t2_pc~0; 19619#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19621#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19440#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19441#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19593#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19594#L571-36 assume 1 == ~t3_pc~0; 19978#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19683#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19684#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19805#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20361#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19651#L590-36 assume !(1 == ~t4_pc~0); 19652#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20261#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19839#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19840#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20340#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20341#L609-36 assume 1 == ~t5_pc~0; 20216#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20051#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19869#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19870#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20123#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19949#L628-36 assume !(1 == ~t6_pc~0); 19808#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 19807#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20236#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20237#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20161#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20162#L647-36 assume 1 == ~t7_pc~0; 20090#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19347#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19348#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19367#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 19368#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20262#L666-36 assume 1 == ~t8_pc~0; 19547#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19548#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20451#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20452#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19710#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19711#L685-36 assume 1 == ~t9_pc~0; 20137#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19452#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19967#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19968#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19849#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19850#L704-36 assume 1 == ~t10_pc~0; 19442#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19443#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20203#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20204#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19472#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19473#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20439#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20317#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20318#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20498#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19778#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19779#L1179-3 assume !(1 == ~T6_E~0); 20410#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19349#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19350#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19723#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19724#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20022#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19212#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19213#L1219-3 assume !(1 == ~E_3~0); 20211#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20212#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20231#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19485#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19486#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20065#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20448#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20214#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20215#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19293#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20038#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20039#L1584 assume !(0 == start_simulation_~tmp~3#1); 20169#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19499#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19194#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19641#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19642#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19825#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19793#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19794#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19327#L1565-2 [2022-02-21 04:23:04,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2022-02-21 04:23:04,214 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,214 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668651498] [2022-02-21 04:23:04,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,261 INFO L290 TraceCheckUtils]: 0: Hoare triple {23275#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {23275#true} is VALID [2022-02-21 04:23:04,261 INFO L290 TraceCheckUtils]: 1: Hoare triple {23275#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,262 INFO L290 TraceCheckUtils]: 2: Hoare triple {23277#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,262 INFO L290 TraceCheckUtils]: 3: Hoare triple {23277#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,262 INFO L290 TraceCheckUtils]: 4: Hoare triple {23277#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,263 INFO L290 TraceCheckUtils]: 5: Hoare triple {23277#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,263 INFO L290 TraceCheckUtils]: 6: Hoare triple {23277#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,263 INFO L290 TraceCheckUtils]: 7: Hoare triple {23277#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,263 INFO L290 TraceCheckUtils]: 8: Hoare triple {23277#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {23277#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:04,264 INFO L290 TraceCheckUtils]: 9: Hoare triple {23277#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,264 INFO L290 TraceCheckUtils]: 10: Hoare triple {23276#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,264 INFO L290 TraceCheckUtils]: 11: Hoare triple {23276#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,264 INFO L290 TraceCheckUtils]: 12: Hoare triple {23276#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,264 INFO L290 TraceCheckUtils]: 13: Hoare triple {23276#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {23276#false} is VALID [2022-02-21 04:23:04,264 INFO L290 TraceCheckUtils]: 14: Hoare triple {23276#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,264 INFO L290 TraceCheckUtils]: 15: Hoare triple {23276#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {23276#false} is VALID [2022-02-21 04:23:04,265 INFO L290 TraceCheckUtils]: 16: Hoare triple {23276#false} assume !(0 == ~M_E~0); {23276#false} is VALID [2022-02-21 04:23:04,265 INFO L290 TraceCheckUtils]: 17: Hoare triple {23276#false} assume !(0 == ~T1_E~0); {23276#false} is VALID [2022-02-21 04:23:04,265 INFO L290 TraceCheckUtils]: 18: Hoare triple {23276#false} assume !(0 == ~T2_E~0); {23276#false} is VALID [2022-02-21 04:23:04,265 INFO L290 TraceCheckUtils]: 19: Hoare triple {23276#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23276#false} is VALID [2022-02-21 04:23:04,265 INFO L290 TraceCheckUtils]: 20: Hoare triple {23276#false} assume !(0 == ~T4_E~0); {23276#false} is VALID [2022-02-21 04:23:04,265 INFO L290 TraceCheckUtils]: 21: Hoare triple {23276#false} assume !(0 == ~T5_E~0); {23276#false} is VALID [2022-02-21 04:23:04,265 INFO L290 TraceCheckUtils]: 22: Hoare triple {23276#false} assume !(0 == ~T6_E~0); {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 23: Hoare triple {23276#false} assume !(0 == ~T7_E~0); {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 24: Hoare triple {23276#false} assume !(0 == ~T8_E~0); {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 25: Hoare triple {23276#false} assume !(0 == ~T9_E~0); {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 26: Hoare triple {23276#false} assume !(0 == ~T10_E~0); {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 27: Hoare triple {23276#false} assume 0 == ~E_M~0;~E_M~0 := 1; {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 28: Hoare triple {23276#false} assume !(0 == ~E_1~0); {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 29: Hoare triple {23276#false} assume !(0 == ~E_2~0); {23276#false} is VALID [2022-02-21 04:23:04,266 INFO L290 TraceCheckUtils]: 30: Hoare triple {23276#false} assume !(0 == ~E_3~0); {23276#false} is VALID [2022-02-21 04:23:04,267 INFO L290 TraceCheckUtils]: 31: Hoare triple {23276#false} assume !(0 == ~E_4~0); {23276#false} is VALID [2022-02-21 04:23:04,267 INFO L290 TraceCheckUtils]: 32: Hoare triple {23276#false} assume !(0 == ~E_5~0); {23276#false} is VALID [2022-02-21 04:23:04,267 INFO L290 TraceCheckUtils]: 33: Hoare triple {23276#false} assume !(0 == ~E_6~0); {23276#false} is VALID [2022-02-21 04:23:04,267 INFO L290 TraceCheckUtils]: 34: Hoare triple {23276#false} assume !(0 == ~E_7~0); {23276#false} is VALID [2022-02-21 04:23:04,267 INFO L290 TraceCheckUtils]: 35: Hoare triple {23276#false} assume 0 == ~E_8~0;~E_8~0 := 1; {23276#false} is VALID [2022-02-21 04:23:04,267 INFO L290 TraceCheckUtils]: 36: Hoare triple {23276#false} assume !(0 == ~E_9~0); {23276#false} is VALID [2022-02-21 04:23:04,267 INFO L290 TraceCheckUtils]: 37: Hoare triple {23276#false} assume !(0 == ~E_10~0); {23276#false} is VALID [2022-02-21 04:23:04,268 INFO L290 TraceCheckUtils]: 38: Hoare triple {23276#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23276#false} is VALID [2022-02-21 04:23:04,268 INFO L290 TraceCheckUtils]: 39: Hoare triple {23276#false} assume 1 == ~m_pc~0; {23276#false} is VALID [2022-02-21 04:23:04,268 INFO L290 TraceCheckUtils]: 40: Hoare triple {23276#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {23276#false} is VALID [2022-02-21 04:23:04,268 INFO L290 TraceCheckUtils]: 41: Hoare triple {23276#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23276#false} is VALID [2022-02-21 04:23:04,268 INFO L290 TraceCheckUtils]: 42: Hoare triple {23276#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23276#false} is VALID [2022-02-21 04:23:04,268 INFO L290 TraceCheckUtils]: 43: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp~1#1); {23276#false} is VALID [2022-02-21 04:23:04,268 INFO L290 TraceCheckUtils]: 44: Hoare triple {23276#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 45: Hoare triple {23276#false} assume !(1 == ~t1_pc~0); {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 46: Hoare triple {23276#false} is_transmit1_triggered_~__retres1~1#1 := 0; {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 47: Hoare triple {23276#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 48: Hoare triple {23276#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 49: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___0~0#1); {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 50: Hoare triple {23276#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 51: Hoare triple {23276#false} assume 1 == ~t2_pc~0; {23276#false} is VALID [2022-02-21 04:23:04,269 INFO L290 TraceCheckUtils]: 52: Hoare triple {23276#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23276#false} is VALID [2022-02-21 04:23:04,270 INFO L290 TraceCheckUtils]: 53: Hoare triple {23276#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23276#false} is VALID [2022-02-21 04:23:04,270 INFO L290 TraceCheckUtils]: 54: Hoare triple {23276#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23276#false} is VALID [2022-02-21 04:23:04,270 INFO L290 TraceCheckUtils]: 55: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___1~0#1); {23276#false} is VALID [2022-02-21 04:23:04,270 INFO L290 TraceCheckUtils]: 56: Hoare triple {23276#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23276#false} is VALID [2022-02-21 04:23:04,270 INFO L290 TraceCheckUtils]: 57: Hoare triple {23276#false} assume 1 == ~t3_pc~0; {23276#false} is VALID [2022-02-21 04:23:04,270 INFO L290 TraceCheckUtils]: 58: Hoare triple {23276#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23276#false} is VALID [2022-02-21 04:23:04,270 INFO L290 TraceCheckUtils]: 59: Hoare triple {23276#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 60: Hoare triple {23276#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 61: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___2~0#1); {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 62: Hoare triple {23276#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 63: Hoare triple {23276#false} assume !(1 == ~t4_pc~0); {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 64: Hoare triple {23276#false} is_transmit4_triggered_~__retres1~4#1 := 0; {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 65: Hoare triple {23276#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 66: Hoare triple {23276#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23276#false} is VALID [2022-02-21 04:23:04,271 INFO L290 TraceCheckUtils]: 67: Hoare triple {23276#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {23276#false} is VALID [2022-02-21 04:23:04,272 INFO L290 TraceCheckUtils]: 68: Hoare triple {23276#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23276#false} is VALID [2022-02-21 04:23:04,272 INFO L290 TraceCheckUtils]: 69: Hoare triple {23276#false} assume 1 == ~t5_pc~0; {23276#false} is VALID [2022-02-21 04:23:04,272 INFO L290 TraceCheckUtils]: 70: Hoare triple {23276#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {23276#false} is VALID [2022-02-21 04:23:04,272 INFO L290 TraceCheckUtils]: 71: Hoare triple {23276#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23276#false} is VALID [2022-02-21 04:23:04,272 INFO L290 TraceCheckUtils]: 72: Hoare triple {23276#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23276#false} is VALID [2022-02-21 04:23:04,272 INFO L290 TraceCheckUtils]: 73: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___4~0#1); {23276#false} is VALID [2022-02-21 04:23:04,272 INFO L290 TraceCheckUtils]: 74: Hoare triple {23276#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 75: Hoare triple {23276#false} assume !(1 == ~t6_pc~0); {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 76: Hoare triple {23276#false} is_transmit6_triggered_~__retres1~6#1 := 0; {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 77: Hoare triple {23276#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 78: Hoare triple {23276#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 79: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___5~0#1); {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 80: Hoare triple {23276#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 81: Hoare triple {23276#false} assume 1 == ~t7_pc~0; {23276#false} is VALID [2022-02-21 04:23:04,273 INFO L290 TraceCheckUtils]: 82: Hoare triple {23276#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23276#false} is VALID [2022-02-21 04:23:04,274 INFO L290 TraceCheckUtils]: 83: Hoare triple {23276#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23276#false} is VALID [2022-02-21 04:23:04,274 INFO L290 TraceCheckUtils]: 84: Hoare triple {23276#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23276#false} is VALID [2022-02-21 04:23:04,274 INFO L290 TraceCheckUtils]: 85: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___6~0#1); {23276#false} is VALID [2022-02-21 04:23:04,274 INFO L290 TraceCheckUtils]: 86: Hoare triple {23276#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23276#false} is VALID [2022-02-21 04:23:04,274 INFO L290 TraceCheckUtils]: 87: Hoare triple {23276#false} assume !(1 == ~t8_pc~0); {23276#false} is VALID [2022-02-21 04:23:04,274 INFO L290 TraceCheckUtils]: 88: Hoare triple {23276#false} is_transmit8_triggered_~__retres1~8#1 := 0; {23276#false} is VALID [2022-02-21 04:23:04,274 INFO L290 TraceCheckUtils]: 89: Hoare triple {23276#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 90: Hoare triple {23276#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 91: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___7~0#1); {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 92: Hoare triple {23276#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 93: Hoare triple {23276#false} assume 1 == ~t9_pc~0; {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 94: Hoare triple {23276#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 95: Hoare triple {23276#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 96: Hoare triple {23276#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23276#false} is VALID [2022-02-21 04:23:04,275 INFO L290 TraceCheckUtils]: 97: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___8~0#1); {23276#false} is VALID [2022-02-21 04:23:04,276 INFO L290 TraceCheckUtils]: 98: Hoare triple {23276#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23276#false} is VALID [2022-02-21 04:23:04,276 INFO L290 TraceCheckUtils]: 99: Hoare triple {23276#false} assume !(1 == ~t10_pc~0); {23276#false} is VALID [2022-02-21 04:23:04,276 INFO L290 TraceCheckUtils]: 100: Hoare triple {23276#false} is_transmit10_triggered_~__retres1~10#1 := 0; {23276#false} is VALID [2022-02-21 04:23:04,276 INFO L290 TraceCheckUtils]: 101: Hoare triple {23276#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23276#false} is VALID [2022-02-21 04:23:04,276 INFO L290 TraceCheckUtils]: 102: Hoare triple {23276#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {23276#false} is VALID [2022-02-21 04:23:04,276 INFO L290 TraceCheckUtils]: 103: Hoare triple {23276#false} assume !(0 != activate_threads_~tmp___9~0#1); {23276#false} is VALID [2022-02-21 04:23:04,276 INFO L290 TraceCheckUtils]: 104: Hoare triple {23276#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 105: Hoare triple {23276#false} assume !(1 == ~M_E~0); {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 106: Hoare triple {23276#false} assume !(1 == ~T1_E~0); {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 107: Hoare triple {23276#false} assume !(1 == ~T2_E~0); {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 108: Hoare triple {23276#false} assume !(1 == ~T3_E~0); {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 109: Hoare triple {23276#false} assume !(1 == ~T4_E~0); {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 110: Hoare triple {23276#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 111: Hoare triple {23276#false} assume !(1 == ~T6_E~0); {23276#false} is VALID [2022-02-21 04:23:04,277 INFO L290 TraceCheckUtils]: 112: Hoare triple {23276#false} assume !(1 == ~T7_E~0); {23276#false} is VALID [2022-02-21 04:23:04,278 INFO L290 TraceCheckUtils]: 113: Hoare triple {23276#false} assume !(1 == ~T8_E~0); {23276#false} is VALID [2022-02-21 04:23:04,278 INFO L290 TraceCheckUtils]: 114: Hoare triple {23276#false} assume !(1 == ~T9_E~0); {23276#false} is VALID [2022-02-21 04:23:04,278 INFO L290 TraceCheckUtils]: 115: Hoare triple {23276#false} assume !(1 == ~T10_E~0); {23276#false} is VALID [2022-02-21 04:23:04,278 INFO L290 TraceCheckUtils]: 116: Hoare triple {23276#false} assume !(1 == ~E_M~0); {23276#false} is VALID [2022-02-21 04:23:04,278 INFO L290 TraceCheckUtils]: 117: Hoare triple {23276#false} assume !(1 == ~E_1~0); {23276#false} is VALID [2022-02-21 04:23:04,278 INFO L290 TraceCheckUtils]: 118: Hoare triple {23276#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,278 INFO L290 TraceCheckUtils]: 119: Hoare triple {23276#false} assume !(1 == ~E_3~0); {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 120: Hoare triple {23276#false} assume !(1 == ~E_4~0); {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 121: Hoare triple {23276#false} assume !(1 == ~E_5~0); {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 122: Hoare triple {23276#false} assume !(1 == ~E_6~0); {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 123: Hoare triple {23276#false} assume !(1 == ~E_7~0); {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 124: Hoare triple {23276#false} assume !(1 == ~E_8~0); {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 125: Hoare triple {23276#false} assume !(1 == ~E_9~0); {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 126: Hoare triple {23276#false} assume 1 == ~E_10~0;~E_10~0 := 2; {23276#false} is VALID [2022-02-21 04:23:04,279 INFO L290 TraceCheckUtils]: 127: Hoare triple {23276#false} assume { :end_inline_reset_delta_events } true; {23276#false} is VALID [2022-02-21 04:23:04,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,280 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,280 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668651498] [2022-02-21 04:23:04,280 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668651498] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,280 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,281 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:04,281 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675690854] [2022-02-21 04:23:04,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,281 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:04,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,282 INFO L85 PathProgramCache]: Analyzing trace with hash -1331390508, now seen corresponding path program 1 times [2022-02-21 04:23:04,282 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,282 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170473591] [2022-02-21 04:23:04,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,310 INFO L290 TraceCheckUtils]: 0: Hoare triple {23278#true} assume !false; {23278#true} is VALID [2022-02-21 04:23:04,310 INFO L290 TraceCheckUtils]: 1: Hoare triple {23278#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {23278#true} is VALID [2022-02-21 04:23:04,310 INFO L290 TraceCheckUtils]: 2: Hoare triple {23278#true} assume !false; {23278#true} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 3: Hoare triple {23278#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {23278#true} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 4: Hoare triple {23278#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {23278#true} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 5: Hoare triple {23278#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {23278#true} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 6: Hoare triple {23278#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {23278#true} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 7: Hoare triple {23278#true} assume !(0 != eval_~tmp~0#1); {23278#true} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 8: Hoare triple {23278#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {23278#true} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 9: Hoare triple {23278#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {23278#true} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 10: Hoare triple {23278#true} assume 0 == ~M_E~0;~M_E~0 := 1; {23278#true} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 11: Hoare triple {23278#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23278#true} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 12: Hoare triple {23278#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {23278#true} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 13: Hoare triple {23278#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23278#true} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 14: Hoare triple {23278#true} assume !(0 == ~T4_E~0); {23278#true} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 15: Hoare triple {23278#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {23278#true} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 16: Hoare triple {23278#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 17: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 18: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 19: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,314 INFO L290 TraceCheckUtils]: 20: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,314 INFO L290 TraceCheckUtils]: 21: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,314 INFO L290 TraceCheckUtils]: 22: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,315 INFO L290 TraceCheckUtils]: 23: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,315 INFO L290 TraceCheckUtils]: 24: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,315 INFO L290 TraceCheckUtils]: 25: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,315 INFO L290 TraceCheckUtils]: 26: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,316 INFO L290 TraceCheckUtils]: 27: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,316 INFO L290 TraceCheckUtils]: 28: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,316 INFO L290 TraceCheckUtils]: 29: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 30: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 31: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 32: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 33: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,318 INFO L290 TraceCheckUtils]: 34: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,318 INFO L290 TraceCheckUtils]: 35: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,318 INFO L290 TraceCheckUtils]: 36: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,319 INFO L290 TraceCheckUtils]: 37: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,319 INFO L290 TraceCheckUtils]: 38: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,319 INFO L290 TraceCheckUtils]: 39: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,319 INFO L290 TraceCheckUtils]: 40: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,320 INFO L290 TraceCheckUtils]: 41: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,320 INFO L290 TraceCheckUtils]: 42: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,320 INFO L290 TraceCheckUtils]: 43: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,321 INFO L290 TraceCheckUtils]: 44: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,321 INFO L290 TraceCheckUtils]: 45: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,321 INFO L290 TraceCheckUtils]: 46: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,321 INFO L290 TraceCheckUtils]: 47: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,322 INFO L290 TraceCheckUtils]: 48: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,322 INFO L290 TraceCheckUtils]: 49: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,322 INFO L290 TraceCheckUtils]: 50: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 51: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 52: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 53: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 54: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 55: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 56: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 57: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 58: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 59: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 60: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 61: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 62: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 63: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 64: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 65: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 66: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 67: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 68: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,328 INFO L290 TraceCheckUtils]: 69: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,328 INFO L290 TraceCheckUtils]: 70: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,328 INFO L290 TraceCheckUtils]: 71: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,329 INFO L290 TraceCheckUtils]: 72: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,329 INFO L290 TraceCheckUtils]: 73: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,329 INFO L290 TraceCheckUtils]: 74: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,329 INFO L290 TraceCheckUtils]: 75: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,330 INFO L290 TraceCheckUtils]: 76: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,330 INFO L290 TraceCheckUtils]: 77: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,330 INFO L290 TraceCheckUtils]: 78: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,331 INFO L290 TraceCheckUtils]: 79: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,331 INFO L290 TraceCheckUtils]: 80: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,331 INFO L290 TraceCheckUtils]: 81: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,331 INFO L290 TraceCheckUtils]: 82: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,332 INFO L290 TraceCheckUtils]: 83: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,332 INFO L290 TraceCheckUtils]: 84: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,332 INFO L290 TraceCheckUtils]: 85: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,333 INFO L290 TraceCheckUtils]: 86: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,333 INFO L290 TraceCheckUtils]: 87: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,333 INFO L290 TraceCheckUtils]: 88: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,333 INFO L290 TraceCheckUtils]: 89: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,334 INFO L290 TraceCheckUtils]: 90: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,334 INFO L290 TraceCheckUtils]: 91: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,334 INFO L290 TraceCheckUtils]: 92: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,335 INFO L290 TraceCheckUtils]: 93: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,335 INFO L290 TraceCheckUtils]: 94: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,335 INFO L290 TraceCheckUtils]: 95: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,335 INFO L290 TraceCheckUtils]: 96: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,336 INFO L290 TraceCheckUtils]: 97: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,336 INFO L290 TraceCheckUtils]: 98: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,336 INFO L290 TraceCheckUtils]: 99: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,337 INFO L290 TraceCheckUtils]: 100: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,337 INFO L290 TraceCheckUtils]: 101: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,337 INFO L290 TraceCheckUtils]: 102: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,337 INFO L290 TraceCheckUtils]: 103: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,338 INFO L290 TraceCheckUtils]: 104: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23280#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:04,338 INFO L290 TraceCheckUtils]: 105: Hoare triple {23280#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {23279#false} is VALID [2022-02-21 04:23:04,338 INFO L290 TraceCheckUtils]: 106: Hoare triple {23279#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,338 INFO L290 TraceCheckUtils]: 107: Hoare triple {23279#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,338 INFO L290 TraceCheckUtils]: 108: Hoare triple {23279#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,338 INFO L290 TraceCheckUtils]: 109: Hoare triple {23279#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 110: Hoare triple {23279#false} assume 1 == ~E_M~0;~E_M~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 111: Hoare triple {23279#false} assume 1 == ~E_1~0;~E_1~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 112: Hoare triple {23279#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 113: Hoare triple {23279#false} assume !(1 == ~E_3~0); {23279#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 114: Hoare triple {23279#false} assume 1 == ~E_4~0;~E_4~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 115: Hoare triple {23279#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 116: Hoare triple {23279#false} assume 1 == ~E_6~0;~E_6~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 117: Hoare triple {23279#false} assume 1 == ~E_7~0;~E_7~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 118: Hoare triple {23279#false} assume 1 == ~E_8~0;~E_8~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 119: Hoare triple {23279#false} assume 1 == ~E_9~0;~E_9~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 120: Hoare triple {23279#false} assume 1 == ~E_10~0;~E_10~0 := 2; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 121: Hoare triple {23279#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 122: Hoare triple {23279#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 123: Hoare triple {23279#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {23279#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 124: Hoare triple {23279#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {23279#false} is VALID [2022-02-21 04:23:04,341 INFO L290 TraceCheckUtils]: 125: Hoare triple {23279#false} assume !(0 == start_simulation_~tmp~3#1); {23279#false} is VALID [2022-02-21 04:23:04,341 INFO L290 TraceCheckUtils]: 126: Hoare triple {23279#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {23279#false} is VALID [2022-02-21 04:23:04,341 INFO L290 TraceCheckUtils]: 127: Hoare triple {23279#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {23279#false} is VALID [2022-02-21 04:23:04,341 INFO L290 TraceCheckUtils]: 128: Hoare triple {23279#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {23279#false} is VALID [2022-02-21 04:23:04,341 INFO L290 TraceCheckUtils]: 129: Hoare triple {23279#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {23279#false} is VALID [2022-02-21 04:23:04,341 INFO L290 TraceCheckUtils]: 130: Hoare triple {23279#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {23279#false} is VALID [2022-02-21 04:23:04,341 INFO L290 TraceCheckUtils]: 131: Hoare triple {23279#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {23279#false} is VALID [2022-02-21 04:23:04,342 INFO L290 TraceCheckUtils]: 132: Hoare triple {23279#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {23279#false} is VALID [2022-02-21 04:23:04,342 INFO L290 TraceCheckUtils]: 133: Hoare triple {23279#false} assume !(0 != start_simulation_~tmp___0~1#1); {23279#false} is VALID [2022-02-21 04:23:04,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,342 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,342 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170473591] [2022-02-21 04:23:04,343 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170473591] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,343 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,343 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:04,343 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674808574] [2022-02-21 04:23:04,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,343 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:04,344 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:04,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:04,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:04,344 INFO L87 Difference]: Start difference. First operand 1366 states and 2029 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,314 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2022-02-21 04:23:05,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:05,315 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,388 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:05,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:05,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2028 transitions. [2022-02-21 04:23:05,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:05,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:05,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:05,518 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2022-02-21 04:23:05,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:05,534 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:05,536 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2028 transitions. Second operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,538 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2028 transitions. Second operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,541 INFO L87 Difference]: Start difference. First operand 1366 states and 2028 transitions. Second operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,588 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2022-02-21 04:23:05,588 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,591 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:05,591 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:05,594 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,596 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,664 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2022-02-21 04:23:05,664 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,667 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:05,667 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:05,667 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:05,667 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:05,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2028 transitions. [2022-02-21 04:23:05,720 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2022-02-21 04:23:05,720 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2022-02-21 04:23:05,720 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:05,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2028 transitions. [2022-02-21 04:23:05,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:05,725 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:05,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:05,727 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,727 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,727 INFO L791 eck$LassoCheckResult]: Stem: 25704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 25913#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24696#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24697#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 25937#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25896#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25897#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25927#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25005#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25006#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25111#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25356#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25287#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25007#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24669#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24670#L1036 assume !(0 == ~M_E~0); 24768#L1036-2 assume !(0 == ~T1_E~0); 25644#L1041-1 assume !(0 == ~T2_E~0); 25645#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25043#L1051-1 assume !(0 == ~T4_E~0); 25044#L1056-1 assume !(0 == ~T5_E~0); 25782#L1061-1 assume !(0 == ~T6_E~0); 24941#L1066-1 assume !(0 == ~T7_E~0); 24942#L1071-1 assume !(0 == ~T8_E~0); 25765#L1076-1 assume !(0 == ~T9_E~0); 24836#L1081-1 assume !(0 == ~T10_E~0); 24837#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25240#L1091-1 assume !(0 == ~E_1~0); 25941#L1096-1 assume !(0 == ~E_2~0); 25942#L1101-1 assume !(0 == ~E_3~0); 25301#L1106-1 assume !(0 == ~E_4~0); 25302#L1111-1 assume !(0 == ~E_5~0); 25458#L1116-1 assume !(0 == ~E_6~0); 25459#L1121-1 assume !(0 == ~E_7~0); 25294#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25295#L1131-1 assume !(0 == ~E_9~0); 25545#L1136-1 assume !(0 == ~E_10~0); 25652#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25809#L514 assume 1 == ~m_pc~0; 25772#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25314#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25231#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25232#L1285 assume !(0 != activate_threads_~tmp~1#1); 25977#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24960#L533 assume !(1 == ~t1_pc~0); 24961#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25474#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25347#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25348#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25674#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25675#L552 assume 1 == ~t2_pc~0; 25185#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25186#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25753#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25754#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25326#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25327#L571 assume 1 == ~t3_pc~0; 25504#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25505#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24874#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24875#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25464#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24750#L590 assume !(1 == ~t4_pc~0); 24751#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25517#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25749#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25750#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25706#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25460#L609 assume 1 == ~t5_pc~0; 25461#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25975#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24787#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24788#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25455#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25456#L628 assume !(1 == ~t6_pc~0); 25389#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25388#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25960#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25961#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25745#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25746#L647 assume 1 == ~t7_pc~0; 25303#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25304#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25580#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25306#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25307#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26007#L666 assume !(1 == ~t8_pc~0); 25090#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25091#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25325#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25481#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25237#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25238#L685 assume 1 == ~t9_pc~0; 25984#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25881#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25873#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25263#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25264#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25616#L704 assume !(1 == ~t10_pc~0); 25255#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25254#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25780#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24806#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 24807#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25054#L1154 assume !(1 == ~M_E~0); 25733#L1154-2 assume !(1 == ~T1_E~0); 25026#L1159-1 assume !(1 == ~T2_E~0); 25027#L1164-1 assume !(1 == ~T3_E~0); 25479#L1169-1 assume !(1 == ~T4_E~0); 25351#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25156#L1179-1 assume !(1 == ~T6_E~0); 25012#L1184-1 assume !(1 == ~T7_E~0); 25013#L1189-1 assume !(1 == ~T8_E~0); 25088#L1194-1 assume !(1 == ~T9_E~0); 25227#L1199-1 assume !(1 == ~T10_E~0); 25171#L1204-1 assume !(1 == ~E_M~0); 25172#L1209-1 assume !(1 == ~E_1~0); 25698#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25699#L1219-1 assume !(1 == ~E_3~0); 26000#L1224-1 assume !(1 == ~E_4~0); 25499#L1229-1 assume !(1 == ~E_5~0); 24897#L1234-1 assume !(1 == ~E_6~0); 24898#L1239-1 assume !(1 == ~E_7~0); 24956#L1244-1 assume !(1 == ~E_8~0); 24957#L1249-1 assume !(1 == ~E_9~0); 25770#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 24799#L1259-1 assume { :end_inline_reset_delta_events } true; 24800#L1565-2 [2022-02-21 04:23:05,728 INFO L793 eck$LassoCheckResult]: Loop: 24800#L1565-2 assume !false; 25708#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25192#L1011 assume !false; 25193#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25242#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24996#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25861#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25020#L866 assume !(0 != eval_~tmp~0#1); 25022#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25609#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25610#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25776#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25962#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25835#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25836#L1051-3 assume !(0 == ~T4_E~0); 25777#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25040#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25041#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25042#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25963#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24791#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24792#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24846#L1091-3 assume !(0 == ~E_1~0); 24847#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25929#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25930#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25959#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25920#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25626#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25627#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25851#L1131-3 assume !(0 == ~E_9~0); 25852#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26011#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25630#L514-36 assume !(1 == ~m_pc~0); 25367#L514-38 is_master_triggered_~__retres1~0#1 := 0; 25215#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25216#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25673#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25099#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25100#L533-36 assume !(1 == ~t1_pc~0); 25376#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 25468#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25771#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25719#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25522#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25523#L552-36 assume 1 == ~t2_pc~0; 25092#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25094#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24913#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24914#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25066#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25067#L571-36 assume 1 == ~t3_pc~0; 25451#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25157#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25158#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25278#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25834#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25127#L590-36 assume !(1 == ~t4_pc~0); 25128#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25734#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25312#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25313#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25813#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25814#L609-36 assume 1 == ~t5_pc~0; 25689#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25524#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25342#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25343#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25596#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25422#L628-36 assume 1 == ~t6_pc~0; 25281#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25282#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25709#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25710#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25634#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25635#L647-36 assume 1 == ~t7_pc~0; 25563#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24820#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24821#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24840#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 24841#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25735#L666-36 assume !(1 == ~t8_pc~0); 25025#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 25024#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25924#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25925#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25183#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25184#L685-36 assume !(1 == ~t9_pc~0); 24924#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24925#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25440#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25441#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25322#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25323#L704-36 assume 1 == ~t10_pc~0; 24915#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24916#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25676#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25677#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24945#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24946#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25912#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25790#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25791#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25971#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25251#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25252#L1179-3 assume !(1 == ~T6_E~0); 25883#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24822#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24823#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25198#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25199#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25495#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24688#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24689#L1219-3 assume !(1 == ~E_3~0); 25684#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25685#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25707#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24958#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24959#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25542#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25921#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25687#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25688#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24766#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25513#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25514#L1584 assume !(0 == start_simulation_~tmp~3#1); 25642#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24972#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24667#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25114#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 25115#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25299#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25266#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25267#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 24800#L1565-2 [2022-02-21 04:23:05,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:05,729 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2022-02-21 04:23:05,729 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:05,729 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874364082] [2022-02-21 04:23:05,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:05,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:05,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,750 INFO L290 TraceCheckUtils]: 0: Hoare triple {28748#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {28748#true} is VALID [2022-02-21 04:23:05,750 INFO L290 TraceCheckUtils]: 1: Hoare triple {28748#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,751 INFO L290 TraceCheckUtils]: 2: Hoare triple {28750#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,751 INFO L290 TraceCheckUtils]: 3: Hoare triple {28750#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,751 INFO L290 TraceCheckUtils]: 4: Hoare triple {28750#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,752 INFO L290 TraceCheckUtils]: 5: Hoare triple {28750#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,752 INFO L290 TraceCheckUtils]: 6: Hoare triple {28750#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,752 INFO L290 TraceCheckUtils]: 7: Hoare triple {28750#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,753 INFO L290 TraceCheckUtils]: 8: Hoare triple {28750#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,753 INFO L290 TraceCheckUtils]: 9: Hoare triple {28750#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {28750#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:05,753 INFO L290 TraceCheckUtils]: 10: Hoare triple {28750#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {28749#false} is VALID [2022-02-21 04:23:05,753 INFO L290 TraceCheckUtils]: 11: Hoare triple {28749#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {28749#false} is VALID [2022-02-21 04:23:05,754 INFO L290 TraceCheckUtils]: 12: Hoare triple {28749#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {28749#false} is VALID [2022-02-21 04:23:05,754 INFO L290 TraceCheckUtils]: 13: Hoare triple {28749#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {28749#false} is VALID [2022-02-21 04:23:05,754 INFO L290 TraceCheckUtils]: 14: Hoare triple {28749#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {28749#false} is VALID [2022-02-21 04:23:05,754 INFO L290 TraceCheckUtils]: 15: Hoare triple {28749#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {28749#false} is VALID [2022-02-21 04:23:05,754 INFO L290 TraceCheckUtils]: 16: Hoare triple {28749#false} assume !(0 == ~M_E~0); {28749#false} is VALID [2022-02-21 04:23:05,754 INFO L290 TraceCheckUtils]: 17: Hoare triple {28749#false} assume !(0 == ~T1_E~0); {28749#false} is VALID [2022-02-21 04:23:05,754 INFO L290 TraceCheckUtils]: 18: Hoare triple {28749#false} assume !(0 == ~T2_E~0); {28749#false} is VALID [2022-02-21 04:23:05,755 INFO L290 TraceCheckUtils]: 19: Hoare triple {28749#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28749#false} is VALID [2022-02-21 04:23:05,755 INFO L290 TraceCheckUtils]: 20: Hoare triple {28749#false} assume !(0 == ~T4_E~0); {28749#false} is VALID [2022-02-21 04:23:05,755 INFO L290 TraceCheckUtils]: 21: Hoare triple {28749#false} assume !(0 == ~T5_E~0); {28749#false} is VALID [2022-02-21 04:23:05,755 INFO L290 TraceCheckUtils]: 22: Hoare triple {28749#false} assume !(0 == ~T6_E~0); {28749#false} is VALID [2022-02-21 04:23:05,755 INFO L290 TraceCheckUtils]: 23: Hoare triple {28749#false} assume !(0 == ~T7_E~0); {28749#false} is VALID [2022-02-21 04:23:05,755 INFO L290 TraceCheckUtils]: 24: Hoare triple {28749#false} assume !(0 == ~T8_E~0); {28749#false} is VALID [2022-02-21 04:23:05,756 INFO L290 TraceCheckUtils]: 25: Hoare triple {28749#false} assume !(0 == ~T9_E~0); {28749#false} is VALID [2022-02-21 04:23:05,756 INFO L290 TraceCheckUtils]: 26: Hoare triple {28749#false} assume !(0 == ~T10_E~0); {28749#false} is VALID [2022-02-21 04:23:05,756 INFO L290 TraceCheckUtils]: 27: Hoare triple {28749#false} assume 0 == ~E_M~0;~E_M~0 := 1; {28749#false} is VALID [2022-02-21 04:23:05,756 INFO L290 TraceCheckUtils]: 28: Hoare triple {28749#false} assume !(0 == ~E_1~0); {28749#false} is VALID [2022-02-21 04:23:05,756 INFO L290 TraceCheckUtils]: 29: Hoare triple {28749#false} assume !(0 == ~E_2~0); {28749#false} is VALID [2022-02-21 04:23:05,756 INFO L290 TraceCheckUtils]: 30: Hoare triple {28749#false} assume !(0 == ~E_3~0); {28749#false} is VALID [2022-02-21 04:23:05,756 INFO L290 TraceCheckUtils]: 31: Hoare triple {28749#false} assume !(0 == ~E_4~0); {28749#false} is VALID [2022-02-21 04:23:05,757 INFO L290 TraceCheckUtils]: 32: Hoare triple {28749#false} assume !(0 == ~E_5~0); {28749#false} is VALID [2022-02-21 04:23:05,757 INFO L290 TraceCheckUtils]: 33: Hoare triple {28749#false} assume !(0 == ~E_6~0); {28749#false} is VALID [2022-02-21 04:23:05,757 INFO L290 TraceCheckUtils]: 34: Hoare triple {28749#false} assume !(0 == ~E_7~0); {28749#false} is VALID [2022-02-21 04:23:05,757 INFO L290 TraceCheckUtils]: 35: Hoare triple {28749#false} assume 0 == ~E_8~0;~E_8~0 := 1; {28749#false} is VALID [2022-02-21 04:23:05,757 INFO L290 TraceCheckUtils]: 36: Hoare triple {28749#false} assume !(0 == ~E_9~0); {28749#false} is VALID [2022-02-21 04:23:05,757 INFO L290 TraceCheckUtils]: 37: Hoare triple {28749#false} assume !(0 == ~E_10~0); {28749#false} is VALID [2022-02-21 04:23:05,758 INFO L290 TraceCheckUtils]: 38: Hoare triple {28749#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28749#false} is VALID [2022-02-21 04:23:05,758 INFO L290 TraceCheckUtils]: 39: Hoare triple {28749#false} assume 1 == ~m_pc~0; {28749#false} is VALID [2022-02-21 04:23:05,758 INFO L290 TraceCheckUtils]: 40: Hoare triple {28749#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {28749#false} is VALID [2022-02-21 04:23:05,758 INFO L290 TraceCheckUtils]: 41: Hoare triple {28749#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28749#false} is VALID [2022-02-21 04:23:05,758 INFO L290 TraceCheckUtils]: 42: Hoare triple {28749#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28749#false} is VALID [2022-02-21 04:23:05,758 INFO L290 TraceCheckUtils]: 43: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp~1#1); {28749#false} is VALID [2022-02-21 04:23:05,758 INFO L290 TraceCheckUtils]: 44: Hoare triple {28749#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28749#false} is VALID [2022-02-21 04:23:05,759 INFO L290 TraceCheckUtils]: 45: Hoare triple {28749#false} assume !(1 == ~t1_pc~0); {28749#false} is VALID [2022-02-21 04:23:05,759 INFO L290 TraceCheckUtils]: 46: Hoare triple {28749#false} is_transmit1_triggered_~__retres1~1#1 := 0; {28749#false} is VALID [2022-02-21 04:23:05,759 INFO L290 TraceCheckUtils]: 47: Hoare triple {28749#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28749#false} is VALID [2022-02-21 04:23:05,759 INFO L290 TraceCheckUtils]: 48: Hoare triple {28749#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28749#false} is VALID [2022-02-21 04:23:05,759 INFO L290 TraceCheckUtils]: 49: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___0~0#1); {28749#false} is VALID [2022-02-21 04:23:05,759 INFO L290 TraceCheckUtils]: 50: Hoare triple {28749#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28749#false} is VALID [2022-02-21 04:23:05,760 INFO L290 TraceCheckUtils]: 51: Hoare triple {28749#false} assume 1 == ~t2_pc~0; {28749#false} is VALID [2022-02-21 04:23:05,760 INFO L290 TraceCheckUtils]: 52: Hoare triple {28749#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28749#false} is VALID [2022-02-21 04:23:05,760 INFO L290 TraceCheckUtils]: 53: Hoare triple {28749#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28749#false} is VALID [2022-02-21 04:23:05,760 INFO L290 TraceCheckUtils]: 54: Hoare triple {28749#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28749#false} is VALID [2022-02-21 04:23:05,760 INFO L290 TraceCheckUtils]: 55: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___1~0#1); {28749#false} is VALID [2022-02-21 04:23:05,760 INFO L290 TraceCheckUtils]: 56: Hoare triple {28749#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28749#false} is VALID [2022-02-21 04:23:05,760 INFO L290 TraceCheckUtils]: 57: Hoare triple {28749#false} assume 1 == ~t3_pc~0; {28749#false} is VALID [2022-02-21 04:23:05,761 INFO L290 TraceCheckUtils]: 58: Hoare triple {28749#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28749#false} is VALID [2022-02-21 04:23:05,761 INFO L290 TraceCheckUtils]: 59: Hoare triple {28749#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28749#false} is VALID [2022-02-21 04:23:05,761 INFO L290 TraceCheckUtils]: 60: Hoare triple {28749#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28749#false} is VALID [2022-02-21 04:23:05,761 INFO L290 TraceCheckUtils]: 61: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___2~0#1); {28749#false} is VALID [2022-02-21 04:23:05,761 INFO L290 TraceCheckUtils]: 62: Hoare triple {28749#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28749#false} is VALID [2022-02-21 04:23:05,761 INFO L290 TraceCheckUtils]: 63: Hoare triple {28749#false} assume !(1 == ~t4_pc~0); {28749#false} is VALID [2022-02-21 04:23:05,762 INFO L290 TraceCheckUtils]: 64: Hoare triple {28749#false} is_transmit4_triggered_~__retres1~4#1 := 0; {28749#false} is VALID [2022-02-21 04:23:05,762 INFO L290 TraceCheckUtils]: 65: Hoare triple {28749#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28749#false} is VALID [2022-02-21 04:23:05,762 INFO L290 TraceCheckUtils]: 66: Hoare triple {28749#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28749#false} is VALID [2022-02-21 04:23:05,762 INFO L290 TraceCheckUtils]: 67: Hoare triple {28749#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {28749#false} is VALID [2022-02-21 04:23:05,762 INFO L290 TraceCheckUtils]: 68: Hoare triple {28749#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28749#false} is VALID [2022-02-21 04:23:05,762 INFO L290 TraceCheckUtils]: 69: Hoare triple {28749#false} assume 1 == ~t5_pc~0; {28749#false} is VALID [2022-02-21 04:23:05,762 INFO L290 TraceCheckUtils]: 70: Hoare triple {28749#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {28749#false} is VALID [2022-02-21 04:23:05,763 INFO L290 TraceCheckUtils]: 71: Hoare triple {28749#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28749#false} is VALID [2022-02-21 04:23:05,763 INFO L290 TraceCheckUtils]: 72: Hoare triple {28749#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28749#false} is VALID [2022-02-21 04:23:05,763 INFO L290 TraceCheckUtils]: 73: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___4~0#1); {28749#false} is VALID [2022-02-21 04:23:05,763 INFO L290 TraceCheckUtils]: 74: Hoare triple {28749#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28749#false} is VALID [2022-02-21 04:23:05,763 INFO L290 TraceCheckUtils]: 75: Hoare triple {28749#false} assume !(1 == ~t6_pc~0); {28749#false} is VALID [2022-02-21 04:23:05,763 INFO L290 TraceCheckUtils]: 76: Hoare triple {28749#false} is_transmit6_triggered_~__retres1~6#1 := 0; {28749#false} is VALID [2022-02-21 04:23:05,764 INFO L290 TraceCheckUtils]: 77: Hoare triple {28749#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28749#false} is VALID [2022-02-21 04:23:05,764 INFO L290 TraceCheckUtils]: 78: Hoare triple {28749#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {28749#false} is VALID [2022-02-21 04:23:05,764 INFO L290 TraceCheckUtils]: 79: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___5~0#1); {28749#false} is VALID [2022-02-21 04:23:05,764 INFO L290 TraceCheckUtils]: 80: Hoare triple {28749#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28749#false} is VALID [2022-02-21 04:23:05,764 INFO L290 TraceCheckUtils]: 81: Hoare triple {28749#false} assume 1 == ~t7_pc~0; {28749#false} is VALID [2022-02-21 04:23:05,764 INFO L290 TraceCheckUtils]: 82: Hoare triple {28749#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28749#false} is VALID [2022-02-21 04:23:05,765 INFO L290 TraceCheckUtils]: 83: Hoare triple {28749#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28749#false} is VALID [2022-02-21 04:23:05,765 INFO L290 TraceCheckUtils]: 84: Hoare triple {28749#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {28749#false} is VALID [2022-02-21 04:23:05,765 INFO L290 TraceCheckUtils]: 85: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___6~0#1); {28749#false} is VALID [2022-02-21 04:23:05,765 INFO L290 TraceCheckUtils]: 86: Hoare triple {28749#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28749#false} is VALID [2022-02-21 04:23:05,765 INFO L290 TraceCheckUtils]: 87: Hoare triple {28749#false} assume !(1 == ~t8_pc~0); {28749#false} is VALID [2022-02-21 04:23:05,765 INFO L290 TraceCheckUtils]: 88: Hoare triple {28749#false} is_transmit8_triggered_~__retres1~8#1 := 0; {28749#false} is VALID [2022-02-21 04:23:05,765 INFO L290 TraceCheckUtils]: 89: Hoare triple {28749#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28749#false} is VALID [2022-02-21 04:23:05,766 INFO L290 TraceCheckUtils]: 90: Hoare triple {28749#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {28749#false} is VALID [2022-02-21 04:23:05,766 INFO L290 TraceCheckUtils]: 91: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___7~0#1); {28749#false} is VALID [2022-02-21 04:23:05,766 INFO L290 TraceCheckUtils]: 92: Hoare triple {28749#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {28749#false} is VALID [2022-02-21 04:23:05,766 INFO L290 TraceCheckUtils]: 93: Hoare triple {28749#false} assume 1 == ~t9_pc~0; {28749#false} is VALID [2022-02-21 04:23:05,766 INFO L290 TraceCheckUtils]: 94: Hoare triple {28749#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {28749#false} is VALID [2022-02-21 04:23:05,766 INFO L290 TraceCheckUtils]: 95: Hoare triple {28749#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {28749#false} is VALID [2022-02-21 04:23:05,766 INFO L290 TraceCheckUtils]: 96: Hoare triple {28749#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {28749#false} is VALID [2022-02-21 04:23:05,767 INFO L290 TraceCheckUtils]: 97: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___8~0#1); {28749#false} is VALID [2022-02-21 04:23:05,767 INFO L290 TraceCheckUtils]: 98: Hoare triple {28749#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {28749#false} is VALID [2022-02-21 04:23:05,767 INFO L290 TraceCheckUtils]: 99: Hoare triple {28749#false} assume !(1 == ~t10_pc~0); {28749#false} is VALID [2022-02-21 04:23:05,767 INFO L290 TraceCheckUtils]: 100: Hoare triple {28749#false} is_transmit10_triggered_~__retres1~10#1 := 0; {28749#false} is VALID [2022-02-21 04:23:05,767 INFO L290 TraceCheckUtils]: 101: Hoare triple {28749#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {28749#false} is VALID [2022-02-21 04:23:05,767 INFO L290 TraceCheckUtils]: 102: Hoare triple {28749#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {28749#false} is VALID [2022-02-21 04:23:05,768 INFO L290 TraceCheckUtils]: 103: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___9~0#1); {28749#false} is VALID [2022-02-21 04:23:05,768 INFO L290 TraceCheckUtils]: 104: Hoare triple {28749#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28749#false} is VALID [2022-02-21 04:23:05,768 INFO L290 TraceCheckUtils]: 105: Hoare triple {28749#false} assume !(1 == ~M_E~0); {28749#false} is VALID [2022-02-21 04:23:05,768 INFO L290 TraceCheckUtils]: 106: Hoare triple {28749#false} assume !(1 == ~T1_E~0); {28749#false} is VALID [2022-02-21 04:23:05,768 INFO L290 TraceCheckUtils]: 107: Hoare triple {28749#false} assume !(1 == ~T2_E~0); {28749#false} is VALID [2022-02-21 04:23:05,768 INFO L290 TraceCheckUtils]: 108: Hoare triple {28749#false} assume !(1 == ~T3_E~0); {28749#false} is VALID [2022-02-21 04:23:05,769 INFO L290 TraceCheckUtils]: 109: Hoare triple {28749#false} assume !(1 == ~T4_E~0); {28749#false} is VALID [2022-02-21 04:23:05,769 INFO L290 TraceCheckUtils]: 110: Hoare triple {28749#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28749#false} is VALID [2022-02-21 04:23:05,769 INFO L290 TraceCheckUtils]: 111: Hoare triple {28749#false} assume !(1 == ~T6_E~0); {28749#false} is VALID [2022-02-21 04:23:05,769 INFO L290 TraceCheckUtils]: 112: Hoare triple {28749#false} assume !(1 == ~T7_E~0); {28749#false} is VALID [2022-02-21 04:23:05,769 INFO L290 TraceCheckUtils]: 113: Hoare triple {28749#false} assume !(1 == ~T8_E~0); {28749#false} is VALID [2022-02-21 04:23:05,769 INFO L290 TraceCheckUtils]: 114: Hoare triple {28749#false} assume !(1 == ~T9_E~0); {28749#false} is VALID [2022-02-21 04:23:05,769 INFO L290 TraceCheckUtils]: 115: Hoare triple {28749#false} assume !(1 == ~T10_E~0); {28749#false} is VALID [2022-02-21 04:23:05,770 INFO L290 TraceCheckUtils]: 116: Hoare triple {28749#false} assume !(1 == ~E_M~0); {28749#false} is VALID [2022-02-21 04:23:05,770 INFO L290 TraceCheckUtils]: 117: Hoare triple {28749#false} assume !(1 == ~E_1~0); {28749#false} is VALID [2022-02-21 04:23:05,770 INFO L290 TraceCheckUtils]: 118: Hoare triple {28749#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28749#false} is VALID [2022-02-21 04:23:05,770 INFO L290 TraceCheckUtils]: 119: Hoare triple {28749#false} assume !(1 == ~E_3~0); {28749#false} is VALID [2022-02-21 04:23:05,770 INFO L290 TraceCheckUtils]: 120: Hoare triple {28749#false} assume !(1 == ~E_4~0); {28749#false} is VALID [2022-02-21 04:23:05,770 INFO L290 TraceCheckUtils]: 121: Hoare triple {28749#false} assume !(1 == ~E_5~0); {28749#false} is VALID [2022-02-21 04:23:05,770 INFO L290 TraceCheckUtils]: 122: Hoare triple {28749#false} assume !(1 == ~E_6~0); {28749#false} is VALID [2022-02-21 04:23:05,771 INFO L290 TraceCheckUtils]: 123: Hoare triple {28749#false} assume !(1 == ~E_7~0); {28749#false} is VALID [2022-02-21 04:23:05,771 INFO L290 TraceCheckUtils]: 124: Hoare triple {28749#false} assume !(1 == ~E_8~0); {28749#false} is VALID [2022-02-21 04:23:05,771 INFO L290 TraceCheckUtils]: 125: Hoare triple {28749#false} assume !(1 == ~E_9~0); {28749#false} is VALID [2022-02-21 04:23:05,771 INFO L290 TraceCheckUtils]: 126: Hoare triple {28749#false} assume 1 == ~E_10~0;~E_10~0 := 2; {28749#false} is VALID [2022-02-21 04:23:05,771 INFO L290 TraceCheckUtils]: 127: Hoare triple {28749#false} assume { :end_inline_reset_delta_events } true; {28749#false} is VALID [2022-02-21 04:23:05,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:05,772 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:05,772 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874364082] [2022-02-21 04:23:05,772 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874364082] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:05,772 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:05,772 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:05,773 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443265537] [2022-02-21 04:23:05,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:05,773 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:05,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:05,774 INFO L85 PathProgramCache]: Analyzing trace with hash 291636822, now seen corresponding path program 1 times [2022-02-21 04:23:05,774 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:05,777 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910770953] [2022-02-21 04:23:05,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:05,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:05,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,809 INFO L290 TraceCheckUtils]: 0: Hoare triple {28751#true} assume !false; {28751#true} is VALID [2022-02-21 04:23:05,809 INFO L290 TraceCheckUtils]: 1: Hoare triple {28751#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {28751#true} is VALID [2022-02-21 04:23:05,810 INFO L290 TraceCheckUtils]: 2: Hoare triple {28751#true} assume !false; {28751#true} is VALID [2022-02-21 04:23:05,810 INFO L290 TraceCheckUtils]: 3: Hoare triple {28751#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {28751#true} is VALID [2022-02-21 04:23:05,810 INFO L290 TraceCheckUtils]: 4: Hoare triple {28751#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {28751#true} is VALID [2022-02-21 04:23:05,810 INFO L290 TraceCheckUtils]: 5: Hoare triple {28751#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {28751#true} is VALID [2022-02-21 04:23:05,810 INFO L290 TraceCheckUtils]: 6: Hoare triple {28751#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {28751#true} is VALID [2022-02-21 04:23:05,810 INFO L290 TraceCheckUtils]: 7: Hoare triple {28751#true} assume !(0 != eval_~tmp~0#1); {28751#true} is VALID [2022-02-21 04:23:05,810 INFO L290 TraceCheckUtils]: 8: Hoare triple {28751#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {28751#true} is VALID [2022-02-21 04:23:05,811 INFO L290 TraceCheckUtils]: 9: Hoare triple {28751#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {28751#true} is VALID [2022-02-21 04:23:05,811 INFO L290 TraceCheckUtils]: 10: Hoare triple {28751#true} assume 0 == ~M_E~0;~M_E~0 := 1; {28751#true} is VALID [2022-02-21 04:23:05,811 INFO L290 TraceCheckUtils]: 11: Hoare triple {28751#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {28751#true} is VALID [2022-02-21 04:23:05,811 INFO L290 TraceCheckUtils]: 12: Hoare triple {28751#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {28751#true} is VALID [2022-02-21 04:23:05,811 INFO L290 TraceCheckUtils]: 13: Hoare triple {28751#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28751#true} is VALID [2022-02-21 04:23:05,811 INFO L290 TraceCheckUtils]: 14: Hoare triple {28751#true} assume !(0 == ~T4_E~0); {28751#true} is VALID [2022-02-21 04:23:05,811 INFO L290 TraceCheckUtils]: 15: Hoare triple {28751#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {28751#true} is VALID [2022-02-21 04:23:05,812 INFO L290 TraceCheckUtils]: 16: Hoare triple {28751#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,812 INFO L290 TraceCheckUtils]: 17: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,812 INFO L290 TraceCheckUtils]: 18: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,813 INFO L290 TraceCheckUtils]: 19: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,813 INFO L290 TraceCheckUtils]: 20: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,813 INFO L290 TraceCheckUtils]: 21: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,814 INFO L290 TraceCheckUtils]: 22: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,814 INFO L290 TraceCheckUtils]: 23: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,814 INFO L290 TraceCheckUtils]: 24: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,814 INFO L290 TraceCheckUtils]: 25: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,815 INFO L290 TraceCheckUtils]: 26: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,815 INFO L290 TraceCheckUtils]: 27: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,815 INFO L290 TraceCheckUtils]: 28: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,816 INFO L290 TraceCheckUtils]: 29: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,816 INFO L290 TraceCheckUtils]: 30: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,816 INFO L290 TraceCheckUtils]: 31: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,817 INFO L290 TraceCheckUtils]: 32: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,817 INFO L290 TraceCheckUtils]: 33: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,817 INFO L290 TraceCheckUtils]: 34: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,817 INFO L290 TraceCheckUtils]: 35: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,818 INFO L290 TraceCheckUtils]: 36: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,818 INFO L290 TraceCheckUtils]: 37: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,818 INFO L290 TraceCheckUtils]: 38: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,819 INFO L290 TraceCheckUtils]: 39: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,819 INFO L290 TraceCheckUtils]: 40: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,819 INFO L290 TraceCheckUtils]: 41: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,819 INFO L290 TraceCheckUtils]: 42: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,820 INFO L290 TraceCheckUtils]: 43: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,820 INFO L290 TraceCheckUtils]: 44: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,820 INFO L290 TraceCheckUtils]: 45: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,821 INFO L290 TraceCheckUtils]: 46: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,821 INFO L290 TraceCheckUtils]: 47: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,821 INFO L290 TraceCheckUtils]: 48: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,821 INFO L290 TraceCheckUtils]: 49: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,822 INFO L290 TraceCheckUtils]: 50: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,822 INFO L290 TraceCheckUtils]: 51: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,822 INFO L290 TraceCheckUtils]: 52: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,823 INFO L290 TraceCheckUtils]: 53: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,823 INFO L290 TraceCheckUtils]: 54: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,823 INFO L290 TraceCheckUtils]: 55: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,824 INFO L290 TraceCheckUtils]: 56: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,824 INFO L290 TraceCheckUtils]: 57: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,824 INFO L290 TraceCheckUtils]: 58: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,824 INFO L290 TraceCheckUtils]: 59: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,825 INFO L290 TraceCheckUtils]: 60: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,825 INFO L290 TraceCheckUtils]: 61: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,825 INFO L290 TraceCheckUtils]: 62: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,826 INFO L290 TraceCheckUtils]: 63: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,826 INFO L290 TraceCheckUtils]: 64: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,826 INFO L290 TraceCheckUtils]: 65: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,827 INFO L290 TraceCheckUtils]: 66: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,827 INFO L290 TraceCheckUtils]: 67: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,827 INFO L290 TraceCheckUtils]: 68: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,827 INFO L290 TraceCheckUtils]: 69: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,828 INFO L290 TraceCheckUtils]: 70: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,828 INFO L290 TraceCheckUtils]: 71: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,828 INFO L290 TraceCheckUtils]: 72: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,829 INFO L290 TraceCheckUtils]: 73: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,829 INFO L290 TraceCheckUtils]: 74: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,829 INFO L290 TraceCheckUtils]: 75: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,829 INFO L290 TraceCheckUtils]: 76: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,830 INFO L290 TraceCheckUtils]: 77: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,830 INFO L290 TraceCheckUtils]: 78: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,830 INFO L290 TraceCheckUtils]: 79: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,831 INFO L290 TraceCheckUtils]: 80: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,831 INFO L290 TraceCheckUtils]: 81: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,831 INFO L290 TraceCheckUtils]: 82: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,832 INFO L290 TraceCheckUtils]: 83: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,832 INFO L290 TraceCheckUtils]: 84: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,832 INFO L290 TraceCheckUtils]: 85: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,832 INFO L290 TraceCheckUtils]: 86: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,833 INFO L290 TraceCheckUtils]: 87: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,833 INFO L290 TraceCheckUtils]: 88: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,833 INFO L290 TraceCheckUtils]: 89: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,834 INFO L290 TraceCheckUtils]: 90: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,834 INFO L290 TraceCheckUtils]: 91: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,834 INFO L290 TraceCheckUtils]: 92: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,834 INFO L290 TraceCheckUtils]: 93: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,835 INFO L290 TraceCheckUtils]: 94: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,835 INFO L290 TraceCheckUtils]: 95: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,835 INFO L290 TraceCheckUtils]: 96: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,836 INFO L290 TraceCheckUtils]: 97: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,836 INFO L290 TraceCheckUtils]: 98: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,836 INFO L290 TraceCheckUtils]: 99: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,837 INFO L290 TraceCheckUtils]: 100: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,837 INFO L290 TraceCheckUtils]: 101: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,837 INFO L290 TraceCheckUtils]: 102: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,837 INFO L290 TraceCheckUtils]: 103: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,838 INFO L290 TraceCheckUtils]: 104: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28753#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,838 INFO L290 TraceCheckUtils]: 105: Hoare triple {28753#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {28752#false} is VALID [2022-02-21 04:23:05,838 INFO L290 TraceCheckUtils]: 106: Hoare triple {28752#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,838 INFO L290 TraceCheckUtils]: 107: Hoare triple {28752#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,838 INFO L290 TraceCheckUtils]: 108: Hoare triple {28752#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,839 INFO L290 TraceCheckUtils]: 109: Hoare triple {28752#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,839 INFO L290 TraceCheckUtils]: 110: Hoare triple {28752#false} assume 1 == ~E_M~0;~E_M~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,839 INFO L290 TraceCheckUtils]: 111: Hoare triple {28752#false} assume 1 == ~E_1~0;~E_1~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,839 INFO L290 TraceCheckUtils]: 112: Hoare triple {28752#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,839 INFO L290 TraceCheckUtils]: 113: Hoare triple {28752#false} assume !(1 == ~E_3~0); {28752#false} is VALID [2022-02-21 04:23:05,839 INFO L290 TraceCheckUtils]: 114: Hoare triple {28752#false} assume 1 == ~E_4~0;~E_4~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,839 INFO L290 TraceCheckUtils]: 115: Hoare triple {28752#false} assume 1 == ~E_5~0;~E_5~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,840 INFO L290 TraceCheckUtils]: 116: Hoare triple {28752#false} assume 1 == ~E_6~0;~E_6~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,840 INFO L290 TraceCheckUtils]: 117: Hoare triple {28752#false} assume 1 == ~E_7~0;~E_7~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,840 INFO L290 TraceCheckUtils]: 118: Hoare triple {28752#false} assume 1 == ~E_8~0;~E_8~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,840 INFO L290 TraceCheckUtils]: 119: Hoare triple {28752#false} assume 1 == ~E_9~0;~E_9~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,840 INFO L290 TraceCheckUtils]: 120: Hoare triple {28752#false} assume 1 == ~E_10~0;~E_10~0 := 2; {28752#false} is VALID [2022-02-21 04:23:05,840 INFO L290 TraceCheckUtils]: 121: Hoare triple {28752#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {28752#false} is VALID [2022-02-21 04:23:05,840 INFO L290 TraceCheckUtils]: 122: Hoare triple {28752#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {28752#false} is VALID [2022-02-21 04:23:05,841 INFO L290 TraceCheckUtils]: 123: Hoare triple {28752#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {28752#false} is VALID [2022-02-21 04:23:05,841 INFO L290 TraceCheckUtils]: 124: Hoare triple {28752#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {28752#false} is VALID [2022-02-21 04:23:05,841 INFO L290 TraceCheckUtils]: 125: Hoare triple {28752#false} assume !(0 == start_simulation_~tmp~3#1); {28752#false} is VALID [2022-02-21 04:23:05,841 INFO L290 TraceCheckUtils]: 126: Hoare triple {28752#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {28752#false} is VALID [2022-02-21 04:23:05,841 INFO L290 TraceCheckUtils]: 127: Hoare triple {28752#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {28752#false} is VALID [2022-02-21 04:23:05,841 INFO L290 TraceCheckUtils]: 128: Hoare triple {28752#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {28752#false} is VALID [2022-02-21 04:23:05,841 INFO L290 TraceCheckUtils]: 129: Hoare triple {28752#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {28752#false} is VALID [2022-02-21 04:23:05,842 INFO L290 TraceCheckUtils]: 130: Hoare triple {28752#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {28752#false} is VALID [2022-02-21 04:23:05,842 INFO L290 TraceCheckUtils]: 131: Hoare triple {28752#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {28752#false} is VALID [2022-02-21 04:23:05,842 INFO L290 TraceCheckUtils]: 132: Hoare triple {28752#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {28752#false} is VALID [2022-02-21 04:23:05,842 INFO L290 TraceCheckUtils]: 133: Hoare triple {28752#false} assume !(0 != start_simulation_~tmp___0~1#1); {28752#false} is VALID [2022-02-21 04:23:05,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:05,843 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:05,843 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910770953] [2022-02-21 04:23:05,843 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1910770953] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:05,843 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:05,843 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:05,843 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342973691] [2022-02-21 04:23:05,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:05,844 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:05,844 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:05,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:05,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:05,845 INFO L87 Difference]: Start difference. First operand 1366 states and 2028 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:06,853 INFO L93 Difference]: Finished difference Result 1366 states and 2027 transitions. [2022-02-21 04:23:06,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:06,854 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,961 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:06,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:07,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2027 transitions. [2022-02-21 04:23:07,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:07,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:07,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:07,105 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2022-02-21 04:23:07,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:07,124 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:07,126 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2027 transitions. Second operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,128 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2027 transitions. Second operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,130 INFO L87 Difference]: Start difference. First operand 1366 states and 2027 transitions. Second operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,196 INFO L93 Difference]: Finished difference Result 1366 states and 2027 transitions. [2022-02-21 04:23:07,196 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,198 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,198 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,201 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,203 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,269 INFO L93 Difference]: Finished difference Result 1366 states and 2027 transitions. [2022-02-21 04:23:07,269 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,272 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,272 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,272 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:07,272 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:07,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2027 transitions. [2022-02-21 04:23:07,344 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2022-02-21 04:23:07,344 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2022-02-21 04:23:07,344 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:07,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2027 transitions. [2022-02-21 04:23:07,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:07,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:07,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:07,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,349 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,350 INFO L791 eck$LassoCheckResult]: Stem: 31177#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 31178#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 31386#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30169#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30170#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 31410#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31369#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31370#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31400#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30478#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30479#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30584#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30829#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30760#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30480#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30142#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30143#L1036 assume !(0 == ~M_E~0); 30241#L1036-2 assume !(0 == ~T1_E~0); 31117#L1041-1 assume !(0 == ~T2_E~0); 31118#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30516#L1051-1 assume !(0 == ~T4_E~0); 30517#L1056-1 assume !(0 == ~T5_E~0); 31255#L1061-1 assume !(0 == ~T6_E~0); 30414#L1066-1 assume !(0 == ~T7_E~0); 30415#L1071-1 assume !(0 == ~T8_E~0); 31238#L1076-1 assume !(0 == ~T9_E~0); 30309#L1081-1 assume !(0 == ~T10_E~0); 30310#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 30713#L1091-1 assume !(0 == ~E_1~0); 31414#L1096-1 assume !(0 == ~E_2~0); 31415#L1101-1 assume !(0 == ~E_3~0); 30774#L1106-1 assume !(0 == ~E_4~0); 30775#L1111-1 assume !(0 == ~E_5~0); 30931#L1116-1 assume !(0 == ~E_6~0); 30932#L1121-1 assume !(0 == ~E_7~0); 30767#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 30768#L1131-1 assume !(0 == ~E_9~0); 31018#L1136-1 assume !(0 == ~E_10~0); 31125#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31282#L514 assume 1 == ~m_pc~0; 31245#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30787#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30704#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30705#L1285 assume !(0 != activate_threads_~tmp~1#1); 31450#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30433#L533 assume !(1 == ~t1_pc~0); 30434#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30947#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30820#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30821#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 31147#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31148#L552 assume 1 == ~t2_pc~0; 30658#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30659#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31226#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31227#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 30799#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30800#L571 assume 1 == ~t3_pc~0; 30977#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30978#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30347#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30348#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 30937#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30223#L590 assume !(1 == ~t4_pc~0); 30224#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30990#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31222#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31223#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31179#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30933#L609 assume 1 == ~t5_pc~0; 30934#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31448#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30260#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30261#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 30928#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30929#L628 assume !(1 == ~t6_pc~0); 30862#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30861#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31433#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31434#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 31218#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31219#L647 assume 1 == ~t7_pc~0; 30776#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30777#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31053#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30779#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 30780#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31480#L666 assume !(1 == ~t8_pc~0); 30563#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30564#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30798#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30954#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 30710#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30711#L685 assume 1 == ~t9_pc~0; 31457#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31354#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31346#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30736#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 30737#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31089#L704 assume !(1 == ~t10_pc~0); 30728#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 30727#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31253#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30279#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 30280#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30527#L1154 assume !(1 == ~M_E~0); 31206#L1154-2 assume !(1 == ~T1_E~0); 30499#L1159-1 assume !(1 == ~T2_E~0); 30500#L1164-1 assume !(1 == ~T3_E~0); 30952#L1169-1 assume !(1 == ~T4_E~0); 30824#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30629#L1179-1 assume !(1 == ~T6_E~0); 30485#L1184-1 assume !(1 == ~T7_E~0); 30486#L1189-1 assume !(1 == ~T8_E~0); 30561#L1194-1 assume !(1 == ~T9_E~0); 30700#L1199-1 assume !(1 == ~T10_E~0); 30644#L1204-1 assume !(1 == ~E_M~0); 30645#L1209-1 assume !(1 == ~E_1~0); 31171#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31172#L1219-1 assume !(1 == ~E_3~0); 31473#L1224-1 assume !(1 == ~E_4~0); 30972#L1229-1 assume !(1 == ~E_5~0); 30370#L1234-1 assume !(1 == ~E_6~0); 30371#L1239-1 assume !(1 == ~E_7~0); 30429#L1244-1 assume !(1 == ~E_8~0); 30430#L1249-1 assume !(1 == ~E_9~0); 31243#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30272#L1259-1 assume { :end_inline_reset_delta_events } true; 30273#L1565-2 [2022-02-21 04:23:07,350 INFO L793 eck$LassoCheckResult]: Loop: 30273#L1565-2 assume !false; 31181#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30665#L1011 assume !false; 30666#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30715#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30469#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 31334#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30493#L866 assume !(0 != eval_~tmp~0#1); 30495#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31082#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31083#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31249#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31435#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31308#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31309#L1051-3 assume !(0 == ~T4_E~0); 31250#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30513#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30514#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30515#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31436#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30264#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30265#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30319#L1091-3 assume !(0 == ~E_1~0); 30320#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31402#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31403#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31432#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31393#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31099#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31100#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31324#L1131-3 assume !(0 == ~E_9~0); 31325#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31484#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31103#L514-36 assume 1 == ~m_pc~0; 31104#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30688#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30689#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31146#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30572#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30573#L533-36 assume 1 == ~t1_pc~0; 30848#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30941#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31244#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31192#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30995#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30996#L552-36 assume 1 == ~t2_pc~0; 30565#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30567#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30386#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30387#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30539#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30540#L571-36 assume 1 == ~t3_pc~0; 30924#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30630#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30631#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30751#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31307#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30600#L590-36 assume !(1 == ~t4_pc~0); 30601#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 31207#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30785#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30786#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31286#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31287#L609-36 assume 1 == ~t5_pc~0; 31162#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30997#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30815#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30816#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31069#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30895#L628-36 assume 1 == ~t6_pc~0; 30754#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30755#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31182#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31183#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31107#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31108#L647-36 assume 1 == ~t7_pc~0; 31036#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30293#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30294#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30313#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 30314#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31208#L666-36 assume 1 == ~t8_pc~0; 30496#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30497#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31397#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31398#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30656#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30657#L685-36 assume !(1 == ~t9_pc~0); 30397#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30398#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30913#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30914#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30795#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30796#L704-36 assume 1 == ~t10_pc~0; 30388#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30389#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31149#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31150#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30418#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30419#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31385#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31263#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31264#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31444#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30724#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30725#L1179-3 assume !(1 == ~T6_E~0); 31356#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30295#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30296#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30671#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30672#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30968#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30158#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30159#L1219-3 assume !(1 == ~E_3~0); 31157#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31158#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31180#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30431#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30432#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31015#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31394#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 31160#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 31161#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30239#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30986#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30987#L1584 assume !(0 == start_simulation_~tmp~3#1); 31115#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30445#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30140#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30587#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 30588#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30772#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30739#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30740#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 30273#L1565-2 [2022-02-21 04:23:07,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:07,351 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2022-02-21 04:23:07,351 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:07,351 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942522887] [2022-02-21 04:23:07,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:07,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:07,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:07,376 INFO L290 TraceCheckUtils]: 0: Hoare triple {34221#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {34221#true} is VALID [2022-02-21 04:23:07,376 INFO L290 TraceCheckUtils]: 1: Hoare triple {34221#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,377 INFO L290 TraceCheckUtils]: 2: Hoare triple {34223#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,377 INFO L290 TraceCheckUtils]: 3: Hoare triple {34223#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,377 INFO L290 TraceCheckUtils]: 4: Hoare triple {34223#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,378 INFO L290 TraceCheckUtils]: 5: Hoare triple {34223#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,378 INFO L290 TraceCheckUtils]: 6: Hoare triple {34223#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,378 INFO L290 TraceCheckUtils]: 7: Hoare triple {34223#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,379 INFO L290 TraceCheckUtils]: 8: Hoare triple {34223#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,379 INFO L290 TraceCheckUtils]: 9: Hoare triple {34223#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,380 INFO L290 TraceCheckUtils]: 10: Hoare triple {34223#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {34223#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,380 INFO L290 TraceCheckUtils]: 11: Hoare triple {34223#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {34222#false} is VALID [2022-02-21 04:23:07,380 INFO L290 TraceCheckUtils]: 12: Hoare triple {34222#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {34222#false} is VALID [2022-02-21 04:23:07,380 INFO L290 TraceCheckUtils]: 13: Hoare triple {34222#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {34222#false} is VALID [2022-02-21 04:23:07,380 INFO L290 TraceCheckUtils]: 14: Hoare triple {34222#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {34222#false} is VALID [2022-02-21 04:23:07,381 INFO L290 TraceCheckUtils]: 15: Hoare triple {34222#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34222#false} is VALID [2022-02-21 04:23:07,381 INFO L290 TraceCheckUtils]: 16: Hoare triple {34222#false} assume !(0 == ~M_E~0); {34222#false} is VALID [2022-02-21 04:23:07,381 INFO L290 TraceCheckUtils]: 17: Hoare triple {34222#false} assume !(0 == ~T1_E~0); {34222#false} is VALID [2022-02-21 04:23:07,381 INFO L290 TraceCheckUtils]: 18: Hoare triple {34222#false} assume !(0 == ~T2_E~0); {34222#false} is VALID [2022-02-21 04:23:07,381 INFO L290 TraceCheckUtils]: 19: Hoare triple {34222#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34222#false} is VALID [2022-02-21 04:23:07,381 INFO L290 TraceCheckUtils]: 20: Hoare triple {34222#false} assume !(0 == ~T4_E~0); {34222#false} is VALID [2022-02-21 04:23:07,382 INFO L290 TraceCheckUtils]: 21: Hoare triple {34222#false} assume !(0 == ~T5_E~0); {34222#false} is VALID [2022-02-21 04:23:07,382 INFO L290 TraceCheckUtils]: 22: Hoare triple {34222#false} assume !(0 == ~T6_E~0); {34222#false} is VALID [2022-02-21 04:23:07,382 INFO L290 TraceCheckUtils]: 23: Hoare triple {34222#false} assume !(0 == ~T7_E~0); {34222#false} is VALID [2022-02-21 04:23:07,382 INFO L290 TraceCheckUtils]: 24: Hoare triple {34222#false} assume !(0 == ~T8_E~0); {34222#false} is VALID [2022-02-21 04:23:07,382 INFO L290 TraceCheckUtils]: 25: Hoare triple {34222#false} assume !(0 == ~T9_E~0); {34222#false} is VALID [2022-02-21 04:23:07,382 INFO L290 TraceCheckUtils]: 26: Hoare triple {34222#false} assume !(0 == ~T10_E~0); {34222#false} is VALID [2022-02-21 04:23:07,383 INFO L290 TraceCheckUtils]: 27: Hoare triple {34222#false} assume 0 == ~E_M~0;~E_M~0 := 1; {34222#false} is VALID [2022-02-21 04:23:07,383 INFO L290 TraceCheckUtils]: 28: Hoare triple {34222#false} assume !(0 == ~E_1~0); {34222#false} is VALID [2022-02-21 04:23:07,383 INFO L290 TraceCheckUtils]: 29: Hoare triple {34222#false} assume !(0 == ~E_2~0); {34222#false} is VALID [2022-02-21 04:23:07,383 INFO L290 TraceCheckUtils]: 30: Hoare triple {34222#false} assume !(0 == ~E_3~0); {34222#false} is VALID [2022-02-21 04:23:07,383 INFO L290 TraceCheckUtils]: 31: Hoare triple {34222#false} assume !(0 == ~E_4~0); {34222#false} is VALID [2022-02-21 04:23:07,383 INFO L290 TraceCheckUtils]: 32: Hoare triple {34222#false} assume !(0 == ~E_5~0); {34222#false} is VALID [2022-02-21 04:23:07,384 INFO L290 TraceCheckUtils]: 33: Hoare triple {34222#false} assume !(0 == ~E_6~0); {34222#false} is VALID [2022-02-21 04:23:07,384 INFO L290 TraceCheckUtils]: 34: Hoare triple {34222#false} assume !(0 == ~E_7~0); {34222#false} is VALID [2022-02-21 04:23:07,384 INFO L290 TraceCheckUtils]: 35: Hoare triple {34222#false} assume 0 == ~E_8~0;~E_8~0 := 1; {34222#false} is VALID [2022-02-21 04:23:07,384 INFO L290 TraceCheckUtils]: 36: Hoare triple {34222#false} assume !(0 == ~E_9~0); {34222#false} is VALID [2022-02-21 04:23:07,384 INFO L290 TraceCheckUtils]: 37: Hoare triple {34222#false} assume !(0 == ~E_10~0); {34222#false} is VALID [2022-02-21 04:23:07,384 INFO L290 TraceCheckUtils]: 38: Hoare triple {34222#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34222#false} is VALID [2022-02-21 04:23:07,385 INFO L290 TraceCheckUtils]: 39: Hoare triple {34222#false} assume 1 == ~m_pc~0; {34222#false} is VALID [2022-02-21 04:23:07,385 INFO L290 TraceCheckUtils]: 40: Hoare triple {34222#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34222#false} is VALID [2022-02-21 04:23:07,385 INFO L290 TraceCheckUtils]: 41: Hoare triple {34222#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34222#false} is VALID [2022-02-21 04:23:07,385 INFO L290 TraceCheckUtils]: 42: Hoare triple {34222#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34222#false} is VALID [2022-02-21 04:23:07,385 INFO L290 TraceCheckUtils]: 43: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp~1#1); {34222#false} is VALID [2022-02-21 04:23:07,385 INFO L290 TraceCheckUtils]: 44: Hoare triple {34222#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34222#false} is VALID [2022-02-21 04:23:07,386 INFO L290 TraceCheckUtils]: 45: Hoare triple {34222#false} assume !(1 == ~t1_pc~0); {34222#false} is VALID [2022-02-21 04:23:07,386 INFO L290 TraceCheckUtils]: 46: Hoare triple {34222#false} is_transmit1_triggered_~__retres1~1#1 := 0; {34222#false} is VALID [2022-02-21 04:23:07,386 INFO L290 TraceCheckUtils]: 47: Hoare triple {34222#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34222#false} is VALID [2022-02-21 04:23:07,386 INFO L290 TraceCheckUtils]: 48: Hoare triple {34222#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34222#false} is VALID [2022-02-21 04:23:07,386 INFO L290 TraceCheckUtils]: 49: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___0~0#1); {34222#false} is VALID [2022-02-21 04:23:07,386 INFO L290 TraceCheckUtils]: 50: Hoare triple {34222#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34222#false} is VALID [2022-02-21 04:23:07,387 INFO L290 TraceCheckUtils]: 51: Hoare triple {34222#false} assume 1 == ~t2_pc~0; {34222#false} is VALID [2022-02-21 04:23:07,387 INFO L290 TraceCheckUtils]: 52: Hoare triple {34222#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34222#false} is VALID [2022-02-21 04:23:07,387 INFO L290 TraceCheckUtils]: 53: Hoare triple {34222#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34222#false} is VALID [2022-02-21 04:23:07,387 INFO L290 TraceCheckUtils]: 54: Hoare triple {34222#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34222#false} is VALID [2022-02-21 04:23:07,387 INFO L290 TraceCheckUtils]: 55: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___1~0#1); {34222#false} is VALID [2022-02-21 04:23:07,387 INFO L290 TraceCheckUtils]: 56: Hoare triple {34222#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34222#false} is VALID [2022-02-21 04:23:07,388 INFO L290 TraceCheckUtils]: 57: Hoare triple {34222#false} assume 1 == ~t3_pc~0; {34222#false} is VALID [2022-02-21 04:23:07,388 INFO L290 TraceCheckUtils]: 58: Hoare triple {34222#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34222#false} is VALID [2022-02-21 04:23:07,388 INFO L290 TraceCheckUtils]: 59: Hoare triple {34222#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34222#false} is VALID [2022-02-21 04:23:07,388 INFO L290 TraceCheckUtils]: 60: Hoare triple {34222#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34222#false} is VALID [2022-02-21 04:23:07,388 INFO L290 TraceCheckUtils]: 61: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___2~0#1); {34222#false} is VALID [2022-02-21 04:23:07,388 INFO L290 TraceCheckUtils]: 62: Hoare triple {34222#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34222#false} is VALID [2022-02-21 04:23:07,389 INFO L290 TraceCheckUtils]: 63: Hoare triple {34222#false} assume !(1 == ~t4_pc~0); {34222#false} is VALID [2022-02-21 04:23:07,389 INFO L290 TraceCheckUtils]: 64: Hoare triple {34222#false} is_transmit4_triggered_~__retres1~4#1 := 0; {34222#false} is VALID [2022-02-21 04:23:07,389 INFO L290 TraceCheckUtils]: 65: Hoare triple {34222#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34222#false} is VALID [2022-02-21 04:23:07,389 INFO L290 TraceCheckUtils]: 66: Hoare triple {34222#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34222#false} is VALID [2022-02-21 04:23:07,389 INFO L290 TraceCheckUtils]: 67: Hoare triple {34222#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34222#false} is VALID [2022-02-21 04:23:07,390 INFO L290 TraceCheckUtils]: 68: Hoare triple {34222#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34222#false} is VALID [2022-02-21 04:23:07,390 INFO L290 TraceCheckUtils]: 69: Hoare triple {34222#false} assume 1 == ~t5_pc~0; {34222#false} is VALID [2022-02-21 04:23:07,390 INFO L290 TraceCheckUtils]: 70: Hoare triple {34222#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34222#false} is VALID [2022-02-21 04:23:07,390 INFO L290 TraceCheckUtils]: 71: Hoare triple {34222#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34222#false} is VALID [2022-02-21 04:23:07,390 INFO L290 TraceCheckUtils]: 72: Hoare triple {34222#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34222#false} is VALID [2022-02-21 04:23:07,390 INFO L290 TraceCheckUtils]: 73: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___4~0#1); {34222#false} is VALID [2022-02-21 04:23:07,391 INFO L290 TraceCheckUtils]: 74: Hoare triple {34222#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34222#false} is VALID [2022-02-21 04:23:07,391 INFO L290 TraceCheckUtils]: 75: Hoare triple {34222#false} assume !(1 == ~t6_pc~0); {34222#false} is VALID [2022-02-21 04:23:07,391 INFO L290 TraceCheckUtils]: 76: Hoare triple {34222#false} is_transmit6_triggered_~__retres1~6#1 := 0; {34222#false} is VALID [2022-02-21 04:23:07,391 INFO L290 TraceCheckUtils]: 77: Hoare triple {34222#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34222#false} is VALID [2022-02-21 04:23:07,391 INFO L290 TraceCheckUtils]: 78: Hoare triple {34222#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34222#false} is VALID [2022-02-21 04:23:07,391 INFO L290 TraceCheckUtils]: 79: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___5~0#1); {34222#false} is VALID [2022-02-21 04:23:07,392 INFO L290 TraceCheckUtils]: 80: Hoare triple {34222#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34222#false} is VALID [2022-02-21 04:23:07,392 INFO L290 TraceCheckUtils]: 81: Hoare triple {34222#false} assume 1 == ~t7_pc~0; {34222#false} is VALID [2022-02-21 04:23:07,392 INFO L290 TraceCheckUtils]: 82: Hoare triple {34222#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34222#false} is VALID [2022-02-21 04:23:07,392 INFO L290 TraceCheckUtils]: 83: Hoare triple {34222#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34222#false} is VALID [2022-02-21 04:23:07,392 INFO L290 TraceCheckUtils]: 84: Hoare triple {34222#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34222#false} is VALID [2022-02-21 04:23:07,392 INFO L290 TraceCheckUtils]: 85: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___6~0#1); {34222#false} is VALID [2022-02-21 04:23:07,393 INFO L290 TraceCheckUtils]: 86: Hoare triple {34222#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34222#false} is VALID [2022-02-21 04:23:07,393 INFO L290 TraceCheckUtils]: 87: Hoare triple {34222#false} assume !(1 == ~t8_pc~0); {34222#false} is VALID [2022-02-21 04:23:07,393 INFO L290 TraceCheckUtils]: 88: Hoare triple {34222#false} is_transmit8_triggered_~__retres1~8#1 := 0; {34222#false} is VALID [2022-02-21 04:23:07,393 INFO L290 TraceCheckUtils]: 89: Hoare triple {34222#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34222#false} is VALID [2022-02-21 04:23:07,393 INFO L290 TraceCheckUtils]: 90: Hoare triple {34222#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34222#false} is VALID [2022-02-21 04:23:07,393 INFO L290 TraceCheckUtils]: 91: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___7~0#1); {34222#false} is VALID [2022-02-21 04:23:07,394 INFO L290 TraceCheckUtils]: 92: Hoare triple {34222#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34222#false} is VALID [2022-02-21 04:23:07,394 INFO L290 TraceCheckUtils]: 93: Hoare triple {34222#false} assume 1 == ~t9_pc~0; {34222#false} is VALID [2022-02-21 04:23:07,394 INFO L290 TraceCheckUtils]: 94: Hoare triple {34222#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34222#false} is VALID [2022-02-21 04:23:07,394 INFO L290 TraceCheckUtils]: 95: Hoare triple {34222#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34222#false} is VALID [2022-02-21 04:23:07,394 INFO L290 TraceCheckUtils]: 96: Hoare triple {34222#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34222#false} is VALID [2022-02-21 04:23:07,394 INFO L290 TraceCheckUtils]: 97: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___8~0#1); {34222#false} is VALID [2022-02-21 04:23:07,395 INFO L290 TraceCheckUtils]: 98: Hoare triple {34222#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34222#false} is VALID [2022-02-21 04:23:07,395 INFO L290 TraceCheckUtils]: 99: Hoare triple {34222#false} assume !(1 == ~t10_pc~0); {34222#false} is VALID [2022-02-21 04:23:07,395 INFO L290 TraceCheckUtils]: 100: Hoare triple {34222#false} is_transmit10_triggered_~__retres1~10#1 := 0; {34222#false} is VALID [2022-02-21 04:23:07,395 INFO L290 TraceCheckUtils]: 101: Hoare triple {34222#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34222#false} is VALID [2022-02-21 04:23:07,395 INFO L290 TraceCheckUtils]: 102: Hoare triple {34222#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34222#false} is VALID [2022-02-21 04:23:07,396 INFO L290 TraceCheckUtils]: 103: Hoare triple {34222#false} assume !(0 != activate_threads_~tmp___9~0#1); {34222#false} is VALID [2022-02-21 04:23:07,396 INFO L290 TraceCheckUtils]: 104: Hoare triple {34222#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34222#false} is VALID [2022-02-21 04:23:07,396 INFO L290 TraceCheckUtils]: 105: Hoare triple {34222#false} assume !(1 == ~M_E~0); {34222#false} is VALID [2022-02-21 04:23:07,396 INFO L290 TraceCheckUtils]: 106: Hoare triple {34222#false} assume !(1 == ~T1_E~0); {34222#false} is VALID [2022-02-21 04:23:07,396 INFO L290 TraceCheckUtils]: 107: Hoare triple {34222#false} assume !(1 == ~T2_E~0); {34222#false} is VALID [2022-02-21 04:23:07,396 INFO L290 TraceCheckUtils]: 108: Hoare triple {34222#false} assume !(1 == ~T3_E~0); {34222#false} is VALID [2022-02-21 04:23:07,397 INFO L290 TraceCheckUtils]: 109: Hoare triple {34222#false} assume !(1 == ~T4_E~0); {34222#false} is VALID [2022-02-21 04:23:07,397 INFO L290 TraceCheckUtils]: 110: Hoare triple {34222#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34222#false} is VALID [2022-02-21 04:23:07,397 INFO L290 TraceCheckUtils]: 111: Hoare triple {34222#false} assume !(1 == ~T6_E~0); {34222#false} is VALID [2022-02-21 04:23:07,397 INFO L290 TraceCheckUtils]: 112: Hoare triple {34222#false} assume !(1 == ~T7_E~0); {34222#false} is VALID [2022-02-21 04:23:07,397 INFO L290 TraceCheckUtils]: 113: Hoare triple {34222#false} assume !(1 == ~T8_E~0); {34222#false} is VALID [2022-02-21 04:23:07,397 INFO L290 TraceCheckUtils]: 114: Hoare triple {34222#false} assume !(1 == ~T9_E~0); {34222#false} is VALID [2022-02-21 04:23:07,398 INFO L290 TraceCheckUtils]: 115: Hoare triple {34222#false} assume !(1 == ~T10_E~0); {34222#false} is VALID [2022-02-21 04:23:07,398 INFO L290 TraceCheckUtils]: 116: Hoare triple {34222#false} assume !(1 == ~E_M~0); {34222#false} is VALID [2022-02-21 04:23:07,398 INFO L290 TraceCheckUtils]: 117: Hoare triple {34222#false} assume !(1 == ~E_1~0); {34222#false} is VALID [2022-02-21 04:23:07,398 INFO L290 TraceCheckUtils]: 118: Hoare triple {34222#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34222#false} is VALID [2022-02-21 04:23:07,398 INFO L290 TraceCheckUtils]: 119: Hoare triple {34222#false} assume !(1 == ~E_3~0); {34222#false} is VALID [2022-02-21 04:23:07,398 INFO L290 TraceCheckUtils]: 120: Hoare triple {34222#false} assume !(1 == ~E_4~0); {34222#false} is VALID [2022-02-21 04:23:07,399 INFO L290 TraceCheckUtils]: 121: Hoare triple {34222#false} assume !(1 == ~E_5~0); {34222#false} is VALID [2022-02-21 04:23:07,399 INFO L290 TraceCheckUtils]: 122: Hoare triple {34222#false} assume !(1 == ~E_6~0); {34222#false} is VALID [2022-02-21 04:23:07,399 INFO L290 TraceCheckUtils]: 123: Hoare triple {34222#false} assume !(1 == ~E_7~0); {34222#false} is VALID [2022-02-21 04:23:07,399 INFO L290 TraceCheckUtils]: 124: Hoare triple {34222#false} assume !(1 == ~E_8~0); {34222#false} is VALID [2022-02-21 04:23:07,399 INFO L290 TraceCheckUtils]: 125: Hoare triple {34222#false} assume !(1 == ~E_9~0); {34222#false} is VALID [2022-02-21 04:23:07,399 INFO L290 TraceCheckUtils]: 126: Hoare triple {34222#false} assume 1 == ~E_10~0;~E_10~0 := 2; {34222#false} is VALID [2022-02-21 04:23:07,400 INFO L290 TraceCheckUtils]: 127: Hoare triple {34222#false} assume { :end_inline_reset_delta_events } true; {34222#false} is VALID [2022-02-21 04:23:07,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:07,400 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:07,400 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942522887] [2022-02-21 04:23:07,401 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942522887] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:07,401 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:07,401 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:07,401 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460676503] [2022-02-21 04:23:07,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:07,402 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:07,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:07,403 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 1 times [2022-02-21 04:23:07,403 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:07,403 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77551443] [2022-02-21 04:23:07,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:07,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:07,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:07,435 INFO L290 TraceCheckUtils]: 0: Hoare triple {34224#true} assume !false; {34224#true} is VALID [2022-02-21 04:23:07,435 INFO L290 TraceCheckUtils]: 1: Hoare triple {34224#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34224#true} is VALID [2022-02-21 04:23:07,435 INFO L290 TraceCheckUtils]: 2: Hoare triple {34224#true} assume !false; {34224#true} is VALID [2022-02-21 04:23:07,435 INFO L290 TraceCheckUtils]: 3: Hoare triple {34224#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {34224#true} is VALID [2022-02-21 04:23:07,435 INFO L290 TraceCheckUtils]: 4: Hoare triple {34224#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 5: Hoare triple {34224#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 6: Hoare triple {34224#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 7: Hoare triple {34224#true} assume !(0 != eval_~tmp~0#1); {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 8: Hoare triple {34224#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 9: Hoare triple {34224#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 10: Hoare triple {34224#true} assume 0 == ~M_E~0;~M_E~0 := 1; {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 11: Hoare triple {34224#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34224#true} is VALID [2022-02-21 04:23:07,436 INFO L290 TraceCheckUtils]: 12: Hoare triple {34224#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {34224#true} is VALID [2022-02-21 04:23:07,437 INFO L290 TraceCheckUtils]: 13: Hoare triple {34224#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34224#true} is VALID [2022-02-21 04:23:07,437 INFO L290 TraceCheckUtils]: 14: Hoare triple {34224#true} assume !(0 == ~T4_E~0); {34224#true} is VALID [2022-02-21 04:23:07,437 INFO L290 TraceCheckUtils]: 15: Hoare triple {34224#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34224#true} is VALID [2022-02-21 04:23:07,437 INFO L290 TraceCheckUtils]: 16: Hoare triple {34224#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,438 INFO L290 TraceCheckUtils]: 17: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,438 INFO L290 TraceCheckUtils]: 18: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,438 INFO L290 TraceCheckUtils]: 19: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,438 INFO L290 TraceCheckUtils]: 20: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,439 INFO L290 TraceCheckUtils]: 21: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,439 INFO L290 TraceCheckUtils]: 22: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,439 INFO L290 TraceCheckUtils]: 23: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,440 INFO L290 TraceCheckUtils]: 24: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,440 INFO L290 TraceCheckUtils]: 25: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,440 INFO L290 TraceCheckUtils]: 26: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,440 INFO L290 TraceCheckUtils]: 27: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,441 INFO L290 TraceCheckUtils]: 28: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,441 INFO L290 TraceCheckUtils]: 29: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,441 INFO L290 TraceCheckUtils]: 30: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,442 INFO L290 TraceCheckUtils]: 31: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,442 INFO L290 TraceCheckUtils]: 32: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,442 INFO L290 TraceCheckUtils]: 33: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,442 INFO L290 TraceCheckUtils]: 34: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,443 INFO L290 TraceCheckUtils]: 35: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,443 INFO L290 TraceCheckUtils]: 36: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,443 INFO L290 TraceCheckUtils]: 37: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,444 INFO L290 TraceCheckUtils]: 38: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,444 INFO L290 TraceCheckUtils]: 39: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,444 INFO L290 TraceCheckUtils]: 40: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,444 INFO L290 TraceCheckUtils]: 41: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,445 INFO L290 TraceCheckUtils]: 42: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,445 INFO L290 TraceCheckUtils]: 43: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,445 INFO L290 TraceCheckUtils]: 44: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,446 INFO L290 TraceCheckUtils]: 45: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,446 INFO L290 TraceCheckUtils]: 46: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,446 INFO L290 TraceCheckUtils]: 47: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,447 INFO L290 TraceCheckUtils]: 48: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,447 INFO L290 TraceCheckUtils]: 49: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,447 INFO L290 TraceCheckUtils]: 50: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,448 INFO L290 TraceCheckUtils]: 51: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,449 INFO L290 TraceCheckUtils]: 52: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,449 INFO L290 TraceCheckUtils]: 53: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,449 INFO L290 TraceCheckUtils]: 54: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,449 INFO L290 TraceCheckUtils]: 55: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,450 INFO L290 TraceCheckUtils]: 56: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,450 INFO L290 TraceCheckUtils]: 57: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,450 INFO L290 TraceCheckUtils]: 58: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,451 INFO L290 TraceCheckUtils]: 59: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,451 INFO L290 TraceCheckUtils]: 60: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,451 INFO L290 TraceCheckUtils]: 61: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,451 INFO L290 TraceCheckUtils]: 62: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,452 INFO L290 TraceCheckUtils]: 63: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,452 INFO L290 TraceCheckUtils]: 64: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,452 INFO L290 TraceCheckUtils]: 65: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,453 INFO L290 TraceCheckUtils]: 66: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,453 INFO L290 TraceCheckUtils]: 67: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,453 INFO L290 TraceCheckUtils]: 68: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,453 INFO L290 TraceCheckUtils]: 69: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,454 INFO L290 TraceCheckUtils]: 70: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,454 INFO L290 TraceCheckUtils]: 71: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,454 INFO L290 TraceCheckUtils]: 72: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,455 INFO L290 TraceCheckUtils]: 73: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,455 INFO L290 TraceCheckUtils]: 74: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,455 INFO L290 TraceCheckUtils]: 75: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,455 INFO L290 TraceCheckUtils]: 76: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,456 INFO L290 TraceCheckUtils]: 77: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,456 INFO L290 TraceCheckUtils]: 78: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,456 INFO L290 TraceCheckUtils]: 79: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,457 INFO L290 TraceCheckUtils]: 80: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,457 INFO L290 TraceCheckUtils]: 81: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,457 INFO L290 TraceCheckUtils]: 82: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,458 INFO L290 TraceCheckUtils]: 83: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,458 INFO L290 TraceCheckUtils]: 84: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,458 INFO L290 TraceCheckUtils]: 85: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,458 INFO L290 TraceCheckUtils]: 86: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,459 INFO L290 TraceCheckUtils]: 87: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,459 INFO L290 TraceCheckUtils]: 88: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,459 INFO L290 TraceCheckUtils]: 89: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,460 INFO L290 TraceCheckUtils]: 90: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,460 INFO L290 TraceCheckUtils]: 91: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,460 INFO L290 TraceCheckUtils]: 92: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,460 INFO L290 TraceCheckUtils]: 93: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,461 INFO L290 TraceCheckUtils]: 94: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,461 INFO L290 TraceCheckUtils]: 95: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,461 INFO L290 TraceCheckUtils]: 96: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,462 INFO L290 TraceCheckUtils]: 97: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,462 INFO L290 TraceCheckUtils]: 98: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,462 INFO L290 TraceCheckUtils]: 99: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,462 INFO L290 TraceCheckUtils]: 100: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,463 INFO L290 TraceCheckUtils]: 101: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,463 INFO L290 TraceCheckUtils]: 102: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,463 INFO L290 TraceCheckUtils]: 103: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,464 INFO L290 TraceCheckUtils]: 104: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34226#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,464 INFO L290 TraceCheckUtils]: 105: Hoare triple {34226#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {34225#false} is VALID [2022-02-21 04:23:07,464 INFO L290 TraceCheckUtils]: 106: Hoare triple {34225#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,464 INFO L290 TraceCheckUtils]: 107: Hoare triple {34225#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,464 INFO L290 TraceCheckUtils]: 108: Hoare triple {34225#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 109: Hoare triple {34225#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 110: Hoare triple {34225#false} assume 1 == ~E_M~0;~E_M~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 111: Hoare triple {34225#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 112: Hoare triple {34225#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 113: Hoare triple {34225#false} assume !(1 == ~E_3~0); {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 114: Hoare triple {34225#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 115: Hoare triple {34225#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,465 INFO L290 TraceCheckUtils]: 116: Hoare triple {34225#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,466 INFO L290 TraceCheckUtils]: 117: Hoare triple {34225#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,466 INFO L290 TraceCheckUtils]: 118: Hoare triple {34225#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,466 INFO L290 TraceCheckUtils]: 119: Hoare triple {34225#false} assume 1 == ~E_9~0;~E_9~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,466 INFO L290 TraceCheckUtils]: 120: Hoare triple {34225#false} assume 1 == ~E_10~0;~E_10~0 := 2; {34225#false} is VALID [2022-02-21 04:23:07,466 INFO L290 TraceCheckUtils]: 121: Hoare triple {34225#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {34225#false} is VALID [2022-02-21 04:23:07,466 INFO L290 TraceCheckUtils]: 122: Hoare triple {34225#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {34225#false} is VALID [2022-02-21 04:23:07,466 INFO L290 TraceCheckUtils]: 123: Hoare triple {34225#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {34225#false} is VALID [2022-02-21 04:23:07,467 INFO L290 TraceCheckUtils]: 124: Hoare triple {34225#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {34225#false} is VALID [2022-02-21 04:23:07,467 INFO L290 TraceCheckUtils]: 125: Hoare triple {34225#false} assume !(0 == start_simulation_~tmp~3#1); {34225#false} is VALID [2022-02-21 04:23:07,467 INFO L290 TraceCheckUtils]: 126: Hoare triple {34225#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {34225#false} is VALID [2022-02-21 04:23:07,467 INFO L290 TraceCheckUtils]: 127: Hoare triple {34225#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {34225#false} is VALID [2022-02-21 04:23:07,467 INFO L290 TraceCheckUtils]: 128: Hoare triple {34225#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {34225#false} is VALID [2022-02-21 04:23:07,467 INFO L290 TraceCheckUtils]: 129: Hoare triple {34225#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {34225#false} is VALID [2022-02-21 04:23:07,467 INFO L290 TraceCheckUtils]: 130: Hoare triple {34225#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {34225#false} is VALID [2022-02-21 04:23:07,468 INFO L290 TraceCheckUtils]: 131: Hoare triple {34225#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34225#false} is VALID [2022-02-21 04:23:07,468 INFO L290 TraceCheckUtils]: 132: Hoare triple {34225#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {34225#false} is VALID [2022-02-21 04:23:07,468 INFO L290 TraceCheckUtils]: 133: Hoare triple {34225#false} assume !(0 != start_simulation_~tmp___0~1#1); {34225#false} is VALID [2022-02-21 04:23:07,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:07,468 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:07,469 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77551443] [2022-02-21 04:23:07,469 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77551443] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:07,469 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:07,469 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:07,469 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565039033] [2022-02-21 04:23:07,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:07,470 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:07,470 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:07,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:07,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:07,471 INFO L87 Difference]: Start difference. First operand 1366 states and 2027 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,446 INFO L93 Difference]: Finished difference Result 1366 states and 2026 transitions. [2022-02-21 04:23:08,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:08,447 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,535 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:08,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:08,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2026 transitions. [2022-02-21 04:23:08,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:08,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:08,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:08,622 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2022-02-21 04:23:08,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:08,634 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:08,636 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2026 transitions. Second operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,637 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2026 transitions. Second operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,638 INFO L87 Difference]: Start difference. First operand 1366 states and 2026 transitions. Second operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,678 INFO L93 Difference]: Finished difference Result 1366 states and 2026 transitions. [2022-02-21 04:23:08,678 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,679 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:08,679 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:08,681 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,682 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,723 INFO L93 Difference]: Finished difference Result 1366 states and 2026 transitions. [2022-02-21 04:23:08,723 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,725 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:08,725 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:08,725 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:08,725 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:08,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2026 transitions. [2022-02-21 04:23:08,768 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2022-02-21 04:23:08,768 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2022-02-21 04:23:08,768 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:08,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2026 transitions. [2022-02-21 04:23:08,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:08,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:08,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:08,772 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:08,772 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:08,772 INFO L791 eck$LassoCheckResult]: Stem: 36651#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 36859#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35644#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35645#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 36884#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36842#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36843#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36873#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35953#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35954#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36057#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36302#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 36233#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35955#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35615#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35616#L1036 assume !(0 == ~M_E~0); 35714#L1036-2 assume !(0 == ~T1_E~0); 36590#L1041-1 assume !(0 == ~T2_E~0); 36591#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35989#L1051-1 assume !(0 == ~T4_E~0); 35990#L1056-1 assume !(0 == ~T5_E~0); 36728#L1061-1 assume !(0 == ~T6_E~0); 35887#L1066-1 assume !(0 == ~T7_E~0); 35888#L1071-1 assume !(0 == ~T8_E~0); 36711#L1076-1 assume !(0 == ~T9_E~0); 35782#L1081-1 assume !(0 == ~T10_E~0); 35783#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 36186#L1091-1 assume !(0 == ~E_1~0); 36888#L1096-1 assume !(0 == ~E_2~0); 36889#L1101-1 assume !(0 == ~E_3~0); 36247#L1106-1 assume !(0 == ~E_4~0); 36248#L1111-1 assume !(0 == ~E_5~0); 36404#L1116-1 assume !(0 == ~E_6~0); 36405#L1121-1 assume !(0 == ~E_7~0); 36240#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36241#L1131-1 assume !(0 == ~E_9~0); 36491#L1136-1 assume !(0 == ~E_10~0); 36598#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36755#L514 assume 1 == ~m_pc~0; 36718#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36261#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36180#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36181#L1285 assume !(0 != activate_threads_~tmp~1#1); 36924#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35906#L533 assume !(1 == ~t1_pc~0); 35907#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36420#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36293#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36294#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 36620#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36621#L552 assume 1 == ~t2_pc~0; 36132#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36133#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36699#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36700#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36275#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36276#L571 assume 1 == ~t3_pc~0; 36452#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36453#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35822#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35823#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36410#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35698#L590 assume !(1 == ~t4_pc~0); 35699#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36463#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36696#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36697#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36653#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36406#L609 assume 1 == ~t5_pc~0; 36407#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36921#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35733#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35734#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36401#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36402#L628 assume !(1 == ~t6_pc~0); 36335#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36334#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36906#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36907#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 36691#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36692#L647 assume 1 == ~t7_pc~0; 36249#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36250#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36528#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36256#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36257#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36953#L666 assume !(1 == ~t8_pc~0); 36036#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36037#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36271#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36428#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36184#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36185#L685 assume 1 == ~t9_pc~0; 36930#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36827#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36819#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36209#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36210#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36562#L704 assume !(1 == ~t10_pc~0); 36201#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36200#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36726#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35754#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 35755#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36000#L1154 assume !(1 == ~M_E~0); 36679#L1154-2 assume !(1 == ~T1_E~0); 35972#L1159-1 assume !(1 == ~T2_E~0); 35973#L1164-1 assume !(1 == ~T3_E~0); 36425#L1169-1 assume !(1 == ~T4_E~0); 36297#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36104#L1179-1 assume !(1 == ~T6_E~0); 35958#L1184-1 assume !(1 == ~T7_E~0); 35959#L1189-1 assume !(1 == ~T8_E~0); 36034#L1194-1 assume !(1 == ~T9_E~0); 36173#L1199-1 assume !(1 == ~T10_E~0); 36119#L1204-1 assume !(1 == ~E_M~0); 36120#L1209-1 assume !(1 == ~E_1~0); 36646#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 36647#L1219-1 assume !(1 == ~E_3~0); 36946#L1224-1 assume !(1 == ~E_4~0); 36445#L1229-1 assume !(1 == ~E_5~0); 35843#L1234-1 assume !(1 == ~E_6~0); 35844#L1239-1 assume !(1 == ~E_7~0); 35902#L1244-1 assume !(1 == ~E_8~0); 35903#L1249-1 assume !(1 == ~E_9~0); 36716#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35745#L1259-1 assume { :end_inline_reset_delta_events } true; 35746#L1565-2 [2022-02-21 04:23:08,772 INFO L793 eck$LassoCheckResult]: Loop: 35746#L1565-2 assume !false; 36654#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36138#L1011 assume !false; 36139#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 36188#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35942#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 36807#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35969#L866 assume !(0 != eval_~tmp~0#1); 35971#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36557#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36558#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36722#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36908#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36781#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36782#L1051-3 assume !(0 == ~T4_E~0); 36723#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35986#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35987#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35988#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36909#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35737#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35738#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35796#L1091-3 assume !(0 == ~E_1~0); 35797#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36875#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36876#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36905#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36866#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36573#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36574#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36797#L1131-3 assume !(0 == ~E_9~0); 36798#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36957#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36576#L514-36 assume 1 == ~m_pc~0; 36577#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36163#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36164#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36619#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36045#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36046#L533-36 assume 1 == ~t1_pc~0; 36321#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36417#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36717#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36665#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36468#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36469#L552-36 assume 1 == ~t2_pc~0; 36038#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36040#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35859#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35860#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36012#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36013#L571-36 assume 1 == ~t3_pc~0; 36397#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36102#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36103#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36224#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36780#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36073#L590-36 assume !(1 == ~t4_pc~0); 36074#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 36680#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36258#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36259#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36759#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36760#L609-36 assume 1 == ~t5_pc~0; 36635#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36470#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36288#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36289#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36542#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36368#L628-36 assume 1 == ~t6_pc~0; 36227#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36228#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36655#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36656#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36580#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36581#L647-36 assume 1 == ~t7_pc~0; 36509#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35766#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35767#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35786#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 35787#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36681#L666-36 assume !(1 == ~t8_pc~0); 35968#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 35967#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36870#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36871#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36129#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36130#L685-36 assume 1 == ~t9_pc~0; 36556#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35871#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36386#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36387#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36268#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36269#L704-36 assume 1 == ~t10_pc~0; 35861#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35862#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36622#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36623#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35891#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35892#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36858#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36736#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36737#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36917#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36197#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36198#L1179-3 assume !(1 == ~T6_E~0); 36829#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35768#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35769#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36142#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36143#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36441#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35631#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35632#L1219-3 assume !(1 == ~E_3~0); 36630#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36631#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36650#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35904#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35905#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36484#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36867#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36633#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 36634#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35712#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 36457#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36458#L1584 assume !(0 == start_simulation_~tmp~3#1); 36588#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35918#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35613#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 36060#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 36061#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36245#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36212#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36213#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 35746#L1565-2 [2022-02-21 04:23:08,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:08,773 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2022-02-21 04:23:08,773 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:08,773 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626169594] [2022-02-21 04:23:08,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:08,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:08,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:08,795 INFO L290 TraceCheckUtils]: 0: Hoare triple {39694#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {39694#true} is VALID [2022-02-21 04:23:08,796 INFO L290 TraceCheckUtils]: 1: Hoare triple {39694#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,796 INFO L290 TraceCheckUtils]: 2: Hoare triple {39696#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,797 INFO L290 TraceCheckUtils]: 3: Hoare triple {39696#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,797 INFO L290 TraceCheckUtils]: 4: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,797 INFO L290 TraceCheckUtils]: 5: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,797 INFO L290 TraceCheckUtils]: 6: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,798 INFO L290 TraceCheckUtils]: 7: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,798 INFO L290 TraceCheckUtils]: 8: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,798 INFO L290 TraceCheckUtils]: 9: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,799 INFO L290 TraceCheckUtils]: 10: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,799 INFO L290 TraceCheckUtils]: 11: Hoare triple {39696#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {39696#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:08,799 INFO L290 TraceCheckUtils]: 12: Hoare triple {39696#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {39695#false} is VALID [2022-02-21 04:23:08,799 INFO L290 TraceCheckUtils]: 13: Hoare triple {39695#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {39695#false} is VALID [2022-02-21 04:23:08,799 INFO L290 TraceCheckUtils]: 14: Hoare triple {39695#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {39695#false} is VALID [2022-02-21 04:23:08,800 INFO L290 TraceCheckUtils]: 15: Hoare triple {39695#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {39695#false} is VALID [2022-02-21 04:23:08,800 INFO L290 TraceCheckUtils]: 16: Hoare triple {39695#false} assume !(0 == ~M_E~0); {39695#false} is VALID [2022-02-21 04:23:08,800 INFO L290 TraceCheckUtils]: 17: Hoare triple {39695#false} assume !(0 == ~T1_E~0); {39695#false} is VALID [2022-02-21 04:23:08,800 INFO L290 TraceCheckUtils]: 18: Hoare triple {39695#false} assume !(0 == ~T2_E~0); {39695#false} is VALID [2022-02-21 04:23:08,800 INFO L290 TraceCheckUtils]: 19: Hoare triple {39695#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {39695#false} is VALID [2022-02-21 04:23:08,800 INFO L290 TraceCheckUtils]: 20: Hoare triple {39695#false} assume !(0 == ~T4_E~0); {39695#false} is VALID [2022-02-21 04:23:08,800 INFO L290 TraceCheckUtils]: 21: Hoare triple {39695#false} assume !(0 == ~T5_E~0); {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 22: Hoare triple {39695#false} assume !(0 == ~T6_E~0); {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 23: Hoare triple {39695#false} assume !(0 == ~T7_E~0); {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 24: Hoare triple {39695#false} assume !(0 == ~T8_E~0); {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 25: Hoare triple {39695#false} assume !(0 == ~T9_E~0); {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 26: Hoare triple {39695#false} assume !(0 == ~T10_E~0); {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 27: Hoare triple {39695#false} assume 0 == ~E_M~0;~E_M~0 := 1; {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 28: Hoare triple {39695#false} assume !(0 == ~E_1~0); {39695#false} is VALID [2022-02-21 04:23:08,801 INFO L290 TraceCheckUtils]: 29: Hoare triple {39695#false} assume !(0 == ~E_2~0); {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 30: Hoare triple {39695#false} assume !(0 == ~E_3~0); {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 31: Hoare triple {39695#false} assume !(0 == ~E_4~0); {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 32: Hoare triple {39695#false} assume !(0 == ~E_5~0); {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 33: Hoare triple {39695#false} assume !(0 == ~E_6~0); {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 34: Hoare triple {39695#false} assume !(0 == ~E_7~0); {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 35: Hoare triple {39695#false} assume 0 == ~E_8~0;~E_8~0 := 1; {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 36: Hoare triple {39695#false} assume !(0 == ~E_9~0); {39695#false} is VALID [2022-02-21 04:23:08,802 INFO L290 TraceCheckUtils]: 37: Hoare triple {39695#false} assume !(0 == ~E_10~0); {39695#false} is VALID [2022-02-21 04:23:08,803 INFO L290 TraceCheckUtils]: 38: Hoare triple {39695#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39695#false} is VALID [2022-02-21 04:23:08,803 INFO L290 TraceCheckUtils]: 39: Hoare triple {39695#false} assume 1 == ~m_pc~0; {39695#false} is VALID [2022-02-21 04:23:08,803 INFO L290 TraceCheckUtils]: 40: Hoare triple {39695#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {39695#false} is VALID [2022-02-21 04:23:08,803 INFO L290 TraceCheckUtils]: 41: Hoare triple {39695#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39695#false} is VALID [2022-02-21 04:23:08,803 INFO L290 TraceCheckUtils]: 42: Hoare triple {39695#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {39695#false} is VALID [2022-02-21 04:23:08,803 INFO L290 TraceCheckUtils]: 43: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp~1#1); {39695#false} is VALID [2022-02-21 04:23:08,803 INFO L290 TraceCheckUtils]: 44: Hoare triple {39695#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39695#false} is VALID [2022-02-21 04:23:08,804 INFO L290 TraceCheckUtils]: 45: Hoare triple {39695#false} assume !(1 == ~t1_pc~0); {39695#false} is VALID [2022-02-21 04:23:08,804 INFO L290 TraceCheckUtils]: 46: Hoare triple {39695#false} is_transmit1_triggered_~__retres1~1#1 := 0; {39695#false} is VALID [2022-02-21 04:23:08,804 INFO L290 TraceCheckUtils]: 47: Hoare triple {39695#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39695#false} is VALID [2022-02-21 04:23:08,804 INFO L290 TraceCheckUtils]: 48: Hoare triple {39695#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {39695#false} is VALID [2022-02-21 04:23:08,804 INFO L290 TraceCheckUtils]: 49: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___0~0#1); {39695#false} is VALID [2022-02-21 04:23:08,804 INFO L290 TraceCheckUtils]: 50: Hoare triple {39695#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39695#false} is VALID [2022-02-21 04:23:08,804 INFO L290 TraceCheckUtils]: 51: Hoare triple {39695#false} assume 1 == ~t2_pc~0; {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 52: Hoare triple {39695#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 53: Hoare triple {39695#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 54: Hoare triple {39695#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 55: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___1~0#1); {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 56: Hoare triple {39695#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 57: Hoare triple {39695#false} assume 1 == ~t3_pc~0; {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 58: Hoare triple {39695#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {39695#false} is VALID [2022-02-21 04:23:08,805 INFO L290 TraceCheckUtils]: 59: Hoare triple {39695#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 60: Hoare triple {39695#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 61: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___2~0#1); {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 62: Hoare triple {39695#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 63: Hoare triple {39695#false} assume !(1 == ~t4_pc~0); {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 64: Hoare triple {39695#false} is_transmit4_triggered_~__retres1~4#1 := 0; {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 65: Hoare triple {39695#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 66: Hoare triple {39695#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {39695#false} is VALID [2022-02-21 04:23:08,806 INFO L290 TraceCheckUtils]: 67: Hoare triple {39695#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {39695#false} is VALID [2022-02-21 04:23:08,807 INFO L290 TraceCheckUtils]: 68: Hoare triple {39695#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {39695#false} is VALID [2022-02-21 04:23:08,807 INFO L290 TraceCheckUtils]: 69: Hoare triple {39695#false} assume 1 == ~t5_pc~0; {39695#false} is VALID [2022-02-21 04:23:08,807 INFO L290 TraceCheckUtils]: 70: Hoare triple {39695#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {39695#false} is VALID [2022-02-21 04:23:08,807 INFO L290 TraceCheckUtils]: 71: Hoare triple {39695#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {39695#false} is VALID [2022-02-21 04:23:08,807 INFO L290 TraceCheckUtils]: 72: Hoare triple {39695#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {39695#false} is VALID [2022-02-21 04:23:08,807 INFO L290 TraceCheckUtils]: 73: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___4~0#1); {39695#false} is VALID [2022-02-21 04:23:08,807 INFO L290 TraceCheckUtils]: 74: Hoare triple {39695#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 75: Hoare triple {39695#false} assume !(1 == ~t6_pc~0); {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 76: Hoare triple {39695#false} is_transmit6_triggered_~__retres1~6#1 := 0; {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 77: Hoare triple {39695#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 78: Hoare triple {39695#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 79: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___5~0#1); {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 80: Hoare triple {39695#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 81: Hoare triple {39695#false} assume 1 == ~t7_pc~0; {39695#false} is VALID [2022-02-21 04:23:08,808 INFO L290 TraceCheckUtils]: 82: Hoare triple {39695#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {39695#false} is VALID [2022-02-21 04:23:08,809 INFO L290 TraceCheckUtils]: 83: Hoare triple {39695#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {39695#false} is VALID [2022-02-21 04:23:08,809 INFO L290 TraceCheckUtils]: 84: Hoare triple {39695#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {39695#false} is VALID [2022-02-21 04:23:08,809 INFO L290 TraceCheckUtils]: 85: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___6~0#1); {39695#false} is VALID [2022-02-21 04:23:08,809 INFO L290 TraceCheckUtils]: 86: Hoare triple {39695#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {39695#false} is VALID [2022-02-21 04:23:08,809 INFO L290 TraceCheckUtils]: 87: Hoare triple {39695#false} assume !(1 == ~t8_pc~0); {39695#false} is VALID [2022-02-21 04:23:08,809 INFO L290 TraceCheckUtils]: 88: Hoare triple {39695#false} is_transmit8_triggered_~__retres1~8#1 := 0; {39695#false} is VALID [2022-02-21 04:23:08,809 INFO L290 TraceCheckUtils]: 89: Hoare triple {39695#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 90: Hoare triple {39695#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 91: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___7~0#1); {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 92: Hoare triple {39695#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 93: Hoare triple {39695#false} assume 1 == ~t9_pc~0; {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 94: Hoare triple {39695#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 95: Hoare triple {39695#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 96: Hoare triple {39695#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {39695#false} is VALID [2022-02-21 04:23:08,810 INFO L290 TraceCheckUtils]: 97: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___8~0#1); {39695#false} is VALID [2022-02-21 04:23:08,811 INFO L290 TraceCheckUtils]: 98: Hoare triple {39695#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {39695#false} is VALID [2022-02-21 04:23:08,811 INFO L290 TraceCheckUtils]: 99: Hoare triple {39695#false} assume !(1 == ~t10_pc~0); {39695#false} is VALID [2022-02-21 04:23:08,811 INFO L290 TraceCheckUtils]: 100: Hoare triple {39695#false} is_transmit10_triggered_~__retres1~10#1 := 0; {39695#false} is VALID [2022-02-21 04:23:08,811 INFO L290 TraceCheckUtils]: 101: Hoare triple {39695#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {39695#false} is VALID [2022-02-21 04:23:08,811 INFO L290 TraceCheckUtils]: 102: Hoare triple {39695#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {39695#false} is VALID [2022-02-21 04:23:08,811 INFO L290 TraceCheckUtils]: 103: Hoare triple {39695#false} assume !(0 != activate_threads_~tmp___9~0#1); {39695#false} is VALID [2022-02-21 04:23:08,811 INFO L290 TraceCheckUtils]: 104: Hoare triple {39695#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39695#false} is VALID [2022-02-21 04:23:08,812 INFO L290 TraceCheckUtils]: 105: Hoare triple {39695#false} assume !(1 == ~M_E~0); {39695#false} is VALID [2022-02-21 04:23:08,812 INFO L290 TraceCheckUtils]: 106: Hoare triple {39695#false} assume !(1 == ~T1_E~0); {39695#false} is VALID [2022-02-21 04:23:08,812 INFO L290 TraceCheckUtils]: 107: Hoare triple {39695#false} assume !(1 == ~T2_E~0); {39695#false} is VALID [2022-02-21 04:23:08,812 INFO L290 TraceCheckUtils]: 108: Hoare triple {39695#false} assume !(1 == ~T3_E~0); {39695#false} is VALID [2022-02-21 04:23:08,812 INFO L290 TraceCheckUtils]: 109: Hoare triple {39695#false} assume !(1 == ~T4_E~0); {39695#false} is VALID [2022-02-21 04:23:08,812 INFO L290 TraceCheckUtils]: 110: Hoare triple {39695#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {39695#false} is VALID [2022-02-21 04:23:08,812 INFO L290 TraceCheckUtils]: 111: Hoare triple {39695#false} assume !(1 == ~T6_E~0); {39695#false} is VALID [2022-02-21 04:23:08,813 INFO L290 TraceCheckUtils]: 112: Hoare triple {39695#false} assume !(1 == ~T7_E~0); {39695#false} is VALID [2022-02-21 04:23:08,813 INFO L290 TraceCheckUtils]: 113: Hoare triple {39695#false} assume !(1 == ~T8_E~0); {39695#false} is VALID [2022-02-21 04:23:08,813 INFO L290 TraceCheckUtils]: 114: Hoare triple {39695#false} assume !(1 == ~T9_E~0); {39695#false} is VALID [2022-02-21 04:23:08,813 INFO L290 TraceCheckUtils]: 115: Hoare triple {39695#false} assume !(1 == ~T10_E~0); {39695#false} is VALID [2022-02-21 04:23:08,813 INFO L290 TraceCheckUtils]: 116: Hoare triple {39695#false} assume !(1 == ~E_M~0); {39695#false} is VALID [2022-02-21 04:23:08,813 INFO L290 TraceCheckUtils]: 117: Hoare triple {39695#false} assume !(1 == ~E_1~0); {39695#false} is VALID [2022-02-21 04:23:08,813 INFO L290 TraceCheckUtils]: 118: Hoare triple {39695#false} assume 1 == ~E_2~0;~E_2~0 := 2; {39695#false} is VALID [2022-02-21 04:23:08,814 INFO L290 TraceCheckUtils]: 119: Hoare triple {39695#false} assume !(1 == ~E_3~0); {39695#false} is VALID [2022-02-21 04:23:08,814 INFO L290 TraceCheckUtils]: 120: Hoare triple {39695#false} assume !(1 == ~E_4~0); {39695#false} is VALID [2022-02-21 04:23:08,814 INFO L290 TraceCheckUtils]: 121: Hoare triple {39695#false} assume !(1 == ~E_5~0); {39695#false} is VALID [2022-02-21 04:23:08,814 INFO L290 TraceCheckUtils]: 122: Hoare triple {39695#false} assume !(1 == ~E_6~0); {39695#false} is VALID [2022-02-21 04:23:08,814 INFO L290 TraceCheckUtils]: 123: Hoare triple {39695#false} assume !(1 == ~E_7~0); {39695#false} is VALID [2022-02-21 04:23:08,814 INFO L290 TraceCheckUtils]: 124: Hoare triple {39695#false} assume !(1 == ~E_8~0); {39695#false} is VALID [2022-02-21 04:23:08,814 INFO L290 TraceCheckUtils]: 125: Hoare triple {39695#false} assume !(1 == ~E_9~0); {39695#false} is VALID [2022-02-21 04:23:08,815 INFO L290 TraceCheckUtils]: 126: Hoare triple {39695#false} assume 1 == ~E_10~0;~E_10~0 := 2; {39695#false} is VALID [2022-02-21 04:23:08,815 INFO L290 TraceCheckUtils]: 127: Hoare triple {39695#false} assume { :end_inline_reset_delta_events } true; {39695#false} is VALID [2022-02-21 04:23:08,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:08,815 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:08,815 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626169594] [2022-02-21 04:23:08,816 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [626169594] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:08,817 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:08,817 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:08,817 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160048656] [2022-02-21 04:23:08,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:08,817 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:08,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:08,818 INFO L85 PathProgramCache]: Analyzing trace with hash -952820077, now seen corresponding path program 1 times [2022-02-21 04:23:08,818 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:08,818 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774860324] [2022-02-21 04:23:08,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:08,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:08,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:08,845 INFO L290 TraceCheckUtils]: 0: Hoare triple {39697#true} assume !false; {39697#true} is VALID [2022-02-21 04:23:08,845 INFO L290 TraceCheckUtils]: 1: Hoare triple {39697#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {39697#true} is VALID [2022-02-21 04:23:08,846 INFO L290 TraceCheckUtils]: 2: Hoare triple {39697#true} assume !false; {39697#true} is VALID [2022-02-21 04:23:08,846 INFO L290 TraceCheckUtils]: 3: Hoare triple {39697#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {39697#true} is VALID [2022-02-21 04:23:08,846 INFO L290 TraceCheckUtils]: 4: Hoare triple {39697#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {39697#true} is VALID [2022-02-21 04:23:08,846 INFO L290 TraceCheckUtils]: 5: Hoare triple {39697#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {39697#true} is VALID [2022-02-21 04:23:08,846 INFO L290 TraceCheckUtils]: 6: Hoare triple {39697#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {39697#true} is VALID [2022-02-21 04:23:08,846 INFO L290 TraceCheckUtils]: 7: Hoare triple {39697#true} assume !(0 != eval_~tmp~0#1); {39697#true} is VALID [2022-02-21 04:23:08,846 INFO L290 TraceCheckUtils]: 8: Hoare triple {39697#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {39697#true} is VALID [2022-02-21 04:23:08,847 INFO L290 TraceCheckUtils]: 9: Hoare triple {39697#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {39697#true} is VALID [2022-02-21 04:23:08,847 INFO L290 TraceCheckUtils]: 10: Hoare triple {39697#true} assume 0 == ~M_E~0;~M_E~0 := 1; {39697#true} is VALID [2022-02-21 04:23:08,847 INFO L290 TraceCheckUtils]: 11: Hoare triple {39697#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {39697#true} is VALID [2022-02-21 04:23:08,847 INFO L290 TraceCheckUtils]: 12: Hoare triple {39697#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {39697#true} is VALID [2022-02-21 04:23:08,847 INFO L290 TraceCheckUtils]: 13: Hoare triple {39697#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {39697#true} is VALID [2022-02-21 04:23:08,847 INFO L290 TraceCheckUtils]: 14: Hoare triple {39697#true} assume !(0 == ~T4_E~0); {39697#true} is VALID [2022-02-21 04:23:08,847 INFO L290 TraceCheckUtils]: 15: Hoare triple {39697#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {39697#true} is VALID [2022-02-21 04:23:08,848 INFO L290 TraceCheckUtils]: 16: Hoare triple {39697#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,848 INFO L290 TraceCheckUtils]: 17: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,848 INFO L290 TraceCheckUtils]: 18: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,849 INFO L290 TraceCheckUtils]: 19: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,849 INFO L290 TraceCheckUtils]: 20: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,849 INFO L290 TraceCheckUtils]: 21: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,849 INFO L290 TraceCheckUtils]: 22: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,850 INFO L290 TraceCheckUtils]: 23: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,850 INFO L290 TraceCheckUtils]: 24: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,850 INFO L290 TraceCheckUtils]: 25: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,851 INFO L290 TraceCheckUtils]: 26: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,851 INFO L290 TraceCheckUtils]: 27: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,851 INFO L290 TraceCheckUtils]: 28: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,851 INFO L290 TraceCheckUtils]: 29: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,852 INFO L290 TraceCheckUtils]: 30: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,852 INFO L290 TraceCheckUtils]: 31: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,852 INFO L290 TraceCheckUtils]: 32: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,853 INFO L290 TraceCheckUtils]: 33: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,853 INFO L290 TraceCheckUtils]: 34: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,853 INFO L290 TraceCheckUtils]: 35: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,854 INFO L290 TraceCheckUtils]: 36: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,854 INFO L290 TraceCheckUtils]: 37: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,854 INFO L290 TraceCheckUtils]: 38: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,854 INFO L290 TraceCheckUtils]: 39: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,855 INFO L290 TraceCheckUtils]: 40: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,855 INFO L290 TraceCheckUtils]: 41: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,855 INFO L290 TraceCheckUtils]: 42: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,856 INFO L290 TraceCheckUtils]: 43: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,856 INFO L290 TraceCheckUtils]: 44: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,856 INFO L290 TraceCheckUtils]: 45: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,856 INFO L290 TraceCheckUtils]: 46: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,857 INFO L290 TraceCheckUtils]: 47: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,857 INFO L290 TraceCheckUtils]: 48: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,857 INFO L290 TraceCheckUtils]: 49: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,858 INFO L290 TraceCheckUtils]: 50: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,858 INFO L290 TraceCheckUtils]: 51: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,858 INFO L290 TraceCheckUtils]: 52: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,859 INFO L290 TraceCheckUtils]: 53: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,859 INFO L290 TraceCheckUtils]: 54: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,859 INFO L290 TraceCheckUtils]: 55: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,859 INFO L290 TraceCheckUtils]: 56: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,860 INFO L290 TraceCheckUtils]: 57: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,860 INFO L290 TraceCheckUtils]: 58: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,860 INFO L290 TraceCheckUtils]: 59: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,861 INFO L290 TraceCheckUtils]: 60: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,861 INFO L290 TraceCheckUtils]: 61: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,861 INFO L290 TraceCheckUtils]: 62: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,861 INFO L290 TraceCheckUtils]: 63: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,862 INFO L290 TraceCheckUtils]: 64: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,862 INFO L290 TraceCheckUtils]: 65: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,862 INFO L290 TraceCheckUtils]: 66: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,863 INFO L290 TraceCheckUtils]: 67: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,863 INFO L290 TraceCheckUtils]: 68: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,863 INFO L290 TraceCheckUtils]: 69: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,863 INFO L290 TraceCheckUtils]: 70: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,864 INFO L290 TraceCheckUtils]: 71: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,864 INFO L290 TraceCheckUtils]: 72: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,864 INFO L290 TraceCheckUtils]: 73: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,865 INFO L290 TraceCheckUtils]: 74: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,865 INFO L290 TraceCheckUtils]: 75: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,865 INFO L290 TraceCheckUtils]: 76: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,866 INFO L290 TraceCheckUtils]: 77: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,866 INFO L290 TraceCheckUtils]: 78: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,866 INFO L290 TraceCheckUtils]: 79: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,866 INFO L290 TraceCheckUtils]: 80: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,867 INFO L290 TraceCheckUtils]: 81: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,867 INFO L290 TraceCheckUtils]: 82: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,867 INFO L290 TraceCheckUtils]: 83: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,868 INFO L290 TraceCheckUtils]: 84: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,868 INFO L290 TraceCheckUtils]: 85: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,868 INFO L290 TraceCheckUtils]: 86: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,868 INFO L290 TraceCheckUtils]: 87: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,869 INFO L290 TraceCheckUtils]: 88: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,869 INFO L290 TraceCheckUtils]: 89: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,869 INFO L290 TraceCheckUtils]: 90: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,870 INFO L290 TraceCheckUtils]: 91: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,870 INFO L290 TraceCheckUtils]: 92: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,870 INFO L290 TraceCheckUtils]: 93: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,871 INFO L290 TraceCheckUtils]: 94: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,871 INFO L290 TraceCheckUtils]: 95: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,871 INFO L290 TraceCheckUtils]: 96: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,871 INFO L290 TraceCheckUtils]: 97: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,872 INFO L290 TraceCheckUtils]: 98: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,872 INFO L290 TraceCheckUtils]: 99: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,872 INFO L290 TraceCheckUtils]: 100: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,873 INFO L290 TraceCheckUtils]: 101: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,873 INFO L290 TraceCheckUtils]: 102: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,873 INFO L290 TraceCheckUtils]: 103: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,873 INFO L290 TraceCheckUtils]: 104: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {39699#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,874 INFO L290 TraceCheckUtils]: 105: Hoare triple {39699#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {39698#false} is VALID [2022-02-21 04:23:08,874 INFO L290 TraceCheckUtils]: 106: Hoare triple {39698#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,874 INFO L290 TraceCheckUtils]: 107: Hoare triple {39698#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,874 INFO L290 TraceCheckUtils]: 108: Hoare triple {39698#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,874 INFO L290 TraceCheckUtils]: 109: Hoare triple {39698#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,874 INFO L290 TraceCheckUtils]: 110: Hoare triple {39698#false} assume 1 == ~E_M~0;~E_M~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 111: Hoare triple {39698#false} assume 1 == ~E_1~0;~E_1~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 112: Hoare triple {39698#false} assume 1 == ~E_2~0;~E_2~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 113: Hoare triple {39698#false} assume !(1 == ~E_3~0); {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 114: Hoare triple {39698#false} assume 1 == ~E_4~0;~E_4~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 115: Hoare triple {39698#false} assume 1 == ~E_5~0;~E_5~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 116: Hoare triple {39698#false} assume 1 == ~E_6~0;~E_6~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 117: Hoare triple {39698#false} assume 1 == ~E_7~0;~E_7~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,875 INFO L290 TraceCheckUtils]: 118: Hoare triple {39698#false} assume 1 == ~E_8~0;~E_8~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,876 INFO L290 TraceCheckUtils]: 119: Hoare triple {39698#false} assume 1 == ~E_9~0;~E_9~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,876 INFO L290 TraceCheckUtils]: 120: Hoare triple {39698#false} assume 1 == ~E_10~0;~E_10~0 := 2; {39698#false} is VALID [2022-02-21 04:23:08,876 INFO L290 TraceCheckUtils]: 121: Hoare triple {39698#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {39698#false} is VALID [2022-02-21 04:23:08,876 INFO L290 TraceCheckUtils]: 122: Hoare triple {39698#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {39698#false} is VALID [2022-02-21 04:23:08,876 INFO L290 TraceCheckUtils]: 123: Hoare triple {39698#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {39698#false} is VALID [2022-02-21 04:23:08,876 INFO L290 TraceCheckUtils]: 124: Hoare triple {39698#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {39698#false} is VALID [2022-02-21 04:23:08,876 INFO L290 TraceCheckUtils]: 125: Hoare triple {39698#false} assume !(0 == start_simulation_~tmp~3#1); {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 126: Hoare triple {39698#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 127: Hoare triple {39698#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 128: Hoare triple {39698#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 129: Hoare triple {39698#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 130: Hoare triple {39698#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 131: Hoare triple {39698#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 132: Hoare triple {39698#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {39698#false} is VALID [2022-02-21 04:23:08,877 INFO L290 TraceCheckUtils]: 133: Hoare triple {39698#false} assume !(0 != start_simulation_~tmp___0~1#1); {39698#false} is VALID [2022-02-21 04:23:08,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:08,878 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:08,880 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774860324] [2022-02-21 04:23:08,881 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774860324] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:08,881 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:08,881 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:08,881 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583003469] [2022-02-21 04:23:08,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:08,882 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:08,882 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:08,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:08,882 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:08,883 INFO L87 Difference]: Start difference. First operand 1366 states and 2026 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:09,817 INFO L93 Difference]: Finished difference Result 1366 states and 2025 transitions. [2022-02-21 04:23:09,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:09,818 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,901 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:09,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2025 transitions. [2022-02-21 04:23:09,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:09,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2025 transitions. [2022-02-21 04:23:09,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:09,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:09,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2025 transitions. [2022-02-21 04:23:09,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:09,997 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2022-02-21 04:23:09,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2025 transitions. [2022-02-21 04:23:10,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:10,015 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:10,017 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2025 transitions. Second operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,018 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2025 transitions. Second operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,019 INFO L87 Difference]: Start difference. First operand 1366 states and 2025 transitions. Second operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,068 INFO L93 Difference]: Finished difference Result 1366 states and 2025 transitions. [2022-02-21 04:23:10,068 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2025 transitions. [2022-02-21 04:23:10,069 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,070 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,072 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2025 transitions. [2022-02-21 04:23:10,074 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2025 transitions. [2022-02-21 04:23:10,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,120 INFO L93 Difference]: Finished difference Result 1366 states and 2025 transitions. [2022-02-21 04:23:10,121 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2025 transitions. [2022-02-21 04:23:10,122 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,122 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,122 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:10,122 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:10,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2025 transitions. [2022-02-21 04:23:10,165 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2022-02-21 04:23:10,166 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2022-02-21 04:23:10,166 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:10,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2025 transitions. [2022-02-21 04:23:10,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:10,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:10,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:10,169 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,170 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,170 INFO L791 eck$LassoCheckResult]: Stem: 42123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 42124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 42332#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41115#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41116#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 42356#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42315#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42316#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42346#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41424#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41425#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41530#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41775#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41706#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41426#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 41088#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41089#L1036 assume !(0 == ~M_E~0); 41187#L1036-2 assume !(0 == ~T1_E~0); 42063#L1041-1 assume !(0 == ~T2_E~0); 42064#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41462#L1051-1 assume !(0 == ~T4_E~0); 41463#L1056-1 assume !(0 == ~T5_E~0); 42201#L1061-1 assume !(0 == ~T6_E~0); 41360#L1066-1 assume !(0 == ~T7_E~0); 41361#L1071-1 assume !(0 == ~T8_E~0); 42184#L1076-1 assume !(0 == ~T9_E~0); 41255#L1081-1 assume !(0 == ~T10_E~0); 41256#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 41659#L1091-1 assume !(0 == ~E_1~0); 42360#L1096-1 assume !(0 == ~E_2~0); 42361#L1101-1 assume !(0 == ~E_3~0); 41720#L1106-1 assume !(0 == ~E_4~0); 41721#L1111-1 assume !(0 == ~E_5~0); 41877#L1116-1 assume !(0 == ~E_6~0); 41878#L1121-1 assume !(0 == ~E_7~0); 41713#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 41714#L1131-1 assume !(0 == ~E_9~0); 41964#L1136-1 assume !(0 == ~E_10~0); 42071#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42228#L514 assume 1 == ~m_pc~0; 42191#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41733#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41650#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41651#L1285 assume !(0 != activate_threads_~tmp~1#1); 42396#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41379#L533 assume !(1 == ~t1_pc~0); 41380#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41893#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41766#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41767#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 42093#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42094#L552 assume 1 == ~t2_pc~0; 41604#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41605#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42172#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42173#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 41745#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41746#L571 assume 1 == ~t3_pc~0; 41923#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41924#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41293#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41294#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 41883#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41169#L590 assume !(1 == ~t4_pc~0); 41170#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41936#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42168#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42169#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42125#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41879#L609 assume 1 == ~t5_pc~0; 41880#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42394#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41206#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41207#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 41874#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41875#L628 assume !(1 == ~t6_pc~0); 41808#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41807#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42379#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42380#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 42164#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42165#L647 assume 1 == ~t7_pc~0; 41722#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41723#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41999#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41727#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 41728#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42426#L666 assume !(1 == ~t8_pc~0); 41509#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41510#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41744#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41900#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 41656#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41657#L685 assume 1 == ~t9_pc~0; 42403#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42300#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42292#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41682#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 41683#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42035#L704 assume !(1 == ~t10_pc~0); 41674#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41673#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42199#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41225#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 41226#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41473#L1154 assume !(1 == ~M_E~0); 42152#L1154-2 assume !(1 == ~T1_E~0); 41445#L1159-1 assume !(1 == ~T2_E~0); 41446#L1164-1 assume !(1 == ~T3_E~0); 41898#L1169-1 assume !(1 == ~T4_E~0); 41770#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41575#L1179-1 assume !(1 == ~T6_E~0); 41431#L1184-1 assume !(1 == ~T7_E~0); 41432#L1189-1 assume !(1 == ~T8_E~0); 41507#L1194-1 assume !(1 == ~T9_E~0); 41646#L1199-1 assume !(1 == ~T10_E~0); 41590#L1204-1 assume !(1 == ~E_M~0); 41591#L1209-1 assume !(1 == ~E_1~0); 42117#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 42118#L1219-1 assume !(1 == ~E_3~0); 42419#L1224-1 assume !(1 == ~E_4~0); 41918#L1229-1 assume !(1 == ~E_5~0); 41316#L1234-1 assume !(1 == ~E_6~0); 41317#L1239-1 assume !(1 == ~E_7~0); 41375#L1244-1 assume !(1 == ~E_8~0); 41376#L1249-1 assume !(1 == ~E_9~0); 42189#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 41218#L1259-1 assume { :end_inline_reset_delta_events } true; 41219#L1565-2 [2022-02-21 04:23:10,170 INFO L793 eck$LassoCheckResult]: Loop: 41219#L1565-2 assume !false; 42127#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41611#L1011 assume !false; 41612#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 41661#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 41415#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 42280#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41439#L866 assume !(0 != eval_~tmp~0#1); 41441#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42028#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42029#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42195#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42381#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42254#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42255#L1051-3 assume !(0 == ~T4_E~0); 42196#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41459#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41460#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41461#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42382#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41210#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41211#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41265#L1091-3 assume !(0 == ~E_1~0); 41266#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42348#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42349#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42378#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42339#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42045#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42046#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42270#L1131-3 assume !(0 == ~E_9~0); 42271#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42430#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42049#L514-36 assume 1 == ~m_pc~0; 42050#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41634#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41635#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42092#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41518#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41519#L533-36 assume 1 == ~t1_pc~0; 41794#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41887#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42190#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42138#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41941#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41942#L552-36 assume 1 == ~t2_pc~0; 41511#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41513#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41332#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41333#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41485#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41486#L571-36 assume 1 == ~t3_pc~0; 41870#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41576#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41577#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41697#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42253#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41546#L590-36 assume !(1 == ~t4_pc~0); 41547#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 42153#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41731#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41732#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42232#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42233#L609-36 assume 1 == ~t5_pc~0; 42108#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41943#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41761#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41762#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42015#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41841#L628-36 assume 1 == ~t6_pc~0; 41700#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41701#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42128#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42129#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42053#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42054#L647-36 assume 1 == ~t7_pc~0; 41982#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41239#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41240#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41259#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 41260#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42154#L666-36 assume 1 == ~t8_pc~0; 41442#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41443#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42343#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42344#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41602#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41603#L685-36 assume !(1 == ~t9_pc~0); 41343#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 41344#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41859#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41860#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41741#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41742#L704-36 assume 1 == ~t10_pc~0; 41334#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41335#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42095#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42096#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41364#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41365#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42331#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42209#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42210#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42390#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41670#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41671#L1179-3 assume !(1 == ~T6_E~0); 42302#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41241#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41242#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41617#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41618#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41914#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41107#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41108#L1219-3 assume !(1 == ~E_3~0); 42103#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42104#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42126#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41377#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41378#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41961#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42340#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 42106#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 42107#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 41185#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 41932#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 41933#L1584 assume !(0 == start_simulation_~tmp~3#1); 42061#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 41391#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 41086#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 41533#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 41534#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41718#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41685#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41686#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 41219#L1565-2 [2022-02-21 04:23:10,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2022-02-21 04:23:10,171 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,171 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992249440] [2022-02-21 04:23:10,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,188 INFO L290 TraceCheckUtils]: 0: Hoare triple {45167#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {45167#true} is VALID [2022-02-21 04:23:10,189 INFO L290 TraceCheckUtils]: 1: Hoare triple {45167#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,189 INFO L290 TraceCheckUtils]: 2: Hoare triple {45169#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,189 INFO L290 TraceCheckUtils]: 3: Hoare triple {45169#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,189 INFO L290 TraceCheckUtils]: 4: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,190 INFO L290 TraceCheckUtils]: 5: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,190 INFO L290 TraceCheckUtils]: 6: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,190 INFO L290 TraceCheckUtils]: 7: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,190 INFO L290 TraceCheckUtils]: 8: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,191 INFO L290 TraceCheckUtils]: 9: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,191 INFO L290 TraceCheckUtils]: 10: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,191 INFO L290 TraceCheckUtils]: 11: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,192 INFO L290 TraceCheckUtils]: 12: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,192 INFO L290 TraceCheckUtils]: 13: Hoare triple {45169#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {45169#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,192 INFO L290 TraceCheckUtils]: 14: Hoare triple {45169#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {45168#false} is VALID [2022-02-21 04:23:10,192 INFO L290 TraceCheckUtils]: 15: Hoare triple {45168#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {45168#false} is VALID [2022-02-21 04:23:10,192 INFO L290 TraceCheckUtils]: 16: Hoare triple {45168#false} assume !(0 == ~M_E~0); {45168#false} is VALID [2022-02-21 04:23:10,192 INFO L290 TraceCheckUtils]: 17: Hoare triple {45168#false} assume !(0 == ~T1_E~0); {45168#false} is VALID [2022-02-21 04:23:10,193 INFO L290 TraceCheckUtils]: 18: Hoare triple {45168#false} assume !(0 == ~T2_E~0); {45168#false} is VALID [2022-02-21 04:23:10,193 INFO L290 TraceCheckUtils]: 19: Hoare triple {45168#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {45168#false} is VALID [2022-02-21 04:23:10,193 INFO L290 TraceCheckUtils]: 20: Hoare triple {45168#false} assume !(0 == ~T4_E~0); {45168#false} is VALID [2022-02-21 04:23:10,193 INFO L290 TraceCheckUtils]: 21: Hoare triple {45168#false} assume !(0 == ~T5_E~0); {45168#false} is VALID [2022-02-21 04:23:10,193 INFO L290 TraceCheckUtils]: 22: Hoare triple {45168#false} assume !(0 == ~T6_E~0); {45168#false} is VALID [2022-02-21 04:23:10,193 INFO L290 TraceCheckUtils]: 23: Hoare triple {45168#false} assume !(0 == ~T7_E~0); {45168#false} is VALID [2022-02-21 04:23:10,193 INFO L290 TraceCheckUtils]: 24: Hoare triple {45168#false} assume !(0 == ~T8_E~0); {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 25: Hoare triple {45168#false} assume !(0 == ~T9_E~0); {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 26: Hoare triple {45168#false} assume !(0 == ~T10_E~0); {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 27: Hoare triple {45168#false} assume 0 == ~E_M~0;~E_M~0 := 1; {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 28: Hoare triple {45168#false} assume !(0 == ~E_1~0); {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 29: Hoare triple {45168#false} assume !(0 == ~E_2~0); {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 30: Hoare triple {45168#false} assume !(0 == ~E_3~0); {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 31: Hoare triple {45168#false} assume !(0 == ~E_4~0); {45168#false} is VALID [2022-02-21 04:23:10,194 INFO L290 TraceCheckUtils]: 32: Hoare triple {45168#false} assume !(0 == ~E_5~0); {45168#false} is VALID [2022-02-21 04:23:10,195 INFO L290 TraceCheckUtils]: 33: Hoare triple {45168#false} assume !(0 == ~E_6~0); {45168#false} is VALID [2022-02-21 04:23:10,195 INFO L290 TraceCheckUtils]: 34: Hoare triple {45168#false} assume !(0 == ~E_7~0); {45168#false} is VALID [2022-02-21 04:23:10,195 INFO L290 TraceCheckUtils]: 35: Hoare triple {45168#false} assume 0 == ~E_8~0;~E_8~0 := 1; {45168#false} is VALID [2022-02-21 04:23:10,195 INFO L290 TraceCheckUtils]: 36: Hoare triple {45168#false} assume !(0 == ~E_9~0); {45168#false} is VALID [2022-02-21 04:23:10,195 INFO L290 TraceCheckUtils]: 37: Hoare triple {45168#false} assume !(0 == ~E_10~0); {45168#false} is VALID [2022-02-21 04:23:10,195 INFO L290 TraceCheckUtils]: 38: Hoare triple {45168#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {45168#false} is VALID [2022-02-21 04:23:10,196 INFO L290 TraceCheckUtils]: 39: Hoare triple {45168#false} assume 1 == ~m_pc~0; {45168#false} is VALID [2022-02-21 04:23:10,196 INFO L290 TraceCheckUtils]: 40: Hoare triple {45168#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {45168#false} is VALID [2022-02-21 04:23:10,196 INFO L290 TraceCheckUtils]: 41: Hoare triple {45168#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {45168#false} is VALID [2022-02-21 04:23:10,196 INFO L290 TraceCheckUtils]: 42: Hoare triple {45168#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {45168#false} is VALID [2022-02-21 04:23:10,196 INFO L290 TraceCheckUtils]: 43: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp~1#1); {45168#false} is VALID [2022-02-21 04:23:10,196 INFO L290 TraceCheckUtils]: 44: Hoare triple {45168#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {45168#false} is VALID [2022-02-21 04:23:10,197 INFO L290 TraceCheckUtils]: 45: Hoare triple {45168#false} assume !(1 == ~t1_pc~0); {45168#false} is VALID [2022-02-21 04:23:10,197 INFO L290 TraceCheckUtils]: 46: Hoare triple {45168#false} is_transmit1_triggered_~__retres1~1#1 := 0; {45168#false} is VALID [2022-02-21 04:23:10,197 INFO L290 TraceCheckUtils]: 47: Hoare triple {45168#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {45168#false} is VALID [2022-02-21 04:23:10,197 INFO L290 TraceCheckUtils]: 48: Hoare triple {45168#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {45168#false} is VALID [2022-02-21 04:23:10,197 INFO L290 TraceCheckUtils]: 49: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___0~0#1); {45168#false} is VALID [2022-02-21 04:23:10,197 INFO L290 TraceCheckUtils]: 50: Hoare triple {45168#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {45168#false} is VALID [2022-02-21 04:23:10,197 INFO L290 TraceCheckUtils]: 51: Hoare triple {45168#false} assume 1 == ~t2_pc~0; {45168#false} is VALID [2022-02-21 04:23:10,198 INFO L290 TraceCheckUtils]: 52: Hoare triple {45168#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {45168#false} is VALID [2022-02-21 04:23:10,198 INFO L290 TraceCheckUtils]: 53: Hoare triple {45168#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {45168#false} is VALID [2022-02-21 04:23:10,198 INFO L290 TraceCheckUtils]: 54: Hoare triple {45168#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {45168#false} is VALID [2022-02-21 04:23:10,198 INFO L290 TraceCheckUtils]: 55: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___1~0#1); {45168#false} is VALID [2022-02-21 04:23:10,198 INFO L290 TraceCheckUtils]: 56: Hoare triple {45168#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {45168#false} is VALID [2022-02-21 04:23:10,198 INFO L290 TraceCheckUtils]: 57: Hoare triple {45168#false} assume 1 == ~t3_pc~0; {45168#false} is VALID [2022-02-21 04:23:10,198 INFO L290 TraceCheckUtils]: 58: Hoare triple {45168#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 59: Hoare triple {45168#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 60: Hoare triple {45168#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 61: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___2~0#1); {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 62: Hoare triple {45168#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 63: Hoare triple {45168#false} assume !(1 == ~t4_pc~0); {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 64: Hoare triple {45168#false} is_transmit4_triggered_~__retres1~4#1 := 0; {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 65: Hoare triple {45168#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {45168#false} is VALID [2022-02-21 04:23:10,199 INFO L290 TraceCheckUtils]: 66: Hoare triple {45168#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {45168#false} is VALID [2022-02-21 04:23:10,200 INFO L290 TraceCheckUtils]: 67: Hoare triple {45168#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {45168#false} is VALID [2022-02-21 04:23:10,200 INFO L290 TraceCheckUtils]: 68: Hoare triple {45168#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {45168#false} is VALID [2022-02-21 04:23:10,200 INFO L290 TraceCheckUtils]: 69: Hoare triple {45168#false} assume 1 == ~t5_pc~0; {45168#false} is VALID [2022-02-21 04:23:10,200 INFO L290 TraceCheckUtils]: 70: Hoare triple {45168#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {45168#false} is VALID [2022-02-21 04:23:10,200 INFO L290 TraceCheckUtils]: 71: Hoare triple {45168#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {45168#false} is VALID [2022-02-21 04:23:10,200 INFO L290 TraceCheckUtils]: 72: Hoare triple {45168#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {45168#false} is VALID [2022-02-21 04:23:10,200 INFO L290 TraceCheckUtils]: 73: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___4~0#1); {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 74: Hoare triple {45168#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 75: Hoare triple {45168#false} assume !(1 == ~t6_pc~0); {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 76: Hoare triple {45168#false} is_transmit6_triggered_~__retres1~6#1 := 0; {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 77: Hoare triple {45168#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 78: Hoare triple {45168#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 79: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___5~0#1); {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 80: Hoare triple {45168#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {45168#false} is VALID [2022-02-21 04:23:10,201 INFO L290 TraceCheckUtils]: 81: Hoare triple {45168#false} assume 1 == ~t7_pc~0; {45168#false} is VALID [2022-02-21 04:23:10,202 INFO L290 TraceCheckUtils]: 82: Hoare triple {45168#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {45168#false} is VALID [2022-02-21 04:23:10,202 INFO L290 TraceCheckUtils]: 83: Hoare triple {45168#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {45168#false} is VALID [2022-02-21 04:23:10,202 INFO L290 TraceCheckUtils]: 84: Hoare triple {45168#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {45168#false} is VALID [2022-02-21 04:23:10,202 INFO L290 TraceCheckUtils]: 85: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___6~0#1); {45168#false} is VALID [2022-02-21 04:23:10,202 INFO L290 TraceCheckUtils]: 86: Hoare triple {45168#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {45168#false} is VALID [2022-02-21 04:23:10,202 INFO L290 TraceCheckUtils]: 87: Hoare triple {45168#false} assume !(1 == ~t8_pc~0); {45168#false} is VALID [2022-02-21 04:23:10,202 INFO L290 TraceCheckUtils]: 88: Hoare triple {45168#false} is_transmit8_triggered_~__retres1~8#1 := 0; {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 89: Hoare triple {45168#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 90: Hoare triple {45168#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 91: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___7~0#1); {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 92: Hoare triple {45168#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 93: Hoare triple {45168#false} assume 1 == ~t9_pc~0; {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 94: Hoare triple {45168#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 95: Hoare triple {45168#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {45168#false} is VALID [2022-02-21 04:23:10,203 INFO L290 TraceCheckUtils]: 96: Hoare triple {45168#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {45168#false} is VALID [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 97: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___8~0#1); {45168#false} is VALID [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 98: Hoare triple {45168#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {45168#false} is VALID [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 99: Hoare triple {45168#false} assume !(1 == ~t10_pc~0); {45168#false} is VALID [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 100: Hoare triple {45168#false} is_transmit10_triggered_~__retres1~10#1 := 0; {45168#false} is VALID [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 101: Hoare triple {45168#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {45168#false} is VALID [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 102: Hoare triple {45168#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {45168#false} is VALID [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 103: Hoare triple {45168#false} assume !(0 != activate_threads_~tmp___9~0#1); {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 104: Hoare triple {45168#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 105: Hoare triple {45168#false} assume !(1 == ~M_E~0); {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 106: Hoare triple {45168#false} assume !(1 == ~T1_E~0); {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 107: Hoare triple {45168#false} assume !(1 == ~T2_E~0); {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 108: Hoare triple {45168#false} assume !(1 == ~T3_E~0); {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 109: Hoare triple {45168#false} assume !(1 == ~T4_E~0); {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 110: Hoare triple {45168#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {45168#false} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 111: Hoare triple {45168#false} assume !(1 == ~T6_E~0); {45168#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 112: Hoare triple {45168#false} assume !(1 == ~T7_E~0); {45168#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 113: Hoare triple {45168#false} assume !(1 == ~T8_E~0); {45168#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 114: Hoare triple {45168#false} assume !(1 == ~T9_E~0); {45168#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 115: Hoare triple {45168#false} assume !(1 == ~T10_E~0); {45168#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 116: Hoare triple {45168#false} assume !(1 == ~E_M~0); {45168#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 117: Hoare triple {45168#false} assume !(1 == ~E_1~0); {45168#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 118: Hoare triple {45168#false} assume 1 == ~E_2~0;~E_2~0 := 2; {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 119: Hoare triple {45168#false} assume !(1 == ~E_3~0); {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 120: Hoare triple {45168#false} assume !(1 == ~E_4~0); {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 121: Hoare triple {45168#false} assume !(1 == ~E_5~0); {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 122: Hoare triple {45168#false} assume !(1 == ~E_6~0); {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 123: Hoare triple {45168#false} assume !(1 == ~E_7~0); {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 124: Hoare triple {45168#false} assume !(1 == ~E_8~0); {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 125: Hoare triple {45168#false} assume !(1 == ~E_9~0); {45168#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 126: Hoare triple {45168#false} assume 1 == ~E_10~0;~E_10~0 := 2; {45168#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 127: Hoare triple {45168#false} assume { :end_inline_reset_delta_events } true; {45168#false} is VALID [2022-02-21 04:23:10,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,208 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,208 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992249440] [2022-02-21 04:23:10,208 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992249440] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,209 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,209 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,209 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827487025] [2022-02-21 04:23:10,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,210 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:10,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,210 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 2 times [2022-02-21 04:23:10,210 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,210 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281862813] [2022-02-21 04:23:10,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 0: Hoare triple {45170#true} assume !false; {45170#true} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 1: Hoare triple {45170#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {45170#true} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 2: Hoare triple {45170#true} assume !false; {45170#true} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 3: Hoare triple {45170#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {45170#true} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 4: Hoare triple {45170#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {45170#true} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 5: Hoare triple {45170#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {45170#true} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 6: Hoare triple {45170#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {45170#true} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 7: Hoare triple {45170#true} assume !(0 != eval_~tmp~0#1); {45170#true} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 8: Hoare triple {45170#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {45170#true} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 9: Hoare triple {45170#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {45170#true} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 10: Hoare triple {45170#true} assume 0 == ~M_E~0;~M_E~0 := 1; {45170#true} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 11: Hoare triple {45170#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {45170#true} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 12: Hoare triple {45170#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {45170#true} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 13: Hoare triple {45170#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {45170#true} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 14: Hoare triple {45170#true} assume !(0 == ~T4_E~0); {45170#true} is VALID [2022-02-21 04:23:10,254 INFO L290 TraceCheckUtils]: 15: Hoare triple {45170#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {45170#true} is VALID [2022-02-21 04:23:10,254 INFO L290 TraceCheckUtils]: 16: Hoare triple {45170#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,254 INFO L290 TraceCheckUtils]: 17: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,255 INFO L290 TraceCheckUtils]: 18: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,255 INFO L290 TraceCheckUtils]: 19: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,255 INFO L290 TraceCheckUtils]: 20: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,255 INFO L290 TraceCheckUtils]: 21: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,256 INFO L290 TraceCheckUtils]: 22: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,256 INFO L290 TraceCheckUtils]: 23: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,256 INFO L290 TraceCheckUtils]: 24: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,256 INFO L290 TraceCheckUtils]: 25: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,257 INFO L290 TraceCheckUtils]: 26: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,257 INFO L290 TraceCheckUtils]: 27: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,257 INFO L290 TraceCheckUtils]: 28: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,258 INFO L290 TraceCheckUtils]: 29: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,258 INFO L290 TraceCheckUtils]: 30: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,258 INFO L290 TraceCheckUtils]: 31: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,258 INFO L290 TraceCheckUtils]: 32: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,259 INFO L290 TraceCheckUtils]: 33: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,259 INFO L290 TraceCheckUtils]: 34: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,259 INFO L290 TraceCheckUtils]: 35: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,260 INFO L290 TraceCheckUtils]: 36: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,260 INFO L290 TraceCheckUtils]: 37: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,260 INFO L290 TraceCheckUtils]: 38: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,260 INFO L290 TraceCheckUtils]: 39: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,261 INFO L290 TraceCheckUtils]: 40: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,261 INFO L290 TraceCheckUtils]: 41: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,261 INFO L290 TraceCheckUtils]: 42: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,262 INFO L290 TraceCheckUtils]: 43: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,262 INFO L290 TraceCheckUtils]: 44: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,262 INFO L290 TraceCheckUtils]: 45: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,262 INFO L290 TraceCheckUtils]: 46: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,263 INFO L290 TraceCheckUtils]: 47: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,263 INFO L290 TraceCheckUtils]: 48: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,263 INFO L290 TraceCheckUtils]: 49: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,264 INFO L290 TraceCheckUtils]: 50: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,264 INFO L290 TraceCheckUtils]: 51: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,264 INFO L290 TraceCheckUtils]: 52: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,264 INFO L290 TraceCheckUtils]: 53: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,265 INFO L290 TraceCheckUtils]: 54: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,265 INFO L290 TraceCheckUtils]: 55: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,265 INFO L290 TraceCheckUtils]: 56: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,265 INFO L290 TraceCheckUtils]: 57: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,266 INFO L290 TraceCheckUtils]: 58: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,266 INFO L290 TraceCheckUtils]: 59: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,266 INFO L290 TraceCheckUtils]: 60: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,267 INFO L290 TraceCheckUtils]: 61: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,267 INFO L290 TraceCheckUtils]: 62: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,267 INFO L290 TraceCheckUtils]: 63: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,267 INFO L290 TraceCheckUtils]: 64: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,268 INFO L290 TraceCheckUtils]: 65: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,268 INFO L290 TraceCheckUtils]: 66: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,268 INFO L290 TraceCheckUtils]: 67: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,268 INFO L290 TraceCheckUtils]: 68: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,269 INFO L290 TraceCheckUtils]: 69: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,269 INFO L290 TraceCheckUtils]: 70: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,269 INFO L290 TraceCheckUtils]: 71: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,270 INFO L290 TraceCheckUtils]: 72: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,270 INFO L290 TraceCheckUtils]: 73: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,270 INFO L290 TraceCheckUtils]: 74: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,270 INFO L290 TraceCheckUtils]: 75: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,271 INFO L290 TraceCheckUtils]: 76: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,271 INFO L290 TraceCheckUtils]: 77: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,271 INFO L290 TraceCheckUtils]: 78: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,271 INFO L290 TraceCheckUtils]: 79: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,272 INFO L290 TraceCheckUtils]: 80: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,272 INFO L290 TraceCheckUtils]: 81: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,272 INFO L290 TraceCheckUtils]: 82: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,273 INFO L290 TraceCheckUtils]: 83: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,273 INFO L290 TraceCheckUtils]: 84: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,273 INFO L290 TraceCheckUtils]: 85: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,273 INFO L290 TraceCheckUtils]: 86: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,274 INFO L290 TraceCheckUtils]: 87: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,274 INFO L290 TraceCheckUtils]: 88: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,274 INFO L290 TraceCheckUtils]: 89: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,274 INFO L290 TraceCheckUtils]: 90: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,275 INFO L290 TraceCheckUtils]: 91: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,275 INFO L290 TraceCheckUtils]: 92: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,275 INFO L290 TraceCheckUtils]: 93: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,276 INFO L290 TraceCheckUtils]: 94: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,276 INFO L290 TraceCheckUtils]: 95: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,276 INFO L290 TraceCheckUtils]: 96: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,276 INFO L290 TraceCheckUtils]: 97: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,277 INFO L290 TraceCheckUtils]: 98: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,277 INFO L290 TraceCheckUtils]: 99: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,277 INFO L290 TraceCheckUtils]: 100: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,277 INFO L290 TraceCheckUtils]: 101: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,278 INFO L290 TraceCheckUtils]: 102: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,278 INFO L290 TraceCheckUtils]: 103: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,278 INFO L290 TraceCheckUtils]: 104: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {45172#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,279 INFO L290 TraceCheckUtils]: 105: Hoare triple {45172#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {45171#false} is VALID [2022-02-21 04:23:10,279 INFO L290 TraceCheckUtils]: 106: Hoare triple {45171#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,279 INFO L290 TraceCheckUtils]: 107: Hoare triple {45171#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,279 INFO L290 TraceCheckUtils]: 108: Hoare triple {45171#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,279 INFO L290 TraceCheckUtils]: 109: Hoare triple {45171#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,279 INFO L290 TraceCheckUtils]: 110: Hoare triple {45171#false} assume 1 == ~E_M~0;~E_M~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,279 INFO L290 TraceCheckUtils]: 111: Hoare triple {45171#false} assume 1 == ~E_1~0;~E_1~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 112: Hoare triple {45171#false} assume 1 == ~E_2~0;~E_2~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 113: Hoare triple {45171#false} assume !(1 == ~E_3~0); {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 114: Hoare triple {45171#false} assume 1 == ~E_4~0;~E_4~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 115: Hoare triple {45171#false} assume 1 == ~E_5~0;~E_5~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 116: Hoare triple {45171#false} assume 1 == ~E_6~0;~E_6~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 117: Hoare triple {45171#false} assume 1 == ~E_7~0;~E_7~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 118: Hoare triple {45171#false} assume 1 == ~E_8~0;~E_8~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,280 INFO L290 TraceCheckUtils]: 119: Hoare triple {45171#false} assume 1 == ~E_9~0;~E_9~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,281 INFO L290 TraceCheckUtils]: 120: Hoare triple {45171#false} assume 1 == ~E_10~0;~E_10~0 := 2; {45171#false} is VALID [2022-02-21 04:23:10,281 INFO L290 TraceCheckUtils]: 121: Hoare triple {45171#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {45171#false} is VALID [2022-02-21 04:23:10,281 INFO L290 TraceCheckUtils]: 122: Hoare triple {45171#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {45171#false} is VALID [2022-02-21 04:23:10,281 INFO L290 TraceCheckUtils]: 123: Hoare triple {45171#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {45171#false} is VALID [2022-02-21 04:23:10,281 INFO L290 TraceCheckUtils]: 124: Hoare triple {45171#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {45171#false} is VALID [2022-02-21 04:23:10,281 INFO L290 TraceCheckUtils]: 125: Hoare triple {45171#false} assume !(0 == start_simulation_~tmp~3#1); {45171#false} is VALID [2022-02-21 04:23:10,281 INFO L290 TraceCheckUtils]: 126: Hoare triple {45171#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {45171#false} is VALID [2022-02-21 04:23:10,282 INFO L290 TraceCheckUtils]: 127: Hoare triple {45171#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {45171#false} is VALID [2022-02-21 04:23:10,282 INFO L290 TraceCheckUtils]: 128: Hoare triple {45171#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {45171#false} is VALID [2022-02-21 04:23:10,282 INFO L290 TraceCheckUtils]: 129: Hoare triple {45171#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {45171#false} is VALID [2022-02-21 04:23:10,282 INFO L290 TraceCheckUtils]: 130: Hoare triple {45171#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {45171#false} is VALID [2022-02-21 04:23:10,282 INFO L290 TraceCheckUtils]: 131: Hoare triple {45171#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {45171#false} is VALID [2022-02-21 04:23:10,282 INFO L290 TraceCheckUtils]: 132: Hoare triple {45171#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {45171#false} is VALID [2022-02-21 04:23:10,282 INFO L290 TraceCheckUtils]: 133: Hoare triple {45171#false} assume !(0 != start_simulation_~tmp___0~1#1); {45171#false} is VALID [2022-02-21 04:23:10,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,283 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,283 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281862813] [2022-02-21 04:23:10,283 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281862813] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,283 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,284 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,284 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561510982] [2022-02-21 04:23:10,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,284 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:10,284 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:10,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:10,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:10,285 INFO L87 Difference]: Start difference. First operand 1366 states and 2025 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,246 INFO L93 Difference]: Finished difference Result 1366 states and 2024 transitions. [2022-02-21 04:23:11,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:11,246 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,333 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:11,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:11,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2024 transitions. [2022-02-21 04:23:11,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2022-02-21 04:23:11,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2022-02-21 04:23:11,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:11,419 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2022-02-21 04:23:11,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2022-02-21 04:23:11,431 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:11,433 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1366 states and 2024 transitions. Second operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,434 INFO L74 IsIncluded]: Start isIncluded. First operand 1366 states and 2024 transitions. Second operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,435 INFO L87 Difference]: Start difference. First operand 1366 states and 2024 transitions. Second operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,476 INFO L93 Difference]: Finished difference Result 1366 states and 2024 transitions. [2022-02-21 04:23:11,476 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,477 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,477 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,479 INFO L74 IsIncluded]: Start isIncluded. First operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,481 INFO L87 Difference]: Start difference. First operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,522 INFO L93 Difference]: Finished difference Result 1366 states and 2024 transitions. [2022-02-21 04:23:11,522 INFO L276 IsEmpty]: Start isEmpty. Operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,524 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,524 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,524 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:11,524 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:11,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2024 transitions. [2022-02-21 04:23:11,567 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2022-02-21 04:23:11,567 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2022-02-21 04:23:11,567 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:11,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2024 transitions. [2022-02-21 04:23:11,570 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2022-02-21 04:23:11,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:11,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:11,571 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,571 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,572 INFO L791 eck$LassoCheckResult]: Stem: 47596#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 47597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 47805#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46588#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46589#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 47829#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47788#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47789#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47819#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46897#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46898#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47003#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47248#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47179#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46899#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46561#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46562#L1036 assume !(0 == ~M_E~0); 46660#L1036-2 assume !(0 == ~T1_E~0); 47536#L1041-1 assume !(0 == ~T2_E~0); 47537#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46935#L1051-1 assume !(0 == ~T4_E~0); 46936#L1056-1 assume !(0 == ~T5_E~0); 47674#L1061-1 assume !(0 == ~T6_E~0); 46833#L1066-1 assume !(0 == ~T7_E~0); 46834#L1071-1 assume !(0 == ~T8_E~0); 47657#L1076-1 assume !(0 == ~T9_E~0); 46728#L1081-1 assume !(0 == ~T10_E~0); 46729#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 47132#L1091-1 assume !(0 == ~E_1~0); 47833#L1096-1 assume !(0 == ~E_2~0); 47834#L1101-1 assume !(0 == ~E_3~0); 47193#L1106-1 assume !(0 == ~E_4~0); 47194#L1111-1 assume !(0 == ~E_5~0); 47350#L1116-1 assume !(0 == ~E_6~0); 47351#L1121-1 assume !(0 == ~E_7~0); 47186#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 47187#L1131-1 assume !(0 == ~E_9~0); 47437#L1136-1 assume !(0 == ~E_10~0); 47544#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47701#L514 assume 1 == ~m_pc~0; 47664#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47206#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47123#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47124#L1285 assume !(0 != activate_threads_~tmp~1#1); 47869#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46852#L533 assume !(1 == ~t1_pc~0); 46853#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47366#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47239#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47240#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 47566#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47567#L552 assume 1 == ~t2_pc~0; 47077#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47078#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47645#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47646#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 47218#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47219#L571 assume 1 == ~t3_pc~0; 47396#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47397#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46766#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46767#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 47356#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46642#L590 assume !(1 == ~t4_pc~0); 46643#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47409#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47641#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47642#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47598#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47352#L609 assume 1 == ~t5_pc~0; 47353#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47867#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46679#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46680#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 47347#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47348#L628 assume !(1 == ~t6_pc~0); 47281#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47280#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47852#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47853#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 47637#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47638#L647 assume 1 == ~t7_pc~0; 47195#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47196#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47472#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47198#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 47199#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47899#L666 assume !(1 == ~t8_pc~0); 46982#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46983#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47217#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47373#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 47129#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47130#L685 assume 1 == ~t9_pc~0; 47876#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47773#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47765#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47155#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 47156#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47508#L704 assume !(1 == ~t10_pc~0); 47147#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47146#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47672#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46698#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 46699#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46946#L1154 assume !(1 == ~M_E~0); 47625#L1154-2 assume !(1 == ~T1_E~0); 46918#L1159-1 assume !(1 == ~T2_E~0); 46919#L1164-1 assume !(1 == ~T3_E~0); 47371#L1169-1 assume !(1 == ~T4_E~0); 47243#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47048#L1179-1 assume !(1 == ~T6_E~0); 46904#L1184-1 assume !(1 == ~T7_E~0); 46905#L1189-1 assume !(1 == ~T8_E~0); 46980#L1194-1 assume !(1 == ~T9_E~0); 47119#L1199-1 assume !(1 == ~T10_E~0); 47063#L1204-1 assume !(1 == ~E_M~0); 47064#L1209-1 assume !(1 == ~E_1~0); 47590#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 47591#L1219-1 assume !(1 == ~E_3~0); 47892#L1224-1 assume !(1 == ~E_4~0); 47391#L1229-1 assume !(1 == ~E_5~0); 46789#L1234-1 assume !(1 == ~E_6~0); 46790#L1239-1 assume !(1 == ~E_7~0); 46848#L1244-1 assume !(1 == ~E_8~0); 46849#L1249-1 assume !(1 == ~E_9~0); 47662#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46691#L1259-1 assume { :end_inline_reset_delta_events } true; 46692#L1565-2 [2022-02-21 04:23:11,572 INFO L793 eck$LassoCheckResult]: Loop: 46692#L1565-2 assume !false; 47600#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47084#L1011 assume !false; 47085#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 47134#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 46888#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 47753#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 46912#L866 assume !(0 != eval_~tmp~0#1); 46914#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47501#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47502#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47668#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47854#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47727#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47728#L1051-3 assume !(0 == ~T4_E~0); 47669#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46932#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46933#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46934#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47855#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46683#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46684#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46738#L1091-3 assume !(0 == ~E_1~0); 46739#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47821#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47822#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47851#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47812#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47518#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47519#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47743#L1131-3 assume !(0 == ~E_9~0); 47744#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47903#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47522#L514-36 assume 1 == ~m_pc~0; 47523#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47107#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47108#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47565#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46991#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46992#L533-36 assume 1 == ~t1_pc~0; 47267#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47360#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47663#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47611#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47414#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47415#L552-36 assume 1 == ~t2_pc~0; 46984#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46986#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46805#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46806#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46958#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46959#L571-36 assume !(1 == ~t3_pc~0); 47344#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 47049#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47050#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47170#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47726#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47019#L590-36 assume !(1 == ~t4_pc~0); 47020#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 47626#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47204#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47205#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47705#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47706#L609-36 assume 1 == ~t5_pc~0; 47581#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47416#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47234#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47235#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47488#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47314#L628-36 assume 1 == ~t6_pc~0; 47173#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47174#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47601#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47602#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47526#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47527#L647-36 assume !(1 == ~t7_pc~0); 47456#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 46712#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46713#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46732#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 46733#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47627#L666-36 assume 1 == ~t8_pc~0; 46915#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46916#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47816#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47817#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47075#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47076#L685-36 assume !(1 == ~t9_pc~0); 46816#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 46817#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47332#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47333#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47214#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47215#L704-36 assume 1 == ~t10_pc~0; 46807#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46808#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47568#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47569#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46837#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46838#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47804#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47682#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47683#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47863#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47143#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47144#L1179-3 assume !(1 == ~T6_E~0); 47775#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46714#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46715#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47090#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47091#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47387#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46577#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46578#L1219-3 assume !(1 == ~E_3~0); 47576#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47577#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47599#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46850#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46851#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47434#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47813#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47579#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 47580#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 46658#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 47405#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 47406#L1584 assume !(0 == start_simulation_~tmp~3#1); 47534#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 46864#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 46559#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 47006#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 47007#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47191#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47158#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 47159#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 46692#L1565-2 [2022-02-21 04:23:11,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,573 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2022-02-21 04:23:11,573 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,573 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833137493] [2022-02-21 04:23:11,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,599 INFO L290 TraceCheckUtils]: 0: Hoare triple {50640#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,600 INFO L290 TraceCheckUtils]: 1: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,600 INFO L290 TraceCheckUtils]: 2: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,601 INFO L290 TraceCheckUtils]: 3: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,601 INFO L290 TraceCheckUtils]: 4: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,601 INFO L290 TraceCheckUtils]: 5: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,601 INFO L290 TraceCheckUtils]: 6: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,602 INFO L290 TraceCheckUtils]: 7: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,602 INFO L290 TraceCheckUtils]: 8: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,602 INFO L290 TraceCheckUtils]: 9: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,602 INFO L290 TraceCheckUtils]: 10: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,603 INFO L290 TraceCheckUtils]: 11: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,603 INFO L290 TraceCheckUtils]: 12: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,603 INFO L290 TraceCheckUtils]: 13: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,604 INFO L290 TraceCheckUtils]: 14: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,604 INFO L290 TraceCheckUtils]: 15: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {50642#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,604 INFO L290 TraceCheckUtils]: 16: Hoare triple {50642#(= ~T3_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {50643#(not (= ~T3_E~0 0))} is VALID [2022-02-21 04:23:11,604 INFO L290 TraceCheckUtils]: 17: Hoare triple {50643#(not (= ~T3_E~0 0))} assume !(0 == ~T1_E~0); {50643#(not (= ~T3_E~0 0))} is VALID [2022-02-21 04:23:11,605 INFO L290 TraceCheckUtils]: 18: Hoare triple {50643#(not (= ~T3_E~0 0))} assume !(0 == ~T2_E~0); {50643#(not (= ~T3_E~0 0))} is VALID [2022-02-21 04:23:11,605 INFO L290 TraceCheckUtils]: 19: Hoare triple {50643#(not (= ~T3_E~0 0))} assume 0 == ~T3_E~0;~T3_E~0 := 1; {50641#false} is VALID [2022-02-21 04:23:11,605 INFO L290 TraceCheckUtils]: 20: Hoare triple {50641#false} assume !(0 == ~T4_E~0); {50641#false} is VALID [2022-02-21 04:23:11,605 INFO L290 TraceCheckUtils]: 21: Hoare triple {50641#false} assume !(0 == ~T5_E~0); {50641#false} is VALID [2022-02-21 04:23:11,605 INFO L290 TraceCheckUtils]: 22: Hoare triple {50641#false} assume !(0 == ~T6_E~0); {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 23: Hoare triple {50641#false} assume !(0 == ~T7_E~0); {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 24: Hoare triple {50641#false} assume !(0 == ~T8_E~0); {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 25: Hoare triple {50641#false} assume !(0 == ~T9_E~0); {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 26: Hoare triple {50641#false} assume !(0 == ~T10_E~0); {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 27: Hoare triple {50641#false} assume 0 == ~E_M~0;~E_M~0 := 1; {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 28: Hoare triple {50641#false} assume !(0 == ~E_1~0); {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 29: Hoare triple {50641#false} assume !(0 == ~E_2~0); {50641#false} is VALID [2022-02-21 04:23:11,606 INFO L290 TraceCheckUtils]: 30: Hoare triple {50641#false} assume !(0 == ~E_3~0); {50641#false} is VALID [2022-02-21 04:23:11,607 INFO L290 TraceCheckUtils]: 31: Hoare triple {50641#false} assume !(0 == ~E_4~0); {50641#false} is VALID [2022-02-21 04:23:11,607 INFO L290 TraceCheckUtils]: 32: Hoare triple {50641#false} assume !(0 == ~E_5~0); {50641#false} is VALID [2022-02-21 04:23:11,607 INFO L290 TraceCheckUtils]: 33: Hoare triple {50641#false} assume !(0 == ~E_6~0); {50641#false} is VALID [2022-02-21 04:23:11,607 INFO L290 TraceCheckUtils]: 34: Hoare triple {50641#false} assume !(0 == ~E_7~0); {50641#false} is VALID [2022-02-21 04:23:11,607 INFO L290 TraceCheckUtils]: 35: Hoare triple {50641#false} assume 0 == ~E_8~0;~E_8~0 := 1; {50641#false} is VALID [2022-02-21 04:23:11,607 INFO L290 TraceCheckUtils]: 36: Hoare triple {50641#false} assume !(0 == ~E_9~0); {50641#false} is VALID [2022-02-21 04:23:11,607 INFO L290 TraceCheckUtils]: 37: Hoare triple {50641#false} assume !(0 == ~E_10~0); {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 38: Hoare triple {50641#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 39: Hoare triple {50641#false} assume 1 == ~m_pc~0; {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 40: Hoare triple {50641#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 41: Hoare triple {50641#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 42: Hoare triple {50641#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 43: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp~1#1); {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 44: Hoare triple {50641#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50641#false} is VALID [2022-02-21 04:23:11,608 INFO L290 TraceCheckUtils]: 45: Hoare triple {50641#false} assume !(1 == ~t1_pc~0); {50641#false} is VALID [2022-02-21 04:23:11,609 INFO L290 TraceCheckUtils]: 46: Hoare triple {50641#false} is_transmit1_triggered_~__retres1~1#1 := 0; {50641#false} is VALID [2022-02-21 04:23:11,609 INFO L290 TraceCheckUtils]: 47: Hoare triple {50641#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50641#false} is VALID [2022-02-21 04:23:11,609 INFO L290 TraceCheckUtils]: 48: Hoare triple {50641#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {50641#false} is VALID [2022-02-21 04:23:11,609 INFO L290 TraceCheckUtils]: 49: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___0~0#1); {50641#false} is VALID [2022-02-21 04:23:11,609 INFO L290 TraceCheckUtils]: 50: Hoare triple {50641#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50641#false} is VALID [2022-02-21 04:23:11,609 INFO L290 TraceCheckUtils]: 51: Hoare triple {50641#false} assume 1 == ~t2_pc~0; {50641#false} is VALID [2022-02-21 04:23:11,609 INFO L290 TraceCheckUtils]: 52: Hoare triple {50641#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 53: Hoare triple {50641#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 54: Hoare triple {50641#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 55: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___1~0#1); {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 56: Hoare triple {50641#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 57: Hoare triple {50641#false} assume 1 == ~t3_pc~0; {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 58: Hoare triple {50641#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 59: Hoare triple {50641#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50641#false} is VALID [2022-02-21 04:23:11,610 INFO L290 TraceCheckUtils]: 60: Hoare triple {50641#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 61: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___2~0#1); {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 62: Hoare triple {50641#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 63: Hoare triple {50641#false} assume !(1 == ~t4_pc~0); {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 64: Hoare triple {50641#false} is_transmit4_triggered_~__retres1~4#1 := 0; {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 65: Hoare triple {50641#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 66: Hoare triple {50641#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 67: Hoare triple {50641#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {50641#false} is VALID [2022-02-21 04:23:11,611 INFO L290 TraceCheckUtils]: 68: Hoare triple {50641#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50641#false} is VALID [2022-02-21 04:23:11,612 INFO L290 TraceCheckUtils]: 69: Hoare triple {50641#false} assume 1 == ~t5_pc~0; {50641#false} is VALID [2022-02-21 04:23:11,612 INFO L290 TraceCheckUtils]: 70: Hoare triple {50641#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {50641#false} is VALID [2022-02-21 04:23:11,612 INFO L290 TraceCheckUtils]: 71: Hoare triple {50641#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50641#false} is VALID [2022-02-21 04:23:11,612 INFO L290 TraceCheckUtils]: 72: Hoare triple {50641#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50641#false} is VALID [2022-02-21 04:23:11,612 INFO L290 TraceCheckUtils]: 73: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___4~0#1); {50641#false} is VALID [2022-02-21 04:23:11,612 INFO L290 TraceCheckUtils]: 74: Hoare triple {50641#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50641#false} is VALID [2022-02-21 04:23:11,612 INFO L290 TraceCheckUtils]: 75: Hoare triple {50641#false} assume !(1 == ~t6_pc~0); {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 76: Hoare triple {50641#false} is_transmit6_triggered_~__retres1~6#1 := 0; {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 77: Hoare triple {50641#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 78: Hoare triple {50641#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 79: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___5~0#1); {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 80: Hoare triple {50641#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 81: Hoare triple {50641#false} assume 1 == ~t7_pc~0; {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 82: Hoare triple {50641#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {50641#false} is VALID [2022-02-21 04:23:11,613 INFO L290 TraceCheckUtils]: 83: Hoare triple {50641#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50641#false} is VALID [2022-02-21 04:23:11,614 INFO L290 TraceCheckUtils]: 84: Hoare triple {50641#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50641#false} is VALID [2022-02-21 04:23:11,614 INFO L290 TraceCheckUtils]: 85: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___6~0#1); {50641#false} is VALID [2022-02-21 04:23:11,614 INFO L290 TraceCheckUtils]: 86: Hoare triple {50641#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50641#false} is VALID [2022-02-21 04:23:11,614 INFO L290 TraceCheckUtils]: 87: Hoare triple {50641#false} assume !(1 == ~t8_pc~0); {50641#false} is VALID [2022-02-21 04:23:11,614 INFO L290 TraceCheckUtils]: 88: Hoare triple {50641#false} is_transmit8_triggered_~__retres1~8#1 := 0; {50641#false} is VALID [2022-02-21 04:23:11,614 INFO L290 TraceCheckUtils]: 89: Hoare triple {50641#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50641#false} is VALID [2022-02-21 04:23:11,614 INFO L290 TraceCheckUtils]: 90: Hoare triple {50641#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 91: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___7~0#1); {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 92: Hoare triple {50641#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 93: Hoare triple {50641#false} assume 1 == ~t9_pc~0; {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 94: Hoare triple {50641#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 95: Hoare triple {50641#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 96: Hoare triple {50641#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 97: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___8~0#1); {50641#false} is VALID [2022-02-21 04:23:11,615 INFO L290 TraceCheckUtils]: 98: Hoare triple {50641#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 99: Hoare triple {50641#false} assume !(1 == ~t10_pc~0); {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 100: Hoare triple {50641#false} is_transmit10_triggered_~__retres1~10#1 := 0; {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 101: Hoare triple {50641#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 102: Hoare triple {50641#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 103: Hoare triple {50641#false} assume !(0 != activate_threads_~tmp___9~0#1); {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 104: Hoare triple {50641#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 105: Hoare triple {50641#false} assume !(1 == ~M_E~0); {50641#false} is VALID [2022-02-21 04:23:11,616 INFO L290 TraceCheckUtils]: 106: Hoare triple {50641#false} assume !(1 == ~T1_E~0); {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 107: Hoare triple {50641#false} assume !(1 == ~T2_E~0); {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 108: Hoare triple {50641#false} assume !(1 == ~T3_E~0); {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 109: Hoare triple {50641#false} assume !(1 == ~T4_E~0); {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 110: Hoare triple {50641#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 111: Hoare triple {50641#false} assume !(1 == ~T6_E~0); {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 112: Hoare triple {50641#false} assume !(1 == ~T7_E~0); {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 113: Hoare triple {50641#false} assume !(1 == ~T8_E~0); {50641#false} is VALID [2022-02-21 04:23:11,617 INFO L290 TraceCheckUtils]: 114: Hoare triple {50641#false} assume !(1 == ~T9_E~0); {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 115: Hoare triple {50641#false} assume !(1 == ~T10_E~0); {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 116: Hoare triple {50641#false} assume !(1 == ~E_M~0); {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 117: Hoare triple {50641#false} assume !(1 == ~E_1~0); {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 118: Hoare triple {50641#false} assume 1 == ~E_2~0;~E_2~0 := 2; {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 119: Hoare triple {50641#false} assume !(1 == ~E_3~0); {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 120: Hoare triple {50641#false} assume !(1 == ~E_4~0); {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 121: Hoare triple {50641#false} assume !(1 == ~E_5~0); {50641#false} is VALID [2022-02-21 04:23:11,618 INFO L290 TraceCheckUtils]: 122: Hoare triple {50641#false} assume !(1 == ~E_6~0); {50641#false} is VALID [2022-02-21 04:23:11,619 INFO L290 TraceCheckUtils]: 123: Hoare triple {50641#false} assume !(1 == ~E_7~0); {50641#false} is VALID [2022-02-21 04:23:11,619 INFO L290 TraceCheckUtils]: 124: Hoare triple {50641#false} assume !(1 == ~E_8~0); {50641#false} is VALID [2022-02-21 04:23:11,619 INFO L290 TraceCheckUtils]: 125: Hoare triple {50641#false} assume !(1 == ~E_9~0); {50641#false} is VALID [2022-02-21 04:23:11,619 INFO L290 TraceCheckUtils]: 126: Hoare triple {50641#false} assume 1 == ~E_10~0;~E_10~0 := 2; {50641#false} is VALID [2022-02-21 04:23:11,619 INFO L290 TraceCheckUtils]: 127: Hoare triple {50641#false} assume { :end_inline_reset_delta_events } true; {50641#false} is VALID [2022-02-21 04:23:11,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,620 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,620 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833137493] [2022-02-21 04:23:11,620 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833137493] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,620 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,620 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,620 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769731921] [2022-02-21 04:23:11,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,621 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:11,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,622 INFO L85 PathProgramCache]: Analyzing trace with hash -708994987, now seen corresponding path program 1 times [2022-02-21 04:23:11,622 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,622 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338379002] [2022-02-21 04:23:11,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 0: Hoare triple {50644#true} assume !false; {50644#true} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 1: Hoare triple {50644#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {50644#true} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 2: Hoare triple {50644#true} assume !false; {50644#true} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 3: Hoare triple {50644#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {50644#true} is VALID [2022-02-21 04:23:11,651 INFO L290 TraceCheckUtils]: 4: Hoare triple {50644#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 5: Hoare triple {50644#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 6: Hoare triple {50644#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 7: Hoare triple {50644#true} assume !(0 != eval_~tmp~0#1); {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 8: Hoare triple {50644#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 9: Hoare triple {50644#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 10: Hoare triple {50644#true} assume 0 == ~M_E~0;~M_E~0 := 1; {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 11: Hoare triple {50644#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {50644#true} is VALID [2022-02-21 04:23:11,652 INFO L290 TraceCheckUtils]: 12: Hoare triple {50644#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {50644#true} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 13: Hoare triple {50644#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {50644#true} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 14: Hoare triple {50644#true} assume !(0 == ~T4_E~0); {50644#true} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 15: Hoare triple {50644#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {50644#true} is VALID [2022-02-21 04:23:11,653 INFO L290 TraceCheckUtils]: 16: Hoare triple {50644#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 17: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 18: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 19: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,654 INFO L290 TraceCheckUtils]: 20: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 21: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 22: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,655 INFO L290 TraceCheckUtils]: 23: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 24: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 25: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 26: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,656 INFO L290 TraceCheckUtils]: 27: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 28: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 29: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 30: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,657 INFO L290 TraceCheckUtils]: 31: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,658 INFO L290 TraceCheckUtils]: 32: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,658 INFO L290 TraceCheckUtils]: 33: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,658 INFO L290 TraceCheckUtils]: 34: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,659 INFO L290 TraceCheckUtils]: 35: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,659 INFO L290 TraceCheckUtils]: 36: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,659 INFO L290 TraceCheckUtils]: 37: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,659 INFO L290 TraceCheckUtils]: 38: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 39: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 40: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,660 INFO L290 TraceCheckUtils]: 41: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,661 INFO L290 TraceCheckUtils]: 42: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,661 INFO L290 TraceCheckUtils]: 43: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,661 INFO L290 TraceCheckUtils]: 44: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,661 INFO L290 TraceCheckUtils]: 45: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,662 INFO L290 TraceCheckUtils]: 46: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,662 INFO L290 TraceCheckUtils]: 47: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,662 INFO L290 TraceCheckUtils]: 48: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,662 INFO L290 TraceCheckUtils]: 49: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 50: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 51: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 52: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,663 INFO L290 TraceCheckUtils]: 53: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 54: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 55: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,664 INFO L290 TraceCheckUtils]: 56: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 57: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 58: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 59: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,665 INFO L290 TraceCheckUtils]: 60: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 61: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 62: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 63: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,666 INFO L290 TraceCheckUtils]: 64: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 65: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 66: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,667 INFO L290 TraceCheckUtils]: 67: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 68: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 69: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 70: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,668 INFO L290 TraceCheckUtils]: 71: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 72: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 73: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 74: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,669 INFO L290 TraceCheckUtils]: 75: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 76: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 77: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,670 INFO L290 TraceCheckUtils]: 78: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 79: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 80: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 81: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,671 INFO L290 TraceCheckUtils]: 82: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 83: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 84: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 85: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,672 INFO L290 TraceCheckUtils]: 86: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 87: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 88: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,673 INFO L290 TraceCheckUtils]: 89: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,674 INFO L290 TraceCheckUtils]: 90: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,674 INFO L290 TraceCheckUtils]: 91: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,674 INFO L290 TraceCheckUtils]: 92: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,674 INFO L290 TraceCheckUtils]: 93: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,675 INFO L290 TraceCheckUtils]: 94: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,675 INFO L290 TraceCheckUtils]: 95: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,675 INFO L290 TraceCheckUtils]: 96: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,675 INFO L290 TraceCheckUtils]: 97: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,676 INFO L290 TraceCheckUtils]: 98: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,676 INFO L290 TraceCheckUtils]: 99: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,676 INFO L290 TraceCheckUtils]: 100: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,676 INFO L290 TraceCheckUtils]: 101: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,677 INFO L290 TraceCheckUtils]: 102: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,677 INFO L290 TraceCheckUtils]: 103: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,677 INFO L290 TraceCheckUtils]: 104: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {50646#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 105: Hoare triple {50646#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {50645#false} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 106: Hoare triple {50645#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 107: Hoare triple {50645#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 108: Hoare triple {50645#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 109: Hoare triple {50645#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 110: Hoare triple {50645#false} assume 1 == ~E_M~0;~E_M~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 111: Hoare triple {50645#false} assume 1 == ~E_1~0;~E_1~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,678 INFO L290 TraceCheckUtils]: 112: Hoare triple {50645#false} assume 1 == ~E_2~0;~E_2~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,679 INFO L290 TraceCheckUtils]: 113: Hoare triple {50645#false} assume !(1 == ~E_3~0); {50645#false} is VALID [2022-02-21 04:23:11,679 INFO L290 TraceCheckUtils]: 114: Hoare triple {50645#false} assume 1 == ~E_4~0;~E_4~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,679 INFO L290 TraceCheckUtils]: 115: Hoare triple {50645#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,679 INFO L290 TraceCheckUtils]: 116: Hoare triple {50645#false} assume 1 == ~E_6~0;~E_6~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,679 INFO L290 TraceCheckUtils]: 117: Hoare triple {50645#false} assume 1 == ~E_7~0;~E_7~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,679 INFO L290 TraceCheckUtils]: 118: Hoare triple {50645#false} assume 1 == ~E_8~0;~E_8~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,679 INFO L290 TraceCheckUtils]: 119: Hoare triple {50645#false} assume 1 == ~E_9~0;~E_9~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 120: Hoare triple {50645#false} assume 1 == ~E_10~0;~E_10~0 := 2; {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 121: Hoare triple {50645#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 122: Hoare triple {50645#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 123: Hoare triple {50645#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 124: Hoare triple {50645#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 125: Hoare triple {50645#false} assume !(0 == start_simulation_~tmp~3#1); {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 126: Hoare triple {50645#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {50645#false} is VALID [2022-02-21 04:23:11,680 INFO L290 TraceCheckUtils]: 127: Hoare triple {50645#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {50645#false} is VALID [2022-02-21 04:23:11,681 INFO L290 TraceCheckUtils]: 128: Hoare triple {50645#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {50645#false} is VALID [2022-02-21 04:23:11,681 INFO L290 TraceCheckUtils]: 129: Hoare triple {50645#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {50645#false} is VALID [2022-02-21 04:23:11,681 INFO L290 TraceCheckUtils]: 130: Hoare triple {50645#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {50645#false} is VALID [2022-02-21 04:23:11,681 INFO L290 TraceCheckUtils]: 131: Hoare triple {50645#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {50645#false} is VALID [2022-02-21 04:23:11,681 INFO L290 TraceCheckUtils]: 132: Hoare triple {50645#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {50645#false} is VALID [2022-02-21 04:23:11,681 INFO L290 TraceCheckUtils]: 133: Hoare triple {50645#false} assume !(0 != start_simulation_~tmp___0~1#1); {50645#false} is VALID [2022-02-21 04:23:11,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,682 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,682 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338379002] [2022-02-21 04:23:11,682 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338379002] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,682 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,682 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,682 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795604207] [2022-02-21 04:23:11,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,683 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:11,683 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:11,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:11,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:11,684 INFO L87 Difference]: Start difference. First operand 1366 states and 2024 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,295 INFO L93 Difference]: Finished difference Result 2514 states and 3712 transitions. [2022-02-21 04:23:14,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:14,296 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,387 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:14,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2514 states and 3712 transitions. [2022-02-21 04:23:14,598 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2022-02-21 04:23:14,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2514 states to 2514 states and 3712 transitions. [2022-02-21 04:23:14,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2514 [2022-02-21 04:23:14,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2514 [2022-02-21 04:23:14,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2514 states and 3712 transitions. [2022-02-21 04:23:14,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:14,750 INFO L681 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2022-02-21 04:23:14,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2514 states and 3712 transitions. [2022-02-21 04:23:14,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2514 to 2514. [2022-02-21 04:23:14,776 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:14,779 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2514 states and 3712 transitions. Second operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,783 INFO L74 IsIncluded]: Start isIncluded. First operand 2514 states and 3712 transitions. Second operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,786 INFO L87 Difference]: Start difference. First operand 2514 states and 3712 transitions. Second operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,917 INFO L93 Difference]: Finished difference Result 2514 states and 3712 transitions. [2022-02-21 04:23:14,917 INFO L276 IsEmpty]: Start isEmpty. Operand 2514 states and 3712 transitions. [2022-02-21 04:23:14,919 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,920 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,923 INFO L74 IsIncluded]: Start isIncluded. First operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2514 states and 3712 transitions. [2022-02-21 04:23:14,926 INFO L87 Difference]: Start difference. First operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2514 states and 3712 transitions. [2022-02-21 04:23:15,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,066 INFO L93 Difference]: Finished difference Result 2514 states and 3712 transitions. [2022-02-21 04:23:15,066 INFO L276 IsEmpty]: Start isEmpty. Operand 2514 states and 3712 transitions. [2022-02-21 04:23:15,068 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:15,068 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:15,069 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:15,069 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:15,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2514 states to 2514 states and 3712 transitions. [2022-02-21 04:23:15,218 INFO L704 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2022-02-21 04:23:15,218 INFO L587 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2022-02-21 04:23:15,218 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:15,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2514 states and 3712 transitions. [2022-02-21 04:23:15,222 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2022-02-21 04:23:15,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:15,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:15,224 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,224 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,224 INFO L791 eck$LassoCheckResult]: Stem: 54224#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 54225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 54437#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53212#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53213#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 54463#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54420#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54421#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54452#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53521#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53522#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53627#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53872#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53803#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53523#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53185#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53186#L1036 assume !(0 == ~M_E~0); 53284#L1036-2 assume !(0 == ~T1_E~0); 54164#L1041-1 assume !(0 == ~T2_E~0); 54165#L1046-1 assume !(0 == ~T3_E~0); 53559#L1051-1 assume !(0 == ~T4_E~0); 53560#L1056-1 assume !(0 == ~T5_E~0); 54303#L1061-1 assume !(0 == ~T6_E~0); 53457#L1066-1 assume !(0 == ~T7_E~0); 53458#L1071-1 assume !(0 == ~T8_E~0); 54286#L1076-1 assume !(0 == ~T9_E~0); 53352#L1081-1 assume !(0 == ~T10_E~0); 53353#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 53756#L1091-1 assume !(0 == ~E_1~0); 54467#L1096-1 assume !(0 == ~E_2~0); 54468#L1101-1 assume !(0 == ~E_3~0); 53817#L1106-1 assume !(0 == ~E_4~0); 53818#L1111-1 assume !(0 == ~E_5~0); 53974#L1116-1 assume !(0 == ~E_6~0); 53975#L1121-1 assume !(0 == ~E_7~0); 53810#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 53811#L1131-1 assume !(0 == ~E_9~0); 54064#L1136-1 assume !(0 == ~E_10~0); 54172#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54332#L514 assume 1 == ~m_pc~0; 54293#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53830#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53747#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53748#L1285 assume !(0 != activate_threads_~tmp~1#1); 54510#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53476#L533 assume !(1 == ~t1_pc~0); 53477#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53990#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53863#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53864#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 54194#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54195#L552 assume 1 == ~t2_pc~0; 53701#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53702#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54274#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54275#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 53842#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53843#L571 assume 1 == ~t3_pc~0; 54022#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54023#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53390#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53391#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 53980#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53266#L590 assume !(1 == ~t4_pc~0); 53267#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54035#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54270#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54271#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54226#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53976#L609 assume 1 == ~t5_pc~0; 53977#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54508#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53303#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53304#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 53971#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53972#L628 assume !(1 == ~t6_pc~0); 53905#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53904#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54488#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54489#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 54266#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54267#L647 assume 1 == ~t7_pc~0; 53819#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53820#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54099#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53822#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 53823#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54545#L666 assume !(1 == ~t8_pc~0); 53606#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 53607#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53841#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53998#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 53753#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53754#L685 assume 1 == ~t9_pc~0; 54521#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54404#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54396#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53779#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 53780#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54136#L704 assume !(1 == ~t10_pc~0); 53771#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53770#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54301#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53322#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 53323#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53570#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 54253#L1154-2 assume !(1 == ~T1_E~0); 54732#L1159-1 assume !(1 == ~T2_E~0); 54730#L1164-1 assume !(1 == ~T3_E~0); 54551#L1169-1 assume !(1 == ~T4_E~0); 54727#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54725#L1179-1 assume !(1 == ~T6_E~0); 54722#L1184-1 assume !(1 == ~T7_E~0); 54720#L1189-1 assume !(1 == ~T8_E~0); 54718#L1194-1 assume !(1 == ~T9_E~0); 54716#L1199-1 assume !(1 == ~T10_E~0); 54714#L1204-1 assume !(1 == ~E_M~0); 54712#L1209-1 assume !(1 == ~E_1~0); 54709#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 54707#L1219-1 assume !(1 == ~E_3~0); 54705#L1224-1 assume !(1 == ~E_4~0); 54703#L1229-1 assume !(1 == ~E_5~0); 54701#L1234-1 assume !(1 == ~E_6~0); 54700#L1239-1 assume !(1 == ~E_7~0); 54699#L1244-1 assume !(1 == ~E_8~0); 54604#L1249-1 assume !(1 == ~E_9~0); 54602#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 54592#L1259-1 assume { :end_inline_reset_delta_events } true; 54585#L1565-2 [2022-02-21 04:23:15,225 INFO L793 eck$LassoCheckResult]: Loop: 54585#L1565-2 assume !false; 54579#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54574#L1011 assume !false; 54573#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 54572#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 54561#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 54560#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54559#L866 assume !(0 != eval_~tmp~0#1); 54558#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54557#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54556#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54490#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54491#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54358#L1046-3 assume !(0 == ~T3_E~0); 54359#L1051-3 assume !(0 == ~T4_E~0); 54298#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53556#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53557#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53558#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54492#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53307#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53308#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53362#L1091-3 assume !(0 == ~E_1~0); 53363#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54454#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54455#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54487#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54444#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54146#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54147#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54374#L1131-3 assume !(0 == ~E_9~0); 54375#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 54549#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54150#L514-36 assume 1 == ~m_pc~0; 54151#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53731#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53732#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54193#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53615#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53616#L533-36 assume 1 == ~t1_pc~0; 53891#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53984#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54292#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54239#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54040#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54041#L552-36 assume 1 == ~t2_pc~0; 53608#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53610#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53429#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53430#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53582#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53583#L571-36 assume !(1 == ~t3_pc~0); 53968#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 53673#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53674#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53794#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54357#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53643#L590-36 assume !(1 == ~t4_pc~0); 53644#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 54255#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53828#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53829#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54336#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54337#L609-36 assume 1 == ~t5_pc~0; 54209#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54042#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53858#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53859#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54115#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53938#L628-36 assume 1 == ~t6_pc~0; 53797#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53798#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54229#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54230#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54154#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54155#L647-36 assume 1 == ~t7_pc~0; 54082#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53336#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53337#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53356#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 53357#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54256#L666-36 assume 1 == ~t8_pc~0; 53539#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53540#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54448#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54449#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53699#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53700#L685-36 assume !(1 == ~t9_pc~0); 53440#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 53441#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53956#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53957#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53838#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53839#L704-36 assume 1 == ~t10_pc~0; 53431#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53432#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54196#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54197#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53461#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53462#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54436#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54311#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54312#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54504#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53767#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53768#L1179-3 assume !(1 == ~T6_E~0); 54406#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53338#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53339#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53714#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53715#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54013#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53201#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53202#L1219-3 assume !(1 == ~E_3~0); 54204#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54205#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54227#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53474#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53475#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54061#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54445#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54207#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 54208#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 53282#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 54031#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 54032#L1584 assume !(0 == start_simulation_~tmp~3#1); 54162#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 53488#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 53183#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 53630#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 53631#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53815#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53782#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 53783#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 54585#L1565-2 [2022-02-21 04:23:15,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,225 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2022-02-21 04:23:15,225 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,226 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590960198] [2022-02-21 04:23:15,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,259 INFO L290 TraceCheckUtils]: 0: Hoare triple {60708#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,259 INFO L290 TraceCheckUtils]: 1: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,259 INFO L290 TraceCheckUtils]: 2: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,260 INFO L290 TraceCheckUtils]: 3: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,260 INFO L290 TraceCheckUtils]: 4: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,260 INFO L290 TraceCheckUtils]: 5: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,260 INFO L290 TraceCheckUtils]: 6: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,261 INFO L290 TraceCheckUtils]: 7: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,261 INFO L290 TraceCheckUtils]: 8: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,261 INFO L290 TraceCheckUtils]: 9: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,261 INFO L290 TraceCheckUtils]: 10: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,262 INFO L290 TraceCheckUtils]: 11: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,262 INFO L290 TraceCheckUtils]: 12: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,262 INFO L290 TraceCheckUtils]: 13: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,263 INFO L290 TraceCheckUtils]: 14: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,263 INFO L290 TraceCheckUtils]: 15: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {60710#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,263 INFO L290 TraceCheckUtils]: 16: Hoare triple {60710#(= ~E_M~0 ~M_E~0)} assume !(0 == ~M_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,263 INFO L290 TraceCheckUtils]: 17: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T1_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,264 INFO L290 TraceCheckUtils]: 18: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T2_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,264 INFO L290 TraceCheckUtils]: 19: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T3_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,264 INFO L290 TraceCheckUtils]: 20: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T4_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,264 INFO L290 TraceCheckUtils]: 21: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T5_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,265 INFO L290 TraceCheckUtils]: 22: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T6_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,265 INFO L290 TraceCheckUtils]: 23: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T7_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,265 INFO L290 TraceCheckUtils]: 24: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T8_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,265 INFO L290 TraceCheckUtils]: 25: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T9_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 26: Hoare triple {60711#(not (= ~E_M~0 0))} assume !(0 == ~T10_E~0); {60711#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 27: Hoare triple {60711#(not (= ~E_M~0 0))} assume 0 == ~E_M~0;~E_M~0 := 1; {60709#false} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 28: Hoare triple {60709#false} assume !(0 == ~E_1~0); {60709#false} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 29: Hoare triple {60709#false} assume !(0 == ~E_2~0); {60709#false} is VALID [2022-02-21 04:23:15,266 INFO L290 TraceCheckUtils]: 30: Hoare triple {60709#false} assume !(0 == ~E_3~0); {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 31: Hoare triple {60709#false} assume !(0 == ~E_4~0); {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 32: Hoare triple {60709#false} assume !(0 == ~E_5~0); {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 33: Hoare triple {60709#false} assume !(0 == ~E_6~0); {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 34: Hoare triple {60709#false} assume !(0 == ~E_7~0); {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 35: Hoare triple {60709#false} assume 0 == ~E_8~0;~E_8~0 := 1; {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 36: Hoare triple {60709#false} assume !(0 == ~E_9~0); {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 37: Hoare triple {60709#false} assume !(0 == ~E_10~0); {60709#false} is VALID [2022-02-21 04:23:15,267 INFO L290 TraceCheckUtils]: 38: Hoare triple {60709#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 39: Hoare triple {60709#false} assume 1 == ~m_pc~0; {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 40: Hoare triple {60709#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 41: Hoare triple {60709#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 42: Hoare triple {60709#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 43: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp~1#1); {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 44: Hoare triple {60709#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 45: Hoare triple {60709#false} assume !(1 == ~t1_pc~0); {60709#false} is VALID [2022-02-21 04:23:15,268 INFO L290 TraceCheckUtils]: 46: Hoare triple {60709#false} is_transmit1_triggered_~__retres1~1#1 := 0; {60709#false} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 47: Hoare triple {60709#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {60709#false} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 48: Hoare triple {60709#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {60709#false} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 49: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___0~0#1); {60709#false} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 50: Hoare triple {60709#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {60709#false} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 51: Hoare triple {60709#false} assume 1 == ~t2_pc~0; {60709#false} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 52: Hoare triple {60709#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {60709#false} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 53: Hoare triple {60709#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 54: Hoare triple {60709#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 55: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___1~0#1); {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 56: Hoare triple {60709#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 57: Hoare triple {60709#false} assume 1 == ~t3_pc~0; {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 58: Hoare triple {60709#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 59: Hoare triple {60709#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 60: Hoare triple {60709#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {60709#false} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 61: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___2~0#1); {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 62: Hoare triple {60709#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 63: Hoare triple {60709#false} assume !(1 == ~t4_pc~0); {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 64: Hoare triple {60709#false} is_transmit4_triggered_~__retres1~4#1 := 0; {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 65: Hoare triple {60709#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 66: Hoare triple {60709#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 67: Hoare triple {60709#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 68: Hoare triple {60709#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {60709#false} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 69: Hoare triple {60709#false} assume 1 == ~t5_pc~0; {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 70: Hoare triple {60709#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 71: Hoare triple {60709#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 72: Hoare triple {60709#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 73: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___4~0#1); {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 74: Hoare triple {60709#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 75: Hoare triple {60709#false} assume !(1 == ~t6_pc~0); {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 76: Hoare triple {60709#false} is_transmit6_triggered_~__retres1~6#1 := 0; {60709#false} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 77: Hoare triple {60709#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {60709#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 78: Hoare triple {60709#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {60709#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 79: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___5~0#1); {60709#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 80: Hoare triple {60709#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {60709#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 81: Hoare triple {60709#false} assume 1 == ~t7_pc~0; {60709#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 82: Hoare triple {60709#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {60709#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 83: Hoare triple {60709#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {60709#false} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 84: Hoare triple {60709#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 85: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___6~0#1); {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 86: Hoare triple {60709#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 87: Hoare triple {60709#false} assume !(1 == ~t8_pc~0); {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 88: Hoare triple {60709#false} is_transmit8_triggered_~__retres1~8#1 := 0; {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 89: Hoare triple {60709#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 90: Hoare triple {60709#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 91: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___7~0#1); {60709#false} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 92: Hoare triple {60709#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 93: Hoare triple {60709#false} assume 1 == ~t9_pc~0; {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 94: Hoare triple {60709#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 95: Hoare triple {60709#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 96: Hoare triple {60709#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 97: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___8~0#1); {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 98: Hoare triple {60709#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 99: Hoare triple {60709#false} assume !(1 == ~t10_pc~0); {60709#false} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 100: Hoare triple {60709#false} is_transmit10_triggered_~__retres1~10#1 := 0; {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 101: Hoare triple {60709#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 102: Hoare triple {60709#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 103: Hoare triple {60709#false} assume !(0 != activate_threads_~tmp___9~0#1); {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 104: Hoare triple {60709#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 105: Hoare triple {60709#false} assume 1 == ~M_E~0;~M_E~0 := 2; {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 106: Hoare triple {60709#false} assume !(1 == ~T1_E~0); {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 107: Hoare triple {60709#false} assume !(1 == ~T2_E~0); {60709#false} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 108: Hoare triple {60709#false} assume !(1 == ~T3_E~0); {60709#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 109: Hoare triple {60709#false} assume !(1 == ~T4_E~0); {60709#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 110: Hoare triple {60709#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {60709#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 111: Hoare triple {60709#false} assume !(1 == ~T6_E~0); {60709#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 112: Hoare triple {60709#false} assume !(1 == ~T7_E~0); {60709#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 113: Hoare triple {60709#false} assume !(1 == ~T8_E~0); {60709#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 114: Hoare triple {60709#false} assume !(1 == ~T9_E~0); {60709#false} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 115: Hoare triple {60709#false} assume !(1 == ~T10_E~0); {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 116: Hoare triple {60709#false} assume !(1 == ~E_M~0); {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 117: Hoare triple {60709#false} assume !(1 == ~E_1~0); {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 118: Hoare triple {60709#false} assume 1 == ~E_2~0;~E_2~0 := 2; {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 119: Hoare triple {60709#false} assume !(1 == ~E_3~0); {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 120: Hoare triple {60709#false} assume !(1 == ~E_4~0); {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 121: Hoare triple {60709#false} assume !(1 == ~E_5~0); {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 122: Hoare triple {60709#false} assume !(1 == ~E_6~0); {60709#false} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 123: Hoare triple {60709#false} assume !(1 == ~E_7~0); {60709#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 124: Hoare triple {60709#false} assume !(1 == ~E_8~0); {60709#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 125: Hoare triple {60709#false} assume !(1 == ~E_9~0); {60709#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 126: Hoare triple {60709#false} assume 1 == ~E_10~0;~E_10~0 := 2; {60709#false} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 127: Hoare triple {60709#false} assume { :end_inline_reset_delta_events } true; {60709#false} is VALID [2022-02-21 04:23:15,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,280 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,280 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590960198] [2022-02-21 04:23:15,280 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590960198] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,280 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,280 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,280 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316179216] [2022-02-21 04:23:15,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,281 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:15,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,281 INFO L85 PathProgramCache]: Analyzing trace with hash 810382934, now seen corresponding path program 1 times [2022-02-21 04:23:15,281 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,281 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854787071] [2022-02-21 04:23:15,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,305 INFO L290 TraceCheckUtils]: 0: Hoare triple {60712#true} assume !false; {60712#true} is VALID [2022-02-21 04:23:15,305 INFO L290 TraceCheckUtils]: 1: Hoare triple {60712#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {60712#true} is VALID [2022-02-21 04:23:15,305 INFO L290 TraceCheckUtils]: 2: Hoare triple {60712#true} assume !false; {60712#true} is VALID [2022-02-21 04:23:15,306 INFO L290 TraceCheckUtils]: 3: Hoare triple {60712#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {60712#true} is VALID [2022-02-21 04:23:15,306 INFO L290 TraceCheckUtils]: 4: Hoare triple {60712#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {60712#true} is VALID [2022-02-21 04:23:15,306 INFO L290 TraceCheckUtils]: 5: Hoare triple {60712#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {60712#true} is VALID [2022-02-21 04:23:15,306 INFO L290 TraceCheckUtils]: 6: Hoare triple {60712#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {60712#true} is VALID [2022-02-21 04:23:15,306 INFO L290 TraceCheckUtils]: 7: Hoare triple {60712#true} assume !(0 != eval_~tmp~0#1); {60712#true} is VALID [2022-02-21 04:23:15,306 INFO L290 TraceCheckUtils]: 8: Hoare triple {60712#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {60712#true} is VALID [2022-02-21 04:23:15,306 INFO L290 TraceCheckUtils]: 9: Hoare triple {60712#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {60712#true} is VALID [2022-02-21 04:23:15,307 INFO L290 TraceCheckUtils]: 10: Hoare triple {60712#true} assume 0 == ~M_E~0;~M_E~0 := 1; {60712#true} is VALID [2022-02-21 04:23:15,307 INFO L290 TraceCheckUtils]: 11: Hoare triple {60712#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {60712#true} is VALID [2022-02-21 04:23:15,307 INFO L290 TraceCheckUtils]: 12: Hoare triple {60712#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {60712#true} is VALID [2022-02-21 04:23:15,307 INFO L290 TraceCheckUtils]: 13: Hoare triple {60712#true} assume !(0 == ~T3_E~0); {60712#true} is VALID [2022-02-21 04:23:15,307 INFO L290 TraceCheckUtils]: 14: Hoare triple {60712#true} assume !(0 == ~T4_E~0); {60712#true} is VALID [2022-02-21 04:23:15,307 INFO L290 TraceCheckUtils]: 15: Hoare triple {60712#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {60712#true} is VALID [2022-02-21 04:23:15,307 INFO L290 TraceCheckUtils]: 16: Hoare triple {60712#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,308 INFO L290 TraceCheckUtils]: 17: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,308 INFO L290 TraceCheckUtils]: 18: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,308 INFO L290 TraceCheckUtils]: 19: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,309 INFO L290 TraceCheckUtils]: 20: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,309 INFO L290 TraceCheckUtils]: 21: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,309 INFO L290 TraceCheckUtils]: 22: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,309 INFO L290 TraceCheckUtils]: 23: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,310 INFO L290 TraceCheckUtils]: 24: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,310 INFO L290 TraceCheckUtils]: 25: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,310 INFO L290 TraceCheckUtils]: 26: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,310 INFO L290 TraceCheckUtils]: 27: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,311 INFO L290 TraceCheckUtils]: 28: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,311 INFO L290 TraceCheckUtils]: 29: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,311 INFO L290 TraceCheckUtils]: 30: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,311 INFO L290 TraceCheckUtils]: 31: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,312 INFO L290 TraceCheckUtils]: 32: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,312 INFO L290 TraceCheckUtils]: 33: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,312 INFO L290 TraceCheckUtils]: 34: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,313 INFO L290 TraceCheckUtils]: 35: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,313 INFO L290 TraceCheckUtils]: 36: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,313 INFO L290 TraceCheckUtils]: 37: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,313 INFO L290 TraceCheckUtils]: 38: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,314 INFO L290 TraceCheckUtils]: 39: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,314 INFO L290 TraceCheckUtils]: 40: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,314 INFO L290 TraceCheckUtils]: 41: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,314 INFO L290 TraceCheckUtils]: 42: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,315 INFO L290 TraceCheckUtils]: 43: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,315 INFO L290 TraceCheckUtils]: 44: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,315 INFO L290 TraceCheckUtils]: 45: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,315 INFO L290 TraceCheckUtils]: 46: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,316 INFO L290 TraceCheckUtils]: 47: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,316 INFO L290 TraceCheckUtils]: 48: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,316 INFO L290 TraceCheckUtils]: 49: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,316 INFO L290 TraceCheckUtils]: 50: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,317 INFO L290 TraceCheckUtils]: 51: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,317 INFO L290 TraceCheckUtils]: 52: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,317 INFO L290 TraceCheckUtils]: 53: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 54: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 55: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 56: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,318 INFO L290 TraceCheckUtils]: 57: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 58: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 59: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 60: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,319 INFO L290 TraceCheckUtils]: 61: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 62: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 63: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 64: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,320 INFO L290 TraceCheckUtils]: 65: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 66: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 67: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 68: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,321 INFO L290 TraceCheckUtils]: 69: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 70: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 71: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,322 INFO L290 TraceCheckUtils]: 72: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 73: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 74: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 75: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,323 INFO L290 TraceCheckUtils]: 76: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 77: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 78: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 79: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,324 INFO L290 TraceCheckUtils]: 80: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 81: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 82: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 83: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,325 INFO L290 TraceCheckUtils]: 84: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 85: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 86: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 87: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,326 INFO L290 TraceCheckUtils]: 88: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 89: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 90: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,327 INFO L290 TraceCheckUtils]: 91: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 92: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 93: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 94: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,328 INFO L290 TraceCheckUtils]: 95: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 96: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 97: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 98: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,329 INFO L290 TraceCheckUtils]: 99: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 100: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 101: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 102: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,330 INFO L290 TraceCheckUtils]: 103: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 104: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {60714#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 105: Hoare triple {60714#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {60713#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 106: Hoare triple {60713#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 107: Hoare triple {60713#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,331 INFO L290 TraceCheckUtils]: 108: Hoare triple {60713#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 109: Hoare triple {60713#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 110: Hoare triple {60713#false} assume 1 == ~E_M~0;~E_M~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 111: Hoare triple {60713#false} assume 1 == ~E_1~0;~E_1~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 112: Hoare triple {60713#false} assume 1 == ~E_2~0;~E_2~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 113: Hoare triple {60713#false} assume !(1 == ~E_3~0); {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 114: Hoare triple {60713#false} assume 1 == ~E_4~0;~E_4~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 115: Hoare triple {60713#false} assume 1 == ~E_5~0;~E_5~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,332 INFO L290 TraceCheckUtils]: 116: Hoare triple {60713#false} assume 1 == ~E_6~0;~E_6~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 117: Hoare triple {60713#false} assume 1 == ~E_7~0;~E_7~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 118: Hoare triple {60713#false} assume 1 == ~E_8~0;~E_8~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 119: Hoare triple {60713#false} assume 1 == ~E_9~0;~E_9~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 120: Hoare triple {60713#false} assume 1 == ~E_10~0;~E_10~0 := 2; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 121: Hoare triple {60713#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 122: Hoare triple {60713#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 123: Hoare triple {60713#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {60713#false} is VALID [2022-02-21 04:23:15,333 INFO L290 TraceCheckUtils]: 124: Hoare triple {60713#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 125: Hoare triple {60713#false} assume !(0 == start_simulation_~tmp~3#1); {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 126: Hoare triple {60713#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 127: Hoare triple {60713#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 128: Hoare triple {60713#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 129: Hoare triple {60713#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 130: Hoare triple {60713#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 131: Hoare triple {60713#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {60713#false} is VALID [2022-02-21 04:23:15,334 INFO L290 TraceCheckUtils]: 132: Hoare triple {60713#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {60713#false} is VALID [2022-02-21 04:23:15,335 INFO L290 TraceCheckUtils]: 133: Hoare triple {60713#false} assume !(0 != start_simulation_~tmp___0~1#1); {60713#false} is VALID [2022-02-21 04:23:15,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,335 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,335 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854787071] [2022-02-21 04:23:15,335 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854787071] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,336 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,336 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,336 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171211887] [2022-02-21 04:23:15,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,336 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:15,336 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:15,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:15,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:15,337 INFO L87 Difference]: Start difference. First operand 2514 states and 3712 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,258 INFO L93 Difference]: Finished difference Result 4640 states and 6839 transitions. [2022-02-21 04:23:18,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:18,258 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,336 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:18,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4640 states and 6839 transitions. [2022-02-21 04:23:18,807 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2022-02-21 04:23:19,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4640 states to 4640 states and 6839 transitions. [2022-02-21 04:23:19,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4640 [2022-02-21 04:23:19,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4640 [2022-02-21 04:23:19,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4640 states and 6839 transitions. [2022-02-21 04:23:19,280 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:19,280 INFO L681 BuchiCegarLoop]: Abstraction has 4640 states and 6839 transitions. [2022-02-21 04:23:19,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4640 states and 6839 transitions. [2022-02-21 04:23:19,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4640 to 4638. [2022-02-21 04:23:19,321 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:19,327 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4640 states and 6839 transitions. Second operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,332 INFO L74 IsIncluded]: Start isIncluded. First operand 4640 states and 6839 transitions. Second operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,338 INFO L87 Difference]: Start difference. First operand 4640 states and 6839 transitions. Second operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,816 INFO L93 Difference]: Finished difference Result 4640 states and 6839 transitions. [2022-02-21 04:23:19,816 INFO L276 IsEmpty]: Start isEmpty. Operand 4640 states and 6839 transitions. [2022-02-21 04:23:19,820 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,820 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,825 INFO L74 IsIncluded]: Start isIncluded. First operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4640 states and 6839 transitions. [2022-02-21 04:23:19,827 INFO L87 Difference]: Start difference. First operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4640 states and 6839 transitions. [2022-02-21 04:23:20,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,307 INFO L93 Difference]: Finished difference Result 4640 states and 6839 transitions. [2022-02-21 04:23:20,307 INFO L276 IsEmpty]: Start isEmpty. Operand 4640 states and 6839 transitions. [2022-02-21 04:23:20,311 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:20,311 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:20,311 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:20,311 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:20,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4638 states to 4638 states and 6837 transitions. [2022-02-21 04:23:20,875 INFO L704 BuchiCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2022-02-21 04:23:20,875 INFO L587 BuchiCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2022-02-21 04:23:20,875 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:20,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4638 states and 6837 transitions. [2022-02-21 04:23:20,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2022-02-21 04:23:20,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:20,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:20,884 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:20,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:20,885 INFO L791 eck$LassoCheckResult]: Stem: 66454#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 66455#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 66705#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65406#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65407#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 66737#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66680#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66681#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66724#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65716#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65717#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65829#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66080#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66010#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65718#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65379#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65380#L1036 assume !(0 == ~M_E~0); 65479#L1036-2 assume !(0 == ~T1_E~0); 66389#L1041-1 assume !(0 == ~T2_E~0); 66390#L1046-1 assume !(0 == ~T3_E~0); 65757#L1051-1 assume !(0 == ~T4_E~0); 65758#L1056-1 assume !(0 == ~T5_E~0); 66539#L1061-1 assume !(0 == ~T6_E~0); 65652#L1066-1 assume !(0 == ~T7_E~0); 65653#L1071-1 assume !(0 == ~T8_E~0); 66521#L1076-1 assume !(0 == ~T9_E~0); 65547#L1081-1 assume !(0 == ~T10_E~0); 65548#L1086-1 assume !(0 == ~E_M~0); 65962#L1091-1 assume !(0 == ~E_1~0); 66742#L1096-1 assume !(0 == ~E_2~0); 66743#L1101-1 assume !(0 == ~E_3~0); 66024#L1106-1 assume !(0 == ~E_4~0); 66025#L1111-1 assume !(0 == ~E_5~0); 66186#L1116-1 assume !(0 == ~E_6~0); 66187#L1121-1 assume !(0 == ~E_7~0); 66017#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 66018#L1131-1 assume !(0 == ~E_9~0); 66282#L1136-1 assume !(0 == ~E_10~0); 66397#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66568#L514 assume 1 == ~m_pc~0; 66529#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 66037#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65951#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65952#L1285 assume !(0 != activate_threads_~tmp~1#1); 66784#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65671#L533 assume !(1 == ~t1_pc~0); 65672#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66204#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66071#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66072#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 66421#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66422#L552 assume 1 == ~t2_pc~0; 65905#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65906#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66507#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66508#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 66049#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66050#L571 assume 1 == ~t3_pc~0; 66238#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66239#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65585#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65586#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 66192#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65461#L590 assume !(1 == ~t4_pc~0); 65462#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66252#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66503#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66504#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66456#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66188#L609 assume 1 == ~t5_pc~0; 66189#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66782#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65498#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65499#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 66182#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66183#L628 assume !(1 == ~t6_pc~0); 66113#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66112#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66764#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66765#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 66499#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66500#L647 assume 1 == ~t7_pc~0; 66026#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66027#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66317#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66029#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 66030#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66825#L666 assume !(1 == ~t8_pc~0); 65806#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65807#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66048#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66212#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 65957#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65958#L685 assume 1 == ~t9_pc~0; 66795#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66662#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66650#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65986#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 65987#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66358#L704 assume !(1 == ~t10_pc~0); 65978#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 65977#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66537#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65517#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 65518#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65768#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 66486#L1154-2 assume !(1 == ~T1_E~0); 66814#L1159-1 assume !(1 == ~T2_E~0); 66842#L1164-1 assume !(1 == ~T3_E~0); 66209#L1169-1 assume !(1 == ~T4_E~0); 66210#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67196#L1179-1 assume !(1 == ~T6_E~0); 65723#L1184-1 assume !(1 == ~T7_E~0); 65724#L1189-1 assume !(1 == ~T8_E~0); 65804#L1194-1 assume !(1 == ~T9_E~0); 65947#L1199-1 assume !(1 == ~T10_E~0); 67143#L1204-1 assume !(1 == ~E_M~0); 67139#L1209-1 assume !(1 == ~E_1~0); 67138#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 66927#L1219-1 assume !(1 == ~E_3~0); 66926#L1224-1 assume !(1 == ~E_4~0); 66914#L1229-1 assume !(1 == ~E_5~0); 66912#L1234-1 assume !(1 == ~E_6~0); 66910#L1239-1 assume !(1 == ~E_7~0); 66908#L1244-1 assume !(1 == ~E_8~0); 66906#L1249-1 assume !(1 == ~E_9~0); 66904#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 66890#L1259-1 assume { :end_inline_reset_delta_events } true; 66883#L1565-2 [2022-02-21 04:23:20,885 INFO L793 eck$LassoCheckResult]: Loop: 66883#L1565-2 assume !false; 66877#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66872#L1011 assume !false; 66871#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 66870#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 66859#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 66858#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 66856#L866 assume !(0 != eval_~tmp~0#1); 66855#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66854#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66852#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 66853#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68718#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68716#L1046-3 assume !(0 == ~T3_E~0); 68714#L1051-3 assume !(0 == ~T4_E~0); 68712#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68710#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68708#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68706#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 68704#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 68703#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 68701#L1086-3 assume !(0 == ~E_M~0); 68699#L1091-3 assume !(0 == ~E_1~0); 68697#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68695#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68693#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 68691#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 68689#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68687#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68685#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68683#L1131-3 assume !(0 == ~E_9~0); 68682#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68681#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68680#L514-36 assume !(1 == ~m_pc~0); 68679#L514-38 is_master_triggered_~__retres1~0#1 := 0; 68667#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68665#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68663#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68660#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68658#L533-36 assume !(1 == ~t1_pc~0); 68640#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 68635#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68631#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68628#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68626#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68625#L552-36 assume 1 == ~t2_pc~0; 68623#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68620#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68618#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68616#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68614#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68612#L571-36 assume 1 == ~t3_pc~0; 68609#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68607#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68605#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68603#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68601#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68599#L590-36 assume 1 == ~t4_pc~0; 68597#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68594#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68592#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68590#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68588#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68586#L609-36 assume !(1 == ~t5_pc~0); 68577#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 68574#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68572#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68570#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 68568#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68554#L628-36 assume 1 == ~t6_pc~0; 68551#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68547#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67518#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67515#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 67513#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67511#L647-36 assume !(1 == ~t7_pc~0); 67509#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 67137#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67134#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67132#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 67130#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67128#L666-36 assume 1 == ~t8_pc~0; 67125#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 67123#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67120#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67118#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 67116#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67114#L685-36 assume !(1 == ~t9_pc~0); 67111#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 67109#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67106#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67104#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 67102#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67100#L704-36 assume 1 == ~t10_pc~0; 67097#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 67095#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67092#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 67090#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 67088#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67086#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 66847#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67083#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67080#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67076#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67074#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67072#L1179-3 assume !(1 == ~T6_E~0); 67070#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 67068#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 67065#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67063#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 67061#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 67057#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67055#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67053#L1219-3 assume !(1 == ~E_3~0); 67050#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 67048#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67046#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 67044#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 67042#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67040#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 67039#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 67038#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 67026#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 67021#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 67019#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 67017#L1584 assume !(0 == start_simulation_~tmp~3#1); 66837#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 66924#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 66913#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 66911#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 66909#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66907#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66905#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 66891#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 66883#L1565-2 [2022-02-21 04:23:20,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:20,886 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2022-02-21 04:23:20,886 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:20,886 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789762024] [2022-02-21 04:23:20,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:20,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:20,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:20,929 INFO L290 TraceCheckUtils]: 0: Hoare triple {79278#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,930 INFO L290 TraceCheckUtils]: 1: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,930 INFO L290 TraceCheckUtils]: 2: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,930 INFO L290 TraceCheckUtils]: 3: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,931 INFO L290 TraceCheckUtils]: 4: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,931 INFO L290 TraceCheckUtils]: 5: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,931 INFO L290 TraceCheckUtils]: 6: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,931 INFO L290 TraceCheckUtils]: 7: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,932 INFO L290 TraceCheckUtils]: 8: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,932 INFO L290 TraceCheckUtils]: 9: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,932 INFO L290 TraceCheckUtils]: 10: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,933 INFO L290 TraceCheckUtils]: 11: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,933 INFO L290 TraceCheckUtils]: 12: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,933 INFO L290 TraceCheckUtils]: 13: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,933 INFO L290 TraceCheckUtils]: 14: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,934 INFO L290 TraceCheckUtils]: 15: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {79280#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:20,934 INFO L290 TraceCheckUtils]: 16: Hoare triple {79280#(= ~E_8~0 ~M_E~0)} assume !(0 == ~M_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,934 INFO L290 TraceCheckUtils]: 17: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T1_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,934 INFO L290 TraceCheckUtils]: 18: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T2_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,935 INFO L290 TraceCheckUtils]: 19: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T3_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,935 INFO L290 TraceCheckUtils]: 20: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T4_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,935 INFO L290 TraceCheckUtils]: 21: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T5_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,936 INFO L290 TraceCheckUtils]: 22: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T6_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,936 INFO L290 TraceCheckUtils]: 23: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T7_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,936 INFO L290 TraceCheckUtils]: 24: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T8_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,936 INFO L290 TraceCheckUtils]: 25: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T9_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,937 INFO L290 TraceCheckUtils]: 26: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~T10_E~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,937 INFO L290 TraceCheckUtils]: 27: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_M~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,937 INFO L290 TraceCheckUtils]: 28: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_1~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,937 INFO L290 TraceCheckUtils]: 29: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_2~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,938 INFO L290 TraceCheckUtils]: 30: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_3~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,938 INFO L290 TraceCheckUtils]: 31: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_4~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,938 INFO L290 TraceCheckUtils]: 32: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_5~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,939 INFO L290 TraceCheckUtils]: 33: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_6~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,939 INFO L290 TraceCheckUtils]: 34: Hoare triple {79281#(not (= ~E_8~0 0))} assume !(0 == ~E_7~0); {79281#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:20,939 INFO L290 TraceCheckUtils]: 35: Hoare triple {79281#(not (= ~E_8~0 0))} assume 0 == ~E_8~0;~E_8~0 := 1; {79279#false} is VALID [2022-02-21 04:23:20,939 INFO L290 TraceCheckUtils]: 36: Hoare triple {79279#false} assume !(0 == ~E_9~0); {79279#false} is VALID [2022-02-21 04:23:20,939 INFO L290 TraceCheckUtils]: 37: Hoare triple {79279#false} assume !(0 == ~E_10~0); {79279#false} is VALID [2022-02-21 04:23:20,939 INFO L290 TraceCheckUtils]: 38: Hoare triple {79279#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 39: Hoare triple {79279#false} assume 1 == ~m_pc~0; {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 40: Hoare triple {79279#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 41: Hoare triple {79279#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 42: Hoare triple {79279#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 43: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp~1#1); {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 44: Hoare triple {79279#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 45: Hoare triple {79279#false} assume !(1 == ~t1_pc~0); {79279#false} is VALID [2022-02-21 04:23:20,940 INFO L290 TraceCheckUtils]: 46: Hoare triple {79279#false} is_transmit1_triggered_~__retres1~1#1 := 0; {79279#false} is VALID [2022-02-21 04:23:20,941 INFO L290 TraceCheckUtils]: 47: Hoare triple {79279#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {79279#false} is VALID [2022-02-21 04:23:20,941 INFO L290 TraceCheckUtils]: 48: Hoare triple {79279#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {79279#false} is VALID [2022-02-21 04:23:20,941 INFO L290 TraceCheckUtils]: 49: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___0~0#1); {79279#false} is VALID [2022-02-21 04:23:20,941 INFO L290 TraceCheckUtils]: 50: Hoare triple {79279#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {79279#false} is VALID [2022-02-21 04:23:20,941 INFO L290 TraceCheckUtils]: 51: Hoare triple {79279#false} assume 1 == ~t2_pc~0; {79279#false} is VALID [2022-02-21 04:23:20,941 INFO L290 TraceCheckUtils]: 52: Hoare triple {79279#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {79279#false} is VALID [2022-02-21 04:23:20,941 INFO L290 TraceCheckUtils]: 53: Hoare triple {79279#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 54: Hoare triple {79279#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 55: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___1~0#1); {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 56: Hoare triple {79279#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 57: Hoare triple {79279#false} assume 1 == ~t3_pc~0; {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 58: Hoare triple {79279#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 59: Hoare triple {79279#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 60: Hoare triple {79279#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {79279#false} is VALID [2022-02-21 04:23:20,942 INFO L290 TraceCheckUtils]: 61: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___2~0#1); {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 62: Hoare triple {79279#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 63: Hoare triple {79279#false} assume !(1 == ~t4_pc~0); {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 64: Hoare triple {79279#false} is_transmit4_triggered_~__retres1~4#1 := 0; {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 65: Hoare triple {79279#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 66: Hoare triple {79279#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 67: Hoare triple {79279#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 68: Hoare triple {79279#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {79279#false} is VALID [2022-02-21 04:23:20,943 INFO L290 TraceCheckUtils]: 69: Hoare triple {79279#false} assume 1 == ~t5_pc~0; {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 70: Hoare triple {79279#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 71: Hoare triple {79279#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 72: Hoare triple {79279#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 73: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___4~0#1); {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 74: Hoare triple {79279#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 75: Hoare triple {79279#false} assume !(1 == ~t6_pc~0); {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 76: Hoare triple {79279#false} is_transmit6_triggered_~__retres1~6#1 := 0; {79279#false} is VALID [2022-02-21 04:23:20,944 INFO L290 TraceCheckUtils]: 77: Hoare triple {79279#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 78: Hoare triple {79279#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 79: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___5~0#1); {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 80: Hoare triple {79279#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 81: Hoare triple {79279#false} assume 1 == ~t7_pc~0; {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 82: Hoare triple {79279#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 83: Hoare triple {79279#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 84: Hoare triple {79279#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {79279#false} is VALID [2022-02-21 04:23:20,945 INFO L290 TraceCheckUtils]: 85: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___6~0#1); {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 86: Hoare triple {79279#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 87: Hoare triple {79279#false} assume !(1 == ~t8_pc~0); {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 88: Hoare triple {79279#false} is_transmit8_triggered_~__retres1~8#1 := 0; {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 89: Hoare triple {79279#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 90: Hoare triple {79279#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 91: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___7~0#1); {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 92: Hoare triple {79279#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {79279#false} is VALID [2022-02-21 04:23:20,946 INFO L290 TraceCheckUtils]: 93: Hoare triple {79279#false} assume 1 == ~t9_pc~0; {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 94: Hoare triple {79279#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 95: Hoare triple {79279#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 96: Hoare triple {79279#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 97: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___8~0#1); {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 98: Hoare triple {79279#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 99: Hoare triple {79279#false} assume !(1 == ~t10_pc~0); {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 100: Hoare triple {79279#false} is_transmit10_triggered_~__retres1~10#1 := 0; {79279#false} is VALID [2022-02-21 04:23:20,947 INFO L290 TraceCheckUtils]: 101: Hoare triple {79279#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 102: Hoare triple {79279#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 103: Hoare triple {79279#false} assume !(0 != activate_threads_~tmp___9~0#1); {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 104: Hoare triple {79279#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 105: Hoare triple {79279#false} assume 1 == ~M_E~0;~M_E~0 := 2; {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 106: Hoare triple {79279#false} assume !(1 == ~T1_E~0); {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 107: Hoare triple {79279#false} assume !(1 == ~T2_E~0); {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 108: Hoare triple {79279#false} assume !(1 == ~T3_E~0); {79279#false} is VALID [2022-02-21 04:23:20,948 INFO L290 TraceCheckUtils]: 109: Hoare triple {79279#false} assume !(1 == ~T4_E~0); {79279#false} is VALID [2022-02-21 04:23:20,949 INFO L290 TraceCheckUtils]: 110: Hoare triple {79279#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {79279#false} is VALID [2022-02-21 04:23:20,949 INFO L290 TraceCheckUtils]: 111: Hoare triple {79279#false} assume !(1 == ~T6_E~0); {79279#false} is VALID [2022-02-21 04:23:20,949 INFO L290 TraceCheckUtils]: 112: Hoare triple {79279#false} assume !(1 == ~T7_E~0); {79279#false} is VALID [2022-02-21 04:23:20,949 INFO L290 TraceCheckUtils]: 113: Hoare triple {79279#false} assume !(1 == ~T8_E~0); {79279#false} is VALID [2022-02-21 04:23:20,949 INFO L290 TraceCheckUtils]: 114: Hoare triple {79279#false} assume !(1 == ~T9_E~0); {79279#false} is VALID [2022-02-21 04:23:20,949 INFO L290 TraceCheckUtils]: 115: Hoare triple {79279#false} assume !(1 == ~T10_E~0); {79279#false} is VALID [2022-02-21 04:23:20,949 INFO L290 TraceCheckUtils]: 116: Hoare triple {79279#false} assume !(1 == ~E_M~0); {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 117: Hoare triple {79279#false} assume !(1 == ~E_1~0); {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 118: Hoare triple {79279#false} assume 1 == ~E_2~0;~E_2~0 := 2; {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 119: Hoare triple {79279#false} assume !(1 == ~E_3~0); {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 120: Hoare triple {79279#false} assume !(1 == ~E_4~0); {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 121: Hoare triple {79279#false} assume !(1 == ~E_5~0); {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 122: Hoare triple {79279#false} assume !(1 == ~E_6~0); {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 123: Hoare triple {79279#false} assume !(1 == ~E_7~0); {79279#false} is VALID [2022-02-21 04:23:20,950 INFO L290 TraceCheckUtils]: 124: Hoare triple {79279#false} assume !(1 == ~E_8~0); {79279#false} is VALID [2022-02-21 04:23:20,951 INFO L290 TraceCheckUtils]: 125: Hoare triple {79279#false} assume !(1 == ~E_9~0); {79279#false} is VALID [2022-02-21 04:23:20,951 INFO L290 TraceCheckUtils]: 126: Hoare triple {79279#false} assume 1 == ~E_10~0;~E_10~0 := 2; {79279#false} is VALID [2022-02-21 04:23:20,951 INFO L290 TraceCheckUtils]: 127: Hoare triple {79279#false} assume { :end_inline_reset_delta_events } true; {79279#false} is VALID [2022-02-21 04:23:20,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:20,951 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:20,951 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789762024] [2022-02-21 04:23:20,952 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789762024] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:20,953 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:20,953 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:20,954 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928048710] [2022-02-21 04:23:20,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:20,954 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:20,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:20,955 INFO L85 PathProgramCache]: Analyzing trace with hash 1636269146, now seen corresponding path program 1 times [2022-02-21 04:23:20,955 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:20,955 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977170675] [2022-02-21 04:23:20,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:20,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:20,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:20,981 INFO L290 TraceCheckUtils]: 0: Hoare triple {79282#true} assume !false; {79282#true} is VALID [2022-02-21 04:23:20,981 INFO L290 TraceCheckUtils]: 1: Hoare triple {79282#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 2: Hoare triple {79282#true} assume !false; {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 3: Hoare triple {79282#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 4: Hoare triple {79282#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 5: Hoare triple {79282#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 6: Hoare triple {79282#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 7: Hoare triple {79282#true} assume !(0 != eval_~tmp~0#1); {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 8: Hoare triple {79282#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {79282#true} is VALID [2022-02-21 04:23:20,982 INFO L290 TraceCheckUtils]: 9: Hoare triple {79282#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {79282#true} is VALID [2022-02-21 04:23:20,983 INFO L290 TraceCheckUtils]: 10: Hoare triple {79282#true} assume 0 == ~M_E~0;~M_E~0 := 1; {79282#true} is VALID [2022-02-21 04:23:20,983 INFO L290 TraceCheckUtils]: 11: Hoare triple {79282#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {79282#true} is VALID [2022-02-21 04:23:20,983 INFO L290 TraceCheckUtils]: 12: Hoare triple {79282#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {79282#true} is VALID [2022-02-21 04:23:20,984 INFO L290 TraceCheckUtils]: 13: Hoare triple {79282#true} assume !(0 == ~T3_E~0); {79282#true} is VALID [2022-02-21 04:23:20,984 INFO L290 TraceCheckUtils]: 14: Hoare triple {79282#true} assume !(0 == ~T4_E~0); {79282#true} is VALID [2022-02-21 04:23:20,984 INFO L290 TraceCheckUtils]: 15: Hoare triple {79282#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {79282#true} is VALID [2022-02-21 04:23:20,984 INFO L290 TraceCheckUtils]: 16: Hoare triple {79282#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,985 INFO L290 TraceCheckUtils]: 17: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,985 INFO L290 TraceCheckUtils]: 18: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,985 INFO L290 TraceCheckUtils]: 19: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,985 INFO L290 TraceCheckUtils]: 20: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,986 INFO L290 TraceCheckUtils]: 21: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,986 INFO L290 TraceCheckUtils]: 22: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,986 INFO L290 TraceCheckUtils]: 23: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,987 INFO L290 TraceCheckUtils]: 24: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,987 INFO L290 TraceCheckUtils]: 25: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,987 INFO L290 TraceCheckUtils]: 26: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,987 INFO L290 TraceCheckUtils]: 27: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,988 INFO L290 TraceCheckUtils]: 28: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,988 INFO L290 TraceCheckUtils]: 29: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,988 INFO L290 TraceCheckUtils]: 30: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,988 INFO L290 TraceCheckUtils]: 31: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,989 INFO L290 TraceCheckUtils]: 32: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,989 INFO L290 TraceCheckUtils]: 33: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,989 INFO L290 TraceCheckUtils]: 34: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,990 INFO L290 TraceCheckUtils]: 35: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,990 INFO L290 TraceCheckUtils]: 36: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,990 INFO L290 TraceCheckUtils]: 37: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,990 INFO L290 TraceCheckUtils]: 38: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,991 INFO L290 TraceCheckUtils]: 39: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,991 INFO L290 TraceCheckUtils]: 40: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,991 INFO L290 TraceCheckUtils]: 41: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,991 INFO L290 TraceCheckUtils]: 42: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,992 INFO L290 TraceCheckUtils]: 43: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,992 INFO L290 TraceCheckUtils]: 44: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,992 INFO L290 TraceCheckUtils]: 45: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,992 INFO L290 TraceCheckUtils]: 46: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,993 INFO L290 TraceCheckUtils]: 47: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,993 INFO L290 TraceCheckUtils]: 48: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,993 INFO L290 TraceCheckUtils]: 49: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,994 INFO L290 TraceCheckUtils]: 50: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,994 INFO L290 TraceCheckUtils]: 51: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,994 INFO L290 TraceCheckUtils]: 52: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,994 INFO L290 TraceCheckUtils]: 53: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,995 INFO L290 TraceCheckUtils]: 54: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,995 INFO L290 TraceCheckUtils]: 55: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,995 INFO L290 TraceCheckUtils]: 56: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,995 INFO L290 TraceCheckUtils]: 57: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,996 INFO L290 TraceCheckUtils]: 58: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,996 INFO L290 TraceCheckUtils]: 59: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,996 INFO L290 TraceCheckUtils]: 60: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,997 INFO L290 TraceCheckUtils]: 61: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,997 INFO L290 TraceCheckUtils]: 62: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,997 INFO L290 TraceCheckUtils]: 63: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,997 INFO L290 TraceCheckUtils]: 64: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,998 INFO L290 TraceCheckUtils]: 65: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,998 INFO L290 TraceCheckUtils]: 66: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,998 INFO L290 TraceCheckUtils]: 67: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,998 INFO L290 TraceCheckUtils]: 68: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,999 INFO L290 TraceCheckUtils]: 69: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,999 INFO L290 TraceCheckUtils]: 70: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,999 INFO L290 TraceCheckUtils]: 71: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:20,999 INFO L290 TraceCheckUtils]: 72: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,000 INFO L290 TraceCheckUtils]: 73: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,000 INFO L290 TraceCheckUtils]: 74: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,000 INFO L290 TraceCheckUtils]: 75: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,001 INFO L290 TraceCheckUtils]: 76: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,001 INFO L290 TraceCheckUtils]: 77: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,001 INFO L290 TraceCheckUtils]: 78: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,001 INFO L290 TraceCheckUtils]: 79: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,002 INFO L290 TraceCheckUtils]: 80: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,002 INFO L290 TraceCheckUtils]: 81: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,002 INFO L290 TraceCheckUtils]: 82: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,002 INFO L290 TraceCheckUtils]: 83: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,003 INFO L290 TraceCheckUtils]: 84: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,003 INFO L290 TraceCheckUtils]: 85: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,003 INFO L290 TraceCheckUtils]: 86: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,004 INFO L290 TraceCheckUtils]: 87: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,004 INFO L290 TraceCheckUtils]: 88: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,004 INFO L290 TraceCheckUtils]: 89: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,004 INFO L290 TraceCheckUtils]: 90: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,005 INFO L290 TraceCheckUtils]: 91: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,005 INFO L290 TraceCheckUtils]: 92: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,005 INFO L290 TraceCheckUtils]: 93: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,005 INFO L290 TraceCheckUtils]: 94: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,006 INFO L290 TraceCheckUtils]: 95: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,006 INFO L290 TraceCheckUtils]: 96: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,006 INFO L290 TraceCheckUtils]: 97: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,006 INFO L290 TraceCheckUtils]: 98: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,007 INFO L290 TraceCheckUtils]: 99: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,007 INFO L290 TraceCheckUtils]: 100: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,007 INFO L290 TraceCheckUtils]: 101: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,008 INFO L290 TraceCheckUtils]: 102: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,008 INFO L290 TraceCheckUtils]: 103: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,008 INFO L290 TraceCheckUtils]: 104: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {79284#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,008 INFO L290 TraceCheckUtils]: 105: Hoare triple {79284#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {79283#false} is VALID [2022-02-21 04:23:21,008 INFO L290 TraceCheckUtils]: 106: Hoare triple {79283#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 107: Hoare triple {79283#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 108: Hoare triple {79283#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 109: Hoare triple {79283#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 110: Hoare triple {79283#false} assume 1 == ~E_M~0;~E_M~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 111: Hoare triple {79283#false} assume 1 == ~E_1~0;~E_1~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 112: Hoare triple {79283#false} assume 1 == ~E_2~0;~E_2~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 113: Hoare triple {79283#false} assume !(1 == ~E_3~0); {79283#false} is VALID [2022-02-21 04:23:21,009 INFO L290 TraceCheckUtils]: 114: Hoare triple {79283#false} assume 1 == ~E_4~0;~E_4~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,010 INFO L290 TraceCheckUtils]: 115: Hoare triple {79283#false} assume 1 == ~E_5~0;~E_5~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,010 INFO L290 TraceCheckUtils]: 116: Hoare triple {79283#false} assume 1 == ~E_6~0;~E_6~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,010 INFO L290 TraceCheckUtils]: 117: Hoare triple {79283#false} assume 1 == ~E_7~0;~E_7~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,010 INFO L290 TraceCheckUtils]: 118: Hoare triple {79283#false} assume 1 == ~E_8~0;~E_8~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,010 INFO L290 TraceCheckUtils]: 119: Hoare triple {79283#false} assume 1 == ~E_9~0;~E_9~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,010 INFO L290 TraceCheckUtils]: 120: Hoare triple {79283#false} assume 1 == ~E_10~0;~E_10~0 := 2; {79283#false} is VALID [2022-02-21 04:23:21,010 INFO L290 TraceCheckUtils]: 121: Hoare triple {79283#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 122: Hoare triple {79283#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 123: Hoare triple {79283#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 124: Hoare triple {79283#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 125: Hoare triple {79283#false} assume !(0 == start_simulation_~tmp~3#1); {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 126: Hoare triple {79283#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 127: Hoare triple {79283#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 128: Hoare triple {79283#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {79283#false} is VALID [2022-02-21 04:23:21,011 INFO L290 TraceCheckUtils]: 129: Hoare triple {79283#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {79283#false} is VALID [2022-02-21 04:23:21,012 INFO L290 TraceCheckUtils]: 130: Hoare triple {79283#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {79283#false} is VALID [2022-02-21 04:23:21,012 INFO L290 TraceCheckUtils]: 131: Hoare triple {79283#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {79283#false} is VALID [2022-02-21 04:23:21,012 INFO L290 TraceCheckUtils]: 132: Hoare triple {79283#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {79283#false} is VALID [2022-02-21 04:23:21,012 INFO L290 TraceCheckUtils]: 133: Hoare triple {79283#false} assume !(0 != start_simulation_~tmp___0~1#1); {79283#false} is VALID [2022-02-21 04:23:21,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,013 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,013 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977170675] [2022-02-21 04:23:21,013 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977170675] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,013 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,013 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,013 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365853728] [2022-02-21 04:23:21,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,014 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:21,014 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:21,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:21,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:21,014 INFO L87 Difference]: Start difference. First operand 4638 states and 6837 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:25,139 INFO L93 Difference]: Finished difference Result 8692 states and 12784 transitions. [2022-02-21 04:23:25,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:25,139 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,216 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:25,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8692 states and 12784 transitions. [2022-02-21 04:23:26,909 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2022-02-21 04:23:28,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8692 states to 8692 states and 12784 transitions. [2022-02-21 04:23:28,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8692 [2022-02-21 04:23:28,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8692 [2022-02-21 04:23:28,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8692 states and 12784 transitions. [2022-02-21 04:23:28,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:28,698 INFO L681 BuchiCegarLoop]: Abstraction has 8692 states and 12784 transitions. [2022-02-21 04:23:28,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8692 states and 12784 transitions. [2022-02-21 04:23:28,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8692 to 8688. [2022-02-21 04:23:28,839 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:28,851 INFO L82 GeneralOperation]: Start isEquivalent. First operand 8692 states and 12784 transitions. Second operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,862 INFO L74 IsIncluded]: Start isIncluded. First operand 8692 states and 12784 transitions. Second operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,874 INFO L87 Difference]: Start difference. First operand 8692 states and 12784 transitions. Second operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:30,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:30,692 INFO L93 Difference]: Finished difference Result 8692 states and 12784 transitions. [2022-02-21 04:23:30,692 INFO L276 IsEmpty]: Start isEmpty. Operand 8692 states and 12784 transitions. [2022-02-21 04:23:30,704 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:30,704 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:30,713 INFO L74 IsIncluded]: Start isIncluded. First operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8692 states and 12784 transitions. [2022-02-21 04:23:30,725 INFO L87 Difference]: Start difference. First operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8692 states and 12784 transitions. [2022-02-21 04:23:32,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,632 INFO L93 Difference]: Finished difference Result 8692 states and 12784 transitions. [2022-02-21 04:23:32,632 INFO L276 IsEmpty]: Start isEmpty. Operand 8692 states and 12784 transitions. [2022-02-21 04:23:32,640 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:32,640 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:32,640 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:32,640 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:32,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8688 states to 8688 states and 12780 transitions. [2022-02-21 04:23:34,523 INFO L704 BuchiCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2022-02-21 04:23:34,523 INFO L587 BuchiCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2022-02-21 04:23:34,523 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:34,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8688 states and 12780 transitions. [2022-02-21 04:23:34,544 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2022-02-21 04:23:34,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:34,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:34,545 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,545 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,545 INFO L791 eck$LassoCheckResult]: Stem: 89052#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 89053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 89267#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88030#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88031#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 89293#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89248#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89249#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89281#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88340#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88341#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88444#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88694#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 88624#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 88342#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 88001#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88002#L1036 assume !(0 == ~M_E~0); 88100#L1036-2 assume !(0 == ~T1_E~0); 88991#L1041-1 assume !(0 == ~T2_E~0); 88992#L1046-1 assume !(0 == ~T3_E~0); 88376#L1051-1 assume !(0 == ~T4_E~0); 88377#L1056-1 assume !(0 == ~T5_E~0); 89132#L1061-1 assume !(0 == ~T6_E~0); 88273#L1066-1 assume !(0 == ~T7_E~0); 88274#L1071-1 assume !(0 == ~T8_E~0); 89115#L1076-1 assume !(0 == ~T9_E~0); 88168#L1081-1 assume !(0 == ~T10_E~0); 88169#L1086-1 assume !(0 == ~E_M~0); 88576#L1091-1 assume !(0 == ~E_1~0); 89299#L1096-1 assume !(0 == ~E_2~0); 89300#L1101-1 assume !(0 == ~E_3~0); 88638#L1106-1 assume !(0 == ~E_4~0); 88639#L1111-1 assume !(0 == ~E_5~0); 88797#L1116-1 assume !(0 == ~E_6~0); 88798#L1121-1 assume !(0 == ~E_7~0); 88631#L1126-1 assume !(0 == ~E_8~0); 88632#L1131-1 assume !(0 == ~E_9~0); 88891#L1136-1 assume !(0 == ~E_10~0); 88999#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89159#L514 assume 1 == ~m_pc~0; 89122#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 88652#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88570#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88571#L1285 assume !(0 != activate_threads_~tmp~1#1); 89337#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88296#L533 assume !(1 == ~t1_pc~0); 88297#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88816#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88684#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88685#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 89021#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89022#L552 assume 1 == ~t2_pc~0; 88521#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88522#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89103#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89104#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 88666#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88667#L571 assume 1 == ~t3_pc~0; 88851#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88852#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88208#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88209#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 88804#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88084#L590 assume !(1 == ~t4_pc~0); 88085#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88862#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89100#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89101#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89054#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88799#L609 assume 1 == ~t5_pc~0; 88800#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89334#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88119#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88120#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 88794#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88795#L628 assume !(1 == ~t6_pc~0); 88727#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 88726#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89317#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89318#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 89095#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89096#L647 assume 1 == ~t7_pc~0; 88640#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88641#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88928#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88647#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 88648#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89377#L666 assume !(1 == ~t8_pc~0); 88423#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 88424#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88662#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88826#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 88574#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88575#L685 assume 1 == ~t9_pc~0; 89347#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89232#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89224#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88600#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 88601#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88962#L704 assume !(1 == ~t10_pc~0); 88592#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 88591#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89130#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88140#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 88141#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88387#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 89081#L1154-2 assume !(1 == ~T1_E~0); 88359#L1159-1 assume !(1 == ~T2_E~0); 88360#L1164-1 assume !(1 == ~T3_E~0); 88822#L1169-1 assume !(1 == ~T4_E~0); 88823#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89740#L1179-1 assume !(1 == ~T6_E~0); 89738#L1184-1 assume !(1 == ~T7_E~0); 89734#L1189-1 assume !(1 == ~T8_E~0); 89732#L1194-1 assume !(1 == ~T9_E~0); 89711#L1199-1 assume !(1 == ~T10_E~0); 89709#L1204-1 assume !(1 == ~E_M~0); 89691#L1209-1 assume !(1 == ~E_1~0); 89689#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 89687#L1219-1 assume !(1 == ~E_3~0); 89685#L1224-1 assume !(1 == ~E_4~0); 89665#L1229-1 assume !(1 == ~E_5~0); 89657#L1234-1 assume !(1 == ~E_6~0); 89644#L1239-1 assume !(1 == ~E_7~0); 89458#L1244-1 assume !(1 == ~E_8~0); 89444#L1249-1 assume !(1 == ~E_9~0); 89442#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 89431#L1259-1 assume { :end_inline_reset_delta_events } true; 89424#L1565-2 [2022-02-21 04:23:34,546 INFO L793 eck$LassoCheckResult]: Loop: 89424#L1565-2 assume !false; 89418#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89413#L1011 assume !false; 89412#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 89411#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 89400#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 89399#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 89397#L866 assume !(0 != eval_~tmp~0#1); 89396#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89395#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89394#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 89319#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 89320#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89186#L1046-3 assume !(0 == ~T3_E~0); 89187#L1051-3 assume !(0 == ~T4_E~0); 89127#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88373#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88374#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88375#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 89321#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 88123#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88124#L1086-3 assume !(0 == ~E_M~0); 88182#L1091-3 assume !(0 == ~E_1~0); 88183#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 89283#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 89284#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 89316#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89274#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88974#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88975#L1126-3 assume !(0 == ~E_8~0); 89202#L1131-3 assume !(0 == ~E_9~0); 89203#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 89384#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88976#L514-36 assume 1 == ~m_pc~0; 88977#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 88550#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88551#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89020#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88432#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88433#L533-36 assume !(1 == ~t1_pc~0); 88713#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 88808#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89121#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89067#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88867#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88868#L552-36 assume 1 == ~t2_pc~0; 88425#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88427#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88245#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88246#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88399#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88400#L571-36 assume 1 == ~t3_pc~0; 88789#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88489#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88490#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88615#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89185#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88460#L590-36 assume !(1 == ~t4_pc~0); 88461#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 89083#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88649#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88650#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89163#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89164#L609-36 assume !(1 == ~t5_pc~0); 89037#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 88869#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88679#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88680#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88942#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88760#L628-36 assume 1 == ~t6_pc~0; 88618#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 88619#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94432#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94417#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94390#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94377#L647-36 assume !(1 == ~t7_pc~0); 94369#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 94362#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94351#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94344#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 94339#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94335#L666-36 assume 1 == ~t8_pc~0; 94327#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94320#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94316#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94308#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 94302#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94297#L685-36 assume !(1 == ~t9_pc~0); 91137#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 91135#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 91132#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 91130#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 91128#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91126#L704-36 assume 1 == ~t10_pc~0; 91123#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 91121#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91120#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91117#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 91115#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91113#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 89391#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91110#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 91108#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89386#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 91104#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 91102#L1179-3 assume !(1 == ~T6_E~0); 91100#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 89778#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 89776#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89774#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89737#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 89733#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89731#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 89708#L1219-3 assume !(1 == ~E_3~0); 89706#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89704#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89684#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89682#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89664#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89660#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89659#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89658#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 89647#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 89642#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 89641#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 89639#L1584 assume !(0 == start_simulation_~tmp~3#1); 89383#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 89632#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 89620#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 89617#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 89614#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89455#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89443#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 89432#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 89424#L1565-2 [2022-02-21 04:23:34,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,546 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2022-02-21 04:23:34,547 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,547 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530919519] [2022-02-21 04:23:34,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,567 INFO L290 TraceCheckUtils]: 0: Hoare triple {114054#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,568 INFO L290 TraceCheckUtils]: 1: Hoare triple {114056#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,568 INFO L290 TraceCheckUtils]: 2: Hoare triple {114056#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,568 INFO L290 TraceCheckUtils]: 3: Hoare triple {114056#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,569 INFO L290 TraceCheckUtils]: 4: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,569 INFO L290 TraceCheckUtils]: 5: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,569 INFO L290 TraceCheckUtils]: 6: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,570 INFO L290 TraceCheckUtils]: 7: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,570 INFO L290 TraceCheckUtils]: 8: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,570 INFO L290 TraceCheckUtils]: 9: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,570 INFO L290 TraceCheckUtils]: 10: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,571 INFO L290 TraceCheckUtils]: 11: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,571 INFO L290 TraceCheckUtils]: 12: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,571 INFO L290 TraceCheckUtils]: 13: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,572 INFO L290 TraceCheckUtils]: 14: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,572 INFO L290 TraceCheckUtils]: 15: Hoare triple {114056#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,572 INFO L290 TraceCheckUtils]: 16: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,572 INFO L290 TraceCheckUtils]: 17: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,573 INFO L290 TraceCheckUtils]: 18: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,573 INFO L290 TraceCheckUtils]: 19: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,573 INFO L290 TraceCheckUtils]: 20: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,574 INFO L290 TraceCheckUtils]: 21: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,574 INFO L290 TraceCheckUtils]: 22: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,574 INFO L290 TraceCheckUtils]: 23: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T7_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,574 INFO L290 TraceCheckUtils]: 24: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T8_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,575 INFO L290 TraceCheckUtils]: 25: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T9_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,575 INFO L290 TraceCheckUtils]: 26: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~T10_E~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,575 INFO L290 TraceCheckUtils]: 27: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,575 INFO L290 TraceCheckUtils]: 28: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,576 INFO L290 TraceCheckUtils]: 29: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,576 INFO L290 TraceCheckUtils]: 30: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,576 INFO L290 TraceCheckUtils]: 31: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,577 INFO L290 TraceCheckUtils]: 32: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,577 INFO L290 TraceCheckUtils]: 33: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,577 INFO L290 TraceCheckUtils]: 34: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_7~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,577 INFO L290 TraceCheckUtils]: 35: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_8~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,578 INFO L290 TraceCheckUtils]: 36: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_9~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,578 INFO L290 TraceCheckUtils]: 37: Hoare triple {114056#(= ~m_pc~0 0)} assume !(0 == ~E_10~0); {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,578 INFO L290 TraceCheckUtils]: 38: Hoare triple {114056#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {114056#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:34,579 INFO L290 TraceCheckUtils]: 39: Hoare triple {114056#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {114055#false} is VALID [2022-02-21 04:23:34,579 INFO L290 TraceCheckUtils]: 40: Hoare triple {114055#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {114055#false} is VALID [2022-02-21 04:23:34,579 INFO L290 TraceCheckUtils]: 41: Hoare triple {114055#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {114055#false} is VALID [2022-02-21 04:23:34,579 INFO L290 TraceCheckUtils]: 42: Hoare triple {114055#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {114055#false} is VALID [2022-02-21 04:23:34,579 INFO L290 TraceCheckUtils]: 43: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp~1#1); {114055#false} is VALID [2022-02-21 04:23:34,579 INFO L290 TraceCheckUtils]: 44: Hoare triple {114055#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {114055#false} is VALID [2022-02-21 04:23:34,579 INFO L290 TraceCheckUtils]: 45: Hoare triple {114055#false} assume !(1 == ~t1_pc~0); {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 46: Hoare triple {114055#false} is_transmit1_triggered_~__retres1~1#1 := 0; {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 47: Hoare triple {114055#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 48: Hoare triple {114055#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 49: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___0~0#1); {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 50: Hoare triple {114055#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 51: Hoare triple {114055#false} assume 1 == ~t2_pc~0; {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 52: Hoare triple {114055#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {114055#false} is VALID [2022-02-21 04:23:34,580 INFO L290 TraceCheckUtils]: 53: Hoare triple {114055#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 54: Hoare triple {114055#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 55: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___1~0#1); {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 56: Hoare triple {114055#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 57: Hoare triple {114055#false} assume 1 == ~t3_pc~0; {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 58: Hoare triple {114055#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 59: Hoare triple {114055#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 60: Hoare triple {114055#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {114055#false} is VALID [2022-02-21 04:23:34,581 INFO L290 TraceCheckUtils]: 61: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___2~0#1); {114055#false} is VALID [2022-02-21 04:23:34,582 INFO L290 TraceCheckUtils]: 62: Hoare triple {114055#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {114055#false} is VALID [2022-02-21 04:23:34,582 INFO L290 TraceCheckUtils]: 63: Hoare triple {114055#false} assume !(1 == ~t4_pc~0); {114055#false} is VALID [2022-02-21 04:23:34,582 INFO L290 TraceCheckUtils]: 64: Hoare triple {114055#false} is_transmit4_triggered_~__retres1~4#1 := 0; {114055#false} is VALID [2022-02-21 04:23:34,582 INFO L290 TraceCheckUtils]: 65: Hoare triple {114055#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {114055#false} is VALID [2022-02-21 04:23:34,582 INFO L290 TraceCheckUtils]: 66: Hoare triple {114055#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {114055#false} is VALID [2022-02-21 04:23:34,582 INFO L290 TraceCheckUtils]: 67: Hoare triple {114055#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {114055#false} is VALID [2022-02-21 04:23:34,582 INFO L290 TraceCheckUtils]: 68: Hoare triple {114055#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 69: Hoare triple {114055#false} assume 1 == ~t5_pc~0; {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 70: Hoare triple {114055#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 71: Hoare triple {114055#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 72: Hoare triple {114055#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 73: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___4~0#1); {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 74: Hoare triple {114055#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 75: Hoare triple {114055#false} assume !(1 == ~t6_pc~0); {114055#false} is VALID [2022-02-21 04:23:34,583 INFO L290 TraceCheckUtils]: 76: Hoare triple {114055#false} is_transmit6_triggered_~__retres1~6#1 := 0; {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 77: Hoare triple {114055#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 78: Hoare triple {114055#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 79: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___5~0#1); {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 80: Hoare triple {114055#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 81: Hoare triple {114055#false} assume 1 == ~t7_pc~0; {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 82: Hoare triple {114055#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 83: Hoare triple {114055#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {114055#false} is VALID [2022-02-21 04:23:34,584 INFO L290 TraceCheckUtils]: 84: Hoare triple {114055#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {114055#false} is VALID [2022-02-21 04:23:34,585 INFO L290 TraceCheckUtils]: 85: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___6~0#1); {114055#false} is VALID [2022-02-21 04:23:34,585 INFO L290 TraceCheckUtils]: 86: Hoare triple {114055#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {114055#false} is VALID [2022-02-21 04:23:34,585 INFO L290 TraceCheckUtils]: 87: Hoare triple {114055#false} assume !(1 == ~t8_pc~0); {114055#false} is VALID [2022-02-21 04:23:34,585 INFO L290 TraceCheckUtils]: 88: Hoare triple {114055#false} is_transmit8_triggered_~__retres1~8#1 := 0; {114055#false} is VALID [2022-02-21 04:23:34,585 INFO L290 TraceCheckUtils]: 89: Hoare triple {114055#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {114055#false} is VALID [2022-02-21 04:23:34,585 INFO L290 TraceCheckUtils]: 90: Hoare triple {114055#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {114055#false} is VALID [2022-02-21 04:23:34,585 INFO L290 TraceCheckUtils]: 91: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___7~0#1); {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 92: Hoare triple {114055#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 93: Hoare triple {114055#false} assume 1 == ~t9_pc~0; {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 94: Hoare triple {114055#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 95: Hoare triple {114055#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 96: Hoare triple {114055#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 97: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___8~0#1); {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 98: Hoare triple {114055#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {114055#false} is VALID [2022-02-21 04:23:34,586 INFO L290 TraceCheckUtils]: 99: Hoare triple {114055#false} assume !(1 == ~t10_pc~0); {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 100: Hoare triple {114055#false} is_transmit10_triggered_~__retres1~10#1 := 0; {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 101: Hoare triple {114055#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 102: Hoare triple {114055#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 103: Hoare triple {114055#false} assume !(0 != activate_threads_~tmp___9~0#1); {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 104: Hoare triple {114055#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 105: Hoare triple {114055#false} assume 1 == ~M_E~0;~M_E~0 := 2; {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 106: Hoare triple {114055#false} assume !(1 == ~T1_E~0); {114055#false} is VALID [2022-02-21 04:23:34,587 INFO L290 TraceCheckUtils]: 107: Hoare triple {114055#false} assume !(1 == ~T2_E~0); {114055#false} is VALID [2022-02-21 04:23:34,588 INFO L290 TraceCheckUtils]: 108: Hoare triple {114055#false} assume !(1 == ~T3_E~0); {114055#false} is VALID [2022-02-21 04:23:34,588 INFO L290 TraceCheckUtils]: 109: Hoare triple {114055#false} assume !(1 == ~T4_E~0); {114055#false} is VALID [2022-02-21 04:23:34,588 INFO L290 TraceCheckUtils]: 110: Hoare triple {114055#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {114055#false} is VALID [2022-02-21 04:23:34,588 INFO L290 TraceCheckUtils]: 111: Hoare triple {114055#false} assume !(1 == ~T6_E~0); {114055#false} is VALID [2022-02-21 04:23:34,588 INFO L290 TraceCheckUtils]: 112: Hoare triple {114055#false} assume !(1 == ~T7_E~0); {114055#false} is VALID [2022-02-21 04:23:34,588 INFO L290 TraceCheckUtils]: 113: Hoare triple {114055#false} assume !(1 == ~T8_E~0); {114055#false} is VALID [2022-02-21 04:23:34,588 INFO L290 TraceCheckUtils]: 114: Hoare triple {114055#false} assume !(1 == ~T9_E~0); {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 115: Hoare triple {114055#false} assume !(1 == ~T10_E~0); {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 116: Hoare triple {114055#false} assume !(1 == ~E_M~0); {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 117: Hoare triple {114055#false} assume !(1 == ~E_1~0); {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 118: Hoare triple {114055#false} assume 1 == ~E_2~0;~E_2~0 := 2; {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 119: Hoare triple {114055#false} assume !(1 == ~E_3~0); {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 120: Hoare triple {114055#false} assume !(1 == ~E_4~0); {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 121: Hoare triple {114055#false} assume !(1 == ~E_5~0); {114055#false} is VALID [2022-02-21 04:23:34,589 INFO L290 TraceCheckUtils]: 122: Hoare triple {114055#false} assume !(1 == ~E_6~0); {114055#false} is VALID [2022-02-21 04:23:34,590 INFO L290 TraceCheckUtils]: 123: Hoare triple {114055#false} assume !(1 == ~E_7~0); {114055#false} is VALID [2022-02-21 04:23:34,590 INFO L290 TraceCheckUtils]: 124: Hoare triple {114055#false} assume !(1 == ~E_8~0); {114055#false} is VALID [2022-02-21 04:23:34,590 INFO L290 TraceCheckUtils]: 125: Hoare triple {114055#false} assume !(1 == ~E_9~0); {114055#false} is VALID [2022-02-21 04:23:34,590 INFO L290 TraceCheckUtils]: 126: Hoare triple {114055#false} assume 1 == ~E_10~0;~E_10~0 := 2; {114055#false} is VALID [2022-02-21 04:23:34,590 INFO L290 TraceCheckUtils]: 127: Hoare triple {114055#false} assume { :end_inline_reset_delta_events } true; {114055#false} is VALID [2022-02-21 04:23:34,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,591 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,591 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1530919519] [2022-02-21 04:23:34,591 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1530919519] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,591 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,591 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:34,591 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365589764] [2022-02-21 04:23:34,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,592 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:34,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,592 INFO L85 PathProgramCache]: Analyzing trace with hash 942388572, now seen corresponding path program 1 times [2022-02-21 04:23:34,592 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,592 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151488647] [2022-02-21 04:23:34,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,614 INFO L290 TraceCheckUtils]: 0: Hoare triple {114057#true} assume !false; {114057#true} is VALID [2022-02-21 04:23:34,615 INFO L290 TraceCheckUtils]: 1: Hoare triple {114057#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {114057#true} is VALID [2022-02-21 04:23:34,615 INFO L290 TraceCheckUtils]: 2: Hoare triple {114057#true} assume !false; {114057#true} is VALID [2022-02-21 04:23:34,615 INFO L290 TraceCheckUtils]: 3: Hoare triple {114057#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {114057#true} is VALID [2022-02-21 04:23:34,615 INFO L290 TraceCheckUtils]: 4: Hoare triple {114057#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {114057#true} is VALID [2022-02-21 04:23:34,615 INFO L290 TraceCheckUtils]: 5: Hoare triple {114057#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {114057#true} is VALID [2022-02-21 04:23:34,615 INFO L290 TraceCheckUtils]: 6: Hoare triple {114057#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {114057#true} is VALID [2022-02-21 04:23:34,615 INFO L290 TraceCheckUtils]: 7: Hoare triple {114057#true} assume !(0 != eval_~tmp~0#1); {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 8: Hoare triple {114057#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 9: Hoare triple {114057#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 10: Hoare triple {114057#true} assume 0 == ~M_E~0;~M_E~0 := 1; {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 11: Hoare triple {114057#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 12: Hoare triple {114057#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 13: Hoare triple {114057#true} assume !(0 == ~T3_E~0); {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 14: Hoare triple {114057#true} assume !(0 == ~T4_E~0); {114057#true} is VALID [2022-02-21 04:23:34,616 INFO L290 TraceCheckUtils]: 15: Hoare triple {114057#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {114057#true} is VALID [2022-02-21 04:23:34,617 INFO L290 TraceCheckUtils]: 16: Hoare triple {114057#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,617 INFO L290 TraceCheckUtils]: 17: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,617 INFO L290 TraceCheckUtils]: 18: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,618 INFO L290 TraceCheckUtils]: 19: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,625 INFO L290 TraceCheckUtils]: 20: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,626 INFO L290 TraceCheckUtils]: 21: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,627 INFO L290 TraceCheckUtils]: 22: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,627 INFO L290 TraceCheckUtils]: 23: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,627 INFO L290 TraceCheckUtils]: 24: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,628 INFO L290 TraceCheckUtils]: 25: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,628 INFO L290 TraceCheckUtils]: 26: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,628 INFO L290 TraceCheckUtils]: 27: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,629 INFO L290 TraceCheckUtils]: 28: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,629 INFO L290 TraceCheckUtils]: 29: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,629 INFO L290 TraceCheckUtils]: 30: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,630 INFO L290 TraceCheckUtils]: 31: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,630 INFO L290 TraceCheckUtils]: 32: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,630 INFO L290 TraceCheckUtils]: 33: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,630 INFO L290 TraceCheckUtils]: 34: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,631 INFO L290 TraceCheckUtils]: 35: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,631 INFO L290 TraceCheckUtils]: 36: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,631 INFO L290 TraceCheckUtils]: 37: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,632 INFO L290 TraceCheckUtils]: 38: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,632 INFO L290 TraceCheckUtils]: 39: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,632 INFO L290 TraceCheckUtils]: 40: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,633 INFO L290 TraceCheckUtils]: 41: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,633 INFO L290 TraceCheckUtils]: 42: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,633 INFO L290 TraceCheckUtils]: 43: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,634 INFO L290 TraceCheckUtils]: 44: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,634 INFO L290 TraceCheckUtils]: 45: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,634 INFO L290 TraceCheckUtils]: 46: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,635 INFO L290 TraceCheckUtils]: 47: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,635 INFO L290 TraceCheckUtils]: 48: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,635 INFO L290 TraceCheckUtils]: 49: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,636 INFO L290 TraceCheckUtils]: 50: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,636 INFO L290 TraceCheckUtils]: 51: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,636 INFO L290 TraceCheckUtils]: 52: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 53: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 54: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,637 INFO L290 TraceCheckUtils]: 55: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 56: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 57: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,638 INFO L290 TraceCheckUtils]: 58: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 59: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 60: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,639 INFO L290 TraceCheckUtils]: 61: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 62: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 63: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,640 INFO L290 TraceCheckUtils]: 64: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 65: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 66: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,641 INFO L290 TraceCheckUtils]: 67: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 68: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 69: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,642 INFO L290 TraceCheckUtils]: 70: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 71: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 72: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,643 INFO L290 TraceCheckUtils]: 73: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 74: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 75: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,644 INFO L290 TraceCheckUtils]: 76: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 77: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 78: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,645 INFO L290 TraceCheckUtils]: 79: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 80: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 81: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 82: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,646 INFO L290 TraceCheckUtils]: 83: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 84: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 85: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,647 INFO L290 TraceCheckUtils]: 86: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 87: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 88: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,648 INFO L290 TraceCheckUtils]: 89: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 90: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 91: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,649 INFO L290 TraceCheckUtils]: 92: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 93: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 94: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,650 INFO L290 TraceCheckUtils]: 95: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 96: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 97: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,651 INFO L290 TraceCheckUtils]: 98: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,652 INFO L290 TraceCheckUtils]: 99: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,652 INFO L290 TraceCheckUtils]: 100: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,652 INFO L290 TraceCheckUtils]: 101: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,653 INFO L290 TraceCheckUtils]: 102: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,653 INFO L290 TraceCheckUtils]: 103: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,653 INFO L290 TraceCheckUtils]: 104: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {114059#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,654 INFO L290 TraceCheckUtils]: 105: Hoare triple {114059#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {114058#false} is VALID [2022-02-21 04:23:34,654 INFO L290 TraceCheckUtils]: 106: Hoare triple {114058#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,654 INFO L290 TraceCheckUtils]: 107: Hoare triple {114058#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,654 INFO L290 TraceCheckUtils]: 108: Hoare triple {114058#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,654 INFO L290 TraceCheckUtils]: 109: Hoare triple {114058#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,655 INFO L290 TraceCheckUtils]: 110: Hoare triple {114058#false} assume 1 == ~E_M~0;~E_M~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,655 INFO L290 TraceCheckUtils]: 111: Hoare triple {114058#false} assume 1 == ~E_1~0;~E_1~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,655 INFO L290 TraceCheckUtils]: 112: Hoare triple {114058#false} assume 1 == ~E_2~0;~E_2~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,655 INFO L290 TraceCheckUtils]: 113: Hoare triple {114058#false} assume !(1 == ~E_3~0); {114058#false} is VALID [2022-02-21 04:23:34,655 INFO L290 TraceCheckUtils]: 114: Hoare triple {114058#false} assume 1 == ~E_4~0;~E_4~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,655 INFO L290 TraceCheckUtils]: 115: Hoare triple {114058#false} assume 1 == ~E_5~0;~E_5~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,656 INFO L290 TraceCheckUtils]: 116: Hoare triple {114058#false} assume 1 == ~E_6~0;~E_6~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,656 INFO L290 TraceCheckUtils]: 117: Hoare triple {114058#false} assume 1 == ~E_7~0;~E_7~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,656 INFO L290 TraceCheckUtils]: 118: Hoare triple {114058#false} assume 1 == ~E_8~0;~E_8~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,656 INFO L290 TraceCheckUtils]: 119: Hoare triple {114058#false} assume 1 == ~E_9~0;~E_9~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,656 INFO L290 TraceCheckUtils]: 120: Hoare triple {114058#false} assume 1 == ~E_10~0;~E_10~0 := 2; {114058#false} is VALID [2022-02-21 04:23:34,656 INFO L290 TraceCheckUtils]: 121: Hoare triple {114058#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {114058#false} is VALID [2022-02-21 04:23:34,656 INFO L290 TraceCheckUtils]: 122: Hoare triple {114058#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {114058#false} is VALID [2022-02-21 04:23:34,657 INFO L290 TraceCheckUtils]: 123: Hoare triple {114058#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {114058#false} is VALID [2022-02-21 04:23:34,657 INFO L290 TraceCheckUtils]: 124: Hoare triple {114058#false} start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {114058#false} is VALID [2022-02-21 04:23:34,657 INFO L290 TraceCheckUtils]: 125: Hoare triple {114058#false} assume !(0 == start_simulation_~tmp~3#1); {114058#false} is VALID [2022-02-21 04:23:34,657 INFO L290 TraceCheckUtils]: 126: Hoare triple {114058#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {114058#false} is VALID [2022-02-21 04:23:34,657 INFO L290 TraceCheckUtils]: 127: Hoare triple {114058#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {114058#false} is VALID [2022-02-21 04:23:34,657 INFO L290 TraceCheckUtils]: 128: Hoare triple {114058#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {114058#false} is VALID [2022-02-21 04:23:34,658 INFO L290 TraceCheckUtils]: 129: Hoare triple {114058#false} stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; {114058#false} is VALID [2022-02-21 04:23:34,658 INFO L290 TraceCheckUtils]: 130: Hoare triple {114058#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {114058#false} is VALID [2022-02-21 04:23:34,658 INFO L290 TraceCheckUtils]: 131: Hoare triple {114058#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {114058#false} is VALID [2022-02-21 04:23:34,658 INFO L290 TraceCheckUtils]: 132: Hoare triple {114058#false} start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {114058#false} is VALID [2022-02-21 04:23:34,658 INFO L290 TraceCheckUtils]: 133: Hoare triple {114058#false} assume !(0 != start_simulation_~tmp___0~1#1); {114058#false} is VALID [2022-02-21 04:23:34,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,659 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,659 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151488647] [2022-02-21 04:23:34,659 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151488647] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,660 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,660 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:34,660 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652420259] [2022-02-21 04:23:34,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,660 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:34,660 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:34,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:34,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:34,661 INFO L87 Difference]: Start difference. First operand 8688 states and 12780 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:43,253 INFO L93 Difference]: Finished difference Result 17011 states and 24827 transitions. [2022-02-21 04:23:43,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:43,254 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:43,323 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:43,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17011 states and 24827 transitions. [2022-02-21 04:23:51,298 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16793 [2022-02-21 04:23:57,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17011 states to 17011 states and 24827 transitions. [2022-02-21 04:23:57,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17011 [2022-02-21 04:23:57,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17011 [2022-02-21 04:23:57,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17011 states and 24827 transitions. [2022-02-21 04:23:57,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:57,685 INFO L681 BuchiCegarLoop]: Abstraction has 17011 states and 24827 transitions. [2022-02-21 04:23:57,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17011 states and 24827 transitions. [2022-02-21 04:23:57,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17011 to 16403. [2022-02-21 04:23:57,824 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:57,843 INFO L82 GeneralOperation]: Start isEquivalent. First operand 17011 states and 24827 transitions. Second operand has 16403 states, 16403 states have (on average 1.4613790160336524) internal successors, (23971), 16402 states have internal predecessors, (23971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:57,862 INFO L74 IsIncluded]: Start isIncluded. First operand 17011 states and 24827 transitions. Second operand has 16403 states, 16403 states have (on average 1.4613790160336524) internal successors, (23971), 16402 states have internal predecessors, (23971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:57,880 INFO L87 Difference]: Start difference. First operand 17011 states and 24827 transitions. Second operand has 16403 states, 16403 states have (on average 1.4613790160336524) internal successors, (23971), 16402 states have internal predecessors, (23971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)