./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:22:54,785 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:22:54,786 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:22:54,808 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:22:54,810 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:22:54,813 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:22:54,816 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:22:54,821 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:22:54,822 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:22:54,827 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:22:54,828 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:22:54,829 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:22:54,829 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:22:54,831 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:22:54,832 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:22:54,834 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:22:54,835 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:22:54,835 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:22:54,839 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:22:54,841 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:22:54,843 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:22:54,844 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:22:54,845 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:22:54,846 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:22:54,849 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:22:54,850 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:22:54,850 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:22:54,851 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:22:54,851 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:22:54,852 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:22:54,852 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:22:54,853 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:22:54,854 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:22:54,855 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:22:54,856 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:22:54,856 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:22:54,856 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:22:54,856 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:22:54,857 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:22:54,857 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:22:54,857 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:22:54,858 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:22:54,884 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:22:54,885 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:22:54,885 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:22:54,885 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:22:54,886 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:22:54,886 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:22:54,887 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:22:54,887 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:22:54,887 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:22:54,887 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:22:54,888 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:22:54,888 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:22:54,888 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:22:54,888 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:22:54,888 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:22:54,888 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:22:54,889 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:22:54,890 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:22:54,890 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:22:54,890 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:22:54,890 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:22:54,890 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:22:54,890 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:22:54,890 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:22:54,891 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:22:54,892 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2022-02-21 04:22:55,113 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:22:55,146 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:22:55,148 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:22:55,149 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:22:55,154 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:22:55,155 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2022-02-21 04:22:55,223 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e1f1a496/73b68f39e67b46f99a765b716e4bb9c9/FLAG819fb5cfe [2022-02-21 04:22:55,541 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:22:55,541 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2022-02-21 04:22:55,559 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e1f1a496/73b68f39e67b46f99a765b716e4bb9c9/FLAG819fb5cfe [2022-02-21 04:22:55,931 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e1f1a496/73b68f39e67b46f99a765b716e4bb9c9 [2022-02-21 04:22:55,933 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:22:55,934 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:22:55,935 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:55,935 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:22:55,938 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:22:55,939 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,940 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44d5ea01 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:55, skipping insertion in model container [2022-02-21 04:22:55,940 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:55" (1/1) ... [2022-02-21 04:22:55,945 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:22:55,975 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:22:56,132 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2022-02-21 04:22:56,214 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:56,229 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:22:56,236 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2022-02-21 04:22:56,290 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:56,312 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:22:56,313 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56 WrapperNode [2022-02-21 04:22:56,313 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:56,314 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:56,314 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:22:56,314 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:22:56,331 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,362 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,456 INFO L137 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 209, statements flattened = 3186 [2022-02-21 04:22:56,459 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:56,460 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:22:56,460 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:22:56,460 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:22:56,466 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,467 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,474 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,474 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,504 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,528 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,533 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,541 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:22:56,542 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:22:56,542 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:22:56,543 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:22:56,543 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (1/1) ... [2022-02-21 04:22:56,556 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:22:56,565 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:22:56,606 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:22:56,641 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:22:56,662 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:22:56,662 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:22:56,662 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:22:56,662 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:22:56,732 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:22:56,733 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:22:58,114 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:22:58,126 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:22:58,127 INFO L299 CfgBuilder]: Removed 13 assume(true) statements. [2022-02-21 04:22:58,129 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:58 BoogieIcfgContainer [2022-02-21 04:22:58,129 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:22:58,130 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:22:58,130 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:22:58,132 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:22:58,133 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:58,133 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:22:55" (1/3) ... [2022-02-21 04:22:58,134 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71510fa0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:58, skipping insertion in model container [2022-02-21 04:22:58,134 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:58,134 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:56" (2/3) ... [2022-02-21 04:22:58,134 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@71510fa0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:22:58, skipping insertion in model container [2022-02-21 04:22:58,134 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:22:58,135 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:22:58" (3/3) ... [2022-02-21 04:22:58,135 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2022-02-21 04:22:58,162 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:22:58,163 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:22:58,163 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:22:58,163 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:22:58,163 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:22:58,163 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:22:58,163 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:22:58,163 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:22:58,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2022-02-21 04:22:58,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:58,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:58,403 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:58,403 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:58,403 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:22:58,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:58,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2022-02-21 04:22:58,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:58,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:58,507 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:58,507 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:58,520 INFO L791 eck$LassoCheckResult]: Stem: 630#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1246#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23#L1516true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 562#L712true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 570#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 347#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 543#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 706#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1236#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 460#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 827#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 379#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 663#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 846#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 619#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 550#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 834#L1024true assume !(0 == ~M_E~0); 936#L1024-2true assume !(0 == ~T1_E~0); 186#L1029-1true assume !(0 == ~T2_E~0); 246#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1313#L1039-1true assume !(0 == ~T4_E~0); 1007#L1044-1true assume !(0 == ~T5_E~0); 394#L1049-1true assume !(0 == ~T6_E~0); 1325#L1054-1true assume !(0 == ~T7_E~0); 569#L1059-1true assume !(0 == ~T8_E~0); 213#L1064-1true assume !(0 == ~T9_E~0); 793#L1069-1true assume !(0 == ~T10_E~0); 1229#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 875#L1079-1true assume !(0 == ~E_1~0); 837#L1084-1true assume !(0 == ~E_2~0); 1034#L1089-1true assume !(0 == ~E_3~0); 907#L1094-1true assume !(0 == ~E_4~0); 453#L1099-1true assume !(0 == ~E_5~0); 1049#L1104-1true assume !(0 == ~E_6~0); 682#L1109-1true assume !(0 == ~E_7~0); 318#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1275#L1119-1true assume !(0 == ~E_9~0); 353#L1124-1true assume !(0 == ~E_10~0); 40#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 698#L502true assume 1 == ~m_pc~0; 567#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 742#L514true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 616#L1273true assume !(0 != activate_threads_~tmp~1#1); 1367#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1123#L521true assume !(1 == ~t1_pc~0); 1044#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 68#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136#L533true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 633#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 59#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 853#L540true assume 1 == ~t2_pc~0; 1104#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 857#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 873#L552true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1230#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 945#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200#L559true assume 1 == ~t3_pc~0; 1015#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 366#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472#L571true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 644#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1253#L578true assume !(1 == ~t4_pc~0); 800#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 833#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56#L590true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1090#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 599#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162#L597true assume 1 == ~t5_pc~0; 1331#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 427#L609true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1351#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 551#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 613#L616true assume !(1 == ~t6_pc~0); 1175#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1064#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1256#L628true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 493#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 446#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 677#L635true assume 1 == ~t7_pc~0; 602#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 258#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 807#L647true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 903#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 546#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 787#L654true assume !(1 == ~t8_pc~0); 411#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 946#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1210#L666true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 789#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 993#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185#L673true assume 1 == ~t9_pc~0; 1009#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1203#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1112#L685true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 745#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 693#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 865#L692true assume !(1 == ~t10_pc~0); 680#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 999#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 553#L704true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 456#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 768#L1353-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1310#L1142true assume !(1 == ~M_E~0); 139#L1142-2true assume !(1 == ~T1_E~0); 746#L1147-1true assume !(1 == ~T2_E~0); 1309#L1152-1true assume !(1 == ~T3_E~0); 371#L1157-1true assume !(1 == ~T4_E~0); 845#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 475#L1167-1true assume !(1 == ~T6_E~0); 929#L1172-1true assume !(1 == ~T7_E~0); 962#L1177-1true assume !(1 == ~T8_E~0); 584#L1182-1true assume !(1 == ~T9_E~0); 687#L1187-1true assume !(1 == ~T10_E~0); 735#L1192-1true assume !(1 == ~E_M~0); 288#L1197-1true assume !(1 == ~E_1~0); 750#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 535#L1207-1true assume !(1 == ~E_3~0); 521#L1212-1true assume !(1 == ~E_4~0); 71#L1217-1true assume !(1 == ~E_5~0); 1369#L1222-1true assume !(1 == ~E_6~0); 517#L1227-1true assume !(1 == ~E_7~0); 580#L1232-1true assume !(1 == ~E_8~0); 9#L1237-1true assume !(1 == ~E_9~0); 1056#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 568#L1247-1true assume { :end_inline_reset_delta_events } true; 90#L1553-2true [2022-02-21 04:22:58,524 INFO L793 eck$LassoCheckResult]: Loop: 90#L1553-2true assume !false; 732#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1336#L999true assume false; 808#L1014true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 234#L712-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1289#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 997#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 444#L1029-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 420#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 711#L1039-3true assume !(0 == ~T4_E~0); 765#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 182#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 643#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 69#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1335#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 401#L1069-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 689#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 975#L1079-3true assume !(0 == ~E_1~0); 576#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 486#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 641#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 434#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 709#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1062#L1109-3true assume 0 == ~E_7~0;~E_7~0 := 1; 696#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1190#L1119-3true assume !(0 == ~E_9~0); 1328#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1227#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1096#L502-36true assume 1 == ~m_pc~0; 712#L503-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1221#L514-12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 214#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 683#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 381#L521-36true assume 1 == ~t1_pc~0; 390#L522-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 511#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 541#L533-12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1196#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 799#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1107#L540-36true assume 1 == ~t2_pc~0; 1258#L541-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 259#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1248#L552-12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1337#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 471#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8#L559-36true assume !(1 == ~t3_pc~0); 237#L559-38true is_transmit3_triggered_~__retres1~3#1 := 0; 734#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153#L571-12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 586#L1297-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 871#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1240#L578-36true assume 1 == ~t4_pc~0; 560#L579-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1245#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 914#L590-12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1308#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 404#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 575#L597-36true assume !(1 == ~t5_pc~0); 1120#L597-38true is_transmit5_triggered_~__retres1~5#1 := 0; 1054#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510#L609-12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 536#L1313-36true assume !(0 != activate_threads_~tmp___4~0#1); 289#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1109#L616-36true assume 1 == ~t6_pc~0; 1334#L617-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 369#L628-12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 440#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 730#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1348#L635-36true assume 1 == ~t7_pc~0; 1003#L636-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 814#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 476#L647-12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1268#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 432#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1282#L654-36true assume !(1 == ~t8_pc~0); 1005#L654-38true is_transmit8_triggered_~__retres1~8#1 := 0; 1330#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1280#L666-12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1174#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1125#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 230#L673-36true assume !(1 == ~t9_pc~0); 717#L673-38true is_transmit9_triggered_~__retres1~9#1 := 0; 461#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 822#L685-12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1023#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1186#L692-36true assume !(1 == ~t10_pc~0); 112#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 439#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 887#L704-12true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 210#L1353-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 438#L1353-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1170#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1006#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1068#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 497#L1157-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 809#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1066#L1167-3true assume !(1 == ~T6_E~0); 985#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 430#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 364#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 844#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 373#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 265#L1197-3true assume 1 == ~E_1~0;~E_1~0 := 2; 418#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 503#L1207-3true assume !(1 == ~E_3~0); 1105#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 707#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 205#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 50#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 876#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 848#L1237-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1293#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1251#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 919#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 120#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1228#L840-1true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 561#L1572true assume !(0 == start_simulation_~tmp~3#1); 383#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1218#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1081#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1085#L840-2true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1285#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 819#L1535true start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1358#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 90#L1553-2true [2022-02-21 04:22:58,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:58,529 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2022-02-21 04:22:58,535 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:58,537 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800669434] [2022-02-21 04:22:58,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:58,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:58,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:58,734 INFO L290 TraceCheckUtils]: 0: Hoare triple {1371#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {1371#true} is VALID [2022-02-21 04:22:58,735 INFO L290 TraceCheckUtils]: 1: Hoare triple {1371#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {1373#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:58,735 INFO L290 TraceCheckUtils]: 2: Hoare triple {1373#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1373#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:58,737 INFO L290 TraceCheckUtils]: 3: Hoare triple {1373#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1373#(= ~m_i~0 1)} is VALID [2022-02-21 04:22:58,737 INFO L290 TraceCheckUtils]: 4: Hoare triple {1373#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,738 INFO L290 TraceCheckUtils]: 5: Hoare triple {1372#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1372#false} is VALID [2022-02-21 04:22:58,738 INFO L290 TraceCheckUtils]: 6: Hoare triple {1372#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,738 INFO L290 TraceCheckUtils]: 7: Hoare triple {1372#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,739 INFO L290 TraceCheckUtils]: 8: Hoare triple {1372#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,739 INFO L290 TraceCheckUtils]: 9: Hoare triple {1372#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,739 INFO L290 TraceCheckUtils]: 10: Hoare triple {1372#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,739 INFO L290 TraceCheckUtils]: 11: Hoare triple {1372#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,740 INFO L290 TraceCheckUtils]: 12: Hoare triple {1372#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,740 INFO L290 TraceCheckUtils]: 13: Hoare triple {1372#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1372#false} is VALID [2022-02-21 04:22:58,740 INFO L290 TraceCheckUtils]: 14: Hoare triple {1372#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,740 INFO L290 TraceCheckUtils]: 15: Hoare triple {1372#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1372#false} is VALID [2022-02-21 04:22:58,741 INFO L290 TraceCheckUtils]: 16: Hoare triple {1372#false} assume !(0 == ~M_E~0); {1372#false} is VALID [2022-02-21 04:22:58,741 INFO L290 TraceCheckUtils]: 17: Hoare triple {1372#false} assume !(0 == ~T1_E~0); {1372#false} is VALID [2022-02-21 04:22:58,741 INFO L290 TraceCheckUtils]: 18: Hoare triple {1372#false} assume !(0 == ~T2_E~0); {1372#false} is VALID [2022-02-21 04:22:58,741 INFO L290 TraceCheckUtils]: 19: Hoare triple {1372#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1372#false} is VALID [2022-02-21 04:22:58,741 INFO L290 TraceCheckUtils]: 20: Hoare triple {1372#false} assume !(0 == ~T4_E~0); {1372#false} is VALID [2022-02-21 04:22:58,741 INFO L290 TraceCheckUtils]: 21: Hoare triple {1372#false} assume !(0 == ~T5_E~0); {1372#false} is VALID [2022-02-21 04:22:58,742 INFO L290 TraceCheckUtils]: 22: Hoare triple {1372#false} assume !(0 == ~T6_E~0); {1372#false} is VALID [2022-02-21 04:22:58,742 INFO L290 TraceCheckUtils]: 23: Hoare triple {1372#false} assume !(0 == ~T7_E~0); {1372#false} is VALID [2022-02-21 04:22:58,742 INFO L290 TraceCheckUtils]: 24: Hoare triple {1372#false} assume !(0 == ~T8_E~0); {1372#false} is VALID [2022-02-21 04:22:58,742 INFO L290 TraceCheckUtils]: 25: Hoare triple {1372#false} assume !(0 == ~T9_E~0); {1372#false} is VALID [2022-02-21 04:22:58,742 INFO L290 TraceCheckUtils]: 26: Hoare triple {1372#false} assume !(0 == ~T10_E~0); {1372#false} is VALID [2022-02-21 04:22:58,743 INFO L290 TraceCheckUtils]: 27: Hoare triple {1372#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1372#false} is VALID [2022-02-21 04:22:58,743 INFO L290 TraceCheckUtils]: 28: Hoare triple {1372#false} assume !(0 == ~E_1~0); {1372#false} is VALID [2022-02-21 04:22:58,744 INFO L290 TraceCheckUtils]: 29: Hoare triple {1372#false} assume !(0 == ~E_2~0); {1372#false} is VALID [2022-02-21 04:22:58,744 INFO L290 TraceCheckUtils]: 30: Hoare triple {1372#false} assume !(0 == ~E_3~0); {1372#false} is VALID [2022-02-21 04:22:58,744 INFO L290 TraceCheckUtils]: 31: Hoare triple {1372#false} assume !(0 == ~E_4~0); {1372#false} is VALID [2022-02-21 04:22:58,744 INFO L290 TraceCheckUtils]: 32: Hoare triple {1372#false} assume !(0 == ~E_5~0); {1372#false} is VALID [2022-02-21 04:22:58,744 INFO L290 TraceCheckUtils]: 33: Hoare triple {1372#false} assume !(0 == ~E_6~0); {1372#false} is VALID [2022-02-21 04:22:58,745 INFO L290 TraceCheckUtils]: 34: Hoare triple {1372#false} assume !(0 == ~E_7~0); {1372#false} is VALID [2022-02-21 04:22:58,745 INFO L290 TraceCheckUtils]: 35: Hoare triple {1372#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1372#false} is VALID [2022-02-21 04:22:58,745 INFO L290 TraceCheckUtils]: 36: Hoare triple {1372#false} assume !(0 == ~E_9~0); {1372#false} is VALID [2022-02-21 04:22:58,745 INFO L290 TraceCheckUtils]: 37: Hoare triple {1372#false} assume !(0 == ~E_10~0); {1372#false} is VALID [2022-02-21 04:22:58,745 INFO L290 TraceCheckUtils]: 38: Hoare triple {1372#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1372#false} is VALID [2022-02-21 04:22:58,746 INFO L290 TraceCheckUtils]: 39: Hoare triple {1372#false} assume 1 == ~m_pc~0; {1372#false} is VALID [2022-02-21 04:22:58,746 INFO L290 TraceCheckUtils]: 40: Hoare triple {1372#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1372#false} is VALID [2022-02-21 04:22:58,746 INFO L290 TraceCheckUtils]: 41: Hoare triple {1372#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1372#false} is VALID [2022-02-21 04:22:58,746 INFO L290 TraceCheckUtils]: 42: Hoare triple {1372#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1372#false} is VALID [2022-02-21 04:22:58,747 INFO L290 TraceCheckUtils]: 43: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp~1#1); {1372#false} is VALID [2022-02-21 04:22:58,747 INFO L290 TraceCheckUtils]: 44: Hoare triple {1372#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1372#false} is VALID [2022-02-21 04:22:58,747 INFO L290 TraceCheckUtils]: 45: Hoare triple {1372#false} assume !(1 == ~t1_pc~0); {1372#false} is VALID [2022-02-21 04:22:58,748 INFO L290 TraceCheckUtils]: 46: Hoare triple {1372#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1372#false} is VALID [2022-02-21 04:22:58,748 INFO L290 TraceCheckUtils]: 47: Hoare triple {1372#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1372#false} is VALID [2022-02-21 04:22:58,748 INFO L290 TraceCheckUtils]: 48: Hoare triple {1372#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1372#false} is VALID [2022-02-21 04:22:58,748 INFO L290 TraceCheckUtils]: 49: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___0~0#1); {1372#false} is VALID [2022-02-21 04:22:58,751 INFO L290 TraceCheckUtils]: 50: Hoare triple {1372#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1372#false} is VALID [2022-02-21 04:22:58,751 INFO L290 TraceCheckUtils]: 51: Hoare triple {1372#false} assume 1 == ~t2_pc~0; {1372#false} is VALID [2022-02-21 04:22:58,751 INFO L290 TraceCheckUtils]: 52: Hoare triple {1372#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1372#false} is VALID [2022-02-21 04:22:58,751 INFO L290 TraceCheckUtils]: 53: Hoare triple {1372#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1372#false} is VALID [2022-02-21 04:22:58,752 INFO L290 TraceCheckUtils]: 54: Hoare triple {1372#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1372#false} is VALID [2022-02-21 04:22:58,752 INFO L290 TraceCheckUtils]: 55: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___1~0#1); {1372#false} is VALID [2022-02-21 04:22:58,753 INFO L290 TraceCheckUtils]: 56: Hoare triple {1372#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1372#false} is VALID [2022-02-21 04:22:58,753 INFO L290 TraceCheckUtils]: 57: Hoare triple {1372#false} assume 1 == ~t3_pc~0; {1372#false} is VALID [2022-02-21 04:22:58,754 INFO L290 TraceCheckUtils]: 58: Hoare triple {1372#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1372#false} is VALID [2022-02-21 04:22:58,754 INFO L290 TraceCheckUtils]: 59: Hoare triple {1372#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1372#false} is VALID [2022-02-21 04:22:58,755 INFO L290 TraceCheckUtils]: 60: Hoare triple {1372#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1372#false} is VALID [2022-02-21 04:22:58,755 INFO L290 TraceCheckUtils]: 61: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___2~0#1); {1372#false} is VALID [2022-02-21 04:22:58,756 INFO L290 TraceCheckUtils]: 62: Hoare triple {1372#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1372#false} is VALID [2022-02-21 04:22:58,756 INFO L290 TraceCheckUtils]: 63: Hoare triple {1372#false} assume !(1 == ~t4_pc~0); {1372#false} is VALID [2022-02-21 04:22:58,756 INFO L290 TraceCheckUtils]: 64: Hoare triple {1372#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1372#false} is VALID [2022-02-21 04:22:58,758 INFO L290 TraceCheckUtils]: 65: Hoare triple {1372#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1372#false} is VALID [2022-02-21 04:22:58,758 INFO L290 TraceCheckUtils]: 66: Hoare triple {1372#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1372#false} is VALID [2022-02-21 04:22:58,759 INFO L290 TraceCheckUtils]: 67: Hoare triple {1372#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1372#false} is VALID [2022-02-21 04:22:58,759 INFO L290 TraceCheckUtils]: 68: Hoare triple {1372#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1372#false} is VALID [2022-02-21 04:22:58,759 INFO L290 TraceCheckUtils]: 69: Hoare triple {1372#false} assume 1 == ~t5_pc~0; {1372#false} is VALID [2022-02-21 04:22:58,760 INFO L290 TraceCheckUtils]: 70: Hoare triple {1372#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1372#false} is VALID [2022-02-21 04:22:58,760 INFO L290 TraceCheckUtils]: 71: Hoare triple {1372#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1372#false} is VALID [2022-02-21 04:22:58,760 INFO L290 TraceCheckUtils]: 72: Hoare triple {1372#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1372#false} is VALID [2022-02-21 04:22:58,761 INFO L290 TraceCheckUtils]: 73: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___4~0#1); {1372#false} is VALID [2022-02-21 04:22:58,765 INFO L290 TraceCheckUtils]: 74: Hoare triple {1372#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1372#false} is VALID [2022-02-21 04:22:58,765 INFO L290 TraceCheckUtils]: 75: Hoare triple {1372#false} assume !(1 == ~t6_pc~0); {1372#false} is VALID [2022-02-21 04:22:58,765 INFO L290 TraceCheckUtils]: 76: Hoare triple {1372#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1372#false} is VALID [2022-02-21 04:22:58,766 INFO L290 TraceCheckUtils]: 77: Hoare triple {1372#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1372#false} is VALID [2022-02-21 04:22:58,766 INFO L290 TraceCheckUtils]: 78: Hoare triple {1372#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1372#false} is VALID [2022-02-21 04:22:58,766 INFO L290 TraceCheckUtils]: 79: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___5~0#1); {1372#false} is VALID [2022-02-21 04:22:58,766 INFO L290 TraceCheckUtils]: 80: Hoare triple {1372#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1372#false} is VALID [2022-02-21 04:22:58,766 INFO L290 TraceCheckUtils]: 81: Hoare triple {1372#false} assume 1 == ~t7_pc~0; {1372#false} is VALID [2022-02-21 04:22:58,766 INFO L290 TraceCheckUtils]: 82: Hoare triple {1372#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1372#false} is VALID [2022-02-21 04:22:58,767 INFO L290 TraceCheckUtils]: 83: Hoare triple {1372#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1372#false} is VALID [2022-02-21 04:22:58,767 INFO L290 TraceCheckUtils]: 84: Hoare triple {1372#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1372#false} is VALID [2022-02-21 04:22:58,767 INFO L290 TraceCheckUtils]: 85: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___6~0#1); {1372#false} is VALID [2022-02-21 04:22:58,767 INFO L290 TraceCheckUtils]: 86: Hoare triple {1372#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1372#false} is VALID [2022-02-21 04:22:58,767 INFO L290 TraceCheckUtils]: 87: Hoare triple {1372#false} assume !(1 == ~t8_pc~0); {1372#false} is VALID [2022-02-21 04:22:58,767 INFO L290 TraceCheckUtils]: 88: Hoare triple {1372#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1372#false} is VALID [2022-02-21 04:22:58,768 INFO L290 TraceCheckUtils]: 89: Hoare triple {1372#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1372#false} is VALID [2022-02-21 04:22:58,768 INFO L290 TraceCheckUtils]: 90: Hoare triple {1372#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1372#false} is VALID [2022-02-21 04:22:58,768 INFO L290 TraceCheckUtils]: 91: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___7~0#1); {1372#false} is VALID [2022-02-21 04:22:58,768 INFO L290 TraceCheckUtils]: 92: Hoare triple {1372#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1372#false} is VALID [2022-02-21 04:22:58,768 INFO L290 TraceCheckUtils]: 93: Hoare triple {1372#false} assume 1 == ~t9_pc~0; {1372#false} is VALID [2022-02-21 04:22:58,768 INFO L290 TraceCheckUtils]: 94: Hoare triple {1372#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1372#false} is VALID [2022-02-21 04:22:58,769 INFO L290 TraceCheckUtils]: 95: Hoare triple {1372#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1372#false} is VALID [2022-02-21 04:22:58,769 INFO L290 TraceCheckUtils]: 96: Hoare triple {1372#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1372#false} is VALID [2022-02-21 04:22:58,769 INFO L290 TraceCheckUtils]: 97: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___8~0#1); {1372#false} is VALID [2022-02-21 04:22:58,769 INFO L290 TraceCheckUtils]: 98: Hoare triple {1372#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1372#false} is VALID [2022-02-21 04:22:58,769 INFO L290 TraceCheckUtils]: 99: Hoare triple {1372#false} assume !(1 == ~t10_pc~0); {1372#false} is VALID [2022-02-21 04:22:58,769 INFO L290 TraceCheckUtils]: 100: Hoare triple {1372#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1372#false} is VALID [2022-02-21 04:22:58,770 INFO L290 TraceCheckUtils]: 101: Hoare triple {1372#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1372#false} is VALID [2022-02-21 04:22:58,770 INFO L290 TraceCheckUtils]: 102: Hoare triple {1372#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1372#false} is VALID [2022-02-21 04:22:58,770 INFO L290 TraceCheckUtils]: 103: Hoare triple {1372#false} assume !(0 != activate_threads_~tmp___9~0#1); {1372#false} is VALID [2022-02-21 04:22:58,770 INFO L290 TraceCheckUtils]: 104: Hoare triple {1372#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1372#false} is VALID [2022-02-21 04:22:58,770 INFO L290 TraceCheckUtils]: 105: Hoare triple {1372#false} assume !(1 == ~M_E~0); {1372#false} is VALID [2022-02-21 04:22:58,772 INFO L290 TraceCheckUtils]: 106: Hoare triple {1372#false} assume !(1 == ~T1_E~0); {1372#false} is VALID [2022-02-21 04:22:58,772 INFO L290 TraceCheckUtils]: 107: Hoare triple {1372#false} assume !(1 == ~T2_E~0); {1372#false} is VALID [2022-02-21 04:22:58,773 INFO L290 TraceCheckUtils]: 108: Hoare triple {1372#false} assume !(1 == ~T3_E~0); {1372#false} is VALID [2022-02-21 04:22:58,773 INFO L290 TraceCheckUtils]: 109: Hoare triple {1372#false} assume !(1 == ~T4_E~0); {1372#false} is VALID [2022-02-21 04:22:58,773 INFO L290 TraceCheckUtils]: 110: Hoare triple {1372#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,773 INFO L290 TraceCheckUtils]: 111: Hoare triple {1372#false} assume !(1 == ~T6_E~0); {1372#false} is VALID [2022-02-21 04:22:58,773 INFO L290 TraceCheckUtils]: 112: Hoare triple {1372#false} assume !(1 == ~T7_E~0); {1372#false} is VALID [2022-02-21 04:22:58,773 INFO L290 TraceCheckUtils]: 113: Hoare triple {1372#false} assume !(1 == ~T8_E~0); {1372#false} is VALID [2022-02-21 04:22:58,774 INFO L290 TraceCheckUtils]: 114: Hoare triple {1372#false} assume !(1 == ~T9_E~0); {1372#false} is VALID [2022-02-21 04:22:58,774 INFO L290 TraceCheckUtils]: 115: Hoare triple {1372#false} assume !(1 == ~T10_E~0); {1372#false} is VALID [2022-02-21 04:22:58,774 INFO L290 TraceCheckUtils]: 116: Hoare triple {1372#false} assume !(1 == ~E_M~0); {1372#false} is VALID [2022-02-21 04:22:58,775 INFO L290 TraceCheckUtils]: 117: Hoare triple {1372#false} assume !(1 == ~E_1~0); {1372#false} is VALID [2022-02-21 04:22:58,775 INFO L290 TraceCheckUtils]: 118: Hoare triple {1372#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,775 INFO L290 TraceCheckUtils]: 119: Hoare triple {1372#false} assume !(1 == ~E_3~0); {1372#false} is VALID [2022-02-21 04:22:58,776 INFO L290 TraceCheckUtils]: 120: Hoare triple {1372#false} assume !(1 == ~E_4~0); {1372#false} is VALID [2022-02-21 04:22:58,776 INFO L290 TraceCheckUtils]: 121: Hoare triple {1372#false} assume !(1 == ~E_5~0); {1372#false} is VALID [2022-02-21 04:22:58,783 INFO L290 TraceCheckUtils]: 122: Hoare triple {1372#false} assume !(1 == ~E_6~0); {1372#false} is VALID [2022-02-21 04:22:58,783 INFO L290 TraceCheckUtils]: 123: Hoare triple {1372#false} assume !(1 == ~E_7~0); {1372#false} is VALID [2022-02-21 04:22:58,786 INFO L290 TraceCheckUtils]: 124: Hoare triple {1372#false} assume !(1 == ~E_8~0); {1372#false} is VALID [2022-02-21 04:22:58,786 INFO L290 TraceCheckUtils]: 125: Hoare triple {1372#false} assume !(1 == ~E_9~0); {1372#false} is VALID [2022-02-21 04:22:58,786 INFO L290 TraceCheckUtils]: 126: Hoare triple {1372#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1372#false} is VALID [2022-02-21 04:22:58,786 INFO L290 TraceCheckUtils]: 127: Hoare triple {1372#false} assume { :end_inline_reset_delta_events } true; {1372#false} is VALID [2022-02-21 04:22:58,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:58,788 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:58,788 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800669434] [2022-02-21 04:22:58,788 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800669434] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:58,789 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:58,790 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:58,791 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815141498] [2022-02-21 04:22:58,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:58,795 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:58,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:58,797 INFO L85 PathProgramCache]: Analyzing trace with hash -724132039, now seen corresponding path program 1 times [2022-02-21 04:22:58,798 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:58,798 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546244317] [2022-02-21 04:22:58,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:58,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:58,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:58,846 INFO L290 TraceCheckUtils]: 0: Hoare triple {1374#true} assume !false; {1374#true} is VALID [2022-02-21 04:22:58,847 INFO L290 TraceCheckUtils]: 1: Hoare triple {1374#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1374#true} is VALID [2022-02-21 04:22:58,847 INFO L290 TraceCheckUtils]: 2: Hoare triple {1374#true} assume false; {1375#false} is VALID [2022-02-21 04:22:58,847 INFO L290 TraceCheckUtils]: 3: Hoare triple {1375#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1375#false} is VALID [2022-02-21 04:22:58,847 INFO L290 TraceCheckUtils]: 4: Hoare triple {1375#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1375#false} is VALID [2022-02-21 04:22:58,848 INFO L290 TraceCheckUtils]: 5: Hoare triple {1375#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,848 INFO L290 TraceCheckUtils]: 6: Hoare triple {1375#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,848 INFO L290 TraceCheckUtils]: 7: Hoare triple {1375#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,848 INFO L290 TraceCheckUtils]: 8: Hoare triple {1375#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,849 INFO L290 TraceCheckUtils]: 9: Hoare triple {1375#false} assume !(0 == ~T4_E~0); {1375#false} is VALID [2022-02-21 04:22:58,849 INFO L290 TraceCheckUtils]: 10: Hoare triple {1375#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,849 INFO L290 TraceCheckUtils]: 11: Hoare triple {1375#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,849 INFO L290 TraceCheckUtils]: 12: Hoare triple {1375#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,849 INFO L290 TraceCheckUtils]: 13: Hoare triple {1375#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,850 INFO L290 TraceCheckUtils]: 14: Hoare triple {1375#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,850 INFO L290 TraceCheckUtils]: 15: Hoare triple {1375#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,850 INFO L290 TraceCheckUtils]: 16: Hoare triple {1375#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,850 INFO L290 TraceCheckUtils]: 17: Hoare triple {1375#false} assume !(0 == ~E_1~0); {1375#false} is VALID [2022-02-21 04:22:58,850 INFO L290 TraceCheckUtils]: 18: Hoare triple {1375#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,850 INFO L290 TraceCheckUtils]: 19: Hoare triple {1375#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,850 INFO L290 TraceCheckUtils]: 20: Hoare triple {1375#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,851 INFO L290 TraceCheckUtils]: 21: Hoare triple {1375#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,851 INFO L290 TraceCheckUtils]: 22: Hoare triple {1375#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,851 INFO L290 TraceCheckUtils]: 23: Hoare triple {1375#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,851 INFO L290 TraceCheckUtils]: 24: Hoare triple {1375#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,851 INFO L290 TraceCheckUtils]: 25: Hoare triple {1375#false} assume !(0 == ~E_9~0); {1375#false} is VALID [2022-02-21 04:22:58,851 INFO L290 TraceCheckUtils]: 26: Hoare triple {1375#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1375#false} is VALID [2022-02-21 04:22:58,851 INFO L290 TraceCheckUtils]: 27: Hoare triple {1375#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1375#false} is VALID [2022-02-21 04:22:58,852 INFO L290 TraceCheckUtils]: 28: Hoare triple {1375#false} assume 1 == ~m_pc~0; {1375#false} is VALID [2022-02-21 04:22:58,852 INFO L290 TraceCheckUtils]: 29: Hoare triple {1375#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,852 INFO L290 TraceCheckUtils]: 30: Hoare triple {1375#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1375#false} is VALID [2022-02-21 04:22:58,852 INFO L290 TraceCheckUtils]: 31: Hoare triple {1375#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1375#false} is VALID [2022-02-21 04:22:58,852 INFO L290 TraceCheckUtils]: 32: Hoare triple {1375#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,852 INFO L290 TraceCheckUtils]: 33: Hoare triple {1375#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1375#false} is VALID [2022-02-21 04:22:58,853 INFO L290 TraceCheckUtils]: 34: Hoare triple {1375#false} assume 1 == ~t1_pc~0; {1375#false} is VALID [2022-02-21 04:22:58,853 INFO L290 TraceCheckUtils]: 35: Hoare triple {1375#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,853 INFO L290 TraceCheckUtils]: 36: Hoare triple {1375#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1375#false} is VALID [2022-02-21 04:22:58,853 INFO L290 TraceCheckUtils]: 37: Hoare triple {1375#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1375#false} is VALID [2022-02-21 04:22:58,853 INFO L290 TraceCheckUtils]: 38: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,853 INFO L290 TraceCheckUtils]: 39: Hoare triple {1375#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1375#false} is VALID [2022-02-21 04:22:58,853 INFO L290 TraceCheckUtils]: 40: Hoare triple {1375#false} assume 1 == ~t2_pc~0; {1375#false} is VALID [2022-02-21 04:22:58,854 INFO L290 TraceCheckUtils]: 41: Hoare triple {1375#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,854 INFO L290 TraceCheckUtils]: 42: Hoare triple {1375#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1375#false} is VALID [2022-02-21 04:22:58,854 INFO L290 TraceCheckUtils]: 43: Hoare triple {1375#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1375#false} is VALID [2022-02-21 04:22:58,854 INFO L290 TraceCheckUtils]: 44: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,854 INFO L290 TraceCheckUtils]: 45: Hoare triple {1375#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1375#false} is VALID [2022-02-21 04:22:58,854 INFO L290 TraceCheckUtils]: 46: Hoare triple {1375#false} assume !(1 == ~t3_pc~0); {1375#false} is VALID [2022-02-21 04:22:58,855 INFO L290 TraceCheckUtils]: 47: Hoare triple {1375#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1375#false} is VALID [2022-02-21 04:22:58,858 INFO L290 TraceCheckUtils]: 48: Hoare triple {1375#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1375#false} is VALID [2022-02-21 04:22:58,858 INFO L290 TraceCheckUtils]: 49: Hoare triple {1375#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1375#false} is VALID [2022-02-21 04:22:58,858 INFO L290 TraceCheckUtils]: 50: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,858 INFO L290 TraceCheckUtils]: 51: Hoare triple {1375#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1375#false} is VALID [2022-02-21 04:22:58,859 INFO L290 TraceCheckUtils]: 52: Hoare triple {1375#false} assume 1 == ~t4_pc~0; {1375#false} is VALID [2022-02-21 04:22:58,859 INFO L290 TraceCheckUtils]: 53: Hoare triple {1375#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,859 INFO L290 TraceCheckUtils]: 54: Hoare triple {1375#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1375#false} is VALID [2022-02-21 04:22:58,859 INFO L290 TraceCheckUtils]: 55: Hoare triple {1375#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1375#false} is VALID [2022-02-21 04:22:58,859 INFO L290 TraceCheckUtils]: 56: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,860 INFO L290 TraceCheckUtils]: 57: Hoare triple {1375#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1375#false} is VALID [2022-02-21 04:22:58,861 INFO L290 TraceCheckUtils]: 58: Hoare triple {1375#false} assume !(1 == ~t5_pc~0); {1375#false} is VALID [2022-02-21 04:22:58,861 INFO L290 TraceCheckUtils]: 59: Hoare triple {1375#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1375#false} is VALID [2022-02-21 04:22:58,861 INFO L290 TraceCheckUtils]: 60: Hoare triple {1375#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1375#false} is VALID [2022-02-21 04:22:58,861 INFO L290 TraceCheckUtils]: 61: Hoare triple {1375#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1375#false} is VALID [2022-02-21 04:22:58,861 INFO L290 TraceCheckUtils]: 62: Hoare triple {1375#false} assume !(0 != activate_threads_~tmp___4~0#1); {1375#false} is VALID [2022-02-21 04:22:58,861 INFO L290 TraceCheckUtils]: 63: Hoare triple {1375#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1375#false} is VALID [2022-02-21 04:22:58,862 INFO L290 TraceCheckUtils]: 64: Hoare triple {1375#false} assume 1 == ~t6_pc~0; {1375#false} is VALID [2022-02-21 04:22:58,862 INFO L290 TraceCheckUtils]: 65: Hoare triple {1375#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,862 INFO L290 TraceCheckUtils]: 66: Hoare triple {1375#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1375#false} is VALID [2022-02-21 04:22:58,862 INFO L290 TraceCheckUtils]: 67: Hoare triple {1375#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1375#false} is VALID [2022-02-21 04:22:58,863 INFO L290 TraceCheckUtils]: 68: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,863 INFO L290 TraceCheckUtils]: 69: Hoare triple {1375#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1375#false} is VALID [2022-02-21 04:22:58,863 INFO L290 TraceCheckUtils]: 70: Hoare triple {1375#false} assume 1 == ~t7_pc~0; {1375#false} is VALID [2022-02-21 04:22:58,863 INFO L290 TraceCheckUtils]: 71: Hoare triple {1375#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,863 INFO L290 TraceCheckUtils]: 72: Hoare triple {1375#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1375#false} is VALID [2022-02-21 04:22:58,863 INFO L290 TraceCheckUtils]: 73: Hoare triple {1375#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1375#false} is VALID [2022-02-21 04:22:58,863 INFO L290 TraceCheckUtils]: 74: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,864 INFO L290 TraceCheckUtils]: 75: Hoare triple {1375#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1375#false} is VALID [2022-02-21 04:22:58,867 INFO L290 TraceCheckUtils]: 76: Hoare triple {1375#false} assume !(1 == ~t8_pc~0); {1375#false} is VALID [2022-02-21 04:22:58,867 INFO L290 TraceCheckUtils]: 77: Hoare triple {1375#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 78: Hoare triple {1375#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 79: Hoare triple {1375#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 80: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 81: Hoare triple {1375#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 82: Hoare triple {1375#false} assume !(1 == ~t9_pc~0); {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 83: Hoare triple {1375#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 84: Hoare triple {1375#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1375#false} is VALID [2022-02-21 04:22:58,868 INFO L290 TraceCheckUtils]: 85: Hoare triple {1375#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1375#false} is VALID [2022-02-21 04:22:58,869 INFO L290 TraceCheckUtils]: 86: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,869 INFO L290 TraceCheckUtils]: 87: Hoare triple {1375#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1375#false} is VALID [2022-02-21 04:22:58,869 INFO L290 TraceCheckUtils]: 88: Hoare triple {1375#false} assume !(1 == ~t10_pc~0); {1375#false} is VALID [2022-02-21 04:22:58,869 INFO L290 TraceCheckUtils]: 89: Hoare triple {1375#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1375#false} is VALID [2022-02-21 04:22:58,869 INFO L290 TraceCheckUtils]: 90: Hoare triple {1375#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1375#false} is VALID [2022-02-21 04:22:58,869 INFO L290 TraceCheckUtils]: 91: Hoare triple {1375#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1375#false} is VALID [2022-02-21 04:22:58,869 INFO L290 TraceCheckUtils]: 92: Hoare triple {1375#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 93: Hoare triple {1375#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 94: Hoare triple {1375#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 95: Hoare triple {1375#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 96: Hoare triple {1375#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 97: Hoare triple {1375#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 98: Hoare triple {1375#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 99: Hoare triple {1375#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,870 INFO L290 TraceCheckUtils]: 100: Hoare triple {1375#false} assume !(1 == ~T6_E~0); {1375#false} is VALID [2022-02-21 04:22:58,871 INFO L290 TraceCheckUtils]: 101: Hoare triple {1375#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,871 INFO L290 TraceCheckUtils]: 102: Hoare triple {1375#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,871 INFO L290 TraceCheckUtils]: 103: Hoare triple {1375#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,871 INFO L290 TraceCheckUtils]: 104: Hoare triple {1375#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,871 INFO L290 TraceCheckUtils]: 105: Hoare triple {1375#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,872 INFO L290 TraceCheckUtils]: 106: Hoare triple {1375#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,872 INFO L290 TraceCheckUtils]: 107: Hoare triple {1375#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,872 INFO L290 TraceCheckUtils]: 108: Hoare triple {1375#false} assume !(1 == ~E_3~0); {1375#false} is VALID [2022-02-21 04:22:58,872 INFO L290 TraceCheckUtils]: 109: Hoare triple {1375#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,872 INFO L290 TraceCheckUtils]: 110: Hoare triple {1375#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,872 INFO L290 TraceCheckUtils]: 111: Hoare triple {1375#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,872 INFO L290 TraceCheckUtils]: 112: Hoare triple {1375#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,873 INFO L290 TraceCheckUtils]: 113: Hoare triple {1375#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,873 INFO L290 TraceCheckUtils]: 114: Hoare triple {1375#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,873 INFO L290 TraceCheckUtils]: 115: Hoare triple {1375#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1375#false} is VALID [2022-02-21 04:22:58,873 INFO L290 TraceCheckUtils]: 116: Hoare triple {1375#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {1375#false} is VALID [2022-02-21 04:22:58,873 INFO L290 TraceCheckUtils]: 117: Hoare triple {1375#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,873 INFO L290 TraceCheckUtils]: 118: Hoare triple {1375#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {1375#false} is VALID [2022-02-21 04:22:58,873 INFO L290 TraceCheckUtils]: 119: Hoare triple {1375#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {1375#false} is VALID [2022-02-21 04:22:58,874 INFO L290 TraceCheckUtils]: 120: Hoare triple {1375#false} assume !(0 == start_simulation_~tmp~3#1); {1375#false} is VALID [2022-02-21 04:22:58,876 INFO L290 TraceCheckUtils]: 121: Hoare triple {1375#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {1375#false} is VALID [2022-02-21 04:22:58,876 INFO L290 TraceCheckUtils]: 122: Hoare triple {1375#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {1375#false} is VALID [2022-02-21 04:22:58,878 INFO L290 TraceCheckUtils]: 123: Hoare triple {1375#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {1375#false} is VALID [2022-02-21 04:22:58,878 INFO L290 TraceCheckUtils]: 124: Hoare triple {1375#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {1375#false} is VALID [2022-02-21 04:22:58,879 INFO L290 TraceCheckUtils]: 125: Hoare triple {1375#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1375#false} is VALID [2022-02-21 04:22:58,880 INFO L290 TraceCheckUtils]: 126: Hoare triple {1375#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1375#false} is VALID [2022-02-21 04:22:58,880 INFO L290 TraceCheckUtils]: 127: Hoare triple {1375#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {1375#false} is VALID [2022-02-21 04:22:58,883 INFO L290 TraceCheckUtils]: 128: Hoare triple {1375#false} assume !(0 != start_simulation_~tmp___0~1#1); {1375#false} is VALID [2022-02-21 04:22:58,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:58,885 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:58,885 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1546244317] [2022-02-21 04:22:58,885 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1546244317] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:58,885 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:58,885 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:58,885 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014724560] [2022-02-21 04:22:58,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:58,887 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:58,889 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:58,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:58,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:58,914 INFO L87 Difference]: Start difference. First operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:00,035 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2022-02-21 04:23:00,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:00,036 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,115 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:00,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2022-02-21 04:23:00,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:00,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1361 states and 2023 transitions. [2022-02-21 04:23:00,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:00,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:00,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2023 transitions. [2022-02-21 04:23:00,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:00,232 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-02-21 04:23:00,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2023 transitions. [2022-02-21 04:23:00,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:00,283 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:00,288 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2023 transitions. Second operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,291 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2023 transitions. Second operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,294 INFO L87 Difference]: Start difference. First operand 1361 states and 2023 transitions. Second operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:00,342 INFO L93 Difference]: Finished difference Result 1361 states and 2023 transitions. [2022-02-21 04:23:00,342 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2023 transitions. [2022-02-21 04:23:00,346 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:00,346 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:00,349 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2023 transitions. [2022-02-21 04:23:00,351 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2023 transitions. [2022-02-21 04:23:00,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:00,395 INFO L93 Difference]: Finished difference Result 1361 states and 2023 transitions. [2022-02-21 04:23:00,395 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2023 transitions. [2022-02-21 04:23:00,396 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:00,397 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:00,397 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:00,397 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:00,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2023 transitions. [2022-02-21 04:23:00,443 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-02-21 04:23:00,443 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-02-21 04:23:00,443 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:00,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2023 transitions. [2022-02-21 04:23:00,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:00,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:00,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:00,449 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,449 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,450 INFO L791 eck$LassoCheckResult]: Stem: 3750#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3751#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2791#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2792#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3680#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3384#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3385#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3662#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3818#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3550#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3551#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3440#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3441#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3778#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3740#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3668#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3669#L1024 assume !(0 == ~M_E~0); 3914#L1024-2 assume !(0 == ~T1_E~0); 3118#L1029-1 assume !(0 == ~T2_E~0); 3119#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3225#L1039-1 assume !(0 == ~T4_E~0); 4031#L1044-1 assume !(0 == ~T5_E~0); 3462#L1049-1 assume !(0 == ~T6_E~0); 3463#L1054-1 assume !(0 == ~T7_E~0); 3688#L1059-1 assume !(0 == ~T8_E~0); 3165#L1064-1 assume !(0 == ~T9_E~0); 3166#L1069-1 assume !(0 == ~T10_E~0); 3882#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3948#L1079-1 assume !(0 == ~E_1~0); 3916#L1084-1 assume !(0 == ~E_2~0); 3917#L1089-1 assume !(0 == ~E_3~0); 3967#L1094-1 assume !(0 == ~E_4~0); 3538#L1099-1 assume !(0 == ~E_5~0); 3539#L1104-1 assume !(0 == ~E_6~0); 3796#L1109-1 assume !(0 == ~E_7~0); 3339#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3340#L1119-1 assume !(0 == ~E_9~0); 3396#L1124-1 assume !(0 == ~E_10~0); 2824#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2825#L502 assume 1 == ~m_pc~0; 3686#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2953#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2954#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3736#L1273 assume !(0 != activate_threads_~tmp~1#1); 3737#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4066#L521 assume !(1 == ~t1_pc~0); 3999#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2884#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2885#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3028#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2868#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2869#L540 assume 1 == ~t2_pc~0; 3930#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3651#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3933#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3946#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3993#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3140#L559 assume 1 == ~t3_pc~0; 3141#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3421#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3563#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2971#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2972#L578 assume !(1 == ~t4_pc~0); 3092#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3091#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2860#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2861#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3720#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3721#L597 assume 1 == ~t5_pc~0; 4083#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2905#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2906#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3511#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3670#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3671#L616 assume !(1 == ~t6_pc~0); 3685#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3684#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4048#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3593#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3530#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3531#L635 assume 1 == ~t7_pc~0; 3725#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2874#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3245#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3891#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3663#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3664#L654 assume !(1 == ~t8_pc~0); 3486#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3487#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3994#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3879#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3880#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3116#L673 assume 1 == ~t9_pc~0; 3117#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2815#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4063#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3849#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3805#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3806#L692 assume !(1 == ~t10_pc~0); 3754#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3753#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3672#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3542#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3543#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3860#L1142 assume !(1 == ~M_E~0); 3031#L1142-2 assume !(1 == ~T1_E~0); 3032#L1147-1 assume !(1 == ~T2_E~0); 3850#L1152-1 assume !(1 == ~T3_E~0); 3426#L1157-1 assume !(1 == ~T4_E~0); 3427#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3567#L1167-1 assume !(1 == ~T6_E~0); 3568#L1172-1 assume !(1 == ~T7_E~0); 3987#L1177-1 assume !(1 == ~T8_E~0); 3705#L1182-1 assume !(1 == ~T9_E~0); 3706#L1187-1 assume !(1 == ~T10_E~0); 3799#L1192-1 assume !(1 == ~E_M~0); 3292#L1197-1 assume !(1 == ~E_1~0); 3293#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3654#L1207-1 assume !(1 == ~E_3~0); 3633#L1212-1 assume !(1 == ~E_4~0); 2890#L1217-1 assume !(1 == ~E_5~0); 2891#L1222-1 assume !(1 == ~E_6~0); 3629#L1227-1 assume !(1 == ~E_7~0); 3630#L1232-1 assume !(1 == ~E_8~0); 2756#L1237-1 assume !(1 == ~E_9~0); 2757#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3687#L1247-1 assume { :end_inline_reset_delta_events } true; 2930#L1553-2 [2022-02-21 04:23:00,450 INFO L793 eck$LassoCheckResult]: Loop: 2930#L1553-2 assume !false; 2931#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3840#L999 assume !false; 3888#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3015#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2908#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3403#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3757#L854 assume !(0 != eval_~tmp~0#1); 3758#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3202#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3203#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4020#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3499#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3500#L1039-3 assume !(0 == ~T4_E~0); 3823#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3110#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3111#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2886#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2887#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3471#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3472#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3801#L1079-3 assume !(0 == ~E_1~0); 3699#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3586#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3587#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3516#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3517#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3821#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3809#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3810#L1119-3 assume !(0 == ~E_9~0); 4090#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4097#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4057#L502-36 assume 1 == ~m_pc~0; 3824#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2742#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2743#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3167#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3168#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3445#L521-36 assume 1 == ~t1_pc~0; 3446#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3455#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3622#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3659#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3884#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3885#L540-36 assume !(1 == ~t2_pc~0); 2833#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2834#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3246#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4098#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3561#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2750#L559-36 assume !(1 == ~t3_pc~0); 2752#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3204#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3060#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3061#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3707#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3943#L578-36 assume !(1 == ~t4_pc~0); 3636#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3637#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3973#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3974#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3475#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3476#L597-36 assume !(1 == ~t5_pc~0); 3696#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4046#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3620#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3621#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3290#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3291#L616-36 assume !(1 == ~t6_pc~0); 4018#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2820#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2821#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3423#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3524#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3839#L635-36 assume 1 == ~t7_pc~0; 4023#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3896#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3569#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3570#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3512#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3513#L654-36 assume !(1 == ~t8_pc~0); 4027#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4028#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4100#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4085#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4067#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3195#L673-36 assume !(1 == ~t9_pc~0); 3196#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3548#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3549#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3903#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2763#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2764#L692-36 assume 1 == ~t10_pc~0; 3698#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2980#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3523#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3158#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3159#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3522#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3667#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4029#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4030#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3600#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3601#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3892#L1167-3 assume !(1 == ~T6_E~0); 4014#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3510#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3415#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3416#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3429#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3254#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3255#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3496#L1207-3 assume !(1 == ~E_3~0); 3611#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3819#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3149#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2847#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2848#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3923#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3924#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4099#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3977#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2999#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3000#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3679#L1572 assume !(0 == start_simulation_~tmp~3#1); 3295#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3448#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2777#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4051#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4052#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2746#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2747#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3901#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2930#L1553-2 [2022-02-21 04:23:00,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:00,451 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2022-02-21 04:23:00,451 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:00,451 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40645420] [2022-02-21 04:23:00,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:00,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:00,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:00,488 INFO L290 TraceCheckUtils]: 0: Hoare triple {6828#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {6828#true} is VALID [2022-02-21 04:23:00,489 INFO L290 TraceCheckUtils]: 1: Hoare triple {6828#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {6830#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:00,489 INFO L290 TraceCheckUtils]: 2: Hoare triple {6830#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6830#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:00,489 INFO L290 TraceCheckUtils]: 3: Hoare triple {6830#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6830#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:00,489 INFO L290 TraceCheckUtils]: 4: Hoare triple {6830#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {6830#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:00,490 INFO L290 TraceCheckUtils]: 5: Hoare triple {6830#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6830#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:00,490 INFO L290 TraceCheckUtils]: 6: Hoare triple {6830#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,490 INFO L290 TraceCheckUtils]: 7: Hoare triple {6829#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,490 INFO L290 TraceCheckUtils]: 8: Hoare triple {6829#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,490 INFO L290 TraceCheckUtils]: 9: Hoare triple {6829#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,490 INFO L290 TraceCheckUtils]: 10: Hoare triple {6829#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 11: Hoare triple {6829#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 12: Hoare triple {6829#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 13: Hoare triple {6829#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 14: Hoare triple {6829#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 15: Hoare triple {6829#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 16: Hoare triple {6829#false} assume !(0 == ~M_E~0); {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 17: Hoare triple {6829#false} assume !(0 == ~T1_E~0); {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 18: Hoare triple {6829#false} assume !(0 == ~T2_E~0); {6829#false} is VALID [2022-02-21 04:23:00,491 INFO L290 TraceCheckUtils]: 19: Hoare triple {6829#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 20: Hoare triple {6829#false} assume !(0 == ~T4_E~0); {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 21: Hoare triple {6829#false} assume !(0 == ~T5_E~0); {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 22: Hoare triple {6829#false} assume !(0 == ~T6_E~0); {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 23: Hoare triple {6829#false} assume !(0 == ~T7_E~0); {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 24: Hoare triple {6829#false} assume !(0 == ~T8_E~0); {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 25: Hoare triple {6829#false} assume !(0 == ~T9_E~0); {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 26: Hoare triple {6829#false} assume !(0 == ~T10_E~0); {6829#false} is VALID [2022-02-21 04:23:00,492 INFO L290 TraceCheckUtils]: 27: Hoare triple {6829#false} assume 0 == ~E_M~0;~E_M~0 := 1; {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 28: Hoare triple {6829#false} assume !(0 == ~E_1~0); {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 29: Hoare triple {6829#false} assume !(0 == ~E_2~0); {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 30: Hoare triple {6829#false} assume !(0 == ~E_3~0); {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 31: Hoare triple {6829#false} assume !(0 == ~E_4~0); {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 32: Hoare triple {6829#false} assume !(0 == ~E_5~0); {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 33: Hoare triple {6829#false} assume !(0 == ~E_6~0); {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 34: Hoare triple {6829#false} assume !(0 == ~E_7~0); {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 35: Hoare triple {6829#false} assume 0 == ~E_8~0;~E_8~0 := 1; {6829#false} is VALID [2022-02-21 04:23:00,493 INFO L290 TraceCheckUtils]: 36: Hoare triple {6829#false} assume !(0 == ~E_9~0); {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 37: Hoare triple {6829#false} assume !(0 == ~E_10~0); {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 38: Hoare triple {6829#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 39: Hoare triple {6829#false} assume 1 == ~m_pc~0; {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 40: Hoare triple {6829#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 41: Hoare triple {6829#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 42: Hoare triple {6829#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 43: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp~1#1); {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 44: Hoare triple {6829#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6829#false} is VALID [2022-02-21 04:23:00,494 INFO L290 TraceCheckUtils]: 45: Hoare triple {6829#false} assume !(1 == ~t1_pc~0); {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 46: Hoare triple {6829#false} is_transmit1_triggered_~__retres1~1#1 := 0; {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 47: Hoare triple {6829#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 48: Hoare triple {6829#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 49: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___0~0#1); {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 50: Hoare triple {6829#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 51: Hoare triple {6829#false} assume 1 == ~t2_pc~0; {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 52: Hoare triple {6829#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6829#false} is VALID [2022-02-21 04:23:00,495 INFO L290 TraceCheckUtils]: 53: Hoare triple {6829#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 54: Hoare triple {6829#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 55: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___1~0#1); {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 56: Hoare triple {6829#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 57: Hoare triple {6829#false} assume 1 == ~t3_pc~0; {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 58: Hoare triple {6829#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 59: Hoare triple {6829#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 60: Hoare triple {6829#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 61: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___2~0#1); {6829#false} is VALID [2022-02-21 04:23:00,496 INFO L290 TraceCheckUtils]: 62: Hoare triple {6829#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 63: Hoare triple {6829#false} assume !(1 == ~t4_pc~0); {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 64: Hoare triple {6829#false} is_transmit4_triggered_~__retres1~4#1 := 0; {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 65: Hoare triple {6829#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 66: Hoare triple {6829#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 67: Hoare triple {6829#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 68: Hoare triple {6829#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 69: Hoare triple {6829#false} assume 1 == ~t5_pc~0; {6829#false} is VALID [2022-02-21 04:23:00,497 INFO L290 TraceCheckUtils]: 70: Hoare triple {6829#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 71: Hoare triple {6829#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 72: Hoare triple {6829#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 73: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___4~0#1); {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 74: Hoare triple {6829#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 75: Hoare triple {6829#false} assume !(1 == ~t6_pc~0); {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 76: Hoare triple {6829#false} is_transmit6_triggered_~__retres1~6#1 := 0; {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 77: Hoare triple {6829#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 78: Hoare triple {6829#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {6829#false} is VALID [2022-02-21 04:23:00,498 INFO L290 TraceCheckUtils]: 79: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___5~0#1); {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 80: Hoare triple {6829#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 81: Hoare triple {6829#false} assume 1 == ~t7_pc~0; {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 82: Hoare triple {6829#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 83: Hoare triple {6829#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 84: Hoare triple {6829#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 85: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___6~0#1); {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 86: Hoare triple {6829#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 87: Hoare triple {6829#false} assume !(1 == ~t8_pc~0); {6829#false} is VALID [2022-02-21 04:23:00,499 INFO L290 TraceCheckUtils]: 88: Hoare triple {6829#false} is_transmit8_triggered_~__retres1~8#1 := 0; {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 89: Hoare triple {6829#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 90: Hoare triple {6829#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 91: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___7~0#1); {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 92: Hoare triple {6829#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 93: Hoare triple {6829#false} assume 1 == ~t9_pc~0; {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 94: Hoare triple {6829#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 95: Hoare triple {6829#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {6829#false} is VALID [2022-02-21 04:23:00,500 INFO L290 TraceCheckUtils]: 96: Hoare triple {6829#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 97: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___8~0#1); {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 98: Hoare triple {6829#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 99: Hoare triple {6829#false} assume !(1 == ~t10_pc~0); {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 100: Hoare triple {6829#false} is_transmit10_triggered_~__retres1~10#1 := 0; {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 101: Hoare triple {6829#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 102: Hoare triple {6829#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 103: Hoare triple {6829#false} assume !(0 != activate_threads_~tmp___9~0#1); {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 104: Hoare triple {6829#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6829#false} is VALID [2022-02-21 04:23:00,501 INFO L290 TraceCheckUtils]: 105: Hoare triple {6829#false} assume !(1 == ~M_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 106: Hoare triple {6829#false} assume !(1 == ~T1_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 107: Hoare triple {6829#false} assume !(1 == ~T2_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 108: Hoare triple {6829#false} assume !(1 == ~T3_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 109: Hoare triple {6829#false} assume !(1 == ~T4_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 110: Hoare triple {6829#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 111: Hoare triple {6829#false} assume !(1 == ~T6_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 112: Hoare triple {6829#false} assume !(1 == ~T7_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 113: Hoare triple {6829#false} assume !(1 == ~T8_E~0); {6829#false} is VALID [2022-02-21 04:23:00,502 INFO L290 TraceCheckUtils]: 114: Hoare triple {6829#false} assume !(1 == ~T9_E~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 115: Hoare triple {6829#false} assume !(1 == ~T10_E~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 116: Hoare triple {6829#false} assume !(1 == ~E_M~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 117: Hoare triple {6829#false} assume !(1 == ~E_1~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 118: Hoare triple {6829#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 119: Hoare triple {6829#false} assume !(1 == ~E_3~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 120: Hoare triple {6829#false} assume !(1 == ~E_4~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 121: Hoare triple {6829#false} assume !(1 == ~E_5~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 122: Hoare triple {6829#false} assume !(1 == ~E_6~0); {6829#false} is VALID [2022-02-21 04:23:00,503 INFO L290 TraceCheckUtils]: 123: Hoare triple {6829#false} assume !(1 == ~E_7~0); {6829#false} is VALID [2022-02-21 04:23:00,504 INFO L290 TraceCheckUtils]: 124: Hoare triple {6829#false} assume !(1 == ~E_8~0); {6829#false} is VALID [2022-02-21 04:23:00,504 INFO L290 TraceCheckUtils]: 125: Hoare triple {6829#false} assume !(1 == ~E_9~0); {6829#false} is VALID [2022-02-21 04:23:00,504 INFO L290 TraceCheckUtils]: 126: Hoare triple {6829#false} assume 1 == ~E_10~0;~E_10~0 := 2; {6829#false} is VALID [2022-02-21 04:23:00,504 INFO L290 TraceCheckUtils]: 127: Hoare triple {6829#false} assume { :end_inline_reset_delta_events } true; {6829#false} is VALID [2022-02-21 04:23:00,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:00,505 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:00,505 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40645420] [2022-02-21 04:23:00,505 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40645420] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:00,505 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:00,505 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:00,505 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894163553] [2022-02-21 04:23:00,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:00,506 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:00,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:00,506 INFO L85 PathProgramCache]: Analyzing trace with hash -2058537928, now seen corresponding path program 1 times [2022-02-21 04:23:00,506 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:00,507 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45138491] [2022-02-21 04:23:00,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:00,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:00,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:00,568 INFO L290 TraceCheckUtils]: 0: Hoare triple {6831#true} assume !false; {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 1: Hoare triple {6831#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 2: Hoare triple {6831#true} assume !false; {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 3: Hoare triple {6831#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 4: Hoare triple {6831#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 5: Hoare triple {6831#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 6: Hoare triple {6831#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 7: Hoare triple {6831#true} assume !(0 != eval_~tmp~0#1); {6831#true} is VALID [2022-02-21 04:23:00,569 INFO L290 TraceCheckUtils]: 8: Hoare triple {6831#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6831#true} is VALID [2022-02-21 04:23:00,570 INFO L290 TraceCheckUtils]: 9: Hoare triple {6831#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6831#true} is VALID [2022-02-21 04:23:00,570 INFO L290 TraceCheckUtils]: 10: Hoare triple {6831#true} assume 0 == ~M_E~0;~M_E~0 := 1; {6831#true} is VALID [2022-02-21 04:23:00,570 INFO L290 TraceCheckUtils]: 11: Hoare triple {6831#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6831#true} is VALID [2022-02-21 04:23:00,570 INFO L290 TraceCheckUtils]: 12: Hoare triple {6831#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {6831#true} is VALID [2022-02-21 04:23:00,570 INFO L290 TraceCheckUtils]: 13: Hoare triple {6831#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6831#true} is VALID [2022-02-21 04:23:00,570 INFO L290 TraceCheckUtils]: 14: Hoare triple {6831#true} assume !(0 == ~T4_E~0); {6831#true} is VALID [2022-02-21 04:23:00,570 INFO L290 TraceCheckUtils]: 15: Hoare triple {6831#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {6831#true} is VALID [2022-02-21 04:23:00,571 INFO L290 TraceCheckUtils]: 16: Hoare triple {6831#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,571 INFO L290 TraceCheckUtils]: 17: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,571 INFO L290 TraceCheckUtils]: 18: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,571 INFO L290 TraceCheckUtils]: 19: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,572 INFO L290 TraceCheckUtils]: 20: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,572 INFO L290 TraceCheckUtils]: 21: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,572 INFO L290 TraceCheckUtils]: 22: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,573 INFO L290 TraceCheckUtils]: 23: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,573 INFO L290 TraceCheckUtils]: 24: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,573 INFO L290 TraceCheckUtils]: 25: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,573 INFO L290 TraceCheckUtils]: 26: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,574 INFO L290 TraceCheckUtils]: 27: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,576 INFO L290 TraceCheckUtils]: 28: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,576 INFO L290 TraceCheckUtils]: 29: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,576 INFO L290 TraceCheckUtils]: 30: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,577 INFO L290 TraceCheckUtils]: 31: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,577 INFO L290 TraceCheckUtils]: 32: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,577 INFO L290 TraceCheckUtils]: 33: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,577 INFO L290 TraceCheckUtils]: 34: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,578 INFO L290 TraceCheckUtils]: 35: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,578 INFO L290 TraceCheckUtils]: 36: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,578 INFO L290 TraceCheckUtils]: 37: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,578 INFO L290 TraceCheckUtils]: 38: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,579 INFO L290 TraceCheckUtils]: 39: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,579 INFO L290 TraceCheckUtils]: 40: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,579 INFO L290 TraceCheckUtils]: 41: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,580 INFO L290 TraceCheckUtils]: 42: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,580 INFO L290 TraceCheckUtils]: 43: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,580 INFO L290 TraceCheckUtils]: 44: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,580 INFO L290 TraceCheckUtils]: 45: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,581 INFO L290 TraceCheckUtils]: 46: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,581 INFO L290 TraceCheckUtils]: 47: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,581 INFO L290 TraceCheckUtils]: 48: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,581 INFO L290 TraceCheckUtils]: 49: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,582 INFO L290 TraceCheckUtils]: 50: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,582 INFO L290 TraceCheckUtils]: 51: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,582 INFO L290 TraceCheckUtils]: 52: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,583 INFO L290 TraceCheckUtils]: 53: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,583 INFO L290 TraceCheckUtils]: 54: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,583 INFO L290 TraceCheckUtils]: 55: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,607 INFO L290 TraceCheckUtils]: 56: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,608 INFO L290 TraceCheckUtils]: 57: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,608 INFO L290 TraceCheckUtils]: 58: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,608 INFO L290 TraceCheckUtils]: 59: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,609 INFO L290 TraceCheckUtils]: 60: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,609 INFO L290 TraceCheckUtils]: 61: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,609 INFO L290 TraceCheckUtils]: 62: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,610 INFO L290 TraceCheckUtils]: 63: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,610 INFO L290 TraceCheckUtils]: 64: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,610 INFO L290 TraceCheckUtils]: 65: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,611 INFO L290 TraceCheckUtils]: 66: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,611 INFO L290 TraceCheckUtils]: 67: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,611 INFO L290 TraceCheckUtils]: 68: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,611 INFO L290 TraceCheckUtils]: 69: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,612 INFO L290 TraceCheckUtils]: 70: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,612 INFO L290 TraceCheckUtils]: 71: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,612 INFO L290 TraceCheckUtils]: 72: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,613 INFO L290 TraceCheckUtils]: 73: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,613 INFO L290 TraceCheckUtils]: 74: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,613 INFO L290 TraceCheckUtils]: 75: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,613 INFO L290 TraceCheckUtils]: 76: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,614 INFO L290 TraceCheckUtils]: 77: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,614 INFO L290 TraceCheckUtils]: 78: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,614 INFO L290 TraceCheckUtils]: 79: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,615 INFO L290 TraceCheckUtils]: 80: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,615 INFO L290 TraceCheckUtils]: 81: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,615 INFO L290 TraceCheckUtils]: 82: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,616 INFO L290 TraceCheckUtils]: 83: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,616 INFO L290 TraceCheckUtils]: 84: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,616 INFO L290 TraceCheckUtils]: 85: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,616 INFO L290 TraceCheckUtils]: 86: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,617 INFO L290 TraceCheckUtils]: 87: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,617 INFO L290 TraceCheckUtils]: 88: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,617 INFO L290 TraceCheckUtils]: 89: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,618 INFO L290 TraceCheckUtils]: 90: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,618 INFO L290 TraceCheckUtils]: 91: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,618 INFO L290 TraceCheckUtils]: 92: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,618 INFO L290 TraceCheckUtils]: 93: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,619 INFO L290 TraceCheckUtils]: 94: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,619 INFO L290 TraceCheckUtils]: 95: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,619 INFO L290 TraceCheckUtils]: 96: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,620 INFO L290 TraceCheckUtils]: 97: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,620 INFO L290 TraceCheckUtils]: 98: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,620 INFO L290 TraceCheckUtils]: 99: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,620 INFO L290 TraceCheckUtils]: 100: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,621 INFO L290 TraceCheckUtils]: 101: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,621 INFO L290 TraceCheckUtils]: 102: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,621 INFO L290 TraceCheckUtils]: 103: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,621 INFO L290 TraceCheckUtils]: 104: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6833#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:00,622 INFO L290 TraceCheckUtils]: 105: Hoare triple {6833#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {6832#false} is VALID [2022-02-21 04:23:00,622 INFO L290 TraceCheckUtils]: 106: Hoare triple {6832#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,622 INFO L290 TraceCheckUtils]: 107: Hoare triple {6832#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,622 INFO L290 TraceCheckUtils]: 108: Hoare triple {6832#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,622 INFO L290 TraceCheckUtils]: 109: Hoare triple {6832#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,622 INFO L290 TraceCheckUtils]: 110: Hoare triple {6832#false} assume 1 == ~E_M~0;~E_M~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,622 INFO L290 TraceCheckUtils]: 111: Hoare triple {6832#false} assume 1 == ~E_1~0;~E_1~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 112: Hoare triple {6832#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 113: Hoare triple {6832#false} assume !(1 == ~E_3~0); {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 114: Hoare triple {6832#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 115: Hoare triple {6832#false} assume 1 == ~E_5~0;~E_5~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 116: Hoare triple {6832#false} assume 1 == ~E_6~0;~E_6~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 117: Hoare triple {6832#false} assume 1 == ~E_7~0;~E_7~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 118: Hoare triple {6832#false} assume 1 == ~E_8~0;~E_8~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 119: Hoare triple {6832#false} assume 1 == ~E_9~0;~E_9~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,623 INFO L290 TraceCheckUtils]: 120: Hoare triple {6832#false} assume 1 == ~E_10~0;~E_10~0 := 2; {6832#false} is VALID [2022-02-21 04:23:00,624 INFO L290 TraceCheckUtils]: 121: Hoare triple {6832#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6832#false} is VALID [2022-02-21 04:23:00,624 INFO L290 TraceCheckUtils]: 122: Hoare triple {6832#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6832#false} is VALID [2022-02-21 04:23:00,624 INFO L290 TraceCheckUtils]: 123: Hoare triple {6832#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6832#false} is VALID [2022-02-21 04:23:00,624 INFO L290 TraceCheckUtils]: 124: Hoare triple {6832#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {6832#false} is VALID [2022-02-21 04:23:00,624 INFO L290 TraceCheckUtils]: 125: Hoare triple {6832#false} assume !(0 == start_simulation_~tmp~3#1); {6832#false} is VALID [2022-02-21 04:23:00,624 INFO L290 TraceCheckUtils]: 126: Hoare triple {6832#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6832#false} is VALID [2022-02-21 04:23:00,624 INFO L290 TraceCheckUtils]: 127: Hoare triple {6832#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6832#false} is VALID [2022-02-21 04:23:00,625 INFO L290 TraceCheckUtils]: 128: Hoare triple {6832#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6832#false} is VALID [2022-02-21 04:23:00,625 INFO L290 TraceCheckUtils]: 129: Hoare triple {6832#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {6832#false} is VALID [2022-02-21 04:23:00,625 INFO L290 TraceCheckUtils]: 130: Hoare triple {6832#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6832#false} is VALID [2022-02-21 04:23:00,625 INFO L290 TraceCheckUtils]: 131: Hoare triple {6832#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6832#false} is VALID [2022-02-21 04:23:00,625 INFO L290 TraceCheckUtils]: 132: Hoare triple {6832#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {6832#false} is VALID [2022-02-21 04:23:00,625 INFO L290 TraceCheckUtils]: 133: Hoare triple {6832#false} assume !(0 != start_simulation_~tmp___0~1#1); {6832#false} is VALID [2022-02-21 04:23:00,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:00,626 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:00,626 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45138491] [2022-02-21 04:23:00,626 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [45138491] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:00,626 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:00,627 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:00,627 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046382375] [2022-02-21 04:23:00,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:00,627 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:00,627 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:00,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:00,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:00,628 INFO L87 Difference]: Start difference. First operand 1361 states and 2023 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:01,676 INFO L93 Difference]: Finished difference Result 1361 states and 2022 transitions. [2022-02-21 04:23:01,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:01,676 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,756 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:01,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2022 transitions. [2022-02-21 04:23:01,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:01,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2022 transitions. [2022-02-21 04:23:01,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:01,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:01,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2022 transitions. [2022-02-21 04:23:01,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:01,851 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-02-21 04:23:01,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2022 transitions. [2022-02-21 04:23:01,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:01,870 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:01,874 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2022 transitions. Second operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,877 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2022 transitions. Second operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,880 INFO L87 Difference]: Start difference. First operand 1361 states and 2022 transitions. Second operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:01,926 INFO L93 Difference]: Finished difference Result 1361 states and 2022 transitions. [2022-02-21 04:23:01,926 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2022 transitions. [2022-02-21 04:23:01,959 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:01,959 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:01,963 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2022 transitions. [2022-02-21 04:23:01,967 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2022 transitions. [2022-02-21 04:23:02,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,016 INFO L93 Difference]: Finished difference Result 1361 states and 2022 transitions. [2022-02-21 04:23:02,016 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2022 transitions. [2022-02-21 04:23:02,018 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:02,018 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:02,018 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:02,018 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:02,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2022 transitions. [2022-02-21 04:23:02,066 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-02-21 04:23:02,067 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-02-21 04:23:02,067 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:02,067 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2022 transitions. [2022-02-21 04:23:02,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:02,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:02,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:02,073 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,073 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,074 INFO L791 eck$LassoCheckResult]: Stem: 9203#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 9204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8244#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8245#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9133#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8836#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8837#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9115#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9271#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9001#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9002#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8891#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8892#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9231#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9193#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9120#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9121#L1024 assume !(0 == ~M_E~0); 9367#L1024-2 assume !(0 == ~T1_E~0); 8571#L1029-1 assume !(0 == ~T2_E~0); 8572#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8678#L1039-1 assume !(0 == ~T4_E~0); 9484#L1044-1 assume !(0 == ~T5_E~0); 8913#L1049-1 assume !(0 == ~T6_E~0); 8914#L1054-1 assume !(0 == ~T7_E~0); 9141#L1059-1 assume !(0 == ~T8_E~0); 8618#L1064-1 assume !(0 == ~T9_E~0); 8619#L1069-1 assume !(0 == ~T10_E~0); 9335#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9401#L1079-1 assume !(0 == ~E_1~0); 9369#L1084-1 assume !(0 == ~E_2~0); 9370#L1089-1 assume !(0 == ~E_3~0); 9420#L1094-1 assume !(0 == ~E_4~0); 8991#L1099-1 assume !(0 == ~E_5~0); 8992#L1104-1 assume !(0 == ~E_6~0); 9249#L1109-1 assume !(0 == ~E_7~0); 8792#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8793#L1119-1 assume !(0 == ~E_9~0); 8847#L1124-1 assume !(0 == ~E_10~0); 8277#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8278#L502 assume 1 == ~m_pc~0; 9139#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8406#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8407#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9188#L1273 assume !(0 != activate_threads_~tmp~1#1); 9189#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9519#L521 assume !(1 == ~t1_pc~0); 9452#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8337#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8338#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8480#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8319#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8320#L540 assume 1 == ~t2_pc~0; 9383#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9104#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9386#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9399#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9446#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8593#L559 assume 1 == ~t3_pc~0; 8594#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8872#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8873#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9016#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8424#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8425#L578 assume !(1 == ~t4_pc~0); 8543#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8542#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8313#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8314#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9171#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9172#L597 assume 1 == ~t5_pc~0; 9534#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8358#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8359#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8959#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9122#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9123#L616 assume !(1 == ~t6_pc~0); 9137#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9136#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9501#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9046#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 8983#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8984#L635 assume 1 == ~t7_pc~0; 9176#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8327#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8698#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9344#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9116#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9117#L654 assume !(1 == ~t8_pc~0); 8939#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8940#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9447#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9332#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9333#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8569#L673 assume 1 == ~t9_pc~0; 8570#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8268#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9516#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9302#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9258#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9259#L692 assume !(1 == ~t10_pc~0); 9207#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9206#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9125#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8995#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 8996#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9313#L1142 assume !(1 == ~M_E~0); 8484#L1142-2 assume !(1 == ~T1_E~0); 8485#L1147-1 assume !(1 == ~T2_E~0); 9303#L1152-1 assume !(1 == ~T3_E~0); 8879#L1157-1 assume !(1 == ~T4_E~0); 8880#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9020#L1167-1 assume !(1 == ~T6_E~0); 9021#L1172-1 assume !(1 == ~T7_E~0); 9440#L1177-1 assume !(1 == ~T8_E~0); 9158#L1182-1 assume !(1 == ~T9_E~0); 9159#L1187-1 assume !(1 == ~T10_E~0); 9252#L1192-1 assume !(1 == ~E_M~0); 8743#L1197-1 assume !(1 == ~E_1~0); 8744#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9107#L1207-1 assume !(1 == ~E_3~0); 9086#L1212-1 assume !(1 == ~E_4~0); 8343#L1217-1 assume !(1 == ~E_5~0); 8344#L1222-1 assume !(1 == ~E_6~0); 9082#L1227-1 assume !(1 == ~E_7~0); 9083#L1232-1 assume !(1 == ~E_8~0); 8209#L1237-1 assume !(1 == ~E_9~0); 8210#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9140#L1247-1 assume { :end_inline_reset_delta_events } true; 8383#L1553-2 [2022-02-21 04:23:02,074 INFO L793 eck$LassoCheckResult]: Loop: 8383#L1553-2 assume !false; 8384#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9293#L999 assume !false; 9339#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8468#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8361#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8856#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9210#L854 assume !(0 != eval_~tmp~0#1); 9211#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8655#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8656#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9473#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8982#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8952#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8953#L1039-3 assume !(0 == ~T4_E~0); 9276#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8563#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8564#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8339#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8340#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8924#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8925#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9254#L1079-3 assume !(0 == ~E_1~0); 9151#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9039#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9040#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8969#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8970#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9274#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9262#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9263#L1119-3 assume !(0 == ~E_9~0); 9543#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9550#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9510#L502-36 assume !(1 == ~m_pc~0); 8710#L502-38 is_master_triggered_~__retres1~0#1 := 0; 8195#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8196#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8620#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8621#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8896#L521-36 assume 1 == ~t1_pc~0; 8897#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8908#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9075#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9112#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9337#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9338#L540-36 assume 1 == ~t2_pc~0; 9512#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8285#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8699#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9551#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9015#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8206#L559-36 assume !(1 == ~t3_pc~0); 8208#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8663#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8513#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8514#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9160#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9396#L578-36 assume !(1 == ~t4_pc~0); 9092#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 9093#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9426#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9427#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8930#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8931#L597-36 assume !(1 == ~t5_pc~0); 9149#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9499#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9073#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9074#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 8745#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8746#L616-36 assume 1 == ~t6_pc~0; 9513#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8273#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8274#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8876#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8977#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9292#L635-36 assume 1 == ~t7_pc~0; 9476#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9349#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9022#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9023#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8965#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8966#L654-36 assume !(1 == ~t8_pc~0); 9480#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9481#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9553#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9538#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9520#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8648#L673-36 assume !(1 == ~t9_pc~0); 8649#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 9003#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9004#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9356#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8216#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8217#L692-36 assume 1 == ~t10_pc~0; 9152#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8433#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8976#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8611#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8612#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8975#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9124#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9482#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9483#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9053#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9054#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9345#L1167-3 assume !(1 == ~T6_E~0); 9467#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8964#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8868#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8869#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8882#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8707#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8708#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8949#L1207-3 assume !(1 == ~E_3~0); 9064#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9272#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8603#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8300#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8301#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9377#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9378#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9552#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9430#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8452#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8453#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 9132#L1572 assume !(0 == start_simulation_~tmp~3#1); 8748#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8901#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8230#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9504#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 9505#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8199#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8200#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9354#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8383#L1553-2 [2022-02-21 04:23:02,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2022-02-21 04:23:02,075 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,075 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547018970] [2022-02-21 04:23:02,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:02,103 INFO L290 TraceCheckUtils]: 0: Hoare triple {12281#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {12281#true} is VALID [2022-02-21 04:23:02,103 INFO L290 TraceCheckUtils]: 1: Hoare triple {12281#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {12283#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:02,103 INFO L290 TraceCheckUtils]: 2: Hoare triple {12283#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {12283#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:02,104 INFO L290 TraceCheckUtils]: 3: Hoare triple {12283#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {12283#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:02,104 INFO L290 TraceCheckUtils]: 4: Hoare triple {12283#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {12283#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:02,104 INFO L290 TraceCheckUtils]: 5: Hoare triple {12283#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {12283#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:02,104 INFO L290 TraceCheckUtils]: 6: Hoare triple {12283#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {12283#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 7: Hoare triple {12283#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 8: Hoare triple {12282#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 9: Hoare triple {12282#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 10: Hoare triple {12282#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 11: Hoare triple {12282#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 12: Hoare triple {12282#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 13: Hoare triple {12282#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 14: Hoare triple {12282#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,105 INFO L290 TraceCheckUtils]: 15: Hoare triple {12282#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 16: Hoare triple {12282#false} assume !(0 == ~M_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 17: Hoare triple {12282#false} assume !(0 == ~T1_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 18: Hoare triple {12282#false} assume !(0 == ~T2_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 19: Hoare triple {12282#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 20: Hoare triple {12282#false} assume !(0 == ~T4_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 21: Hoare triple {12282#false} assume !(0 == ~T5_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 22: Hoare triple {12282#false} assume !(0 == ~T6_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 23: Hoare triple {12282#false} assume !(0 == ~T7_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 24: Hoare triple {12282#false} assume !(0 == ~T8_E~0); {12282#false} is VALID [2022-02-21 04:23:02,106 INFO L290 TraceCheckUtils]: 25: Hoare triple {12282#false} assume !(0 == ~T9_E~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 26: Hoare triple {12282#false} assume !(0 == ~T10_E~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 27: Hoare triple {12282#false} assume 0 == ~E_M~0;~E_M~0 := 1; {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 28: Hoare triple {12282#false} assume !(0 == ~E_1~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 29: Hoare triple {12282#false} assume !(0 == ~E_2~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 30: Hoare triple {12282#false} assume !(0 == ~E_3~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 31: Hoare triple {12282#false} assume !(0 == ~E_4~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 32: Hoare triple {12282#false} assume !(0 == ~E_5~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 33: Hoare triple {12282#false} assume !(0 == ~E_6~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 34: Hoare triple {12282#false} assume !(0 == ~E_7~0); {12282#false} is VALID [2022-02-21 04:23:02,107 INFO L290 TraceCheckUtils]: 35: Hoare triple {12282#false} assume 0 == ~E_8~0;~E_8~0 := 1; {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 36: Hoare triple {12282#false} assume !(0 == ~E_9~0); {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 37: Hoare triple {12282#false} assume !(0 == ~E_10~0); {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 38: Hoare triple {12282#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 39: Hoare triple {12282#false} assume 1 == ~m_pc~0; {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 40: Hoare triple {12282#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 41: Hoare triple {12282#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 42: Hoare triple {12282#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 43: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp~1#1); {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 44: Hoare triple {12282#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12282#false} is VALID [2022-02-21 04:23:02,108 INFO L290 TraceCheckUtils]: 45: Hoare triple {12282#false} assume !(1 == ~t1_pc~0); {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 46: Hoare triple {12282#false} is_transmit1_triggered_~__retres1~1#1 := 0; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 47: Hoare triple {12282#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 48: Hoare triple {12282#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 49: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___0~0#1); {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 50: Hoare triple {12282#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 51: Hoare triple {12282#false} assume 1 == ~t2_pc~0; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 52: Hoare triple {12282#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 53: Hoare triple {12282#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 54: Hoare triple {12282#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12282#false} is VALID [2022-02-21 04:23:02,109 INFO L290 TraceCheckUtils]: 55: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___1~0#1); {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 56: Hoare triple {12282#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 57: Hoare triple {12282#false} assume 1 == ~t3_pc~0; {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 58: Hoare triple {12282#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 59: Hoare triple {12282#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 60: Hoare triple {12282#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 61: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___2~0#1); {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 62: Hoare triple {12282#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 63: Hoare triple {12282#false} assume !(1 == ~t4_pc~0); {12282#false} is VALID [2022-02-21 04:23:02,110 INFO L290 TraceCheckUtils]: 64: Hoare triple {12282#false} is_transmit4_triggered_~__retres1~4#1 := 0; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 65: Hoare triple {12282#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 66: Hoare triple {12282#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 67: Hoare triple {12282#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 68: Hoare triple {12282#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 69: Hoare triple {12282#false} assume 1 == ~t5_pc~0; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 70: Hoare triple {12282#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 71: Hoare triple {12282#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 72: Hoare triple {12282#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 73: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___4~0#1); {12282#false} is VALID [2022-02-21 04:23:02,111 INFO L290 TraceCheckUtils]: 74: Hoare triple {12282#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 75: Hoare triple {12282#false} assume !(1 == ~t6_pc~0); {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 76: Hoare triple {12282#false} is_transmit6_triggered_~__retres1~6#1 := 0; {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 77: Hoare triple {12282#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 78: Hoare triple {12282#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 79: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___5~0#1); {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 80: Hoare triple {12282#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 81: Hoare triple {12282#false} assume 1 == ~t7_pc~0; {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 82: Hoare triple {12282#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {12282#false} is VALID [2022-02-21 04:23:02,112 INFO L290 TraceCheckUtils]: 83: Hoare triple {12282#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 84: Hoare triple {12282#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 85: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___6~0#1); {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 86: Hoare triple {12282#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 87: Hoare triple {12282#false} assume !(1 == ~t8_pc~0); {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 88: Hoare triple {12282#false} is_transmit8_triggered_~__retres1~8#1 := 0; {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 89: Hoare triple {12282#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 90: Hoare triple {12282#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 91: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___7~0#1); {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 92: Hoare triple {12282#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {12282#false} is VALID [2022-02-21 04:23:02,113 INFO L290 TraceCheckUtils]: 93: Hoare triple {12282#false} assume 1 == ~t9_pc~0; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 94: Hoare triple {12282#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 95: Hoare triple {12282#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 96: Hoare triple {12282#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 97: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___8~0#1); {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 98: Hoare triple {12282#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 99: Hoare triple {12282#false} assume !(1 == ~t10_pc~0); {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 100: Hoare triple {12282#false} is_transmit10_triggered_~__retres1~10#1 := 0; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 101: Hoare triple {12282#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 102: Hoare triple {12282#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {12282#false} is VALID [2022-02-21 04:23:02,114 INFO L290 TraceCheckUtils]: 103: Hoare triple {12282#false} assume !(0 != activate_threads_~tmp___9~0#1); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 104: Hoare triple {12282#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 105: Hoare triple {12282#false} assume !(1 == ~M_E~0); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 106: Hoare triple {12282#false} assume !(1 == ~T1_E~0); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 107: Hoare triple {12282#false} assume !(1 == ~T2_E~0); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 108: Hoare triple {12282#false} assume !(1 == ~T3_E~0); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 109: Hoare triple {12282#false} assume !(1 == ~T4_E~0); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 110: Hoare triple {12282#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 111: Hoare triple {12282#false} assume !(1 == ~T6_E~0); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 112: Hoare triple {12282#false} assume !(1 == ~T7_E~0); {12282#false} is VALID [2022-02-21 04:23:02,115 INFO L290 TraceCheckUtils]: 113: Hoare triple {12282#false} assume !(1 == ~T8_E~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 114: Hoare triple {12282#false} assume !(1 == ~T9_E~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 115: Hoare triple {12282#false} assume !(1 == ~T10_E~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 116: Hoare triple {12282#false} assume !(1 == ~E_M~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 117: Hoare triple {12282#false} assume !(1 == ~E_1~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 118: Hoare triple {12282#false} assume 1 == ~E_2~0;~E_2~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 119: Hoare triple {12282#false} assume !(1 == ~E_3~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 120: Hoare triple {12282#false} assume !(1 == ~E_4~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 121: Hoare triple {12282#false} assume !(1 == ~E_5~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 122: Hoare triple {12282#false} assume !(1 == ~E_6~0); {12282#false} is VALID [2022-02-21 04:23:02,116 INFO L290 TraceCheckUtils]: 123: Hoare triple {12282#false} assume !(1 == ~E_7~0); {12282#false} is VALID [2022-02-21 04:23:02,117 INFO L290 TraceCheckUtils]: 124: Hoare triple {12282#false} assume !(1 == ~E_8~0); {12282#false} is VALID [2022-02-21 04:23:02,117 INFO L290 TraceCheckUtils]: 125: Hoare triple {12282#false} assume !(1 == ~E_9~0); {12282#false} is VALID [2022-02-21 04:23:02,117 INFO L290 TraceCheckUtils]: 126: Hoare triple {12282#false} assume 1 == ~E_10~0;~E_10~0 := 2; {12282#false} is VALID [2022-02-21 04:23:02,117 INFO L290 TraceCheckUtils]: 127: Hoare triple {12282#false} assume { :end_inline_reset_delta_events } true; {12282#false} is VALID [2022-02-21 04:23:02,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:02,118 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:02,118 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547018970] [2022-02-21 04:23:02,118 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547018970] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:02,118 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:02,118 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:02,118 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [75232008] [2022-02-21 04:23:02,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:02,119 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:02,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,119 INFO L85 PathProgramCache]: Analyzing trace with hash -2079491209, now seen corresponding path program 1 times [2022-02-21 04:23:02,119 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,119 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608488511] [2022-02-21 04:23:02,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:02,158 INFO L290 TraceCheckUtils]: 0: Hoare triple {12284#true} assume !false; {12284#true} is VALID [2022-02-21 04:23:02,158 INFO L290 TraceCheckUtils]: 1: Hoare triple {12284#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {12284#true} is VALID [2022-02-21 04:23:02,158 INFO L290 TraceCheckUtils]: 2: Hoare triple {12284#true} assume !false; {12284#true} is VALID [2022-02-21 04:23:02,158 INFO L290 TraceCheckUtils]: 3: Hoare triple {12284#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {12284#true} is VALID [2022-02-21 04:23:02,158 INFO L290 TraceCheckUtils]: 4: Hoare triple {12284#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 5: Hoare triple {12284#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 6: Hoare triple {12284#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 7: Hoare triple {12284#true} assume !(0 != eval_~tmp~0#1); {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 8: Hoare triple {12284#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 9: Hoare triple {12284#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 10: Hoare triple {12284#true} assume 0 == ~M_E~0;~M_E~0 := 1; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 11: Hoare triple {12284#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 12: Hoare triple {12284#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {12284#true} is VALID [2022-02-21 04:23:02,159 INFO L290 TraceCheckUtils]: 13: Hoare triple {12284#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {12284#true} is VALID [2022-02-21 04:23:02,160 INFO L290 TraceCheckUtils]: 14: Hoare triple {12284#true} assume !(0 == ~T4_E~0); {12284#true} is VALID [2022-02-21 04:23:02,160 INFO L290 TraceCheckUtils]: 15: Hoare triple {12284#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {12284#true} is VALID [2022-02-21 04:23:02,160 INFO L290 TraceCheckUtils]: 16: Hoare triple {12284#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,160 INFO L290 TraceCheckUtils]: 17: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,161 INFO L290 TraceCheckUtils]: 18: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,161 INFO L290 TraceCheckUtils]: 19: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,161 INFO L290 TraceCheckUtils]: 20: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,161 INFO L290 TraceCheckUtils]: 21: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,162 INFO L290 TraceCheckUtils]: 22: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,162 INFO L290 TraceCheckUtils]: 23: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,162 INFO L290 TraceCheckUtils]: 24: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,162 INFO L290 TraceCheckUtils]: 25: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,163 INFO L290 TraceCheckUtils]: 26: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,163 INFO L290 TraceCheckUtils]: 27: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,163 INFO L290 TraceCheckUtils]: 28: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,163 INFO L290 TraceCheckUtils]: 29: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,164 INFO L290 TraceCheckUtils]: 30: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,164 INFO L290 TraceCheckUtils]: 31: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,164 INFO L290 TraceCheckUtils]: 32: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,164 INFO L290 TraceCheckUtils]: 33: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,165 INFO L290 TraceCheckUtils]: 34: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,165 INFO L290 TraceCheckUtils]: 35: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,165 INFO L290 TraceCheckUtils]: 36: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,165 INFO L290 TraceCheckUtils]: 37: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,166 INFO L290 TraceCheckUtils]: 38: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,166 INFO L290 TraceCheckUtils]: 39: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,166 INFO L290 TraceCheckUtils]: 40: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,166 INFO L290 TraceCheckUtils]: 41: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,167 INFO L290 TraceCheckUtils]: 42: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,167 INFO L290 TraceCheckUtils]: 43: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,167 INFO L290 TraceCheckUtils]: 44: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,167 INFO L290 TraceCheckUtils]: 45: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,168 INFO L290 TraceCheckUtils]: 46: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,168 INFO L290 TraceCheckUtils]: 47: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,168 INFO L290 TraceCheckUtils]: 48: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,168 INFO L290 TraceCheckUtils]: 49: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,169 INFO L290 TraceCheckUtils]: 50: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,169 INFO L290 TraceCheckUtils]: 51: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,169 INFO L290 TraceCheckUtils]: 52: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,169 INFO L290 TraceCheckUtils]: 53: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,170 INFO L290 TraceCheckUtils]: 54: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,170 INFO L290 TraceCheckUtils]: 55: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,170 INFO L290 TraceCheckUtils]: 56: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,170 INFO L290 TraceCheckUtils]: 57: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,171 INFO L290 TraceCheckUtils]: 58: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,171 INFO L290 TraceCheckUtils]: 59: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,171 INFO L290 TraceCheckUtils]: 60: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,171 INFO L290 TraceCheckUtils]: 61: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,172 INFO L290 TraceCheckUtils]: 62: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,172 INFO L290 TraceCheckUtils]: 63: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,172 INFO L290 TraceCheckUtils]: 64: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,172 INFO L290 TraceCheckUtils]: 65: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,173 INFO L290 TraceCheckUtils]: 66: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,173 INFO L290 TraceCheckUtils]: 67: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,173 INFO L290 TraceCheckUtils]: 68: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,174 INFO L290 TraceCheckUtils]: 69: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,174 INFO L290 TraceCheckUtils]: 70: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,174 INFO L290 TraceCheckUtils]: 71: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,174 INFO L290 TraceCheckUtils]: 72: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,175 INFO L290 TraceCheckUtils]: 73: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,175 INFO L290 TraceCheckUtils]: 74: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,175 INFO L290 TraceCheckUtils]: 75: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,175 INFO L290 TraceCheckUtils]: 76: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,176 INFO L290 TraceCheckUtils]: 77: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,176 INFO L290 TraceCheckUtils]: 78: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,176 INFO L290 TraceCheckUtils]: 79: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,176 INFO L290 TraceCheckUtils]: 80: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,177 INFO L290 TraceCheckUtils]: 81: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,177 INFO L290 TraceCheckUtils]: 82: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,177 INFO L290 TraceCheckUtils]: 83: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,177 INFO L290 TraceCheckUtils]: 84: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,178 INFO L290 TraceCheckUtils]: 85: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,178 INFO L290 TraceCheckUtils]: 86: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,178 INFO L290 TraceCheckUtils]: 87: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,178 INFO L290 TraceCheckUtils]: 88: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,179 INFO L290 TraceCheckUtils]: 89: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,179 INFO L290 TraceCheckUtils]: 90: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,179 INFO L290 TraceCheckUtils]: 91: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,179 INFO L290 TraceCheckUtils]: 92: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,180 INFO L290 TraceCheckUtils]: 93: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,180 INFO L290 TraceCheckUtils]: 94: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,180 INFO L290 TraceCheckUtils]: 95: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,180 INFO L290 TraceCheckUtils]: 96: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,181 INFO L290 TraceCheckUtils]: 97: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,181 INFO L290 TraceCheckUtils]: 98: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,181 INFO L290 TraceCheckUtils]: 99: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,181 INFO L290 TraceCheckUtils]: 100: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,182 INFO L290 TraceCheckUtils]: 101: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,182 INFO L290 TraceCheckUtils]: 102: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,182 INFO L290 TraceCheckUtils]: 103: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,182 INFO L290 TraceCheckUtils]: 104: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {12286#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 105: Hoare triple {12286#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {12285#false} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 106: Hoare triple {12285#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 107: Hoare triple {12285#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 108: Hoare triple {12285#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 109: Hoare triple {12285#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 110: Hoare triple {12285#false} assume 1 == ~E_M~0;~E_M~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 111: Hoare triple {12285#false} assume 1 == ~E_1~0;~E_1~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,183 INFO L290 TraceCheckUtils]: 112: Hoare triple {12285#false} assume 1 == ~E_2~0;~E_2~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 113: Hoare triple {12285#false} assume !(1 == ~E_3~0); {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 114: Hoare triple {12285#false} assume 1 == ~E_4~0;~E_4~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 115: Hoare triple {12285#false} assume 1 == ~E_5~0;~E_5~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 116: Hoare triple {12285#false} assume 1 == ~E_6~0;~E_6~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 117: Hoare triple {12285#false} assume 1 == ~E_7~0;~E_7~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 118: Hoare triple {12285#false} assume 1 == ~E_8~0;~E_8~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 119: Hoare triple {12285#false} assume 1 == ~E_9~0;~E_9~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 120: Hoare triple {12285#false} assume 1 == ~E_10~0;~E_10~0 := 2; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 121: Hoare triple {12285#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {12285#false} is VALID [2022-02-21 04:23:02,184 INFO L290 TraceCheckUtils]: 122: Hoare triple {12285#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 123: Hoare triple {12285#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 124: Hoare triple {12285#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 125: Hoare triple {12285#false} assume !(0 == start_simulation_~tmp~3#1); {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 126: Hoare triple {12285#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 127: Hoare triple {12285#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 128: Hoare triple {12285#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 129: Hoare triple {12285#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 130: Hoare triple {12285#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {12285#false} is VALID [2022-02-21 04:23:02,185 INFO L290 TraceCheckUtils]: 131: Hoare triple {12285#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {12285#false} is VALID [2022-02-21 04:23:02,186 INFO L290 TraceCheckUtils]: 132: Hoare triple {12285#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {12285#false} is VALID [2022-02-21 04:23:02,186 INFO L290 TraceCheckUtils]: 133: Hoare triple {12285#false} assume !(0 != start_simulation_~tmp___0~1#1); {12285#false} is VALID [2022-02-21 04:23:02,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:02,186 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:02,186 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608488511] [2022-02-21 04:23:02,187 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608488511] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:02,187 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:02,187 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:02,187 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057432717] [2022-02-21 04:23:02,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:02,187 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:02,188 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:02,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:02,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:02,188 INFO L87 Difference]: Start difference. First operand 1361 states and 2022 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:03,137 INFO L93 Difference]: Finished difference Result 1361 states and 2021 transitions. [2022-02-21 04:23:03,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:03,137 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,234 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:03,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:03,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2021 transitions. [2022-02-21 04:23:03,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:03,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:03,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:03,323 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-02-21 04:23:03,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:03,335 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:03,337 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2021 transitions. Second operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,339 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2021 transitions. Second operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,341 INFO L87 Difference]: Start difference. First operand 1361 states and 2021 transitions. Second operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:03,382 INFO L93 Difference]: Finished difference Result 1361 states and 2021 transitions. [2022-02-21 04:23:03,382 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,384 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:03,384 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:03,387 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,389 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:03,431 INFO L93 Difference]: Finished difference Result 1361 states and 2021 transitions. [2022-02-21 04:23:03,431 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,432 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:03,433 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:03,433 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:03,433 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:03,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2021 transitions. [2022-02-21 04:23:03,478 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-02-21 04:23:03,478 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-02-21 04:23:03,478 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:03,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2021 transitions. [2022-02-21 04:23:03,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:03,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:03,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:03,484 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:03,484 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:03,484 INFO L791 eck$LassoCheckResult]: Stem: 14656#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 13697#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13698#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14586#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14289#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14290#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14568#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14724#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14454#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14455#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14344#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14345#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14684#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14646#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14573#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14574#L1024 assume !(0 == ~M_E~0); 14820#L1024-2 assume !(0 == ~T1_E~0); 14024#L1029-1 assume !(0 == ~T2_E~0); 14025#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14131#L1039-1 assume !(0 == ~T4_E~0); 14937#L1044-1 assume !(0 == ~T5_E~0); 14366#L1049-1 assume !(0 == ~T6_E~0); 14367#L1054-1 assume !(0 == ~T7_E~0); 14594#L1059-1 assume !(0 == ~T8_E~0); 14071#L1064-1 assume !(0 == ~T9_E~0); 14072#L1069-1 assume !(0 == ~T10_E~0); 14788#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14854#L1079-1 assume !(0 == ~E_1~0); 14822#L1084-1 assume !(0 == ~E_2~0); 14823#L1089-1 assume !(0 == ~E_3~0); 14873#L1094-1 assume !(0 == ~E_4~0); 14444#L1099-1 assume !(0 == ~E_5~0); 14445#L1104-1 assume !(0 == ~E_6~0); 14702#L1109-1 assume !(0 == ~E_7~0); 14245#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14246#L1119-1 assume !(0 == ~E_9~0); 14300#L1124-1 assume !(0 == ~E_10~0); 13730#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13731#L502 assume 1 == ~m_pc~0; 14592#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13859#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13860#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14641#L1273 assume !(0 != activate_threads_~tmp~1#1); 14642#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14972#L521 assume !(1 == ~t1_pc~0); 14905#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13790#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13791#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13933#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13772#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13773#L540 assume 1 == ~t2_pc~0; 14836#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14557#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14839#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14852#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 14899#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14046#L559 assume 1 == ~t3_pc~0; 14047#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14325#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14326#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14469#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13877#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13878#L578 assume !(1 == ~t4_pc~0); 13996#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13995#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13766#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13767#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14624#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14625#L597 assume 1 == ~t5_pc~0; 14987#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13811#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13812#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14412#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14575#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14576#L616 assume !(1 == ~t6_pc~0); 14590#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14589#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14954#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14499#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14436#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14437#L635 assume 1 == ~t7_pc~0; 14629#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13780#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14151#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14797#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14569#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14570#L654 assume !(1 == ~t8_pc~0); 14392#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14393#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14900#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14785#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14786#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14022#L673 assume 1 == ~t9_pc~0; 14023#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13721#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14969#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14755#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14711#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14712#L692 assume !(1 == ~t10_pc~0); 14660#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14659#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14578#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14448#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14449#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14766#L1142 assume !(1 == ~M_E~0); 13937#L1142-2 assume !(1 == ~T1_E~0); 13938#L1147-1 assume !(1 == ~T2_E~0); 14756#L1152-1 assume !(1 == ~T3_E~0); 14332#L1157-1 assume !(1 == ~T4_E~0); 14333#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14473#L1167-1 assume !(1 == ~T6_E~0); 14474#L1172-1 assume !(1 == ~T7_E~0); 14893#L1177-1 assume !(1 == ~T8_E~0); 14611#L1182-1 assume !(1 == ~T9_E~0); 14612#L1187-1 assume !(1 == ~T10_E~0); 14705#L1192-1 assume !(1 == ~E_M~0); 14196#L1197-1 assume !(1 == ~E_1~0); 14197#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14560#L1207-1 assume !(1 == ~E_3~0); 14539#L1212-1 assume !(1 == ~E_4~0); 13796#L1217-1 assume !(1 == ~E_5~0); 13797#L1222-1 assume !(1 == ~E_6~0); 14535#L1227-1 assume !(1 == ~E_7~0); 14536#L1232-1 assume !(1 == ~E_8~0); 13662#L1237-1 assume !(1 == ~E_9~0); 13663#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14593#L1247-1 assume { :end_inline_reset_delta_events } true; 13836#L1553-2 [2022-02-21 04:23:03,484 INFO L793 eck$LassoCheckResult]: Loop: 13836#L1553-2 assume !false; 13837#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14746#L999 assume !false; 14792#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13921#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13814#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14309#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14663#L854 assume !(0 != eval_~tmp~0#1); 14664#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14108#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14109#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14926#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14435#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14405#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14406#L1039-3 assume !(0 == ~T4_E~0); 14729#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14016#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14017#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13792#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13793#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14377#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14378#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14707#L1079-3 assume !(0 == ~E_1~0); 14604#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14492#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14493#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14422#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14423#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14727#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14715#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14716#L1119-3 assume !(0 == ~E_9~0); 14996#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15003#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14963#L502-36 assume !(1 == ~m_pc~0); 14163#L502-38 is_master_triggered_~__retres1~0#1 := 0; 13648#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13649#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14073#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14074#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14349#L521-36 assume 1 == ~t1_pc~0; 14350#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14361#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14528#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14565#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14790#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14791#L540-36 assume 1 == ~t2_pc~0; 14965#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13738#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14152#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15004#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14468#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13659#L559-36 assume 1 == ~t3_pc~0; 13660#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14116#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13966#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13967#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14613#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14849#L578-36 assume !(1 == ~t4_pc~0); 14545#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 14546#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14879#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14880#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14383#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14384#L597-36 assume !(1 == ~t5_pc~0); 14602#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 14952#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14526#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14527#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 14198#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14199#L616-36 assume 1 == ~t6_pc~0; 14966#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13726#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13727#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14329#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14430#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14745#L635-36 assume 1 == ~t7_pc~0; 14929#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14802#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14475#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14476#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14418#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14419#L654-36 assume !(1 == ~t8_pc~0); 14933#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 14934#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15006#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14991#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14973#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14101#L673-36 assume !(1 == ~t9_pc~0); 14102#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14456#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14457#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14809#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13669#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13670#L692-36 assume 1 == ~t10_pc~0; 14605#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13886#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14429#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14064#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14065#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14428#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14577#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14935#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14936#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14506#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14507#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14798#L1167-3 assume !(1 == ~T6_E~0); 14920#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14417#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14321#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14322#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14335#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14160#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14161#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14402#L1207-3 assume !(1 == ~E_3~0); 14517#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14725#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14056#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13753#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13754#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14830#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14831#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15005#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14883#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13905#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13906#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14585#L1572 assume !(0 == start_simulation_~tmp~3#1); 14203#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14354#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13683#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14957#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 14958#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13652#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13653#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14807#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13836#L1553-2 [2022-02-21 04:23:03,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:03,485 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2022-02-21 04:23:03,485 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:03,485 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862326038] [2022-02-21 04:23:03,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:03,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:03,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:03,509 INFO L290 TraceCheckUtils]: 0: Hoare triple {17734#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {17734#true} is VALID [2022-02-21 04:23:03,509 INFO L290 TraceCheckUtils]: 1: Hoare triple {17734#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {17736#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:03,510 INFO L290 TraceCheckUtils]: 2: Hoare triple {17736#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17736#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:03,510 INFO L290 TraceCheckUtils]: 3: Hoare triple {17736#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17736#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:03,510 INFO L290 TraceCheckUtils]: 4: Hoare triple {17736#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {17736#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:03,510 INFO L290 TraceCheckUtils]: 5: Hoare triple {17736#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17736#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:03,511 INFO L290 TraceCheckUtils]: 6: Hoare triple {17736#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17736#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:03,511 INFO L290 TraceCheckUtils]: 7: Hoare triple {17736#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {17736#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:03,511 INFO L290 TraceCheckUtils]: 8: Hoare triple {17736#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,511 INFO L290 TraceCheckUtils]: 9: Hoare triple {17735#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,511 INFO L290 TraceCheckUtils]: 10: Hoare triple {17735#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 11: Hoare triple {17735#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 12: Hoare triple {17735#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 13: Hoare triple {17735#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 14: Hoare triple {17735#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 15: Hoare triple {17735#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 16: Hoare triple {17735#false} assume !(0 == ~M_E~0); {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 17: Hoare triple {17735#false} assume !(0 == ~T1_E~0); {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 18: Hoare triple {17735#false} assume !(0 == ~T2_E~0); {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 19: Hoare triple {17735#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17735#false} is VALID [2022-02-21 04:23:03,512 INFO L290 TraceCheckUtils]: 20: Hoare triple {17735#false} assume !(0 == ~T4_E~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 21: Hoare triple {17735#false} assume !(0 == ~T5_E~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 22: Hoare triple {17735#false} assume !(0 == ~T6_E~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 23: Hoare triple {17735#false} assume !(0 == ~T7_E~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 24: Hoare triple {17735#false} assume !(0 == ~T8_E~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 25: Hoare triple {17735#false} assume !(0 == ~T9_E~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 26: Hoare triple {17735#false} assume !(0 == ~T10_E~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 27: Hoare triple {17735#false} assume 0 == ~E_M~0;~E_M~0 := 1; {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 28: Hoare triple {17735#false} assume !(0 == ~E_1~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 29: Hoare triple {17735#false} assume !(0 == ~E_2~0); {17735#false} is VALID [2022-02-21 04:23:03,513 INFO L290 TraceCheckUtils]: 30: Hoare triple {17735#false} assume !(0 == ~E_3~0); {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 31: Hoare triple {17735#false} assume !(0 == ~E_4~0); {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 32: Hoare triple {17735#false} assume !(0 == ~E_5~0); {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 33: Hoare triple {17735#false} assume !(0 == ~E_6~0); {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 34: Hoare triple {17735#false} assume !(0 == ~E_7~0); {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 35: Hoare triple {17735#false} assume 0 == ~E_8~0;~E_8~0 := 1; {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 36: Hoare triple {17735#false} assume !(0 == ~E_9~0); {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 37: Hoare triple {17735#false} assume !(0 == ~E_10~0); {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 38: Hoare triple {17735#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17735#false} is VALID [2022-02-21 04:23:03,514 INFO L290 TraceCheckUtils]: 39: Hoare triple {17735#false} assume 1 == ~m_pc~0; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 40: Hoare triple {17735#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 41: Hoare triple {17735#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 42: Hoare triple {17735#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 43: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp~1#1); {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 44: Hoare triple {17735#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 45: Hoare triple {17735#false} assume !(1 == ~t1_pc~0); {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 46: Hoare triple {17735#false} is_transmit1_triggered_~__retres1~1#1 := 0; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 47: Hoare triple {17735#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 48: Hoare triple {17735#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17735#false} is VALID [2022-02-21 04:23:03,515 INFO L290 TraceCheckUtils]: 49: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___0~0#1); {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 50: Hoare triple {17735#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 51: Hoare triple {17735#false} assume 1 == ~t2_pc~0; {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 52: Hoare triple {17735#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 53: Hoare triple {17735#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 54: Hoare triple {17735#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 55: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___1~0#1); {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 56: Hoare triple {17735#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 57: Hoare triple {17735#false} assume 1 == ~t3_pc~0; {17735#false} is VALID [2022-02-21 04:23:03,516 INFO L290 TraceCheckUtils]: 58: Hoare triple {17735#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 59: Hoare triple {17735#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 60: Hoare triple {17735#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 61: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___2~0#1); {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 62: Hoare triple {17735#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 63: Hoare triple {17735#false} assume !(1 == ~t4_pc~0); {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 64: Hoare triple {17735#false} is_transmit4_triggered_~__retres1~4#1 := 0; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 65: Hoare triple {17735#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 66: Hoare triple {17735#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 67: Hoare triple {17735#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17735#false} is VALID [2022-02-21 04:23:03,517 INFO L290 TraceCheckUtils]: 68: Hoare triple {17735#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 69: Hoare triple {17735#false} assume 1 == ~t5_pc~0; {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 70: Hoare triple {17735#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 71: Hoare triple {17735#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 72: Hoare triple {17735#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 73: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___4~0#1); {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 74: Hoare triple {17735#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 75: Hoare triple {17735#false} assume !(1 == ~t6_pc~0); {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 76: Hoare triple {17735#false} is_transmit6_triggered_~__retres1~6#1 := 0; {17735#false} is VALID [2022-02-21 04:23:03,518 INFO L290 TraceCheckUtils]: 77: Hoare triple {17735#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 78: Hoare triple {17735#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 79: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___5~0#1); {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 80: Hoare triple {17735#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 81: Hoare triple {17735#false} assume 1 == ~t7_pc~0; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 82: Hoare triple {17735#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 83: Hoare triple {17735#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 84: Hoare triple {17735#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 85: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___6~0#1); {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 86: Hoare triple {17735#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17735#false} is VALID [2022-02-21 04:23:03,519 INFO L290 TraceCheckUtils]: 87: Hoare triple {17735#false} assume !(1 == ~t8_pc~0); {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 88: Hoare triple {17735#false} is_transmit8_triggered_~__retres1~8#1 := 0; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 89: Hoare triple {17735#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 90: Hoare triple {17735#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 91: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___7~0#1); {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 92: Hoare triple {17735#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 93: Hoare triple {17735#false} assume 1 == ~t9_pc~0; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 94: Hoare triple {17735#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 95: Hoare triple {17735#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 96: Hoare triple {17735#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17735#false} is VALID [2022-02-21 04:23:03,520 INFO L290 TraceCheckUtils]: 97: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___8~0#1); {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 98: Hoare triple {17735#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 99: Hoare triple {17735#false} assume !(1 == ~t10_pc~0); {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 100: Hoare triple {17735#false} is_transmit10_triggered_~__retres1~10#1 := 0; {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 101: Hoare triple {17735#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 102: Hoare triple {17735#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 103: Hoare triple {17735#false} assume !(0 != activate_threads_~tmp___9~0#1); {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 104: Hoare triple {17735#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 105: Hoare triple {17735#false} assume !(1 == ~M_E~0); {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 106: Hoare triple {17735#false} assume !(1 == ~T1_E~0); {17735#false} is VALID [2022-02-21 04:23:03,521 INFO L290 TraceCheckUtils]: 107: Hoare triple {17735#false} assume !(1 == ~T2_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 108: Hoare triple {17735#false} assume !(1 == ~T3_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 109: Hoare triple {17735#false} assume !(1 == ~T4_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 110: Hoare triple {17735#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 111: Hoare triple {17735#false} assume !(1 == ~T6_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 112: Hoare triple {17735#false} assume !(1 == ~T7_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 113: Hoare triple {17735#false} assume !(1 == ~T8_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 114: Hoare triple {17735#false} assume !(1 == ~T9_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 115: Hoare triple {17735#false} assume !(1 == ~T10_E~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 116: Hoare triple {17735#false} assume !(1 == ~E_M~0); {17735#false} is VALID [2022-02-21 04:23:03,522 INFO L290 TraceCheckUtils]: 117: Hoare triple {17735#false} assume !(1 == ~E_1~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 118: Hoare triple {17735#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 119: Hoare triple {17735#false} assume !(1 == ~E_3~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 120: Hoare triple {17735#false} assume !(1 == ~E_4~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 121: Hoare triple {17735#false} assume !(1 == ~E_5~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 122: Hoare triple {17735#false} assume !(1 == ~E_6~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 123: Hoare triple {17735#false} assume !(1 == ~E_7~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 124: Hoare triple {17735#false} assume !(1 == ~E_8~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 125: Hoare triple {17735#false} assume !(1 == ~E_9~0); {17735#false} is VALID [2022-02-21 04:23:03,523 INFO L290 TraceCheckUtils]: 126: Hoare triple {17735#false} assume 1 == ~E_10~0;~E_10~0 := 2; {17735#false} is VALID [2022-02-21 04:23:03,524 INFO L290 TraceCheckUtils]: 127: Hoare triple {17735#false} assume { :end_inline_reset_delta_events } true; {17735#false} is VALID [2022-02-21 04:23:03,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:03,524 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:03,524 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862326038] [2022-02-21 04:23:03,524 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862326038] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:03,525 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:03,525 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:03,525 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717495302] [2022-02-21 04:23:03,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:03,525 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:03,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:03,526 INFO L85 PathProgramCache]: Analyzing trace with hash -679343498, now seen corresponding path program 1 times [2022-02-21 04:23:03,526 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:03,526 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880478156] [2022-02-21 04:23:03,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:03,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:03,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:03,593 INFO L290 TraceCheckUtils]: 0: Hoare triple {17737#true} assume !false; {17737#true} is VALID [2022-02-21 04:23:03,593 INFO L290 TraceCheckUtils]: 1: Hoare triple {17737#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17737#true} is VALID [2022-02-21 04:23:03,593 INFO L290 TraceCheckUtils]: 2: Hoare triple {17737#true} assume !false; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 3: Hoare triple {17737#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 4: Hoare triple {17737#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 5: Hoare triple {17737#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 6: Hoare triple {17737#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 7: Hoare triple {17737#true} assume !(0 != eval_~tmp~0#1); {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 8: Hoare triple {17737#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 9: Hoare triple {17737#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 10: Hoare triple {17737#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17737#true} is VALID [2022-02-21 04:23:03,594 INFO L290 TraceCheckUtils]: 11: Hoare triple {17737#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {17737#true} is VALID [2022-02-21 04:23:03,595 INFO L290 TraceCheckUtils]: 12: Hoare triple {17737#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17737#true} is VALID [2022-02-21 04:23:03,595 INFO L290 TraceCheckUtils]: 13: Hoare triple {17737#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17737#true} is VALID [2022-02-21 04:23:03,595 INFO L290 TraceCheckUtils]: 14: Hoare triple {17737#true} assume !(0 == ~T4_E~0); {17737#true} is VALID [2022-02-21 04:23:03,595 INFO L290 TraceCheckUtils]: 15: Hoare triple {17737#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17737#true} is VALID [2022-02-21 04:23:03,595 INFO L290 TraceCheckUtils]: 16: Hoare triple {17737#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,596 INFO L290 TraceCheckUtils]: 17: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,596 INFO L290 TraceCheckUtils]: 18: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,596 INFO L290 TraceCheckUtils]: 19: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,596 INFO L290 TraceCheckUtils]: 20: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,597 INFO L290 TraceCheckUtils]: 21: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,597 INFO L290 TraceCheckUtils]: 22: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,597 INFO L290 TraceCheckUtils]: 23: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,598 INFO L290 TraceCheckUtils]: 24: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,598 INFO L290 TraceCheckUtils]: 25: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,598 INFO L290 TraceCheckUtils]: 26: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,598 INFO L290 TraceCheckUtils]: 27: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,599 INFO L290 TraceCheckUtils]: 28: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,599 INFO L290 TraceCheckUtils]: 29: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,599 INFO L290 TraceCheckUtils]: 30: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,599 INFO L290 TraceCheckUtils]: 31: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,600 INFO L290 TraceCheckUtils]: 32: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,600 INFO L290 TraceCheckUtils]: 33: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,600 INFO L290 TraceCheckUtils]: 34: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,601 INFO L290 TraceCheckUtils]: 35: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,601 INFO L290 TraceCheckUtils]: 36: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,601 INFO L290 TraceCheckUtils]: 37: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,601 INFO L290 TraceCheckUtils]: 38: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,602 INFO L290 TraceCheckUtils]: 39: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,602 INFO L290 TraceCheckUtils]: 40: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,602 INFO L290 TraceCheckUtils]: 41: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,602 INFO L290 TraceCheckUtils]: 42: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,603 INFO L290 TraceCheckUtils]: 43: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,603 INFO L290 TraceCheckUtils]: 44: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,603 INFO L290 TraceCheckUtils]: 45: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,604 INFO L290 TraceCheckUtils]: 46: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,604 INFO L290 TraceCheckUtils]: 47: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,604 INFO L290 TraceCheckUtils]: 48: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,604 INFO L290 TraceCheckUtils]: 49: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,605 INFO L290 TraceCheckUtils]: 50: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,605 INFO L290 TraceCheckUtils]: 51: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,605 INFO L290 TraceCheckUtils]: 52: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,605 INFO L290 TraceCheckUtils]: 53: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,606 INFO L290 TraceCheckUtils]: 54: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,606 INFO L290 TraceCheckUtils]: 55: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,606 INFO L290 TraceCheckUtils]: 56: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,607 INFO L290 TraceCheckUtils]: 57: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,607 INFO L290 TraceCheckUtils]: 58: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,607 INFO L290 TraceCheckUtils]: 59: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,607 INFO L290 TraceCheckUtils]: 60: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,608 INFO L290 TraceCheckUtils]: 61: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,608 INFO L290 TraceCheckUtils]: 62: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,608 INFO L290 TraceCheckUtils]: 63: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,608 INFO L290 TraceCheckUtils]: 64: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,609 INFO L290 TraceCheckUtils]: 65: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,609 INFO L290 TraceCheckUtils]: 66: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,609 INFO L290 TraceCheckUtils]: 67: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,610 INFO L290 TraceCheckUtils]: 68: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,610 INFO L290 TraceCheckUtils]: 69: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,610 INFO L290 TraceCheckUtils]: 70: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,610 INFO L290 TraceCheckUtils]: 71: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,611 INFO L290 TraceCheckUtils]: 72: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,611 INFO L290 TraceCheckUtils]: 73: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,611 INFO L290 TraceCheckUtils]: 74: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,611 INFO L290 TraceCheckUtils]: 75: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,612 INFO L290 TraceCheckUtils]: 76: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,612 INFO L290 TraceCheckUtils]: 77: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,612 INFO L290 TraceCheckUtils]: 78: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,613 INFO L290 TraceCheckUtils]: 79: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,613 INFO L290 TraceCheckUtils]: 80: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,613 INFO L290 TraceCheckUtils]: 81: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,613 INFO L290 TraceCheckUtils]: 82: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,614 INFO L290 TraceCheckUtils]: 83: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,614 INFO L290 TraceCheckUtils]: 84: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,614 INFO L290 TraceCheckUtils]: 85: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,614 INFO L290 TraceCheckUtils]: 86: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,615 INFO L290 TraceCheckUtils]: 87: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,615 INFO L290 TraceCheckUtils]: 88: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,615 INFO L290 TraceCheckUtils]: 89: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,616 INFO L290 TraceCheckUtils]: 90: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,616 INFO L290 TraceCheckUtils]: 91: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,616 INFO L290 TraceCheckUtils]: 92: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,616 INFO L290 TraceCheckUtils]: 93: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,617 INFO L290 TraceCheckUtils]: 94: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,617 INFO L290 TraceCheckUtils]: 95: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,617 INFO L290 TraceCheckUtils]: 96: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,617 INFO L290 TraceCheckUtils]: 97: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,618 INFO L290 TraceCheckUtils]: 98: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,618 INFO L290 TraceCheckUtils]: 99: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,618 INFO L290 TraceCheckUtils]: 100: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,619 INFO L290 TraceCheckUtils]: 101: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,619 INFO L290 TraceCheckUtils]: 102: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,619 INFO L290 TraceCheckUtils]: 103: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,619 INFO L290 TraceCheckUtils]: 104: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17739#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 105: Hoare triple {17739#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {17738#false} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 106: Hoare triple {17738#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 107: Hoare triple {17738#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 108: Hoare triple {17738#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 109: Hoare triple {17738#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 110: Hoare triple {17738#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 111: Hoare triple {17738#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,620 INFO L290 TraceCheckUtils]: 112: Hoare triple {17738#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 113: Hoare triple {17738#false} assume !(1 == ~E_3~0); {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 114: Hoare triple {17738#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 115: Hoare triple {17738#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 116: Hoare triple {17738#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 117: Hoare triple {17738#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 118: Hoare triple {17738#false} assume 1 == ~E_8~0;~E_8~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 119: Hoare triple {17738#false} assume 1 == ~E_9~0;~E_9~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 120: Hoare triple {17738#false} assume 1 == ~E_10~0;~E_10~0 := 2; {17738#false} is VALID [2022-02-21 04:23:03,621 INFO L290 TraceCheckUtils]: 121: Hoare triple {17738#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 122: Hoare triple {17738#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 123: Hoare triple {17738#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 124: Hoare triple {17738#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 125: Hoare triple {17738#false} assume !(0 == start_simulation_~tmp~3#1); {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 126: Hoare triple {17738#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 127: Hoare triple {17738#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 128: Hoare triple {17738#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 129: Hoare triple {17738#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 130: Hoare triple {17738#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17738#false} is VALID [2022-02-21 04:23:03,622 INFO L290 TraceCheckUtils]: 131: Hoare triple {17738#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17738#false} is VALID [2022-02-21 04:23:03,623 INFO L290 TraceCheckUtils]: 132: Hoare triple {17738#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {17738#false} is VALID [2022-02-21 04:23:03,623 INFO L290 TraceCheckUtils]: 133: Hoare triple {17738#false} assume !(0 != start_simulation_~tmp___0~1#1); {17738#false} is VALID [2022-02-21 04:23:03,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:03,623 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:03,624 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880478156] [2022-02-21 04:23:03,624 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880478156] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:03,624 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:03,624 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:03,624 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893846841] [2022-02-21 04:23:03,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:03,625 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:03,625 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:03,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:03,625 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:03,626 INFO L87 Difference]: Start difference. First operand 1361 states and 2021 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,626 INFO L93 Difference]: Finished difference Result 1361 states and 2020 transitions. [2022-02-21 04:23:04,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:04,627 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,699 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:04,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:04,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2020 transitions. [2022-02-21 04:23:04,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:04,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:04,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:04,818 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-02-21 04:23:04,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:04,830 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:04,831 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2020 transitions. Second operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,833 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2020 transitions. Second operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,834 INFO L87 Difference]: Start difference. First operand 1361 states and 2020 transitions. Second operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,874 INFO L93 Difference]: Finished difference Result 1361 states and 2020 transitions. [2022-02-21 04:23:04,874 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,876 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,876 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,878 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,880 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,919 INFO L93 Difference]: Finished difference Result 1361 states and 2020 transitions. [2022-02-21 04:23:04,919 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,921 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,921 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,921 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:04,921 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:04,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2020 transitions. [2022-02-21 04:23:04,963 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-02-21 04:23:04,963 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-02-21 04:23:04,963 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:04,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2020 transitions. [2022-02-21 04:23:04,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:04,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:04,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:04,969 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,969 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,969 INFO L791 eck$LassoCheckResult]: Stem: 20109#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 20110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19150#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19151#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20039#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19743#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19744#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20021#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20177#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19909#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19910#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19799#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19800#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20137#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20099#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20027#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20028#L1024 assume !(0 == ~M_E~0); 20273#L1024-2 assume !(0 == ~T1_E~0); 19477#L1029-1 assume !(0 == ~T2_E~0); 19478#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19584#L1039-1 assume !(0 == ~T4_E~0); 20390#L1044-1 assume !(0 == ~T5_E~0); 19821#L1049-1 assume !(0 == ~T6_E~0); 19822#L1054-1 assume !(0 == ~T7_E~0); 20047#L1059-1 assume !(0 == ~T8_E~0); 19524#L1064-1 assume !(0 == ~T9_E~0); 19525#L1069-1 assume !(0 == ~T10_E~0); 20241#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20307#L1079-1 assume !(0 == ~E_1~0); 20275#L1084-1 assume !(0 == ~E_2~0); 20276#L1089-1 assume !(0 == ~E_3~0); 20326#L1094-1 assume !(0 == ~E_4~0); 19897#L1099-1 assume !(0 == ~E_5~0); 19898#L1104-1 assume !(0 == ~E_6~0); 20155#L1109-1 assume !(0 == ~E_7~0); 19698#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19699#L1119-1 assume !(0 == ~E_9~0); 19755#L1124-1 assume !(0 == ~E_10~0); 19183#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19184#L502 assume 1 == ~m_pc~0; 20045#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19312#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19313#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20095#L1273 assume !(0 != activate_threads_~tmp~1#1); 20096#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20425#L521 assume !(1 == ~t1_pc~0); 20358#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19243#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19244#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19387#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19227#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19228#L540 assume 1 == ~t2_pc~0; 20289#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20010#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20292#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20305#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20352#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19499#L559 assume 1 == ~t3_pc~0; 19500#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19779#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19780#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19922#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19330#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19331#L578 assume !(1 == ~t4_pc~0); 19451#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19450#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19219#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19220#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20079#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20080#L597 assume 1 == ~t5_pc~0; 20442#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19264#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19265#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19870#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20029#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20030#L616 assume !(1 == ~t6_pc~0); 20044#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20043#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20407#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19952#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 19889#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19890#L635 assume 1 == ~t7_pc~0; 20084#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19233#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19604#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20250#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20022#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20023#L654 assume !(1 == ~t8_pc~0); 19845#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19846#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20353#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20238#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20239#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19475#L673 assume 1 == ~t9_pc~0; 19476#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19174#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20422#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20208#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20164#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20165#L692 assume !(1 == ~t10_pc~0); 20113#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20112#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20031#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19901#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 19902#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20219#L1142 assume !(1 == ~M_E~0); 19390#L1142-2 assume !(1 == ~T1_E~0); 19391#L1147-1 assume !(1 == ~T2_E~0); 20209#L1152-1 assume !(1 == ~T3_E~0); 19785#L1157-1 assume !(1 == ~T4_E~0); 19786#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19926#L1167-1 assume !(1 == ~T6_E~0); 19927#L1172-1 assume !(1 == ~T7_E~0); 20346#L1177-1 assume !(1 == ~T8_E~0); 20064#L1182-1 assume !(1 == ~T9_E~0); 20065#L1187-1 assume !(1 == ~T10_E~0); 20158#L1192-1 assume !(1 == ~E_M~0); 19651#L1197-1 assume !(1 == ~E_1~0); 19652#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20013#L1207-1 assume !(1 == ~E_3~0); 19992#L1212-1 assume !(1 == ~E_4~0); 19249#L1217-1 assume !(1 == ~E_5~0); 19250#L1222-1 assume !(1 == ~E_6~0); 19988#L1227-1 assume !(1 == ~E_7~0); 19989#L1232-1 assume !(1 == ~E_8~0); 19115#L1237-1 assume !(1 == ~E_9~0); 19116#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20046#L1247-1 assume { :end_inline_reset_delta_events } true; 19289#L1553-2 [2022-02-21 04:23:04,969 INFO L793 eck$LassoCheckResult]: Loop: 19289#L1553-2 assume !false; 19290#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20199#L999 assume !false; 20247#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19374#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19267#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19762#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20116#L854 assume !(0 != eval_~tmp~0#1); 20117#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19561#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19562#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20379#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19888#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19858#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19859#L1039-3 assume !(0 == ~T4_E~0); 20182#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19469#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19470#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19245#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19246#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19830#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19831#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20160#L1079-3 assume !(0 == ~E_1~0); 20058#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19945#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19946#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19875#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19876#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20180#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20168#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20169#L1119-3 assume !(0 == ~E_9~0); 20449#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20456#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20416#L502-36 assume !(1 == ~m_pc~0); 19616#L502-38 is_master_triggered_~__retres1~0#1 := 0; 19101#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19102#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19526#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19527#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19804#L521-36 assume 1 == ~t1_pc~0; 19805#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19814#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19981#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20018#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20243#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20244#L540-36 assume 1 == ~t2_pc~0; 20418#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19193#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19605#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20457#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19920#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19109#L559-36 assume 1 == ~t3_pc~0; 19110#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19563#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19419#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19420#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20066#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20302#L578-36 assume 1 == ~t4_pc~0; 20037#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19996#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20332#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20333#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19834#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19835#L597-36 assume !(1 == ~t5_pc~0); 20052#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20405#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19979#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19980#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 19649#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19650#L616-36 assume 1 == ~t6_pc~0; 20419#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19179#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19180#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19782#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19883#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20198#L635-36 assume 1 == ~t7_pc~0; 20382#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20255#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19928#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19929#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19871#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19872#L654-36 assume !(1 == ~t8_pc~0); 20386#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 20387#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20459#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20444#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20426#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19554#L673-36 assume !(1 == ~t9_pc~0); 19555#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19907#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19908#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20262#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19122#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19123#L692-36 assume 1 == ~t10_pc~0; 20057#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19339#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19882#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19517#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19518#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19881#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20026#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20388#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20389#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19959#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19960#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20251#L1167-3 assume !(1 == ~T6_E~0); 20373#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19869#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19774#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19775#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19788#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19613#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19614#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19855#L1207-3 assume !(1 == ~E_3~0); 19970#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20178#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19508#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19206#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19207#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20282#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20283#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20458#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20336#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19358#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19359#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 20038#L1572 assume !(0 == start_simulation_~tmp~3#1); 19654#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19807#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19136#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20410#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 20411#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19105#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19106#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20260#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19289#L1553-2 [2022-02-21 04:23:04,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,970 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2022-02-21 04:23:04,970 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,970 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129351077] [2022-02-21 04:23:04,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,003 INFO L290 TraceCheckUtils]: 0: Hoare triple {23187#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {23187#true} is VALID [2022-02-21 04:23:05,004 INFO L290 TraceCheckUtils]: 1: Hoare triple {23187#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,004 INFO L290 TraceCheckUtils]: 2: Hoare triple {23189#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,004 INFO L290 TraceCheckUtils]: 3: Hoare triple {23189#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,004 INFO L290 TraceCheckUtils]: 4: Hoare triple {23189#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,005 INFO L290 TraceCheckUtils]: 5: Hoare triple {23189#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,005 INFO L290 TraceCheckUtils]: 6: Hoare triple {23189#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,005 INFO L290 TraceCheckUtils]: 7: Hoare triple {23189#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,005 INFO L290 TraceCheckUtils]: 8: Hoare triple {23189#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {23189#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 9: Hoare triple {23189#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 10: Hoare triple {23188#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 11: Hoare triple {23188#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 12: Hoare triple {23188#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 13: Hoare triple {23188#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 14: Hoare triple {23188#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 15: Hoare triple {23188#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 16: Hoare triple {23188#false} assume !(0 == ~M_E~0); {23188#false} is VALID [2022-02-21 04:23:05,006 INFO L290 TraceCheckUtils]: 17: Hoare triple {23188#false} assume !(0 == ~T1_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 18: Hoare triple {23188#false} assume !(0 == ~T2_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 19: Hoare triple {23188#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 20: Hoare triple {23188#false} assume !(0 == ~T4_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 21: Hoare triple {23188#false} assume !(0 == ~T5_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 22: Hoare triple {23188#false} assume !(0 == ~T6_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 23: Hoare triple {23188#false} assume !(0 == ~T7_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 24: Hoare triple {23188#false} assume !(0 == ~T8_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 25: Hoare triple {23188#false} assume !(0 == ~T9_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 26: Hoare triple {23188#false} assume !(0 == ~T10_E~0); {23188#false} is VALID [2022-02-21 04:23:05,007 INFO L290 TraceCheckUtils]: 27: Hoare triple {23188#false} assume 0 == ~E_M~0;~E_M~0 := 1; {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 28: Hoare triple {23188#false} assume !(0 == ~E_1~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 29: Hoare triple {23188#false} assume !(0 == ~E_2~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 30: Hoare triple {23188#false} assume !(0 == ~E_3~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 31: Hoare triple {23188#false} assume !(0 == ~E_4~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 32: Hoare triple {23188#false} assume !(0 == ~E_5~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 33: Hoare triple {23188#false} assume !(0 == ~E_6~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 34: Hoare triple {23188#false} assume !(0 == ~E_7~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 35: Hoare triple {23188#false} assume 0 == ~E_8~0;~E_8~0 := 1; {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 36: Hoare triple {23188#false} assume !(0 == ~E_9~0); {23188#false} is VALID [2022-02-21 04:23:05,008 INFO L290 TraceCheckUtils]: 37: Hoare triple {23188#false} assume !(0 == ~E_10~0); {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 38: Hoare triple {23188#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 39: Hoare triple {23188#false} assume 1 == ~m_pc~0; {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 40: Hoare triple {23188#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 41: Hoare triple {23188#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 42: Hoare triple {23188#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 43: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp~1#1); {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 44: Hoare triple {23188#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 45: Hoare triple {23188#false} assume !(1 == ~t1_pc~0); {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 46: Hoare triple {23188#false} is_transmit1_triggered_~__retres1~1#1 := 0; {23188#false} is VALID [2022-02-21 04:23:05,009 INFO L290 TraceCheckUtils]: 47: Hoare triple {23188#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 48: Hoare triple {23188#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 49: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___0~0#1); {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 50: Hoare triple {23188#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 51: Hoare triple {23188#false} assume 1 == ~t2_pc~0; {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 52: Hoare triple {23188#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 53: Hoare triple {23188#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 54: Hoare triple {23188#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 55: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___1~0#1); {23188#false} is VALID [2022-02-21 04:23:05,010 INFO L290 TraceCheckUtils]: 56: Hoare triple {23188#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 57: Hoare triple {23188#false} assume 1 == ~t3_pc~0; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 58: Hoare triple {23188#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 59: Hoare triple {23188#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 60: Hoare triple {23188#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 61: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___2~0#1); {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 62: Hoare triple {23188#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 63: Hoare triple {23188#false} assume !(1 == ~t4_pc~0); {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 64: Hoare triple {23188#false} is_transmit4_triggered_~__retres1~4#1 := 0; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 65: Hoare triple {23188#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23188#false} is VALID [2022-02-21 04:23:05,011 INFO L290 TraceCheckUtils]: 66: Hoare triple {23188#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 67: Hoare triple {23188#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 68: Hoare triple {23188#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 69: Hoare triple {23188#false} assume 1 == ~t5_pc~0; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 70: Hoare triple {23188#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 71: Hoare triple {23188#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 72: Hoare triple {23188#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 73: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___4~0#1); {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 74: Hoare triple {23188#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 75: Hoare triple {23188#false} assume !(1 == ~t6_pc~0); {23188#false} is VALID [2022-02-21 04:23:05,012 INFO L290 TraceCheckUtils]: 76: Hoare triple {23188#false} is_transmit6_triggered_~__retres1~6#1 := 0; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 77: Hoare triple {23188#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 78: Hoare triple {23188#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 79: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___5~0#1); {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 80: Hoare triple {23188#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 81: Hoare triple {23188#false} assume 1 == ~t7_pc~0; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 82: Hoare triple {23188#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 83: Hoare triple {23188#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 84: Hoare triple {23188#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 85: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___6~0#1); {23188#false} is VALID [2022-02-21 04:23:05,013 INFO L290 TraceCheckUtils]: 86: Hoare triple {23188#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 87: Hoare triple {23188#false} assume !(1 == ~t8_pc~0); {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 88: Hoare triple {23188#false} is_transmit8_triggered_~__retres1~8#1 := 0; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 89: Hoare triple {23188#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 90: Hoare triple {23188#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 91: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___7~0#1); {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 92: Hoare triple {23188#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 93: Hoare triple {23188#false} assume 1 == ~t9_pc~0; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 94: Hoare triple {23188#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 95: Hoare triple {23188#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23188#false} is VALID [2022-02-21 04:23:05,014 INFO L290 TraceCheckUtils]: 96: Hoare triple {23188#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 97: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___8~0#1); {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 98: Hoare triple {23188#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 99: Hoare triple {23188#false} assume !(1 == ~t10_pc~0); {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 100: Hoare triple {23188#false} is_transmit10_triggered_~__retres1~10#1 := 0; {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 101: Hoare triple {23188#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 102: Hoare triple {23188#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 103: Hoare triple {23188#false} assume !(0 != activate_threads_~tmp___9~0#1); {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 104: Hoare triple {23188#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 105: Hoare triple {23188#false} assume !(1 == ~M_E~0); {23188#false} is VALID [2022-02-21 04:23:05,015 INFO L290 TraceCheckUtils]: 106: Hoare triple {23188#false} assume !(1 == ~T1_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 107: Hoare triple {23188#false} assume !(1 == ~T2_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 108: Hoare triple {23188#false} assume !(1 == ~T3_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 109: Hoare triple {23188#false} assume !(1 == ~T4_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 110: Hoare triple {23188#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 111: Hoare triple {23188#false} assume !(1 == ~T6_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 112: Hoare triple {23188#false} assume !(1 == ~T7_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 113: Hoare triple {23188#false} assume !(1 == ~T8_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 114: Hoare triple {23188#false} assume !(1 == ~T9_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 115: Hoare triple {23188#false} assume !(1 == ~T10_E~0); {23188#false} is VALID [2022-02-21 04:23:05,016 INFO L290 TraceCheckUtils]: 116: Hoare triple {23188#false} assume !(1 == ~E_M~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 117: Hoare triple {23188#false} assume !(1 == ~E_1~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 118: Hoare triple {23188#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 119: Hoare triple {23188#false} assume !(1 == ~E_3~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 120: Hoare triple {23188#false} assume !(1 == ~E_4~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 121: Hoare triple {23188#false} assume !(1 == ~E_5~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 122: Hoare triple {23188#false} assume !(1 == ~E_6~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 123: Hoare triple {23188#false} assume !(1 == ~E_7~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 124: Hoare triple {23188#false} assume !(1 == ~E_8~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 125: Hoare triple {23188#false} assume !(1 == ~E_9~0); {23188#false} is VALID [2022-02-21 04:23:05,017 INFO L290 TraceCheckUtils]: 126: Hoare triple {23188#false} assume 1 == ~E_10~0;~E_10~0 := 2; {23188#false} is VALID [2022-02-21 04:23:05,018 INFO L290 TraceCheckUtils]: 127: Hoare triple {23188#false} assume { :end_inline_reset_delta_events } true; {23188#false} is VALID [2022-02-21 04:23:05,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:05,018 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:05,018 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129351077] [2022-02-21 04:23:05,018 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129351077] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:05,019 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:05,019 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:05,019 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278691070] [2022-02-21 04:23:05,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:05,019 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:05,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:05,020 INFO L85 PathProgramCache]: Analyzing trace with hash 1162970293, now seen corresponding path program 1 times [2022-02-21 04:23:05,020 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:05,020 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556828932] [2022-02-21 04:23:05,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:05,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:05,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,053 INFO L290 TraceCheckUtils]: 0: Hoare triple {23190#true} assume !false; {23190#true} is VALID [2022-02-21 04:23:05,053 INFO L290 TraceCheckUtils]: 1: Hoare triple {23190#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {23190#true} is VALID [2022-02-21 04:23:05,053 INFO L290 TraceCheckUtils]: 2: Hoare triple {23190#true} assume !false; {23190#true} is VALID [2022-02-21 04:23:05,053 INFO L290 TraceCheckUtils]: 3: Hoare triple {23190#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 4: Hoare triple {23190#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 5: Hoare triple {23190#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 6: Hoare triple {23190#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 7: Hoare triple {23190#true} assume !(0 != eval_~tmp~0#1); {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 8: Hoare triple {23190#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 9: Hoare triple {23190#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 10: Hoare triple {23190#true} assume 0 == ~M_E~0;~M_E~0 := 1; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 11: Hoare triple {23190#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 12: Hoare triple {23190#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {23190#true} is VALID [2022-02-21 04:23:05,054 INFO L290 TraceCheckUtils]: 13: Hoare triple {23190#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23190#true} is VALID [2022-02-21 04:23:05,055 INFO L290 TraceCheckUtils]: 14: Hoare triple {23190#true} assume !(0 == ~T4_E~0); {23190#true} is VALID [2022-02-21 04:23:05,055 INFO L290 TraceCheckUtils]: 15: Hoare triple {23190#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {23190#true} is VALID [2022-02-21 04:23:05,055 INFO L290 TraceCheckUtils]: 16: Hoare triple {23190#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,055 INFO L290 TraceCheckUtils]: 17: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,056 INFO L290 TraceCheckUtils]: 18: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,056 INFO L290 TraceCheckUtils]: 19: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,056 INFO L290 TraceCheckUtils]: 20: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,056 INFO L290 TraceCheckUtils]: 21: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,057 INFO L290 TraceCheckUtils]: 22: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,057 INFO L290 TraceCheckUtils]: 23: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,057 INFO L290 TraceCheckUtils]: 24: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,057 INFO L290 TraceCheckUtils]: 25: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,058 INFO L290 TraceCheckUtils]: 26: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,058 INFO L290 TraceCheckUtils]: 27: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,058 INFO L290 TraceCheckUtils]: 28: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,059 INFO L290 TraceCheckUtils]: 29: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,059 INFO L290 TraceCheckUtils]: 30: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,059 INFO L290 TraceCheckUtils]: 31: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,059 INFO L290 TraceCheckUtils]: 32: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,060 INFO L290 TraceCheckUtils]: 33: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,060 INFO L290 TraceCheckUtils]: 34: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,060 INFO L290 TraceCheckUtils]: 35: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,060 INFO L290 TraceCheckUtils]: 36: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,061 INFO L290 TraceCheckUtils]: 37: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,061 INFO L290 TraceCheckUtils]: 38: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,061 INFO L290 TraceCheckUtils]: 39: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,062 INFO L290 TraceCheckUtils]: 40: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,062 INFO L290 TraceCheckUtils]: 41: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,062 INFO L290 TraceCheckUtils]: 42: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,062 INFO L290 TraceCheckUtils]: 43: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,063 INFO L290 TraceCheckUtils]: 44: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,063 INFO L290 TraceCheckUtils]: 45: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,063 INFO L290 TraceCheckUtils]: 46: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,063 INFO L290 TraceCheckUtils]: 47: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,064 INFO L290 TraceCheckUtils]: 48: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,064 INFO L290 TraceCheckUtils]: 49: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,064 INFO L290 TraceCheckUtils]: 50: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,065 INFO L290 TraceCheckUtils]: 51: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,065 INFO L290 TraceCheckUtils]: 52: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,065 INFO L290 TraceCheckUtils]: 53: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,065 INFO L290 TraceCheckUtils]: 54: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,066 INFO L290 TraceCheckUtils]: 55: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,066 INFO L290 TraceCheckUtils]: 56: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,069 INFO L290 TraceCheckUtils]: 57: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,069 INFO L290 TraceCheckUtils]: 58: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,070 INFO L290 TraceCheckUtils]: 59: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,070 INFO L290 TraceCheckUtils]: 60: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,070 INFO L290 TraceCheckUtils]: 61: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,071 INFO L290 TraceCheckUtils]: 62: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,071 INFO L290 TraceCheckUtils]: 63: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,071 INFO L290 TraceCheckUtils]: 64: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,071 INFO L290 TraceCheckUtils]: 65: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,072 INFO L290 TraceCheckUtils]: 66: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,072 INFO L290 TraceCheckUtils]: 67: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,072 INFO L290 TraceCheckUtils]: 68: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,072 INFO L290 TraceCheckUtils]: 69: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,073 INFO L290 TraceCheckUtils]: 70: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,073 INFO L290 TraceCheckUtils]: 71: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,073 INFO L290 TraceCheckUtils]: 72: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,074 INFO L290 TraceCheckUtils]: 73: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,074 INFO L290 TraceCheckUtils]: 74: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,074 INFO L290 TraceCheckUtils]: 75: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,074 INFO L290 TraceCheckUtils]: 76: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,075 INFO L290 TraceCheckUtils]: 77: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,075 INFO L290 TraceCheckUtils]: 78: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,075 INFO L290 TraceCheckUtils]: 79: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,076 INFO L290 TraceCheckUtils]: 80: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,076 INFO L290 TraceCheckUtils]: 81: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,076 INFO L290 TraceCheckUtils]: 82: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,076 INFO L290 TraceCheckUtils]: 83: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,077 INFO L290 TraceCheckUtils]: 84: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,077 INFO L290 TraceCheckUtils]: 85: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,077 INFO L290 TraceCheckUtils]: 86: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,078 INFO L290 TraceCheckUtils]: 87: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,078 INFO L290 TraceCheckUtils]: 88: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,078 INFO L290 TraceCheckUtils]: 89: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,078 INFO L290 TraceCheckUtils]: 90: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,079 INFO L290 TraceCheckUtils]: 91: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,079 INFO L290 TraceCheckUtils]: 92: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,079 INFO L290 TraceCheckUtils]: 93: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,079 INFO L290 TraceCheckUtils]: 94: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,080 INFO L290 TraceCheckUtils]: 95: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,080 INFO L290 TraceCheckUtils]: 96: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,080 INFO L290 TraceCheckUtils]: 97: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,081 INFO L290 TraceCheckUtils]: 98: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,081 INFO L290 TraceCheckUtils]: 99: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,081 INFO L290 TraceCheckUtils]: 100: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,081 INFO L290 TraceCheckUtils]: 101: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,082 INFO L290 TraceCheckUtils]: 102: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,082 INFO L290 TraceCheckUtils]: 103: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,082 INFO L290 TraceCheckUtils]: 104: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23192#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 105: Hoare triple {23192#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 106: Hoare triple {23191#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 107: Hoare triple {23191#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 108: Hoare triple {23191#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 109: Hoare triple {23191#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 110: Hoare triple {23191#false} assume 1 == ~E_M~0;~E_M~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 111: Hoare triple {23191#false} assume 1 == ~E_1~0;~E_1~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 112: Hoare triple {23191#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 113: Hoare triple {23191#false} assume !(1 == ~E_3~0); {23191#false} is VALID [2022-02-21 04:23:05,083 INFO L290 TraceCheckUtils]: 114: Hoare triple {23191#false} assume 1 == ~E_4~0;~E_4~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 115: Hoare triple {23191#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 116: Hoare triple {23191#false} assume 1 == ~E_6~0;~E_6~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 117: Hoare triple {23191#false} assume 1 == ~E_7~0;~E_7~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 118: Hoare triple {23191#false} assume 1 == ~E_8~0;~E_8~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 119: Hoare triple {23191#false} assume 1 == ~E_9~0;~E_9~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 120: Hoare triple {23191#false} assume 1 == ~E_10~0;~E_10~0 := 2; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 121: Hoare triple {23191#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 122: Hoare triple {23191#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {23191#false} is VALID [2022-02-21 04:23:05,084 INFO L290 TraceCheckUtils]: 123: Hoare triple {23191#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 124: Hoare triple {23191#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 125: Hoare triple {23191#false} assume !(0 == start_simulation_~tmp~3#1); {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 126: Hoare triple {23191#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 127: Hoare triple {23191#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 128: Hoare triple {23191#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 129: Hoare triple {23191#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 130: Hoare triple {23191#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 131: Hoare triple {23191#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 132: Hoare triple {23191#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {23191#false} is VALID [2022-02-21 04:23:05,085 INFO L290 TraceCheckUtils]: 133: Hoare triple {23191#false} assume !(0 != start_simulation_~tmp___0~1#1); {23191#false} is VALID [2022-02-21 04:23:05,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:05,086 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:05,086 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556828932] [2022-02-21 04:23:05,086 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556828932] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:05,086 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:05,086 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:05,087 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931654634] [2022-02-21 04:23:05,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:05,087 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:05,087 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:05,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:05,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:05,088 INFO L87 Difference]: Start difference. First operand 1361 states and 2020 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:06,220 INFO L93 Difference]: Finished difference Result 1361 states and 2019 transitions. [2022-02-21 04:23:06,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:06,220 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,282 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:06,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:06,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2019 transitions. [2022-02-21 04:23:06,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:06,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:06,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:06,371 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-02-21 04:23:06,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:06,382 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:06,384 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2019 transitions. Second operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,385 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2019 transitions. Second operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,386 INFO L87 Difference]: Start difference. First operand 1361 states and 2019 transitions. Second operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:06,424 INFO L93 Difference]: Finished difference Result 1361 states and 2019 transitions. [2022-02-21 04:23:06,425 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,426 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:06,426 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:06,428 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,429 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:06,468 INFO L93 Difference]: Finished difference Result 1361 states and 2019 transitions. [2022-02-21 04:23:06,468 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,470 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:06,470 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:06,470 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:06,470 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:06,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2019 transitions. [2022-02-21 04:23:06,511 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-02-21 04:23:06,511 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-02-21 04:23:06,511 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:06,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2019 transitions. [2022-02-21 04:23:06,515 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:06,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:06,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:06,517 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:06,517 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:06,517 INFO L791 eck$LassoCheckResult]: Stem: 25562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24603#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24604#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25492#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25195#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25196#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25474#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25630#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25360#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25361#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25250#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25251#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25590#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25552#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25479#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25480#L1024 assume !(0 == ~M_E~0); 25726#L1024-2 assume !(0 == ~T1_E~0); 24930#L1029-1 assume !(0 == ~T2_E~0); 24931#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25037#L1039-1 assume !(0 == ~T4_E~0); 25843#L1044-1 assume !(0 == ~T5_E~0); 25272#L1049-1 assume !(0 == ~T6_E~0); 25273#L1054-1 assume !(0 == ~T7_E~0); 25500#L1059-1 assume !(0 == ~T8_E~0); 24977#L1064-1 assume !(0 == ~T9_E~0); 24978#L1069-1 assume !(0 == ~T10_E~0); 25694#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25760#L1079-1 assume !(0 == ~E_1~0); 25728#L1084-1 assume !(0 == ~E_2~0); 25729#L1089-1 assume !(0 == ~E_3~0); 25779#L1094-1 assume !(0 == ~E_4~0); 25350#L1099-1 assume !(0 == ~E_5~0); 25351#L1104-1 assume !(0 == ~E_6~0); 25608#L1109-1 assume !(0 == ~E_7~0); 25151#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25152#L1119-1 assume !(0 == ~E_9~0); 25206#L1124-1 assume !(0 == ~E_10~0); 24636#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24637#L502 assume 1 == ~m_pc~0; 25498#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24765#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24766#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25547#L1273 assume !(0 != activate_threads_~tmp~1#1); 25548#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25878#L521 assume !(1 == ~t1_pc~0); 25811#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24696#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24697#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24839#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24678#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24679#L540 assume 1 == ~t2_pc~0; 25742#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25463#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25745#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25758#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 25805#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24952#L559 assume 1 == ~t3_pc~0; 24953#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25231#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25232#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25375#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24783#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24784#L578 assume !(1 == ~t4_pc~0); 24902#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24901#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24672#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24673#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25530#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25531#L597 assume 1 == ~t5_pc~0; 25893#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24717#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24718#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25318#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25481#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25482#L616 assume !(1 == ~t6_pc~0); 25496#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25495#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25860#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25405#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25342#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25343#L635 assume 1 == ~t7_pc~0; 25535#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24686#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25057#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25703#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25475#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25476#L654 assume !(1 == ~t8_pc~0); 25298#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25299#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25806#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25691#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25692#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24928#L673 assume 1 == ~t9_pc~0; 24929#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24627#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25875#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25661#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25617#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25618#L692 assume !(1 == ~t10_pc~0); 25566#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25565#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25484#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25354#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25355#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25672#L1142 assume !(1 == ~M_E~0); 24843#L1142-2 assume !(1 == ~T1_E~0); 24844#L1147-1 assume !(1 == ~T2_E~0); 25662#L1152-1 assume !(1 == ~T3_E~0); 25238#L1157-1 assume !(1 == ~T4_E~0); 25239#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25379#L1167-1 assume !(1 == ~T6_E~0); 25380#L1172-1 assume !(1 == ~T7_E~0); 25799#L1177-1 assume !(1 == ~T8_E~0); 25517#L1182-1 assume !(1 == ~T9_E~0); 25518#L1187-1 assume !(1 == ~T10_E~0); 25611#L1192-1 assume !(1 == ~E_M~0); 25102#L1197-1 assume !(1 == ~E_1~0); 25103#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25466#L1207-1 assume !(1 == ~E_3~0); 25445#L1212-1 assume !(1 == ~E_4~0); 24702#L1217-1 assume !(1 == ~E_5~0); 24703#L1222-1 assume !(1 == ~E_6~0); 25441#L1227-1 assume !(1 == ~E_7~0); 25442#L1232-1 assume !(1 == ~E_8~0); 24568#L1237-1 assume !(1 == ~E_9~0); 24569#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25499#L1247-1 assume { :end_inline_reset_delta_events } true; 24742#L1553-2 [2022-02-21 04:23:06,517 INFO L793 eck$LassoCheckResult]: Loop: 24742#L1553-2 assume !false; 24743#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25652#L999 assume !false; 25698#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24827#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24720#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25215#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25569#L854 assume !(0 != eval_~tmp~0#1); 25570#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25014#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25015#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25832#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25341#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25311#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25312#L1039-3 assume !(0 == ~T4_E~0); 25635#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24922#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24923#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24698#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24699#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25283#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25284#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25613#L1079-3 assume !(0 == ~E_1~0); 25510#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25398#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25399#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25328#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25329#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25633#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25621#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25622#L1119-3 assume !(0 == ~E_9~0); 25902#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25909#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25869#L502-36 assume 1 == ~m_pc~0; 25636#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24554#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24555#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24979#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24980#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25255#L521-36 assume 1 == ~t1_pc~0; 25256#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25267#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25434#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25471#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25696#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25697#L540-36 assume !(1 == ~t2_pc~0); 24643#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 24644#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25058#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25910#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25374#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24565#L559-36 assume 1 == ~t3_pc~0; 24566#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25022#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24872#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24873#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25519#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25755#L578-36 assume 1 == ~t4_pc~0; 25490#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25452#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25785#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25786#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25289#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25290#L597-36 assume !(1 == ~t5_pc~0); 25508#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 25858#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25432#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25433#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 25104#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25105#L616-36 assume 1 == ~t6_pc~0; 25872#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24632#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24633#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25235#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25336#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25651#L635-36 assume 1 == ~t7_pc~0; 25835#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25708#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25381#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25382#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25324#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25325#L654-36 assume 1 == ~t8_pc~0; 25905#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25840#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25912#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25897#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25879#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25007#L673-36 assume !(1 == ~t9_pc~0); 25008#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25362#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25363#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25715#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24575#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24576#L692-36 assume 1 == ~t10_pc~0; 25511#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24792#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25335#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24970#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24971#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25334#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25483#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25841#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25842#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25412#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25413#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25704#L1167-3 assume !(1 == ~T6_E~0); 25826#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25323#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25227#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25228#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25241#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25066#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25067#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25308#L1207-3 assume !(1 == ~E_3~0); 25423#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25631#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24962#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24659#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24660#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25736#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25737#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25911#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25789#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24811#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24812#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25491#L1572 assume !(0 == start_simulation_~tmp~3#1); 25109#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25260#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24589#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25863#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 25864#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24558#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24559#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25713#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24742#L1553-2 [2022-02-21 04:23:06,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:06,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2022-02-21 04:23:06,518 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:06,518 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31302712] [2022-02-21 04:23:06,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:06,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:06,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:06,545 INFO L290 TraceCheckUtils]: 0: Hoare triple {28640#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {28640#true} is VALID [2022-02-21 04:23:06,545 INFO L290 TraceCheckUtils]: 1: Hoare triple {28640#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,546 INFO L290 TraceCheckUtils]: 2: Hoare triple {28642#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,546 INFO L290 TraceCheckUtils]: 3: Hoare triple {28642#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,546 INFO L290 TraceCheckUtils]: 4: Hoare triple {28642#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,546 INFO L290 TraceCheckUtils]: 5: Hoare triple {28642#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,547 INFO L290 TraceCheckUtils]: 6: Hoare triple {28642#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,547 INFO L290 TraceCheckUtils]: 7: Hoare triple {28642#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,547 INFO L290 TraceCheckUtils]: 8: Hoare triple {28642#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 9: Hoare triple {28642#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {28642#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 10: Hoare triple {28642#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {28641#false} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 11: Hoare triple {28641#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {28641#false} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 12: Hoare triple {28641#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {28641#false} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 13: Hoare triple {28641#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {28641#false} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 14: Hoare triple {28641#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {28641#false} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 15: Hoare triple {28641#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {28641#false} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 16: Hoare triple {28641#false} assume !(0 == ~M_E~0); {28641#false} is VALID [2022-02-21 04:23:06,548 INFO L290 TraceCheckUtils]: 17: Hoare triple {28641#false} assume !(0 == ~T1_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 18: Hoare triple {28641#false} assume !(0 == ~T2_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 19: Hoare triple {28641#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 20: Hoare triple {28641#false} assume !(0 == ~T4_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 21: Hoare triple {28641#false} assume !(0 == ~T5_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 22: Hoare triple {28641#false} assume !(0 == ~T6_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 23: Hoare triple {28641#false} assume !(0 == ~T7_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 24: Hoare triple {28641#false} assume !(0 == ~T8_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 25: Hoare triple {28641#false} assume !(0 == ~T9_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 26: Hoare triple {28641#false} assume !(0 == ~T10_E~0); {28641#false} is VALID [2022-02-21 04:23:06,549 INFO L290 TraceCheckUtils]: 27: Hoare triple {28641#false} assume 0 == ~E_M~0;~E_M~0 := 1; {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 28: Hoare triple {28641#false} assume !(0 == ~E_1~0); {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 29: Hoare triple {28641#false} assume !(0 == ~E_2~0); {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 30: Hoare triple {28641#false} assume !(0 == ~E_3~0); {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 31: Hoare triple {28641#false} assume !(0 == ~E_4~0); {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 32: Hoare triple {28641#false} assume !(0 == ~E_5~0); {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 33: Hoare triple {28641#false} assume !(0 == ~E_6~0); {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 34: Hoare triple {28641#false} assume !(0 == ~E_7~0); {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 35: Hoare triple {28641#false} assume 0 == ~E_8~0;~E_8~0 := 1; {28641#false} is VALID [2022-02-21 04:23:06,550 INFO L290 TraceCheckUtils]: 36: Hoare triple {28641#false} assume !(0 == ~E_9~0); {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 37: Hoare triple {28641#false} assume !(0 == ~E_10~0); {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 38: Hoare triple {28641#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 39: Hoare triple {28641#false} assume 1 == ~m_pc~0; {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 40: Hoare triple {28641#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 41: Hoare triple {28641#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 42: Hoare triple {28641#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 43: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp~1#1); {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 44: Hoare triple {28641#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 45: Hoare triple {28641#false} assume !(1 == ~t1_pc~0); {28641#false} is VALID [2022-02-21 04:23:06,551 INFO L290 TraceCheckUtils]: 46: Hoare triple {28641#false} is_transmit1_triggered_~__retres1~1#1 := 0; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 47: Hoare triple {28641#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 48: Hoare triple {28641#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 49: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___0~0#1); {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 50: Hoare triple {28641#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 51: Hoare triple {28641#false} assume 1 == ~t2_pc~0; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 52: Hoare triple {28641#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 53: Hoare triple {28641#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 54: Hoare triple {28641#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 55: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___1~0#1); {28641#false} is VALID [2022-02-21 04:23:06,552 INFO L290 TraceCheckUtils]: 56: Hoare triple {28641#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 57: Hoare triple {28641#false} assume 1 == ~t3_pc~0; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 58: Hoare triple {28641#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 59: Hoare triple {28641#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 60: Hoare triple {28641#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 61: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___2~0#1); {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 62: Hoare triple {28641#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 63: Hoare triple {28641#false} assume !(1 == ~t4_pc~0); {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 64: Hoare triple {28641#false} is_transmit4_triggered_~__retres1~4#1 := 0; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 65: Hoare triple {28641#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28641#false} is VALID [2022-02-21 04:23:06,553 INFO L290 TraceCheckUtils]: 66: Hoare triple {28641#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 67: Hoare triple {28641#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 68: Hoare triple {28641#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 69: Hoare triple {28641#false} assume 1 == ~t5_pc~0; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 70: Hoare triple {28641#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 71: Hoare triple {28641#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 72: Hoare triple {28641#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 73: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___4~0#1); {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 74: Hoare triple {28641#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 75: Hoare triple {28641#false} assume !(1 == ~t6_pc~0); {28641#false} is VALID [2022-02-21 04:23:06,554 INFO L290 TraceCheckUtils]: 76: Hoare triple {28641#false} is_transmit6_triggered_~__retres1~6#1 := 0; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 77: Hoare triple {28641#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 78: Hoare triple {28641#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 79: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___5~0#1); {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 80: Hoare triple {28641#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 81: Hoare triple {28641#false} assume 1 == ~t7_pc~0; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 82: Hoare triple {28641#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 83: Hoare triple {28641#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 84: Hoare triple {28641#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 85: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___6~0#1); {28641#false} is VALID [2022-02-21 04:23:06,555 INFO L290 TraceCheckUtils]: 86: Hoare triple {28641#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 87: Hoare triple {28641#false} assume !(1 == ~t8_pc~0); {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 88: Hoare triple {28641#false} is_transmit8_triggered_~__retres1~8#1 := 0; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 89: Hoare triple {28641#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 90: Hoare triple {28641#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 91: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___7~0#1); {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 92: Hoare triple {28641#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 93: Hoare triple {28641#false} assume 1 == ~t9_pc~0; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 94: Hoare triple {28641#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 95: Hoare triple {28641#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {28641#false} is VALID [2022-02-21 04:23:06,556 INFO L290 TraceCheckUtils]: 96: Hoare triple {28641#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 97: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___8~0#1); {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 98: Hoare triple {28641#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 99: Hoare triple {28641#false} assume !(1 == ~t10_pc~0); {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 100: Hoare triple {28641#false} is_transmit10_triggered_~__retres1~10#1 := 0; {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 101: Hoare triple {28641#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 102: Hoare triple {28641#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 103: Hoare triple {28641#false} assume !(0 != activate_threads_~tmp___9~0#1); {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 104: Hoare triple {28641#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28641#false} is VALID [2022-02-21 04:23:06,557 INFO L290 TraceCheckUtils]: 105: Hoare triple {28641#false} assume !(1 == ~M_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 106: Hoare triple {28641#false} assume !(1 == ~T1_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 107: Hoare triple {28641#false} assume !(1 == ~T2_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 108: Hoare triple {28641#false} assume !(1 == ~T3_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 109: Hoare triple {28641#false} assume !(1 == ~T4_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 110: Hoare triple {28641#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 111: Hoare triple {28641#false} assume !(1 == ~T6_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 112: Hoare triple {28641#false} assume !(1 == ~T7_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 113: Hoare triple {28641#false} assume !(1 == ~T8_E~0); {28641#false} is VALID [2022-02-21 04:23:06,558 INFO L290 TraceCheckUtils]: 114: Hoare triple {28641#false} assume !(1 == ~T9_E~0); {28641#false} is VALID [2022-02-21 04:23:06,570 INFO L290 TraceCheckUtils]: 115: Hoare triple {28641#false} assume !(1 == ~T10_E~0); {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 116: Hoare triple {28641#false} assume !(1 == ~E_M~0); {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 117: Hoare triple {28641#false} assume !(1 == ~E_1~0); {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 118: Hoare triple {28641#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 119: Hoare triple {28641#false} assume !(1 == ~E_3~0); {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 120: Hoare triple {28641#false} assume !(1 == ~E_4~0); {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 121: Hoare triple {28641#false} assume !(1 == ~E_5~0); {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 122: Hoare triple {28641#false} assume !(1 == ~E_6~0); {28641#false} is VALID [2022-02-21 04:23:06,581 INFO L290 TraceCheckUtils]: 123: Hoare triple {28641#false} assume !(1 == ~E_7~0); {28641#false} is VALID [2022-02-21 04:23:06,582 INFO L290 TraceCheckUtils]: 124: Hoare triple {28641#false} assume !(1 == ~E_8~0); {28641#false} is VALID [2022-02-21 04:23:06,582 INFO L290 TraceCheckUtils]: 125: Hoare triple {28641#false} assume !(1 == ~E_9~0); {28641#false} is VALID [2022-02-21 04:23:06,582 INFO L290 TraceCheckUtils]: 126: Hoare triple {28641#false} assume 1 == ~E_10~0;~E_10~0 := 2; {28641#false} is VALID [2022-02-21 04:23:06,582 INFO L290 TraceCheckUtils]: 127: Hoare triple {28641#false} assume { :end_inline_reset_delta_events } true; {28641#false} is VALID [2022-02-21 04:23:06,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:06,582 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:06,583 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31302712] [2022-02-21 04:23:06,583 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31302712] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:06,583 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:06,583 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:06,583 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427319512] [2022-02-21 04:23:06,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:06,583 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:06,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:06,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1080059252, now seen corresponding path program 1 times [2022-02-21 04:23:06,584 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:06,584 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312391489] [2022-02-21 04:23:06,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:06,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:06,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:06,613 INFO L290 TraceCheckUtils]: 0: Hoare triple {28643#true} assume !false; {28643#true} is VALID [2022-02-21 04:23:06,614 INFO L290 TraceCheckUtils]: 1: Hoare triple {28643#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {28643#true} is VALID [2022-02-21 04:23:06,614 INFO L290 TraceCheckUtils]: 2: Hoare triple {28643#true} assume !false; {28643#true} is VALID [2022-02-21 04:23:06,614 INFO L290 TraceCheckUtils]: 3: Hoare triple {28643#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {28643#true} is VALID [2022-02-21 04:23:06,614 INFO L290 TraceCheckUtils]: 4: Hoare triple {28643#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {28643#true} is VALID [2022-02-21 04:23:06,614 INFO L290 TraceCheckUtils]: 5: Hoare triple {28643#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {28643#true} is VALID [2022-02-21 04:23:06,614 INFO L290 TraceCheckUtils]: 6: Hoare triple {28643#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {28643#true} is VALID [2022-02-21 04:23:06,614 INFO L290 TraceCheckUtils]: 7: Hoare triple {28643#true} assume !(0 != eval_~tmp~0#1); {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 8: Hoare triple {28643#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 9: Hoare triple {28643#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 10: Hoare triple {28643#true} assume 0 == ~M_E~0;~M_E~0 := 1; {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 11: Hoare triple {28643#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 12: Hoare triple {28643#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 13: Hoare triple {28643#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 14: Hoare triple {28643#true} assume !(0 == ~T4_E~0); {28643#true} is VALID [2022-02-21 04:23:06,615 INFO L290 TraceCheckUtils]: 15: Hoare triple {28643#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {28643#true} is VALID [2022-02-21 04:23:06,616 INFO L290 TraceCheckUtils]: 16: Hoare triple {28643#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,616 INFO L290 TraceCheckUtils]: 17: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,616 INFO L290 TraceCheckUtils]: 18: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,616 INFO L290 TraceCheckUtils]: 19: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,617 INFO L290 TraceCheckUtils]: 20: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,617 INFO L290 TraceCheckUtils]: 21: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,617 INFO L290 TraceCheckUtils]: 22: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,617 INFO L290 TraceCheckUtils]: 23: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,618 INFO L290 TraceCheckUtils]: 24: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,618 INFO L290 TraceCheckUtils]: 25: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,618 INFO L290 TraceCheckUtils]: 26: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,619 INFO L290 TraceCheckUtils]: 27: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,619 INFO L290 TraceCheckUtils]: 28: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,619 INFO L290 TraceCheckUtils]: 29: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,619 INFO L290 TraceCheckUtils]: 30: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,620 INFO L290 TraceCheckUtils]: 31: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,620 INFO L290 TraceCheckUtils]: 32: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,620 INFO L290 TraceCheckUtils]: 33: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,620 INFO L290 TraceCheckUtils]: 34: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,621 INFO L290 TraceCheckUtils]: 35: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,621 INFO L290 TraceCheckUtils]: 36: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,621 INFO L290 TraceCheckUtils]: 37: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,621 INFO L290 TraceCheckUtils]: 38: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,622 INFO L290 TraceCheckUtils]: 39: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,622 INFO L290 TraceCheckUtils]: 40: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,622 INFO L290 TraceCheckUtils]: 41: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,623 INFO L290 TraceCheckUtils]: 42: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,623 INFO L290 TraceCheckUtils]: 43: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,623 INFO L290 TraceCheckUtils]: 44: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,623 INFO L290 TraceCheckUtils]: 45: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,624 INFO L290 TraceCheckUtils]: 46: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,624 INFO L290 TraceCheckUtils]: 47: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,624 INFO L290 TraceCheckUtils]: 48: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,624 INFO L290 TraceCheckUtils]: 49: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,625 INFO L290 TraceCheckUtils]: 50: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,625 INFO L290 TraceCheckUtils]: 51: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,625 INFO L290 TraceCheckUtils]: 52: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,625 INFO L290 TraceCheckUtils]: 53: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,626 INFO L290 TraceCheckUtils]: 54: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,626 INFO L290 TraceCheckUtils]: 55: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,626 INFO L290 TraceCheckUtils]: 56: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,627 INFO L290 TraceCheckUtils]: 57: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,627 INFO L290 TraceCheckUtils]: 58: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,627 INFO L290 TraceCheckUtils]: 59: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,627 INFO L290 TraceCheckUtils]: 60: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,628 INFO L290 TraceCheckUtils]: 61: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,628 INFO L290 TraceCheckUtils]: 62: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,628 INFO L290 TraceCheckUtils]: 63: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,628 INFO L290 TraceCheckUtils]: 64: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,629 INFO L290 TraceCheckUtils]: 65: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,629 INFO L290 TraceCheckUtils]: 66: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,629 INFO L290 TraceCheckUtils]: 67: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,630 INFO L290 TraceCheckUtils]: 68: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,630 INFO L290 TraceCheckUtils]: 69: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,630 INFO L290 TraceCheckUtils]: 70: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,630 INFO L290 TraceCheckUtils]: 71: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,631 INFO L290 TraceCheckUtils]: 72: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,631 INFO L290 TraceCheckUtils]: 73: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,631 INFO L290 TraceCheckUtils]: 74: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,631 INFO L290 TraceCheckUtils]: 75: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,632 INFO L290 TraceCheckUtils]: 76: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,632 INFO L290 TraceCheckUtils]: 77: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,632 INFO L290 TraceCheckUtils]: 78: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,632 INFO L290 TraceCheckUtils]: 79: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,633 INFO L290 TraceCheckUtils]: 80: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,633 INFO L290 TraceCheckUtils]: 81: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,633 INFO L290 TraceCheckUtils]: 82: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,634 INFO L290 TraceCheckUtils]: 83: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,634 INFO L290 TraceCheckUtils]: 84: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,634 INFO L290 TraceCheckUtils]: 85: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,634 INFO L290 TraceCheckUtils]: 86: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,635 INFO L290 TraceCheckUtils]: 87: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,635 INFO L290 TraceCheckUtils]: 88: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,635 INFO L290 TraceCheckUtils]: 89: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,635 INFO L290 TraceCheckUtils]: 90: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,636 INFO L290 TraceCheckUtils]: 91: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,636 INFO L290 TraceCheckUtils]: 92: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,636 INFO L290 TraceCheckUtils]: 93: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,636 INFO L290 TraceCheckUtils]: 94: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,637 INFO L290 TraceCheckUtils]: 95: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,637 INFO L290 TraceCheckUtils]: 96: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,637 INFO L290 TraceCheckUtils]: 97: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,638 INFO L290 TraceCheckUtils]: 98: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,638 INFO L290 TraceCheckUtils]: 99: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,638 INFO L290 TraceCheckUtils]: 100: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,638 INFO L290 TraceCheckUtils]: 101: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,639 INFO L290 TraceCheckUtils]: 102: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,639 INFO L290 TraceCheckUtils]: 103: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,639 INFO L290 TraceCheckUtils]: 104: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28645#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:06,639 INFO L290 TraceCheckUtils]: 105: Hoare triple {28645#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 106: Hoare triple {28644#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 107: Hoare triple {28644#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 108: Hoare triple {28644#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 109: Hoare triple {28644#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 110: Hoare triple {28644#false} assume 1 == ~E_M~0;~E_M~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 111: Hoare triple {28644#false} assume 1 == ~E_1~0;~E_1~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 112: Hoare triple {28644#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 113: Hoare triple {28644#false} assume !(1 == ~E_3~0); {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 114: Hoare triple {28644#false} assume 1 == ~E_4~0;~E_4~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,640 INFO L290 TraceCheckUtils]: 115: Hoare triple {28644#false} assume 1 == ~E_5~0;~E_5~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 116: Hoare triple {28644#false} assume 1 == ~E_6~0;~E_6~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 117: Hoare triple {28644#false} assume 1 == ~E_7~0;~E_7~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 118: Hoare triple {28644#false} assume 1 == ~E_8~0;~E_8~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 119: Hoare triple {28644#false} assume 1 == ~E_9~0;~E_9~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 120: Hoare triple {28644#false} assume 1 == ~E_10~0;~E_10~0 := 2; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 121: Hoare triple {28644#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 122: Hoare triple {28644#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 123: Hoare triple {28644#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 124: Hoare triple {28644#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {28644#false} is VALID [2022-02-21 04:23:06,641 INFO L290 TraceCheckUtils]: 125: Hoare triple {28644#false} assume !(0 == start_simulation_~tmp~3#1); {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 126: Hoare triple {28644#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 127: Hoare triple {28644#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 128: Hoare triple {28644#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 129: Hoare triple {28644#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 130: Hoare triple {28644#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 131: Hoare triple {28644#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 132: Hoare triple {28644#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {28644#false} is VALID [2022-02-21 04:23:06,642 INFO L290 TraceCheckUtils]: 133: Hoare triple {28644#false} assume !(0 != start_simulation_~tmp___0~1#1); {28644#false} is VALID [2022-02-21 04:23:06,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:06,643 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:06,643 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312391489] [2022-02-21 04:23:06,643 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312391489] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:06,643 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:06,643 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:06,644 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834101675] [2022-02-21 04:23:06,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:06,644 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:06,644 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:06,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:06,645 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:06,645 INFO L87 Difference]: Start difference. First operand 1361 states and 2019 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,517 INFO L93 Difference]: Finished difference Result 1361 states and 2018 transitions. [2022-02-21 04:23:07,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:07,518 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,581 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:07,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:07,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2018 transitions. [2022-02-21 04:23:07,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:07,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:07,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:07,670 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-02-21 04:23:07,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:07,681 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:07,683 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2018 transitions. Second operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,684 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2018 transitions. Second operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,685 INFO L87 Difference]: Start difference. First operand 1361 states and 2018 transitions. Second operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,726 INFO L93 Difference]: Finished difference Result 1361 states and 2018 transitions. [2022-02-21 04:23:07,726 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,728 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,728 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,730 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,731 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,772 INFO L93 Difference]: Finished difference Result 1361 states and 2018 transitions. [2022-02-21 04:23:07,772 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,773 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,773 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,773 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:07,773 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:07,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2018 transitions. [2022-02-21 04:23:07,815 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-02-21 04:23:07,816 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-02-21 04:23:07,816 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:07,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2018 transitions. [2022-02-21 04:23:07,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:07,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:07,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:07,821 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,821 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,821 INFO L791 eck$LassoCheckResult]: Stem: 31015#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 31016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 30056#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30057#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30946#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 30649#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30650#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30927#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31083#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30815#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30816#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30711#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30712#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31043#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31005#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30935#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30936#L1024 assume !(0 == ~M_E~0); 31179#L1024-2 assume !(0 == ~T1_E~0); 30383#L1029-1 assume !(0 == ~T2_E~0); 30384#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30490#L1039-1 assume !(0 == ~T4_E~0); 31297#L1044-1 assume !(0 == ~T5_E~0); 30727#L1049-1 assume !(0 == ~T6_E~0); 30728#L1054-1 assume !(0 == ~T7_E~0); 30953#L1059-1 assume !(0 == ~T8_E~0); 30430#L1064-1 assume !(0 == ~T9_E~0); 30431#L1069-1 assume !(0 == ~T10_E~0); 31147#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 31213#L1079-1 assume !(0 == ~E_1~0); 31181#L1084-1 assume !(0 == ~E_2~0); 31182#L1089-1 assume !(0 == ~E_3~0); 31232#L1094-1 assume !(0 == ~E_4~0); 30803#L1099-1 assume !(0 == ~E_5~0); 30804#L1104-1 assume !(0 == ~E_6~0); 31061#L1109-1 assume !(0 == ~E_7~0); 30604#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 30605#L1119-1 assume !(0 == ~E_9~0); 30659#L1124-1 assume !(0 == ~E_10~0); 30089#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30090#L502 assume 1 == ~m_pc~0; 30951#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30218#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30219#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31000#L1273 assume !(0 != activate_threads_~tmp~1#1); 31001#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31331#L521 assume !(1 == ~t1_pc~0); 31264#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30149#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30150#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30292#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 30131#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30132#L540 assume 1 == ~t2_pc~0; 31195#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30916#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31198#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31211#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 31258#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30405#L559 assume 1 == ~t3_pc~0; 30406#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30684#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30685#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30828#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 30236#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30237#L578 assume !(1 == ~t4_pc~0); 30355#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30354#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30125#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30126#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30983#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30984#L597 assume 1 == ~t5_pc~0; 31346#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30170#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30171#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30771#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 30932#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30933#L616 assume !(1 == ~t6_pc~0); 30949#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30948#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31313#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30858#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 30795#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30796#L635 assume 1 == ~t7_pc~0; 30988#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30139#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30510#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31156#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 30928#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30929#L654 assume !(1 == ~t8_pc~0); 30751#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30752#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31259#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31144#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 31145#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30381#L673 assume 1 == ~t9_pc~0; 30382#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30080#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31328#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31114#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 31070#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31071#L692 assume !(1 == ~t10_pc~0); 31019#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31018#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30937#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30807#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 30808#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31125#L1142 assume !(1 == ~M_E~0); 30296#L1142-2 assume !(1 == ~T1_E~0); 30297#L1147-1 assume !(1 == ~T2_E~0); 31115#L1152-1 assume !(1 == ~T3_E~0); 30691#L1157-1 assume !(1 == ~T4_E~0); 30692#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30832#L1167-1 assume !(1 == ~T6_E~0); 30833#L1172-1 assume !(1 == ~T7_E~0); 31252#L1177-1 assume !(1 == ~T8_E~0); 30970#L1182-1 assume !(1 == ~T9_E~0); 30971#L1187-1 assume !(1 == ~T10_E~0); 31064#L1192-1 assume !(1 == ~E_M~0); 30555#L1197-1 assume !(1 == ~E_1~0); 30556#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30919#L1207-1 assume !(1 == ~E_3~0); 30898#L1212-1 assume !(1 == ~E_4~0); 30155#L1217-1 assume !(1 == ~E_5~0); 30156#L1222-1 assume !(1 == ~E_6~0); 30894#L1227-1 assume !(1 == ~E_7~0); 30895#L1232-1 assume !(1 == ~E_8~0); 30021#L1237-1 assume !(1 == ~E_9~0); 30022#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30952#L1247-1 assume { :end_inline_reset_delta_events } true; 30195#L1553-2 [2022-02-21 04:23:07,822 INFO L793 eck$LassoCheckResult]: Loop: 30195#L1553-2 assume !false; 30196#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31105#L999 assume !false; 31151#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30280#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30173#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30668#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31022#L854 assume !(0 != eval_~tmp~0#1); 31023#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30467#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30468#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31285#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30794#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30764#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30765#L1039-3 assume !(0 == ~T4_E~0); 31088#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30375#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30376#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30151#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30152#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30736#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30737#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31066#L1079-3 assume !(0 == ~E_1~0); 30963#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30851#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30852#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30781#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30782#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31086#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31074#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31075#L1119-3 assume !(0 == ~E_9~0); 31355#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31362#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31322#L502-36 assume 1 == ~m_pc~0; 31089#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30007#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30008#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30432#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30433#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30706#L521-36 assume 1 == ~t1_pc~0; 30707#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30720#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30887#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30924#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31149#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31150#L540-36 assume !(1 == ~t2_pc~0); 30096#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 30097#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30511#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31363#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30827#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30018#L559-36 assume 1 == ~t3_pc~0; 30019#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30475#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30325#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30326#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30972#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31208#L578-36 assume !(1 == ~t4_pc~0); 30904#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 30905#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31238#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31239#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30742#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30743#L597-36 assume !(1 == ~t5_pc~0); 30961#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 31311#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30885#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30886#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 30557#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30558#L616-36 assume !(1 == ~t6_pc~0); 31283#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 30085#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30086#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30688#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30789#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31104#L635-36 assume 1 == ~t7_pc~0; 31288#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31161#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30834#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30835#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30777#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30778#L654-36 assume !(1 == ~t8_pc~0); 31292#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 31293#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31365#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31350#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31332#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30460#L673-36 assume !(1 == ~t9_pc~0); 30461#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30813#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30814#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31168#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30028#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30029#L692-36 assume 1 == ~t10_pc~0; 30964#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30245#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30788#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30423#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30424#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30787#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30934#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31294#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31295#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30865#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30866#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31157#L1167-3 assume !(1 == ~T6_E~0); 31279#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30776#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30680#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30681#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30694#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30519#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30520#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30761#L1207-3 assume !(1 == ~E_3~0); 30876#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31084#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30415#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30112#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30113#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31189#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31190#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 31364#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 31242#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30264#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30265#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 30944#L1572 assume !(0 == start_simulation_~tmp~3#1); 30562#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30713#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30042#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 31316#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 31317#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30011#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30012#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 31166#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 30195#L1553-2 [2022-02-21 04:23:07,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:07,822 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2022-02-21 04:23:07,822 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:07,823 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981352910] [2022-02-21 04:23:07,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:07,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:07,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:07,845 INFO L290 TraceCheckUtils]: 0: Hoare triple {34093#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {34093#true} is VALID [2022-02-21 04:23:07,846 INFO L290 TraceCheckUtils]: 1: Hoare triple {34093#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,846 INFO L290 TraceCheckUtils]: 2: Hoare triple {34095#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,846 INFO L290 TraceCheckUtils]: 3: Hoare triple {34095#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,846 INFO L290 TraceCheckUtils]: 4: Hoare triple {34095#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,847 INFO L290 TraceCheckUtils]: 5: Hoare triple {34095#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,847 INFO L290 TraceCheckUtils]: 6: Hoare triple {34095#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,847 INFO L290 TraceCheckUtils]: 7: Hoare triple {34095#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,848 INFO L290 TraceCheckUtils]: 8: Hoare triple {34095#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,848 INFO L290 TraceCheckUtils]: 9: Hoare triple {34095#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,848 INFO L290 TraceCheckUtils]: 10: Hoare triple {34095#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {34095#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:07,848 INFO L290 TraceCheckUtils]: 11: Hoare triple {34095#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {34094#false} is VALID [2022-02-21 04:23:07,848 INFO L290 TraceCheckUtils]: 12: Hoare triple {34094#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 13: Hoare triple {34094#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 14: Hoare triple {34094#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 15: Hoare triple {34094#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 16: Hoare triple {34094#false} assume !(0 == ~M_E~0); {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 17: Hoare triple {34094#false} assume !(0 == ~T1_E~0); {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 18: Hoare triple {34094#false} assume !(0 == ~T2_E~0); {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 19: Hoare triple {34094#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 20: Hoare triple {34094#false} assume !(0 == ~T4_E~0); {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 21: Hoare triple {34094#false} assume !(0 == ~T5_E~0); {34094#false} is VALID [2022-02-21 04:23:07,849 INFO L290 TraceCheckUtils]: 22: Hoare triple {34094#false} assume !(0 == ~T6_E~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 23: Hoare triple {34094#false} assume !(0 == ~T7_E~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 24: Hoare triple {34094#false} assume !(0 == ~T8_E~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 25: Hoare triple {34094#false} assume !(0 == ~T9_E~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 26: Hoare triple {34094#false} assume !(0 == ~T10_E~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 27: Hoare triple {34094#false} assume 0 == ~E_M~0;~E_M~0 := 1; {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 28: Hoare triple {34094#false} assume !(0 == ~E_1~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 29: Hoare triple {34094#false} assume !(0 == ~E_2~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 30: Hoare triple {34094#false} assume !(0 == ~E_3~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 31: Hoare triple {34094#false} assume !(0 == ~E_4~0); {34094#false} is VALID [2022-02-21 04:23:07,850 INFO L290 TraceCheckUtils]: 32: Hoare triple {34094#false} assume !(0 == ~E_5~0); {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 33: Hoare triple {34094#false} assume !(0 == ~E_6~0); {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 34: Hoare triple {34094#false} assume !(0 == ~E_7~0); {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 35: Hoare triple {34094#false} assume 0 == ~E_8~0;~E_8~0 := 1; {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 36: Hoare triple {34094#false} assume !(0 == ~E_9~0); {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 37: Hoare triple {34094#false} assume !(0 == ~E_10~0); {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 38: Hoare triple {34094#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 39: Hoare triple {34094#false} assume 1 == ~m_pc~0; {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 40: Hoare triple {34094#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34094#false} is VALID [2022-02-21 04:23:07,851 INFO L290 TraceCheckUtils]: 41: Hoare triple {34094#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 42: Hoare triple {34094#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 43: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp~1#1); {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 44: Hoare triple {34094#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 45: Hoare triple {34094#false} assume !(1 == ~t1_pc~0); {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 46: Hoare triple {34094#false} is_transmit1_triggered_~__retres1~1#1 := 0; {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 47: Hoare triple {34094#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 48: Hoare triple {34094#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 49: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___0~0#1); {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 50: Hoare triple {34094#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34094#false} is VALID [2022-02-21 04:23:07,852 INFO L290 TraceCheckUtils]: 51: Hoare triple {34094#false} assume 1 == ~t2_pc~0; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 52: Hoare triple {34094#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 53: Hoare triple {34094#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 54: Hoare triple {34094#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 55: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___1~0#1); {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 56: Hoare triple {34094#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 57: Hoare triple {34094#false} assume 1 == ~t3_pc~0; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 58: Hoare triple {34094#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 59: Hoare triple {34094#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 60: Hoare triple {34094#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34094#false} is VALID [2022-02-21 04:23:07,853 INFO L290 TraceCheckUtils]: 61: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___2~0#1); {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 62: Hoare triple {34094#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 63: Hoare triple {34094#false} assume !(1 == ~t4_pc~0); {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 64: Hoare triple {34094#false} is_transmit4_triggered_~__retres1~4#1 := 0; {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 65: Hoare triple {34094#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 66: Hoare triple {34094#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 67: Hoare triple {34094#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 68: Hoare triple {34094#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 69: Hoare triple {34094#false} assume 1 == ~t5_pc~0; {34094#false} is VALID [2022-02-21 04:23:07,854 INFO L290 TraceCheckUtils]: 70: Hoare triple {34094#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 71: Hoare triple {34094#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 72: Hoare triple {34094#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 73: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___4~0#1); {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 74: Hoare triple {34094#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 75: Hoare triple {34094#false} assume !(1 == ~t6_pc~0); {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 76: Hoare triple {34094#false} is_transmit6_triggered_~__retres1~6#1 := 0; {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 77: Hoare triple {34094#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 78: Hoare triple {34094#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 79: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___5~0#1); {34094#false} is VALID [2022-02-21 04:23:07,855 INFO L290 TraceCheckUtils]: 80: Hoare triple {34094#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 81: Hoare triple {34094#false} assume 1 == ~t7_pc~0; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 82: Hoare triple {34094#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 83: Hoare triple {34094#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 84: Hoare triple {34094#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 85: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___6~0#1); {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 86: Hoare triple {34094#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 87: Hoare triple {34094#false} assume !(1 == ~t8_pc~0); {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 88: Hoare triple {34094#false} is_transmit8_triggered_~__retres1~8#1 := 0; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 89: Hoare triple {34094#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34094#false} is VALID [2022-02-21 04:23:07,856 INFO L290 TraceCheckUtils]: 90: Hoare triple {34094#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 91: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___7~0#1); {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 92: Hoare triple {34094#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 93: Hoare triple {34094#false} assume 1 == ~t9_pc~0; {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 94: Hoare triple {34094#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 95: Hoare triple {34094#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 96: Hoare triple {34094#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 97: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___8~0#1); {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 98: Hoare triple {34094#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 99: Hoare triple {34094#false} assume !(1 == ~t10_pc~0); {34094#false} is VALID [2022-02-21 04:23:07,857 INFO L290 TraceCheckUtils]: 100: Hoare triple {34094#false} is_transmit10_triggered_~__retres1~10#1 := 0; {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 101: Hoare triple {34094#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 102: Hoare triple {34094#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 103: Hoare triple {34094#false} assume !(0 != activate_threads_~tmp___9~0#1); {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 104: Hoare triple {34094#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 105: Hoare triple {34094#false} assume !(1 == ~M_E~0); {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 106: Hoare triple {34094#false} assume !(1 == ~T1_E~0); {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 107: Hoare triple {34094#false} assume !(1 == ~T2_E~0); {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 108: Hoare triple {34094#false} assume !(1 == ~T3_E~0); {34094#false} is VALID [2022-02-21 04:23:07,858 INFO L290 TraceCheckUtils]: 109: Hoare triple {34094#false} assume !(1 == ~T4_E~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 110: Hoare triple {34094#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 111: Hoare triple {34094#false} assume !(1 == ~T6_E~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 112: Hoare triple {34094#false} assume !(1 == ~T7_E~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 113: Hoare triple {34094#false} assume !(1 == ~T8_E~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 114: Hoare triple {34094#false} assume !(1 == ~T9_E~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 115: Hoare triple {34094#false} assume !(1 == ~T10_E~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 116: Hoare triple {34094#false} assume !(1 == ~E_M~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 117: Hoare triple {34094#false} assume !(1 == ~E_1~0); {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 118: Hoare triple {34094#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34094#false} is VALID [2022-02-21 04:23:07,859 INFO L290 TraceCheckUtils]: 119: Hoare triple {34094#false} assume !(1 == ~E_3~0); {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 120: Hoare triple {34094#false} assume !(1 == ~E_4~0); {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 121: Hoare triple {34094#false} assume !(1 == ~E_5~0); {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 122: Hoare triple {34094#false} assume !(1 == ~E_6~0); {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 123: Hoare triple {34094#false} assume !(1 == ~E_7~0); {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 124: Hoare triple {34094#false} assume !(1 == ~E_8~0); {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 125: Hoare triple {34094#false} assume !(1 == ~E_9~0); {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 126: Hoare triple {34094#false} assume 1 == ~E_10~0;~E_10~0 := 2; {34094#false} is VALID [2022-02-21 04:23:07,860 INFO L290 TraceCheckUtils]: 127: Hoare triple {34094#false} assume { :end_inline_reset_delta_events } true; {34094#false} is VALID [2022-02-21 04:23:07,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:07,861 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:07,861 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981352910] [2022-02-21 04:23:07,861 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981352910] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:07,861 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:07,861 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:07,861 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300576621] [2022-02-21 04:23:07,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:07,862 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:07,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:07,862 INFO L85 PathProgramCache]: Analyzing trace with hash -658390217, now seen corresponding path program 1 times [2022-02-21 04:23:07,862 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:07,863 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586849591] [2022-02-21 04:23:07,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:07,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:07,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:07,888 INFO L290 TraceCheckUtils]: 0: Hoare triple {34096#true} assume !false; {34096#true} is VALID [2022-02-21 04:23:07,888 INFO L290 TraceCheckUtils]: 1: Hoare triple {34096#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34096#true} is VALID [2022-02-21 04:23:07,888 INFO L290 TraceCheckUtils]: 2: Hoare triple {34096#true} assume !false; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 3: Hoare triple {34096#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 4: Hoare triple {34096#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 5: Hoare triple {34096#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 6: Hoare triple {34096#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 7: Hoare triple {34096#true} assume !(0 != eval_~tmp~0#1); {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 8: Hoare triple {34096#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 9: Hoare triple {34096#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 10: Hoare triple {34096#true} assume 0 == ~M_E~0;~M_E~0 := 1; {34096#true} is VALID [2022-02-21 04:23:07,889 INFO L290 TraceCheckUtils]: 11: Hoare triple {34096#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34096#true} is VALID [2022-02-21 04:23:07,890 INFO L290 TraceCheckUtils]: 12: Hoare triple {34096#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {34096#true} is VALID [2022-02-21 04:23:07,890 INFO L290 TraceCheckUtils]: 13: Hoare triple {34096#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34096#true} is VALID [2022-02-21 04:23:07,890 INFO L290 TraceCheckUtils]: 14: Hoare triple {34096#true} assume !(0 == ~T4_E~0); {34096#true} is VALID [2022-02-21 04:23:07,890 INFO L290 TraceCheckUtils]: 15: Hoare triple {34096#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34096#true} is VALID [2022-02-21 04:23:07,890 INFO L290 TraceCheckUtils]: 16: Hoare triple {34096#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,890 INFO L290 TraceCheckUtils]: 17: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,891 INFO L290 TraceCheckUtils]: 18: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,891 INFO L290 TraceCheckUtils]: 19: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,891 INFO L290 TraceCheckUtils]: 20: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,892 INFO L290 TraceCheckUtils]: 21: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,892 INFO L290 TraceCheckUtils]: 22: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,892 INFO L290 TraceCheckUtils]: 23: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,892 INFO L290 TraceCheckUtils]: 24: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,893 INFO L290 TraceCheckUtils]: 25: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,893 INFO L290 TraceCheckUtils]: 26: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,893 INFO L290 TraceCheckUtils]: 27: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,893 INFO L290 TraceCheckUtils]: 28: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,894 INFO L290 TraceCheckUtils]: 29: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,894 INFO L290 TraceCheckUtils]: 30: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,894 INFO L290 TraceCheckUtils]: 31: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,894 INFO L290 TraceCheckUtils]: 32: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,895 INFO L290 TraceCheckUtils]: 33: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,895 INFO L290 TraceCheckUtils]: 34: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,895 INFO L290 TraceCheckUtils]: 35: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,896 INFO L290 TraceCheckUtils]: 36: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,896 INFO L290 TraceCheckUtils]: 37: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,896 INFO L290 TraceCheckUtils]: 38: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,896 INFO L290 TraceCheckUtils]: 39: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,897 INFO L290 TraceCheckUtils]: 40: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,897 INFO L290 TraceCheckUtils]: 41: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,897 INFO L290 TraceCheckUtils]: 42: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,897 INFO L290 TraceCheckUtils]: 43: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,898 INFO L290 TraceCheckUtils]: 44: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,898 INFO L290 TraceCheckUtils]: 45: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,898 INFO L290 TraceCheckUtils]: 46: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,899 INFO L290 TraceCheckUtils]: 47: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,899 INFO L290 TraceCheckUtils]: 48: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,899 INFO L290 TraceCheckUtils]: 49: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,899 INFO L290 TraceCheckUtils]: 50: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,900 INFO L290 TraceCheckUtils]: 51: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,900 INFO L290 TraceCheckUtils]: 52: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,900 INFO L290 TraceCheckUtils]: 53: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,900 INFO L290 TraceCheckUtils]: 54: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,901 INFO L290 TraceCheckUtils]: 55: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,901 INFO L290 TraceCheckUtils]: 56: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,901 INFO L290 TraceCheckUtils]: 57: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,902 INFO L290 TraceCheckUtils]: 58: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,902 INFO L290 TraceCheckUtils]: 59: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,902 INFO L290 TraceCheckUtils]: 60: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,902 INFO L290 TraceCheckUtils]: 61: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,903 INFO L290 TraceCheckUtils]: 62: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,903 INFO L290 TraceCheckUtils]: 63: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,903 INFO L290 TraceCheckUtils]: 64: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,903 INFO L290 TraceCheckUtils]: 65: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,904 INFO L290 TraceCheckUtils]: 66: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,904 INFO L290 TraceCheckUtils]: 67: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,904 INFO L290 TraceCheckUtils]: 68: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,904 INFO L290 TraceCheckUtils]: 69: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,905 INFO L290 TraceCheckUtils]: 70: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,905 INFO L290 TraceCheckUtils]: 71: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,905 INFO L290 TraceCheckUtils]: 72: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,906 INFO L290 TraceCheckUtils]: 73: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,906 INFO L290 TraceCheckUtils]: 74: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,906 INFO L290 TraceCheckUtils]: 75: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,906 INFO L290 TraceCheckUtils]: 76: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,907 INFO L290 TraceCheckUtils]: 77: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,907 INFO L290 TraceCheckUtils]: 78: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,907 INFO L290 TraceCheckUtils]: 79: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,907 INFO L290 TraceCheckUtils]: 80: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,908 INFO L290 TraceCheckUtils]: 81: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,908 INFO L290 TraceCheckUtils]: 82: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,908 INFO L290 TraceCheckUtils]: 83: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,909 INFO L290 TraceCheckUtils]: 84: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,909 INFO L290 TraceCheckUtils]: 85: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,909 INFO L290 TraceCheckUtils]: 86: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,909 INFO L290 TraceCheckUtils]: 87: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,910 INFO L290 TraceCheckUtils]: 88: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,910 INFO L290 TraceCheckUtils]: 89: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,910 INFO L290 TraceCheckUtils]: 90: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,910 INFO L290 TraceCheckUtils]: 91: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,911 INFO L290 TraceCheckUtils]: 92: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,911 INFO L290 TraceCheckUtils]: 93: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,911 INFO L290 TraceCheckUtils]: 94: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,911 INFO L290 TraceCheckUtils]: 95: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,912 INFO L290 TraceCheckUtils]: 96: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,912 INFO L290 TraceCheckUtils]: 97: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,912 INFO L290 TraceCheckUtils]: 98: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,913 INFO L290 TraceCheckUtils]: 99: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,913 INFO L290 TraceCheckUtils]: 100: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,913 INFO L290 TraceCheckUtils]: 101: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,913 INFO L290 TraceCheckUtils]: 102: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,914 INFO L290 TraceCheckUtils]: 103: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,914 INFO L290 TraceCheckUtils]: 104: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34098#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:07,914 INFO L290 TraceCheckUtils]: 105: Hoare triple {34098#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {34097#false} is VALID [2022-02-21 04:23:07,914 INFO L290 TraceCheckUtils]: 106: Hoare triple {34097#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,914 INFO L290 TraceCheckUtils]: 107: Hoare triple {34097#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,914 INFO L290 TraceCheckUtils]: 108: Hoare triple {34097#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 109: Hoare triple {34097#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 110: Hoare triple {34097#false} assume 1 == ~E_M~0;~E_M~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 111: Hoare triple {34097#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 112: Hoare triple {34097#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 113: Hoare triple {34097#false} assume !(1 == ~E_3~0); {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 114: Hoare triple {34097#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 115: Hoare triple {34097#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 116: Hoare triple {34097#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,915 INFO L290 TraceCheckUtils]: 117: Hoare triple {34097#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 118: Hoare triple {34097#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 119: Hoare triple {34097#false} assume 1 == ~E_9~0;~E_9~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 120: Hoare triple {34097#false} assume 1 == ~E_10~0;~E_10~0 := 2; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 121: Hoare triple {34097#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 122: Hoare triple {34097#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 123: Hoare triple {34097#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 124: Hoare triple {34097#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 125: Hoare triple {34097#false} assume !(0 == start_simulation_~tmp~3#1); {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 126: Hoare triple {34097#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {34097#false} is VALID [2022-02-21 04:23:07,916 INFO L290 TraceCheckUtils]: 127: Hoare triple {34097#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {34097#false} is VALID [2022-02-21 04:23:07,917 INFO L290 TraceCheckUtils]: 128: Hoare triple {34097#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {34097#false} is VALID [2022-02-21 04:23:07,917 INFO L290 TraceCheckUtils]: 129: Hoare triple {34097#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {34097#false} is VALID [2022-02-21 04:23:07,917 INFO L290 TraceCheckUtils]: 130: Hoare triple {34097#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {34097#false} is VALID [2022-02-21 04:23:07,917 INFO L290 TraceCheckUtils]: 131: Hoare triple {34097#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34097#false} is VALID [2022-02-21 04:23:07,917 INFO L290 TraceCheckUtils]: 132: Hoare triple {34097#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {34097#false} is VALID [2022-02-21 04:23:07,917 INFO L290 TraceCheckUtils]: 133: Hoare triple {34097#false} assume !(0 != start_simulation_~tmp___0~1#1); {34097#false} is VALID [2022-02-21 04:23:07,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:07,918 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:07,918 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1586849591] [2022-02-21 04:23:07,918 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1586849591] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:07,918 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:07,918 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:07,918 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499572330] [2022-02-21 04:23:07,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:07,919 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:07,919 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:07,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:07,920 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:07,920 INFO L87 Difference]: Start difference. First operand 1361 states and 2018 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,803 INFO L93 Difference]: Finished difference Result 1361 states and 2017 transitions. [2022-02-21 04:23:08,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:08,803 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,882 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:08,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2017 transitions. [2022-02-21 04:23:08,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:08,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2017 transitions. [2022-02-21 04:23:08,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:08,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:08,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2017 transitions. [2022-02-21 04:23:08,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:08,971 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-02-21 04:23:08,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2017 transitions. [2022-02-21 04:23:08,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:08,984 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:08,985 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2017 transitions. Second operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,986 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2017 transitions. Second operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,987 INFO L87 Difference]: Start difference. First operand 1361 states and 2017 transitions. Second operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:09,030 INFO L93 Difference]: Finished difference Result 1361 states and 2017 transitions. [2022-02-21 04:23:09,030 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2017 transitions. [2022-02-21 04:23:09,031 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:09,031 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:09,033 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2017 transitions. [2022-02-21 04:23:09,034 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2017 transitions. [2022-02-21 04:23:09,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:09,074 INFO L93 Difference]: Finished difference Result 1361 states and 2017 transitions. [2022-02-21 04:23:09,074 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2017 transitions. [2022-02-21 04:23:09,075 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:09,075 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:09,075 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:09,075 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:09,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2017 transitions. [2022-02-21 04:23:09,117 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-02-21 04:23:09,117 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-02-21 04:23:09,117 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:09,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2017 transitions. [2022-02-21 04:23:09,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:09,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:09,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:09,121 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,121 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,121 INFO L791 eck$LassoCheckResult]: Stem: 36468#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35509#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35510#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36398#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36102#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36103#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36380#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36536#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36268#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36269#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36158#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36159#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 36496#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36458#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 36386#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36387#L1024 assume !(0 == ~M_E~0); 36632#L1024-2 assume !(0 == ~T1_E~0); 35836#L1029-1 assume !(0 == ~T2_E~0); 35837#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35943#L1039-1 assume !(0 == ~T4_E~0); 36749#L1044-1 assume !(0 == ~T5_E~0); 36180#L1049-1 assume !(0 == ~T6_E~0); 36181#L1054-1 assume !(0 == ~T7_E~0); 36406#L1059-1 assume !(0 == ~T8_E~0); 35883#L1064-1 assume !(0 == ~T9_E~0); 35884#L1069-1 assume !(0 == ~T10_E~0); 36600#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 36666#L1079-1 assume !(0 == ~E_1~0); 36634#L1084-1 assume !(0 == ~E_2~0); 36635#L1089-1 assume !(0 == ~E_3~0); 36685#L1094-1 assume !(0 == ~E_4~0); 36256#L1099-1 assume !(0 == ~E_5~0); 36257#L1104-1 assume !(0 == ~E_6~0); 36514#L1109-1 assume !(0 == ~E_7~0); 36057#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36058#L1119-1 assume !(0 == ~E_9~0); 36114#L1124-1 assume !(0 == ~E_10~0); 35542#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35543#L502 assume 1 == ~m_pc~0; 36404#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35671#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35672#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36454#L1273 assume !(0 != activate_threads_~tmp~1#1); 36455#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36784#L521 assume !(1 == ~t1_pc~0); 36717#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35602#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35603#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35746#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 35586#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35587#L540 assume 1 == ~t2_pc~0; 36648#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36369#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36651#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36664#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 36711#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35858#L559 assume 1 == ~t3_pc~0; 35859#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36138#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36139#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36281#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 35689#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35690#L578 assume !(1 == ~t4_pc~0); 35810#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35809#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35578#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35579#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36438#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36439#L597 assume 1 == ~t5_pc~0; 36801#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35623#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35624#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36229#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36388#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36389#L616 assume !(1 == ~t6_pc~0); 36403#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36402#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36766#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36311#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36248#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36249#L635 assume 1 == ~t7_pc~0; 36443#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35592#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35963#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36609#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36381#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36382#L654 assume !(1 == ~t8_pc~0); 36204#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36205#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36712#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36597#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 36598#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35834#L673 assume 1 == ~t9_pc~0; 35835#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35533#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36781#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36567#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36523#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36524#L692 assume !(1 == ~t10_pc~0); 36472#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36471#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36390#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36260#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36261#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36578#L1142 assume !(1 == ~M_E~0); 35749#L1142-2 assume !(1 == ~T1_E~0); 35750#L1147-1 assume !(1 == ~T2_E~0); 36568#L1152-1 assume !(1 == ~T3_E~0); 36144#L1157-1 assume !(1 == ~T4_E~0); 36145#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36285#L1167-1 assume !(1 == ~T6_E~0); 36286#L1172-1 assume !(1 == ~T7_E~0); 36705#L1177-1 assume !(1 == ~T8_E~0); 36423#L1182-1 assume !(1 == ~T9_E~0); 36424#L1187-1 assume !(1 == ~T10_E~0); 36517#L1192-1 assume !(1 == ~E_M~0); 36010#L1197-1 assume !(1 == ~E_1~0); 36011#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 36372#L1207-1 assume !(1 == ~E_3~0); 36351#L1212-1 assume !(1 == ~E_4~0); 35608#L1217-1 assume !(1 == ~E_5~0); 35609#L1222-1 assume !(1 == ~E_6~0); 36347#L1227-1 assume !(1 == ~E_7~0); 36348#L1232-1 assume !(1 == ~E_8~0); 35474#L1237-1 assume !(1 == ~E_9~0); 35475#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 36405#L1247-1 assume { :end_inline_reset_delta_events } true; 35648#L1553-2 [2022-02-21 04:23:09,122 INFO L793 eck$LassoCheckResult]: Loop: 35648#L1553-2 assume !false; 35649#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36558#L999 assume !false; 36606#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35733#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35626#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 36121#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 36475#L854 assume !(0 != eval_~tmp~0#1); 36476#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35920#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35921#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36738#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36247#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36217#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36218#L1039-3 assume !(0 == ~T4_E~0); 36541#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35828#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35829#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35604#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35605#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36189#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36190#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36519#L1079-3 assume !(0 == ~E_1~0); 36417#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36304#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36305#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36234#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36235#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36539#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36527#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36528#L1119-3 assume !(0 == ~E_9~0); 36808#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36815#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36775#L502-36 assume !(1 == ~m_pc~0); 35975#L502-38 is_master_triggered_~__retres1~0#1 := 0; 35460#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35461#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35885#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35886#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36163#L521-36 assume 1 == ~t1_pc~0; 36164#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36173#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36340#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36377#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36602#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36603#L540-36 assume 1 == ~t2_pc~0; 36777#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35550#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35964#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36816#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36280#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35468#L559-36 assume 1 == ~t3_pc~0; 35469#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35922#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35778#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35779#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36425#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36661#L578-36 assume !(1 == ~t4_pc~0); 36354#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 36355#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36691#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36692#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36193#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36194#L597-36 assume !(1 == ~t5_pc~0); 36411#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 36764#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36338#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36339#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 36008#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36009#L616-36 assume !(1 == ~t6_pc~0); 36736#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 35538#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35539#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36141#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36242#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36557#L635-36 assume 1 == ~t7_pc~0; 36741#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36614#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36287#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36288#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36230#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36231#L654-36 assume !(1 == ~t8_pc~0); 36745#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 36746#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36818#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36803#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36785#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35913#L673-36 assume !(1 == ~t9_pc~0); 35914#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 36266#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36267#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36621#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35481#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35482#L692-36 assume 1 == ~t10_pc~0; 36416#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35698#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36241#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35876#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35877#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36240#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36385#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36747#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36748#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36318#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36319#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36610#L1167-3 assume !(1 == ~T6_E~0); 36732#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36228#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36133#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36134#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36147#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35972#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35973#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36214#L1207-3 assume !(1 == ~E_3~0); 36329#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36537#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35867#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35565#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35566#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36641#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36642#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36817#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 36695#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35717#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35718#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 36397#L1572 assume !(0 == start_simulation_~tmp~3#1); 36013#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 36166#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35495#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 36769#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 36770#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35464#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35465#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36619#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 35648#L1553-2 [2022-02-21 04:23:09,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,122 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2022-02-21 04:23:09,122 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,122 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579344388] [2022-02-21 04:23:09,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,151 INFO L290 TraceCheckUtils]: 0: Hoare triple {39546#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {39546#true} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 1: Hoare triple {39546#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 2: Hoare triple {39548#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,152 INFO L290 TraceCheckUtils]: 3: Hoare triple {39548#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 4: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 5: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 6: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,153 INFO L290 TraceCheckUtils]: 7: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,154 INFO L290 TraceCheckUtils]: 8: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,154 INFO L290 TraceCheckUtils]: 9: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,154 INFO L290 TraceCheckUtils]: 10: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,154 INFO L290 TraceCheckUtils]: 11: Hoare triple {39548#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {39548#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 12: Hoare triple {39548#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {39547#false} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 13: Hoare triple {39547#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {39547#false} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 14: Hoare triple {39547#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {39547#false} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 15: Hoare triple {39547#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {39547#false} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 16: Hoare triple {39547#false} assume !(0 == ~M_E~0); {39547#false} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 17: Hoare triple {39547#false} assume !(0 == ~T1_E~0); {39547#false} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 18: Hoare triple {39547#false} assume !(0 == ~T2_E~0); {39547#false} is VALID [2022-02-21 04:23:09,155 INFO L290 TraceCheckUtils]: 19: Hoare triple {39547#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 20: Hoare triple {39547#false} assume !(0 == ~T4_E~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 21: Hoare triple {39547#false} assume !(0 == ~T5_E~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 22: Hoare triple {39547#false} assume !(0 == ~T6_E~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 23: Hoare triple {39547#false} assume !(0 == ~T7_E~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 24: Hoare triple {39547#false} assume !(0 == ~T8_E~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 25: Hoare triple {39547#false} assume !(0 == ~T9_E~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 26: Hoare triple {39547#false} assume !(0 == ~T10_E~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 27: Hoare triple {39547#false} assume 0 == ~E_M~0;~E_M~0 := 1; {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 28: Hoare triple {39547#false} assume !(0 == ~E_1~0); {39547#false} is VALID [2022-02-21 04:23:09,156 INFO L290 TraceCheckUtils]: 29: Hoare triple {39547#false} assume !(0 == ~E_2~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 30: Hoare triple {39547#false} assume !(0 == ~E_3~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 31: Hoare triple {39547#false} assume !(0 == ~E_4~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 32: Hoare triple {39547#false} assume !(0 == ~E_5~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 33: Hoare triple {39547#false} assume !(0 == ~E_6~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 34: Hoare triple {39547#false} assume !(0 == ~E_7~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 35: Hoare triple {39547#false} assume 0 == ~E_8~0;~E_8~0 := 1; {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 36: Hoare triple {39547#false} assume !(0 == ~E_9~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 37: Hoare triple {39547#false} assume !(0 == ~E_10~0); {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 38: Hoare triple {39547#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39547#false} is VALID [2022-02-21 04:23:09,157 INFO L290 TraceCheckUtils]: 39: Hoare triple {39547#false} assume 1 == ~m_pc~0; {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 40: Hoare triple {39547#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 41: Hoare triple {39547#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 42: Hoare triple {39547#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 43: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp~1#1); {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 44: Hoare triple {39547#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 45: Hoare triple {39547#false} assume !(1 == ~t1_pc~0); {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 46: Hoare triple {39547#false} is_transmit1_triggered_~__retres1~1#1 := 0; {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 47: Hoare triple {39547#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39547#false} is VALID [2022-02-21 04:23:09,158 INFO L290 TraceCheckUtils]: 48: Hoare triple {39547#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 49: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___0~0#1); {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 50: Hoare triple {39547#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 51: Hoare triple {39547#false} assume 1 == ~t2_pc~0; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 52: Hoare triple {39547#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 53: Hoare triple {39547#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 54: Hoare triple {39547#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 55: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___1~0#1); {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 56: Hoare triple {39547#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 57: Hoare triple {39547#false} assume 1 == ~t3_pc~0; {39547#false} is VALID [2022-02-21 04:23:09,159 INFO L290 TraceCheckUtils]: 58: Hoare triple {39547#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 59: Hoare triple {39547#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 60: Hoare triple {39547#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 61: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___2~0#1); {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 62: Hoare triple {39547#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 63: Hoare triple {39547#false} assume !(1 == ~t4_pc~0); {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 64: Hoare triple {39547#false} is_transmit4_triggered_~__retres1~4#1 := 0; {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 65: Hoare triple {39547#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 66: Hoare triple {39547#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {39547#false} is VALID [2022-02-21 04:23:09,160 INFO L290 TraceCheckUtils]: 67: Hoare triple {39547#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 68: Hoare triple {39547#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 69: Hoare triple {39547#false} assume 1 == ~t5_pc~0; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 70: Hoare triple {39547#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 71: Hoare triple {39547#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 72: Hoare triple {39547#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 73: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___4~0#1); {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 74: Hoare triple {39547#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 75: Hoare triple {39547#false} assume !(1 == ~t6_pc~0); {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 76: Hoare triple {39547#false} is_transmit6_triggered_~__retres1~6#1 := 0; {39547#false} is VALID [2022-02-21 04:23:09,161 INFO L290 TraceCheckUtils]: 77: Hoare triple {39547#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 78: Hoare triple {39547#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 79: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___5~0#1); {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 80: Hoare triple {39547#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 81: Hoare triple {39547#false} assume 1 == ~t7_pc~0; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 82: Hoare triple {39547#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 83: Hoare triple {39547#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 84: Hoare triple {39547#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 85: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___6~0#1); {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 86: Hoare triple {39547#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {39547#false} is VALID [2022-02-21 04:23:09,162 INFO L290 TraceCheckUtils]: 87: Hoare triple {39547#false} assume !(1 == ~t8_pc~0); {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 88: Hoare triple {39547#false} is_transmit8_triggered_~__retres1~8#1 := 0; {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 89: Hoare triple {39547#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 90: Hoare triple {39547#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 91: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___7~0#1); {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 92: Hoare triple {39547#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 93: Hoare triple {39547#false} assume 1 == ~t9_pc~0; {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 94: Hoare triple {39547#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 95: Hoare triple {39547#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {39547#false} is VALID [2022-02-21 04:23:09,163 INFO L290 TraceCheckUtils]: 96: Hoare triple {39547#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 97: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___8~0#1); {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 98: Hoare triple {39547#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 99: Hoare triple {39547#false} assume !(1 == ~t10_pc~0); {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 100: Hoare triple {39547#false} is_transmit10_triggered_~__retres1~10#1 := 0; {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 101: Hoare triple {39547#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 102: Hoare triple {39547#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 103: Hoare triple {39547#false} assume !(0 != activate_threads_~tmp___9~0#1); {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 104: Hoare triple {39547#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 105: Hoare triple {39547#false} assume !(1 == ~M_E~0); {39547#false} is VALID [2022-02-21 04:23:09,164 INFO L290 TraceCheckUtils]: 106: Hoare triple {39547#false} assume !(1 == ~T1_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 107: Hoare triple {39547#false} assume !(1 == ~T2_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 108: Hoare triple {39547#false} assume !(1 == ~T3_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 109: Hoare triple {39547#false} assume !(1 == ~T4_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 110: Hoare triple {39547#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 111: Hoare triple {39547#false} assume !(1 == ~T6_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 112: Hoare triple {39547#false} assume !(1 == ~T7_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 113: Hoare triple {39547#false} assume !(1 == ~T8_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 114: Hoare triple {39547#false} assume !(1 == ~T9_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 115: Hoare triple {39547#false} assume !(1 == ~T10_E~0); {39547#false} is VALID [2022-02-21 04:23:09,165 INFO L290 TraceCheckUtils]: 116: Hoare triple {39547#false} assume !(1 == ~E_M~0); {39547#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 117: Hoare triple {39547#false} assume !(1 == ~E_1~0); {39547#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 118: Hoare triple {39547#false} assume 1 == ~E_2~0;~E_2~0 := 2; {39547#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 119: Hoare triple {39547#false} assume !(1 == ~E_3~0); {39547#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 120: Hoare triple {39547#false} assume !(1 == ~E_4~0); {39547#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 121: Hoare triple {39547#false} assume !(1 == ~E_5~0); {39547#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 122: Hoare triple {39547#false} assume !(1 == ~E_6~0); {39547#false} is VALID [2022-02-21 04:23:09,166 INFO L290 TraceCheckUtils]: 123: Hoare triple {39547#false} assume !(1 == ~E_7~0); {39547#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 124: Hoare triple {39547#false} assume !(1 == ~E_8~0); {39547#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 125: Hoare triple {39547#false} assume !(1 == ~E_9~0); {39547#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 126: Hoare triple {39547#false} assume 1 == ~E_10~0;~E_10~0 := 2; {39547#false} is VALID [2022-02-21 04:23:09,167 INFO L290 TraceCheckUtils]: 127: Hoare triple {39547#false} assume { :end_inline_reset_delta_events } true; {39547#false} is VALID [2022-02-21 04:23:09,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,167 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,168 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579344388] [2022-02-21 04:23:09,168 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579344388] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,169 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,169 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,169 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813640750] [2022-02-21 04:23:09,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,170 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:09,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,170 INFO L85 PathProgramCache]: Analyzing trace with hash -301700681, now seen corresponding path program 1 times [2022-02-21 04:23:09,170 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,175 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191171157] [2022-02-21 04:23:09,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 0: Hoare triple {39549#true} assume !false; {39549#true} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 1: Hoare triple {39549#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {39549#true} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 2: Hoare triple {39549#true} assume !false; {39549#true} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 3: Hoare triple {39549#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {39549#true} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 4: Hoare triple {39549#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {39549#true} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 5: Hoare triple {39549#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 6: Hoare triple {39549#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 7: Hoare triple {39549#true} assume !(0 != eval_~tmp~0#1); {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 8: Hoare triple {39549#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 9: Hoare triple {39549#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 10: Hoare triple {39549#true} assume 0 == ~M_E~0;~M_E~0 := 1; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 11: Hoare triple {39549#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 12: Hoare triple {39549#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 13: Hoare triple {39549#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {39549#true} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 14: Hoare triple {39549#true} assume !(0 == ~T4_E~0); {39549#true} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 15: Hoare triple {39549#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {39549#true} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 16: Hoare triple {39549#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 17: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 18: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 19: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 20: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 21: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 22: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 23: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 24: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 25: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 26: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 27: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 28: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 29: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 30: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,204 INFO L290 TraceCheckUtils]: 31: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,204 INFO L290 TraceCheckUtils]: 32: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,204 INFO L290 TraceCheckUtils]: 33: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,205 INFO L290 TraceCheckUtils]: 34: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,205 INFO L290 TraceCheckUtils]: 35: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,205 INFO L290 TraceCheckUtils]: 36: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,205 INFO L290 TraceCheckUtils]: 37: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,206 INFO L290 TraceCheckUtils]: 38: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,206 INFO L290 TraceCheckUtils]: 39: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,206 INFO L290 TraceCheckUtils]: 40: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,206 INFO L290 TraceCheckUtils]: 41: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,207 INFO L290 TraceCheckUtils]: 42: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,207 INFO L290 TraceCheckUtils]: 43: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,207 INFO L290 TraceCheckUtils]: 44: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,207 INFO L290 TraceCheckUtils]: 45: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,208 INFO L290 TraceCheckUtils]: 46: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,208 INFO L290 TraceCheckUtils]: 47: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,208 INFO L290 TraceCheckUtils]: 48: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,208 INFO L290 TraceCheckUtils]: 49: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,209 INFO L290 TraceCheckUtils]: 50: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,209 INFO L290 TraceCheckUtils]: 51: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,209 INFO L290 TraceCheckUtils]: 52: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,209 INFO L290 TraceCheckUtils]: 53: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,210 INFO L290 TraceCheckUtils]: 54: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,210 INFO L290 TraceCheckUtils]: 55: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,210 INFO L290 TraceCheckUtils]: 56: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,210 INFO L290 TraceCheckUtils]: 57: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,211 INFO L290 TraceCheckUtils]: 58: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,211 INFO L290 TraceCheckUtils]: 59: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,211 INFO L290 TraceCheckUtils]: 60: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,211 INFO L290 TraceCheckUtils]: 61: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,212 INFO L290 TraceCheckUtils]: 62: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,212 INFO L290 TraceCheckUtils]: 63: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,212 INFO L290 TraceCheckUtils]: 64: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,212 INFO L290 TraceCheckUtils]: 65: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,213 INFO L290 TraceCheckUtils]: 66: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,213 INFO L290 TraceCheckUtils]: 67: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,213 INFO L290 TraceCheckUtils]: 68: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,214 INFO L290 TraceCheckUtils]: 69: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,214 INFO L290 TraceCheckUtils]: 70: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,214 INFO L290 TraceCheckUtils]: 71: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,215 INFO L290 TraceCheckUtils]: 72: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,215 INFO L290 TraceCheckUtils]: 73: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,215 INFO L290 TraceCheckUtils]: 74: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,216 INFO L290 TraceCheckUtils]: 75: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,216 INFO L290 TraceCheckUtils]: 76: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,216 INFO L290 TraceCheckUtils]: 77: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,216 INFO L290 TraceCheckUtils]: 78: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,217 INFO L290 TraceCheckUtils]: 79: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,217 INFO L290 TraceCheckUtils]: 80: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,217 INFO L290 TraceCheckUtils]: 81: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,217 INFO L290 TraceCheckUtils]: 82: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,218 INFO L290 TraceCheckUtils]: 83: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,218 INFO L290 TraceCheckUtils]: 84: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,218 INFO L290 TraceCheckUtils]: 85: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,218 INFO L290 TraceCheckUtils]: 86: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,219 INFO L290 TraceCheckUtils]: 87: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,219 INFO L290 TraceCheckUtils]: 88: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,219 INFO L290 TraceCheckUtils]: 89: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,219 INFO L290 TraceCheckUtils]: 90: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,220 INFO L290 TraceCheckUtils]: 91: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,220 INFO L290 TraceCheckUtils]: 92: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,220 INFO L290 TraceCheckUtils]: 93: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,220 INFO L290 TraceCheckUtils]: 94: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,221 INFO L290 TraceCheckUtils]: 95: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,221 INFO L290 TraceCheckUtils]: 96: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,221 INFO L290 TraceCheckUtils]: 97: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,221 INFO L290 TraceCheckUtils]: 98: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,222 INFO L290 TraceCheckUtils]: 99: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,222 INFO L290 TraceCheckUtils]: 100: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,222 INFO L290 TraceCheckUtils]: 101: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,223 INFO L290 TraceCheckUtils]: 102: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,223 INFO L290 TraceCheckUtils]: 103: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,223 INFO L290 TraceCheckUtils]: 104: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {39551#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:09,223 INFO L290 TraceCheckUtils]: 105: Hoare triple {39551#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {39550#false} is VALID [2022-02-21 04:23:09,223 INFO L290 TraceCheckUtils]: 106: Hoare triple {39550#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 107: Hoare triple {39550#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 108: Hoare triple {39550#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 109: Hoare triple {39550#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 110: Hoare triple {39550#false} assume 1 == ~E_M~0;~E_M~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 111: Hoare triple {39550#false} assume 1 == ~E_1~0;~E_1~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 112: Hoare triple {39550#false} assume 1 == ~E_2~0;~E_2~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 113: Hoare triple {39550#false} assume !(1 == ~E_3~0); {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 114: Hoare triple {39550#false} assume 1 == ~E_4~0;~E_4~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,224 INFO L290 TraceCheckUtils]: 115: Hoare triple {39550#false} assume 1 == ~E_5~0;~E_5~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 116: Hoare triple {39550#false} assume 1 == ~E_6~0;~E_6~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 117: Hoare triple {39550#false} assume 1 == ~E_7~0;~E_7~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 118: Hoare triple {39550#false} assume 1 == ~E_8~0;~E_8~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 119: Hoare triple {39550#false} assume 1 == ~E_9~0;~E_9~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 120: Hoare triple {39550#false} assume 1 == ~E_10~0;~E_10~0 := 2; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 121: Hoare triple {39550#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 122: Hoare triple {39550#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 123: Hoare triple {39550#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 124: Hoare triple {39550#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {39550#false} is VALID [2022-02-21 04:23:09,225 INFO L290 TraceCheckUtils]: 125: Hoare triple {39550#false} assume !(0 == start_simulation_~tmp~3#1); {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 126: Hoare triple {39550#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 127: Hoare triple {39550#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 128: Hoare triple {39550#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 129: Hoare triple {39550#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 130: Hoare triple {39550#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 131: Hoare triple {39550#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 132: Hoare triple {39550#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {39550#false} is VALID [2022-02-21 04:23:09,226 INFO L290 TraceCheckUtils]: 133: Hoare triple {39550#false} assume !(0 != start_simulation_~tmp___0~1#1); {39550#false} is VALID [2022-02-21 04:23:09,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,227 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,229 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191171157] [2022-02-21 04:23:09,230 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191171157] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,230 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,230 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,230 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1011771496] [2022-02-21 04:23:09,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,231 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:09,231 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:09,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:09,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:09,232 INFO L87 Difference]: Start difference. First operand 1361 states and 2017 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,189 INFO L93 Difference]: Finished difference Result 1361 states and 2016 transitions. [2022-02-21 04:23:10,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:10,190 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,257 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:10,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:10,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2016 transitions. [2022-02-21 04:23:10,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:10,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:10,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:10,347 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-02-21 04:23:10,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:10,367 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:10,369 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2016 transitions. Second operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,370 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2016 transitions. Second operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,371 INFO L87 Difference]: Start difference. First operand 1361 states and 2016 transitions. Second operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,410 INFO L93 Difference]: Finished difference Result 1361 states and 2016 transitions. [2022-02-21 04:23:10,410 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,411 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,411 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,413 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,414 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,452 INFO L93 Difference]: Finished difference Result 1361 states and 2016 transitions. [2022-02-21 04:23:10,452 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,454 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,454 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,454 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:10,454 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:10,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2016 transitions. [2022-02-21 04:23:10,494 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-02-21 04:23:10,494 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-02-21 04:23:10,494 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:10,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2016 transitions. [2022-02-21 04:23:10,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:10,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:10,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:10,498 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,498 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,498 INFO L791 eck$LassoCheckResult]: Stem: 41921#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 41922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 40962#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40963#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41851#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 41554#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41555#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41833#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41989#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41719#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41720#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41609#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41610#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41949#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41911#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 41838#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41839#L1024 assume !(0 == ~M_E~0); 42085#L1024-2 assume !(0 == ~T1_E~0); 41289#L1029-1 assume !(0 == ~T2_E~0); 41290#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41396#L1039-1 assume !(0 == ~T4_E~0); 42202#L1044-1 assume !(0 == ~T5_E~0); 41631#L1049-1 assume !(0 == ~T6_E~0); 41632#L1054-1 assume !(0 == ~T7_E~0); 41859#L1059-1 assume !(0 == ~T8_E~0); 41336#L1064-1 assume !(0 == ~T9_E~0); 41337#L1069-1 assume !(0 == ~T10_E~0); 42053#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 42119#L1079-1 assume !(0 == ~E_1~0); 42087#L1084-1 assume !(0 == ~E_2~0); 42088#L1089-1 assume !(0 == ~E_3~0); 42138#L1094-1 assume !(0 == ~E_4~0); 41709#L1099-1 assume !(0 == ~E_5~0); 41710#L1104-1 assume !(0 == ~E_6~0); 41967#L1109-1 assume !(0 == ~E_7~0); 41510#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 41511#L1119-1 assume !(0 == ~E_9~0); 41565#L1124-1 assume !(0 == ~E_10~0); 40995#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40996#L502 assume 1 == ~m_pc~0; 41857#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41124#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41125#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41906#L1273 assume !(0 != activate_threads_~tmp~1#1); 41907#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42237#L521 assume !(1 == ~t1_pc~0); 42170#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41055#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41056#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41198#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 41037#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41038#L540 assume 1 == ~t2_pc~0; 42101#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41822#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42104#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42117#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 42164#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41311#L559 assume 1 == ~t3_pc~0; 41312#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41590#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41591#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41734#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 41142#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41143#L578 assume !(1 == ~t4_pc~0); 41261#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41260#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41031#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41032#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41889#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41890#L597 assume 1 == ~t5_pc~0; 42252#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41076#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41077#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41677#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 41840#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41841#L616 assume !(1 == ~t6_pc~0); 41855#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41854#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42219#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41764#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 41701#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41702#L635 assume 1 == ~t7_pc~0; 41894#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41045#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41416#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42062#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 41834#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41835#L654 assume !(1 == ~t8_pc~0); 41657#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41658#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42165#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42050#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 42051#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41287#L673 assume 1 == ~t9_pc~0; 41288#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40986#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42234#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42020#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 41976#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41977#L692 assume !(1 == ~t10_pc~0); 41925#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41924#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41843#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41713#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 41714#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42031#L1142 assume !(1 == ~M_E~0); 41202#L1142-2 assume !(1 == ~T1_E~0); 41203#L1147-1 assume !(1 == ~T2_E~0); 42021#L1152-1 assume !(1 == ~T3_E~0); 41597#L1157-1 assume !(1 == ~T4_E~0); 41598#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41738#L1167-1 assume !(1 == ~T6_E~0); 41739#L1172-1 assume !(1 == ~T7_E~0); 42158#L1177-1 assume !(1 == ~T8_E~0); 41876#L1182-1 assume !(1 == ~T9_E~0); 41877#L1187-1 assume !(1 == ~T10_E~0); 41970#L1192-1 assume !(1 == ~E_M~0); 41461#L1197-1 assume !(1 == ~E_1~0); 41462#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 41825#L1207-1 assume !(1 == ~E_3~0); 41804#L1212-1 assume !(1 == ~E_4~0); 41061#L1217-1 assume !(1 == ~E_5~0); 41062#L1222-1 assume !(1 == ~E_6~0); 41800#L1227-1 assume !(1 == ~E_7~0); 41801#L1232-1 assume !(1 == ~E_8~0); 40927#L1237-1 assume !(1 == ~E_9~0); 40928#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 41858#L1247-1 assume { :end_inline_reset_delta_events } true; 41101#L1553-2 [2022-02-21 04:23:10,498 INFO L793 eck$LassoCheckResult]: Loop: 41101#L1553-2 assume !false; 41102#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42011#L999 assume !false; 42057#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 41186#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 41079#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 41574#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41928#L854 assume !(0 != eval_~tmp~0#1); 41929#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41373#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41374#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42191#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41700#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41670#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41671#L1039-3 assume !(0 == ~T4_E~0); 41994#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41281#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41282#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41057#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41058#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41642#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41643#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41972#L1079-3 assume !(0 == ~E_1~0); 41869#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41757#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41758#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41687#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41688#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41992#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41980#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41981#L1119-3 assume !(0 == ~E_9~0); 42261#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42268#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42228#L502-36 assume !(1 == ~m_pc~0); 41428#L502-38 is_master_triggered_~__retres1~0#1 := 0; 40913#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40914#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41338#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41339#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41614#L521-36 assume !(1 == ~t1_pc~0); 41616#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 41626#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41793#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41830#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42055#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42056#L540-36 assume 1 == ~t2_pc~0; 42230#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41003#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41417#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42269#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41733#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40924#L559-36 assume 1 == ~t3_pc~0; 40925#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41381#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41231#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41232#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41878#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42114#L578-36 assume !(1 == ~t4_pc~0); 41810#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 41811#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42144#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42145#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41648#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41649#L597-36 assume !(1 == ~t5_pc~0); 41867#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 42217#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41791#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41792#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 41463#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41464#L616-36 assume 1 == ~t6_pc~0; 42231#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40991#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40992#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41594#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41695#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42010#L635-36 assume 1 == ~t7_pc~0; 42194#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42067#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41740#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41741#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41683#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41684#L654-36 assume !(1 == ~t8_pc~0); 42198#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 42199#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42271#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42256#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42238#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41366#L673-36 assume !(1 == ~t9_pc~0); 41367#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 41721#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41722#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42074#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40934#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40935#L692-36 assume 1 == ~t10_pc~0; 41870#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41151#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41694#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41329#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41330#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41693#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41842#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42200#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42201#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41771#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41772#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42063#L1167-3 assume !(1 == ~T6_E~0); 42185#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41682#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41586#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41587#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41600#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41425#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41426#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41667#L1207-3 assume !(1 == ~E_3~0); 41782#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41990#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41321#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41018#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41019#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42095#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42096#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 42270#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 42148#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 41170#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 41171#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 41850#L1572 assume !(0 == start_simulation_~tmp~3#1); 41468#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 41619#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 40948#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 42222#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 42223#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40917#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40918#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 42072#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 41101#L1553-2 [2022-02-21 04:23:10,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,499 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2022-02-21 04:23:10,499 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,499 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546387760] [2022-02-21 04:23:10,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,516 INFO L290 TraceCheckUtils]: 0: Hoare triple {44999#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {44999#true} is VALID [2022-02-21 04:23:10,516 INFO L290 TraceCheckUtils]: 1: Hoare triple {44999#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,517 INFO L290 TraceCheckUtils]: 2: Hoare triple {45001#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,517 INFO L290 TraceCheckUtils]: 3: Hoare triple {45001#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,517 INFO L290 TraceCheckUtils]: 4: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,517 INFO L290 TraceCheckUtils]: 5: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,518 INFO L290 TraceCheckUtils]: 6: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,518 INFO L290 TraceCheckUtils]: 7: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,518 INFO L290 TraceCheckUtils]: 8: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,518 INFO L290 TraceCheckUtils]: 9: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,519 INFO L290 TraceCheckUtils]: 10: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,519 INFO L290 TraceCheckUtils]: 11: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,519 INFO L290 TraceCheckUtils]: 12: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,519 INFO L290 TraceCheckUtils]: 13: Hoare triple {45001#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {45001#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 14: Hoare triple {45001#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 15: Hoare triple {45000#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 16: Hoare triple {45000#false} assume !(0 == ~M_E~0); {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 17: Hoare triple {45000#false} assume !(0 == ~T1_E~0); {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 18: Hoare triple {45000#false} assume !(0 == ~T2_E~0); {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 19: Hoare triple {45000#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 20: Hoare triple {45000#false} assume !(0 == ~T4_E~0); {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 21: Hoare triple {45000#false} assume !(0 == ~T5_E~0); {45000#false} is VALID [2022-02-21 04:23:10,520 INFO L290 TraceCheckUtils]: 22: Hoare triple {45000#false} assume !(0 == ~T6_E~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 23: Hoare triple {45000#false} assume !(0 == ~T7_E~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 24: Hoare triple {45000#false} assume !(0 == ~T8_E~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 25: Hoare triple {45000#false} assume !(0 == ~T9_E~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 26: Hoare triple {45000#false} assume !(0 == ~T10_E~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 27: Hoare triple {45000#false} assume 0 == ~E_M~0;~E_M~0 := 1; {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 28: Hoare triple {45000#false} assume !(0 == ~E_1~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 29: Hoare triple {45000#false} assume !(0 == ~E_2~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 30: Hoare triple {45000#false} assume !(0 == ~E_3~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 31: Hoare triple {45000#false} assume !(0 == ~E_4~0); {45000#false} is VALID [2022-02-21 04:23:10,521 INFO L290 TraceCheckUtils]: 32: Hoare triple {45000#false} assume !(0 == ~E_5~0); {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 33: Hoare triple {45000#false} assume !(0 == ~E_6~0); {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 34: Hoare triple {45000#false} assume !(0 == ~E_7~0); {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 35: Hoare triple {45000#false} assume 0 == ~E_8~0;~E_8~0 := 1; {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 36: Hoare triple {45000#false} assume !(0 == ~E_9~0); {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 37: Hoare triple {45000#false} assume !(0 == ~E_10~0); {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 38: Hoare triple {45000#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 39: Hoare triple {45000#false} assume 1 == ~m_pc~0; {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 40: Hoare triple {45000#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {45000#false} is VALID [2022-02-21 04:23:10,522 INFO L290 TraceCheckUtils]: 41: Hoare triple {45000#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 42: Hoare triple {45000#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 43: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp~1#1); {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 44: Hoare triple {45000#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 45: Hoare triple {45000#false} assume !(1 == ~t1_pc~0); {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 46: Hoare triple {45000#false} is_transmit1_triggered_~__retres1~1#1 := 0; {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 47: Hoare triple {45000#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 48: Hoare triple {45000#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 49: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___0~0#1); {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 50: Hoare triple {45000#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {45000#false} is VALID [2022-02-21 04:23:10,523 INFO L290 TraceCheckUtils]: 51: Hoare triple {45000#false} assume 1 == ~t2_pc~0; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 52: Hoare triple {45000#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 53: Hoare triple {45000#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 54: Hoare triple {45000#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 55: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___1~0#1); {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 56: Hoare triple {45000#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 57: Hoare triple {45000#false} assume 1 == ~t3_pc~0; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 58: Hoare triple {45000#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 59: Hoare triple {45000#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 60: Hoare triple {45000#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {45000#false} is VALID [2022-02-21 04:23:10,524 INFO L290 TraceCheckUtils]: 61: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___2~0#1); {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 62: Hoare triple {45000#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 63: Hoare triple {45000#false} assume !(1 == ~t4_pc~0); {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 64: Hoare triple {45000#false} is_transmit4_triggered_~__retres1~4#1 := 0; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 65: Hoare triple {45000#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 66: Hoare triple {45000#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 67: Hoare triple {45000#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 68: Hoare triple {45000#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 69: Hoare triple {45000#false} assume 1 == ~t5_pc~0; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 70: Hoare triple {45000#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {45000#false} is VALID [2022-02-21 04:23:10,525 INFO L290 TraceCheckUtils]: 71: Hoare triple {45000#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 72: Hoare triple {45000#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 73: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___4~0#1); {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 74: Hoare triple {45000#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 75: Hoare triple {45000#false} assume !(1 == ~t6_pc~0); {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 76: Hoare triple {45000#false} is_transmit6_triggered_~__retres1~6#1 := 0; {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 77: Hoare triple {45000#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 78: Hoare triple {45000#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 79: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___5~0#1); {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 80: Hoare triple {45000#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {45000#false} is VALID [2022-02-21 04:23:10,526 INFO L290 TraceCheckUtils]: 81: Hoare triple {45000#false} assume 1 == ~t7_pc~0; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 82: Hoare triple {45000#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 83: Hoare triple {45000#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 84: Hoare triple {45000#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 85: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___6~0#1); {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 86: Hoare triple {45000#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 87: Hoare triple {45000#false} assume !(1 == ~t8_pc~0); {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 88: Hoare triple {45000#false} is_transmit8_triggered_~__retres1~8#1 := 0; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 89: Hoare triple {45000#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 90: Hoare triple {45000#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {45000#false} is VALID [2022-02-21 04:23:10,527 INFO L290 TraceCheckUtils]: 91: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___7~0#1); {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 92: Hoare triple {45000#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 93: Hoare triple {45000#false} assume 1 == ~t9_pc~0; {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 94: Hoare triple {45000#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 95: Hoare triple {45000#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 96: Hoare triple {45000#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 97: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___8~0#1); {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 98: Hoare triple {45000#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 99: Hoare triple {45000#false} assume !(1 == ~t10_pc~0); {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 100: Hoare triple {45000#false} is_transmit10_triggered_~__retres1~10#1 := 0; {45000#false} is VALID [2022-02-21 04:23:10,528 INFO L290 TraceCheckUtils]: 101: Hoare triple {45000#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 102: Hoare triple {45000#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 103: Hoare triple {45000#false} assume !(0 != activate_threads_~tmp___9~0#1); {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 104: Hoare triple {45000#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 105: Hoare triple {45000#false} assume !(1 == ~M_E~0); {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 106: Hoare triple {45000#false} assume !(1 == ~T1_E~0); {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 107: Hoare triple {45000#false} assume !(1 == ~T2_E~0); {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 108: Hoare triple {45000#false} assume !(1 == ~T3_E~0); {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 109: Hoare triple {45000#false} assume !(1 == ~T4_E~0); {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 110: Hoare triple {45000#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {45000#false} is VALID [2022-02-21 04:23:10,529 INFO L290 TraceCheckUtils]: 111: Hoare triple {45000#false} assume !(1 == ~T6_E~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 112: Hoare triple {45000#false} assume !(1 == ~T7_E~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 113: Hoare triple {45000#false} assume !(1 == ~T8_E~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 114: Hoare triple {45000#false} assume !(1 == ~T9_E~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 115: Hoare triple {45000#false} assume !(1 == ~T10_E~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 116: Hoare triple {45000#false} assume !(1 == ~E_M~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 117: Hoare triple {45000#false} assume !(1 == ~E_1~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 118: Hoare triple {45000#false} assume 1 == ~E_2~0;~E_2~0 := 2; {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 119: Hoare triple {45000#false} assume !(1 == ~E_3~0); {45000#false} is VALID [2022-02-21 04:23:10,530 INFO L290 TraceCheckUtils]: 120: Hoare triple {45000#false} assume !(1 == ~E_4~0); {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L290 TraceCheckUtils]: 121: Hoare triple {45000#false} assume !(1 == ~E_5~0); {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L290 TraceCheckUtils]: 122: Hoare triple {45000#false} assume !(1 == ~E_6~0); {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L290 TraceCheckUtils]: 123: Hoare triple {45000#false} assume !(1 == ~E_7~0); {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L290 TraceCheckUtils]: 124: Hoare triple {45000#false} assume !(1 == ~E_8~0); {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L290 TraceCheckUtils]: 125: Hoare triple {45000#false} assume !(1 == ~E_9~0); {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L290 TraceCheckUtils]: 126: Hoare triple {45000#false} assume 1 == ~E_10~0;~E_10~0 := 2; {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L290 TraceCheckUtils]: 127: Hoare triple {45000#false} assume { :end_inline_reset_delta_events } true; {45000#false} is VALID [2022-02-21 04:23:10,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,532 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,532 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546387760] [2022-02-21 04:23:10,532 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546387760] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,532 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,532 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,532 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866883920] [2022-02-21 04:23:10,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,533 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:10,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,533 INFO L85 PathProgramCache]: Analyzing trace with hash -806419977, now seen corresponding path program 1 times [2022-02-21 04:23:10,533 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,533 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480999760] [2022-02-21 04:23:10,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,554 INFO L290 TraceCheckUtils]: 0: Hoare triple {45002#true} assume !false; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 1: Hoare triple {45002#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 2: Hoare triple {45002#true} assume !false; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 3: Hoare triple {45002#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 4: Hoare triple {45002#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 5: Hoare triple {45002#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 6: Hoare triple {45002#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 7: Hoare triple {45002#true} assume !(0 != eval_~tmp~0#1); {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 8: Hoare triple {45002#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {45002#true} is VALID [2022-02-21 04:23:10,555 INFO L290 TraceCheckUtils]: 9: Hoare triple {45002#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {45002#true} is VALID [2022-02-21 04:23:10,556 INFO L290 TraceCheckUtils]: 10: Hoare triple {45002#true} assume 0 == ~M_E~0;~M_E~0 := 1; {45002#true} is VALID [2022-02-21 04:23:10,556 INFO L290 TraceCheckUtils]: 11: Hoare triple {45002#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {45002#true} is VALID [2022-02-21 04:23:10,556 INFO L290 TraceCheckUtils]: 12: Hoare triple {45002#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {45002#true} is VALID [2022-02-21 04:23:10,556 INFO L290 TraceCheckUtils]: 13: Hoare triple {45002#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {45002#true} is VALID [2022-02-21 04:23:10,556 INFO L290 TraceCheckUtils]: 14: Hoare triple {45002#true} assume !(0 == ~T4_E~0); {45002#true} is VALID [2022-02-21 04:23:10,556 INFO L290 TraceCheckUtils]: 15: Hoare triple {45002#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {45002#true} is VALID [2022-02-21 04:23:10,556 INFO L290 TraceCheckUtils]: 16: Hoare triple {45002#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,557 INFO L290 TraceCheckUtils]: 17: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,557 INFO L290 TraceCheckUtils]: 18: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,557 INFO L290 TraceCheckUtils]: 19: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,557 INFO L290 TraceCheckUtils]: 20: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,558 INFO L290 TraceCheckUtils]: 21: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,558 INFO L290 TraceCheckUtils]: 22: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,558 INFO L290 TraceCheckUtils]: 23: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,558 INFO L290 TraceCheckUtils]: 24: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,559 INFO L290 TraceCheckUtils]: 25: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,559 INFO L290 TraceCheckUtils]: 26: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,559 INFO L290 TraceCheckUtils]: 27: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,560 INFO L290 TraceCheckUtils]: 28: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,560 INFO L290 TraceCheckUtils]: 29: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,560 INFO L290 TraceCheckUtils]: 30: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,560 INFO L290 TraceCheckUtils]: 31: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,561 INFO L290 TraceCheckUtils]: 32: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,561 INFO L290 TraceCheckUtils]: 33: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,561 INFO L290 TraceCheckUtils]: 34: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,561 INFO L290 TraceCheckUtils]: 35: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,562 INFO L290 TraceCheckUtils]: 36: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,562 INFO L290 TraceCheckUtils]: 37: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,562 INFO L290 TraceCheckUtils]: 38: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,562 INFO L290 TraceCheckUtils]: 39: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,563 INFO L290 TraceCheckUtils]: 40: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,563 INFO L290 TraceCheckUtils]: 41: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,563 INFO L290 TraceCheckUtils]: 42: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,563 INFO L290 TraceCheckUtils]: 43: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,564 INFO L290 TraceCheckUtils]: 44: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,564 INFO L290 TraceCheckUtils]: 45: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,564 INFO L290 TraceCheckUtils]: 46: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,564 INFO L290 TraceCheckUtils]: 47: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,565 INFO L290 TraceCheckUtils]: 48: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,565 INFO L290 TraceCheckUtils]: 49: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,565 INFO L290 TraceCheckUtils]: 50: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,565 INFO L290 TraceCheckUtils]: 51: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,566 INFO L290 TraceCheckUtils]: 52: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,566 INFO L290 TraceCheckUtils]: 53: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,566 INFO L290 TraceCheckUtils]: 54: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,566 INFO L290 TraceCheckUtils]: 55: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,567 INFO L290 TraceCheckUtils]: 56: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,567 INFO L290 TraceCheckUtils]: 57: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,567 INFO L290 TraceCheckUtils]: 58: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,567 INFO L290 TraceCheckUtils]: 59: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,568 INFO L290 TraceCheckUtils]: 60: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,568 INFO L290 TraceCheckUtils]: 61: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,568 INFO L290 TraceCheckUtils]: 62: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,568 INFO L290 TraceCheckUtils]: 63: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,569 INFO L290 TraceCheckUtils]: 64: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,569 INFO L290 TraceCheckUtils]: 65: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,569 INFO L290 TraceCheckUtils]: 66: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,569 INFO L290 TraceCheckUtils]: 67: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,570 INFO L290 TraceCheckUtils]: 68: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,570 INFO L290 TraceCheckUtils]: 69: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,570 INFO L290 TraceCheckUtils]: 70: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,570 INFO L290 TraceCheckUtils]: 71: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,571 INFO L290 TraceCheckUtils]: 72: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,571 INFO L290 TraceCheckUtils]: 73: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,571 INFO L290 TraceCheckUtils]: 74: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,571 INFO L290 TraceCheckUtils]: 75: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,572 INFO L290 TraceCheckUtils]: 76: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,572 INFO L290 TraceCheckUtils]: 77: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,572 INFO L290 TraceCheckUtils]: 78: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,572 INFO L290 TraceCheckUtils]: 79: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,573 INFO L290 TraceCheckUtils]: 80: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,573 INFO L290 TraceCheckUtils]: 81: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,573 INFO L290 TraceCheckUtils]: 82: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,573 INFO L290 TraceCheckUtils]: 83: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,574 INFO L290 TraceCheckUtils]: 84: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,574 INFO L290 TraceCheckUtils]: 85: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,574 INFO L290 TraceCheckUtils]: 86: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,574 INFO L290 TraceCheckUtils]: 87: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,575 INFO L290 TraceCheckUtils]: 88: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,575 INFO L290 TraceCheckUtils]: 89: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,575 INFO L290 TraceCheckUtils]: 90: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,575 INFO L290 TraceCheckUtils]: 91: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,576 INFO L290 TraceCheckUtils]: 92: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,576 INFO L290 TraceCheckUtils]: 93: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,576 INFO L290 TraceCheckUtils]: 94: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,576 INFO L290 TraceCheckUtils]: 95: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,577 INFO L290 TraceCheckUtils]: 96: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,577 INFO L290 TraceCheckUtils]: 97: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,577 INFO L290 TraceCheckUtils]: 98: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,577 INFO L290 TraceCheckUtils]: 99: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,578 INFO L290 TraceCheckUtils]: 100: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,578 INFO L290 TraceCheckUtils]: 101: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,578 INFO L290 TraceCheckUtils]: 102: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,578 INFO L290 TraceCheckUtils]: 103: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 104: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {45004#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 105: Hoare triple {45004#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {45003#false} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 106: Hoare triple {45003#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 107: Hoare triple {45003#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 108: Hoare triple {45003#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 109: Hoare triple {45003#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 110: Hoare triple {45003#false} assume 1 == ~E_M~0;~E_M~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 111: Hoare triple {45003#false} assume 1 == ~E_1~0;~E_1~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,579 INFO L290 TraceCheckUtils]: 112: Hoare triple {45003#false} assume 1 == ~E_2~0;~E_2~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 113: Hoare triple {45003#false} assume !(1 == ~E_3~0); {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 114: Hoare triple {45003#false} assume 1 == ~E_4~0;~E_4~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 115: Hoare triple {45003#false} assume 1 == ~E_5~0;~E_5~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 116: Hoare triple {45003#false} assume 1 == ~E_6~0;~E_6~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 117: Hoare triple {45003#false} assume 1 == ~E_7~0;~E_7~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 118: Hoare triple {45003#false} assume 1 == ~E_8~0;~E_8~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 119: Hoare triple {45003#false} assume 1 == ~E_9~0;~E_9~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 120: Hoare triple {45003#false} assume 1 == ~E_10~0;~E_10~0 := 2; {45003#false} is VALID [2022-02-21 04:23:10,580 INFO L290 TraceCheckUtils]: 121: Hoare triple {45003#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 122: Hoare triple {45003#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 123: Hoare triple {45003#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 124: Hoare triple {45003#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 125: Hoare triple {45003#false} assume !(0 == start_simulation_~tmp~3#1); {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 126: Hoare triple {45003#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 127: Hoare triple {45003#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 128: Hoare triple {45003#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 129: Hoare triple {45003#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 130: Hoare triple {45003#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {45003#false} is VALID [2022-02-21 04:23:10,581 INFO L290 TraceCheckUtils]: 131: Hoare triple {45003#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {45003#false} is VALID [2022-02-21 04:23:10,582 INFO L290 TraceCheckUtils]: 132: Hoare triple {45003#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {45003#false} is VALID [2022-02-21 04:23:10,582 INFO L290 TraceCheckUtils]: 133: Hoare triple {45003#false} assume !(0 != start_simulation_~tmp___0~1#1); {45003#false} is VALID [2022-02-21 04:23:10,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,582 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,582 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480999760] [2022-02-21 04:23:10,582 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480999760] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,582 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,583 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,583 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029478459] [2022-02-21 04:23:10,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,583 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:10,583 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:10,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:10,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:10,584 INFO L87 Difference]: Start difference. First operand 1361 states and 2016 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,523 INFO L93 Difference]: Finished difference Result 1361 states and 2015 transitions. [2022-02-21 04:23:11,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:11,523 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,616 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:11,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:11,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2015 transitions. [2022-02-21 04:23:11,697 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-02-21 04:23:11,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-02-21 04:23:11,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:11,699 INFO L681 BuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-02-21 04:23:11,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-02-21 04:23:11,711 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:11,713 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1361 states and 2015 transitions. Second operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,714 INFO L74 IsIncluded]: Start isIncluded. First operand 1361 states and 2015 transitions. Second operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,715 INFO L87 Difference]: Start difference. First operand 1361 states and 2015 transitions. Second operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,753 INFO L93 Difference]: Finished difference Result 1361 states and 2015 transitions. [2022-02-21 04:23:11,753 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,754 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,755 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,756 INFO L74 IsIncluded]: Start isIncluded. First operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,757 INFO L87 Difference]: Start difference. First operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,796 INFO L93 Difference]: Finished difference Result 1361 states and 2015 transitions. [2022-02-21 04:23:11,796 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,797 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:11,797 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:11,797 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:11,797 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:11,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2015 transitions. [2022-02-21 04:23:11,838 INFO L704 BuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-02-21 04:23:11,838 INFO L587 BuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-02-21 04:23:11,838 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:11,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2015 transitions. [2022-02-21 04:23:11,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-02-21 04:23:11,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:11,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:11,842 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,842 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:11,842 INFO L791 eck$LassoCheckResult]: Stem: 47374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 47375#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 46415#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46416#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47305#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 47008#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47009#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47286#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47442#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47174#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47175#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47070#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47071#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47402#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47364#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47294#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47295#L1024 assume !(0 == ~M_E~0); 47538#L1024-2 assume !(0 == ~T1_E~0); 46742#L1029-1 assume !(0 == ~T2_E~0); 46743#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46849#L1039-1 assume !(0 == ~T4_E~0); 47656#L1044-1 assume !(0 == ~T5_E~0); 47086#L1049-1 assume !(0 == ~T6_E~0); 47087#L1054-1 assume !(0 == ~T7_E~0); 47312#L1059-1 assume !(0 == ~T8_E~0); 46789#L1064-1 assume !(0 == ~T9_E~0); 46790#L1069-1 assume !(0 == ~T10_E~0); 47506#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 47572#L1079-1 assume !(0 == ~E_1~0); 47540#L1084-1 assume !(0 == ~E_2~0); 47541#L1089-1 assume !(0 == ~E_3~0); 47591#L1094-1 assume !(0 == ~E_4~0); 47162#L1099-1 assume !(0 == ~E_5~0); 47163#L1104-1 assume !(0 == ~E_6~0); 47420#L1109-1 assume !(0 == ~E_7~0); 46963#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 46964#L1119-1 assume !(0 == ~E_9~0); 47024#L1124-1 assume !(0 == ~E_10~0); 46448#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46449#L502 assume 1 == ~m_pc~0; 47310#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46579#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46580#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47360#L1273 assume !(0 != activate_threads_~tmp~1#1); 47361#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47690#L521 assume !(1 == ~t1_pc~0); 47623#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46510#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46511#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46652#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 46490#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46491#L540 assume 1 == ~t2_pc~0; 47554#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47275#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47557#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47570#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 47617#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46764#L559 assume 1 == ~t3_pc~0; 46765#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47043#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47044#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47187#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 46595#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46596#L578 assume !(1 == ~t4_pc~0); 46714#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46713#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46484#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46485#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47342#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47343#L597 assume 1 == ~t5_pc~0; 47705#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46529#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46530#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47130#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 47291#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47292#L616 assume !(1 == ~t6_pc~0); 47308#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47307#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47672#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47217#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 47154#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47155#L635 assume 1 == ~t7_pc~0; 47347#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46498#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46869#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47515#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 47287#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47288#L654 assume !(1 == ~t8_pc~0); 47110#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47111#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47618#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47503#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 47504#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46740#L673 assume 1 == ~t9_pc~0; 46741#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46439#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47687#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47473#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 47429#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47430#L692 assume !(1 == ~t10_pc~0); 47378#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47377#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47296#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47166#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 47167#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47484#L1142 assume !(1 == ~M_E~0); 46655#L1142-2 assume !(1 == ~T1_E~0); 46656#L1147-1 assume !(1 == ~T2_E~0); 47474#L1152-1 assume !(1 == ~T3_E~0); 47050#L1157-1 assume !(1 == ~T4_E~0); 47051#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47191#L1167-1 assume !(1 == ~T6_E~0); 47192#L1172-1 assume !(1 == ~T7_E~0); 47611#L1177-1 assume !(1 == ~T8_E~0); 47329#L1182-1 assume !(1 == ~T9_E~0); 47330#L1187-1 assume !(1 == ~T10_E~0); 47423#L1192-1 assume !(1 == ~E_M~0); 46914#L1197-1 assume !(1 == ~E_1~0); 46915#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 47278#L1207-1 assume !(1 == ~E_3~0); 47257#L1212-1 assume !(1 == ~E_4~0); 46514#L1217-1 assume !(1 == ~E_5~0); 46515#L1222-1 assume !(1 == ~E_6~0); 47253#L1227-1 assume !(1 == ~E_7~0); 47254#L1232-1 assume !(1 == ~E_8~0); 46380#L1237-1 assume !(1 == ~E_9~0); 46381#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 47311#L1247-1 assume { :end_inline_reset_delta_events } true; 46554#L1553-2 [2022-02-21 04:23:11,843 INFO L793 eck$LassoCheckResult]: Loop: 46554#L1553-2 assume !false; 46555#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47464#L999 assume !false; 47510#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 46639#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 46532#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 47027#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 47381#L854 assume !(0 != eval_~tmp~0#1); 47382#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46826#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46827#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47644#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47153#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47123#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47124#L1039-3 assume !(0 == ~T4_E~0); 47447#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46734#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46735#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46508#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 46509#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47095#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47096#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47425#L1079-3 assume !(0 == ~E_1~0); 47322#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47210#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47211#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47140#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47141#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47445#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47433#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47434#L1119-3 assume !(0 == ~E_9~0); 47714#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47721#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47681#L502-36 assume !(1 == ~m_pc~0); 46881#L502-38 is_master_triggered_~__retres1~0#1 := 0; 46366#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46367#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46791#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46792#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47065#L521-36 assume 1 == ~t1_pc~0; 47066#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47079#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47246#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47283#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47508#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47509#L540-36 assume 1 == ~t2_pc~0; 47683#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46456#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46870#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47722#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47186#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46377#L559-36 assume 1 == ~t3_pc~0; 46378#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46834#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46684#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46685#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47331#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47567#L578-36 assume 1 == ~t4_pc~0; 47302#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47264#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47597#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47598#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47101#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47102#L597-36 assume !(1 == ~t5_pc~0); 47320#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 47670#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47244#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47245#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 46916#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46917#L616-36 assume 1 == ~t6_pc~0; 47684#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46444#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46445#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47047#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47148#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47463#L635-36 assume !(1 == ~t7_pc~0); 47648#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 47520#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47193#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47194#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47136#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47137#L654-36 assume !(1 == ~t8_pc~0); 47651#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 47652#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47724#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47709#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47691#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46819#L673-36 assume !(1 == ~t9_pc~0); 46820#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 47172#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47173#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47527#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46387#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46388#L692-36 assume 1 == ~t10_pc~0; 47323#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46604#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47147#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46782#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46783#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47146#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47293#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47653#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47654#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47224#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47225#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47516#L1167-3 assume !(1 == ~T6_E~0); 47638#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47135#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47039#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47040#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47053#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46878#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46879#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47120#L1207-3 assume !(1 == ~E_3~0); 47235#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47443#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46774#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46471#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46472#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47548#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47549#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47723#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 47601#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 46623#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 46624#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 47303#L1572 assume !(0 == start_simulation_~tmp~3#1); 46921#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 47072#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 46401#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 47675#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 47676#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46370#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46371#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 47525#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 46554#L1553-2 [2022-02-21 04:23:11,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,844 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2022-02-21 04:23:11,844 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,844 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832753909] [2022-02-21 04:23:11,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,875 INFO L290 TraceCheckUtils]: 0: Hoare triple {50452#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,875 INFO L290 TraceCheckUtils]: 1: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,875 INFO L290 TraceCheckUtils]: 2: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,876 INFO L290 TraceCheckUtils]: 3: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,876 INFO L290 TraceCheckUtils]: 4: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,876 INFO L290 TraceCheckUtils]: 5: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,876 INFO L290 TraceCheckUtils]: 6: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,877 INFO L290 TraceCheckUtils]: 7: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,877 INFO L290 TraceCheckUtils]: 8: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,877 INFO L290 TraceCheckUtils]: 9: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,877 INFO L290 TraceCheckUtils]: 10: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,878 INFO L290 TraceCheckUtils]: 11: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,878 INFO L290 TraceCheckUtils]: 12: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,878 INFO L290 TraceCheckUtils]: 13: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,878 INFO L290 TraceCheckUtils]: 14: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,879 INFO L290 TraceCheckUtils]: 15: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {50454#(= ~T3_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:11,879 INFO L290 TraceCheckUtils]: 16: Hoare triple {50454#(= ~T3_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {50455#(not (= ~T3_E~0 0))} is VALID [2022-02-21 04:23:11,879 INFO L290 TraceCheckUtils]: 17: Hoare triple {50455#(not (= ~T3_E~0 0))} assume !(0 == ~T1_E~0); {50455#(not (= ~T3_E~0 0))} is VALID [2022-02-21 04:23:11,879 INFO L290 TraceCheckUtils]: 18: Hoare triple {50455#(not (= ~T3_E~0 0))} assume !(0 == ~T2_E~0); {50455#(not (= ~T3_E~0 0))} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 19: Hoare triple {50455#(not (= ~T3_E~0 0))} assume 0 == ~T3_E~0;~T3_E~0 := 1; {50453#false} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 20: Hoare triple {50453#false} assume !(0 == ~T4_E~0); {50453#false} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 21: Hoare triple {50453#false} assume !(0 == ~T5_E~0); {50453#false} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 22: Hoare triple {50453#false} assume !(0 == ~T6_E~0); {50453#false} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 23: Hoare triple {50453#false} assume !(0 == ~T7_E~0); {50453#false} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 24: Hoare triple {50453#false} assume !(0 == ~T8_E~0); {50453#false} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 25: Hoare triple {50453#false} assume !(0 == ~T9_E~0); {50453#false} is VALID [2022-02-21 04:23:11,880 INFO L290 TraceCheckUtils]: 26: Hoare triple {50453#false} assume !(0 == ~T10_E~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 27: Hoare triple {50453#false} assume 0 == ~E_M~0;~E_M~0 := 1; {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 28: Hoare triple {50453#false} assume !(0 == ~E_1~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 29: Hoare triple {50453#false} assume !(0 == ~E_2~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 30: Hoare triple {50453#false} assume !(0 == ~E_3~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 31: Hoare triple {50453#false} assume !(0 == ~E_4~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 32: Hoare triple {50453#false} assume !(0 == ~E_5~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 33: Hoare triple {50453#false} assume !(0 == ~E_6~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 34: Hoare triple {50453#false} assume !(0 == ~E_7~0); {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 35: Hoare triple {50453#false} assume 0 == ~E_8~0;~E_8~0 := 1; {50453#false} is VALID [2022-02-21 04:23:11,881 INFO L290 TraceCheckUtils]: 36: Hoare triple {50453#false} assume !(0 == ~E_9~0); {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 37: Hoare triple {50453#false} assume !(0 == ~E_10~0); {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 38: Hoare triple {50453#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 39: Hoare triple {50453#false} assume 1 == ~m_pc~0; {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 40: Hoare triple {50453#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 41: Hoare triple {50453#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 42: Hoare triple {50453#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 43: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp~1#1); {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 44: Hoare triple {50453#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 45: Hoare triple {50453#false} assume !(1 == ~t1_pc~0); {50453#false} is VALID [2022-02-21 04:23:11,882 INFO L290 TraceCheckUtils]: 46: Hoare triple {50453#false} is_transmit1_triggered_~__retres1~1#1 := 0; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 47: Hoare triple {50453#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 48: Hoare triple {50453#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 49: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___0~0#1); {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 50: Hoare triple {50453#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 51: Hoare triple {50453#false} assume 1 == ~t2_pc~0; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 52: Hoare triple {50453#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 53: Hoare triple {50453#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 54: Hoare triple {50453#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 55: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___1~0#1); {50453#false} is VALID [2022-02-21 04:23:11,883 INFO L290 TraceCheckUtils]: 56: Hoare triple {50453#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 57: Hoare triple {50453#false} assume 1 == ~t3_pc~0; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 58: Hoare triple {50453#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 59: Hoare triple {50453#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 60: Hoare triple {50453#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 61: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___2~0#1); {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 62: Hoare triple {50453#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 63: Hoare triple {50453#false} assume !(1 == ~t4_pc~0); {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 64: Hoare triple {50453#false} is_transmit4_triggered_~__retres1~4#1 := 0; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 65: Hoare triple {50453#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50453#false} is VALID [2022-02-21 04:23:11,884 INFO L290 TraceCheckUtils]: 66: Hoare triple {50453#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 67: Hoare triple {50453#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 68: Hoare triple {50453#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 69: Hoare triple {50453#false} assume 1 == ~t5_pc~0; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 70: Hoare triple {50453#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 71: Hoare triple {50453#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 72: Hoare triple {50453#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 73: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___4~0#1); {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 74: Hoare triple {50453#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 75: Hoare triple {50453#false} assume !(1 == ~t6_pc~0); {50453#false} is VALID [2022-02-21 04:23:11,885 INFO L290 TraceCheckUtils]: 76: Hoare triple {50453#false} is_transmit6_triggered_~__retres1~6#1 := 0; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 77: Hoare triple {50453#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 78: Hoare triple {50453#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 79: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___5~0#1); {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 80: Hoare triple {50453#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 81: Hoare triple {50453#false} assume 1 == ~t7_pc~0; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 82: Hoare triple {50453#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 83: Hoare triple {50453#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 84: Hoare triple {50453#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 85: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___6~0#1); {50453#false} is VALID [2022-02-21 04:23:11,886 INFO L290 TraceCheckUtils]: 86: Hoare triple {50453#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 87: Hoare triple {50453#false} assume !(1 == ~t8_pc~0); {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 88: Hoare triple {50453#false} is_transmit8_triggered_~__retres1~8#1 := 0; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 89: Hoare triple {50453#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 90: Hoare triple {50453#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 91: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___7~0#1); {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 92: Hoare triple {50453#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 93: Hoare triple {50453#false} assume 1 == ~t9_pc~0; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 94: Hoare triple {50453#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 95: Hoare triple {50453#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50453#false} is VALID [2022-02-21 04:23:11,887 INFO L290 TraceCheckUtils]: 96: Hoare triple {50453#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 97: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___8~0#1); {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 98: Hoare triple {50453#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 99: Hoare triple {50453#false} assume !(1 == ~t10_pc~0); {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 100: Hoare triple {50453#false} is_transmit10_triggered_~__retres1~10#1 := 0; {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 101: Hoare triple {50453#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 102: Hoare triple {50453#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 103: Hoare triple {50453#false} assume !(0 != activate_threads_~tmp___9~0#1); {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 104: Hoare triple {50453#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50453#false} is VALID [2022-02-21 04:23:11,888 INFO L290 TraceCheckUtils]: 105: Hoare triple {50453#false} assume !(1 == ~M_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 106: Hoare triple {50453#false} assume !(1 == ~T1_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 107: Hoare triple {50453#false} assume !(1 == ~T2_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 108: Hoare triple {50453#false} assume !(1 == ~T3_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 109: Hoare triple {50453#false} assume !(1 == ~T4_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 110: Hoare triple {50453#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 111: Hoare triple {50453#false} assume !(1 == ~T6_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 112: Hoare triple {50453#false} assume !(1 == ~T7_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 113: Hoare triple {50453#false} assume !(1 == ~T8_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 114: Hoare triple {50453#false} assume !(1 == ~T9_E~0); {50453#false} is VALID [2022-02-21 04:23:11,889 INFO L290 TraceCheckUtils]: 115: Hoare triple {50453#false} assume !(1 == ~T10_E~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 116: Hoare triple {50453#false} assume !(1 == ~E_M~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 117: Hoare triple {50453#false} assume !(1 == ~E_1~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 118: Hoare triple {50453#false} assume 1 == ~E_2~0;~E_2~0 := 2; {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 119: Hoare triple {50453#false} assume !(1 == ~E_3~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 120: Hoare triple {50453#false} assume !(1 == ~E_4~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 121: Hoare triple {50453#false} assume !(1 == ~E_5~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 122: Hoare triple {50453#false} assume !(1 == ~E_6~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 123: Hoare triple {50453#false} assume !(1 == ~E_7~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 124: Hoare triple {50453#false} assume !(1 == ~E_8~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 125: Hoare triple {50453#false} assume !(1 == ~E_9~0); {50453#false} is VALID [2022-02-21 04:23:11,890 INFO L290 TraceCheckUtils]: 126: Hoare triple {50453#false} assume 1 == ~E_10~0;~E_10~0 := 2; {50453#false} is VALID [2022-02-21 04:23:11,891 INFO L290 TraceCheckUtils]: 127: Hoare triple {50453#false} assume { :end_inline_reset_delta_events } true; {50453#false} is VALID [2022-02-21 04:23:11,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,891 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,891 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832753909] [2022-02-21 04:23:11,891 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832753909] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,891 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,891 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,892 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239145615] [2022-02-21 04:23:11,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,893 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:11,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:11,893 INFO L85 PathProgramCache]: Analyzing trace with hash 131639478, now seen corresponding path program 1 times [2022-02-21 04:23:11,893 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:11,895 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231203481] [2022-02-21 04:23:11,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:11,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:11,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 0: Hoare triple {50456#true} assume !false; {50456#true} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 1: Hoare triple {50456#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {50456#true} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 2: Hoare triple {50456#true} assume !false; {50456#true} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 3: Hoare triple {50456#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {50456#true} is VALID [2022-02-21 04:23:11,924 INFO L290 TraceCheckUtils]: 4: Hoare triple {50456#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 5: Hoare triple {50456#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 6: Hoare triple {50456#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 7: Hoare triple {50456#true} assume !(0 != eval_~tmp~0#1); {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 8: Hoare triple {50456#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 9: Hoare triple {50456#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 10: Hoare triple {50456#true} assume 0 == ~M_E~0;~M_E~0 := 1; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 11: Hoare triple {50456#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 12: Hoare triple {50456#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 13: Hoare triple {50456#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {50456#true} is VALID [2022-02-21 04:23:11,925 INFO L290 TraceCheckUtils]: 14: Hoare triple {50456#true} assume !(0 == ~T4_E~0); {50456#true} is VALID [2022-02-21 04:23:11,926 INFO L290 TraceCheckUtils]: 15: Hoare triple {50456#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {50456#true} is VALID [2022-02-21 04:23:11,926 INFO L290 TraceCheckUtils]: 16: Hoare triple {50456#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,926 INFO L290 TraceCheckUtils]: 17: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,926 INFO L290 TraceCheckUtils]: 18: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,927 INFO L290 TraceCheckUtils]: 19: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,927 INFO L290 TraceCheckUtils]: 20: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,927 INFO L290 TraceCheckUtils]: 21: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,927 INFO L290 TraceCheckUtils]: 22: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,928 INFO L290 TraceCheckUtils]: 23: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,928 INFO L290 TraceCheckUtils]: 24: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,928 INFO L290 TraceCheckUtils]: 25: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,928 INFO L290 TraceCheckUtils]: 26: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,929 INFO L290 TraceCheckUtils]: 27: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,929 INFO L290 TraceCheckUtils]: 28: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,929 INFO L290 TraceCheckUtils]: 29: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,929 INFO L290 TraceCheckUtils]: 30: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,930 INFO L290 TraceCheckUtils]: 31: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,930 INFO L290 TraceCheckUtils]: 32: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,930 INFO L290 TraceCheckUtils]: 33: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,931 INFO L290 TraceCheckUtils]: 34: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,931 INFO L290 TraceCheckUtils]: 35: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,931 INFO L290 TraceCheckUtils]: 36: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,931 INFO L290 TraceCheckUtils]: 37: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,932 INFO L290 TraceCheckUtils]: 38: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,932 INFO L290 TraceCheckUtils]: 39: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,932 INFO L290 TraceCheckUtils]: 40: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,932 INFO L290 TraceCheckUtils]: 41: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,933 INFO L290 TraceCheckUtils]: 42: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,933 INFO L290 TraceCheckUtils]: 43: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,933 INFO L290 TraceCheckUtils]: 44: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,933 INFO L290 TraceCheckUtils]: 45: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,934 INFO L290 TraceCheckUtils]: 46: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,934 INFO L290 TraceCheckUtils]: 47: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,934 INFO L290 TraceCheckUtils]: 48: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,934 INFO L290 TraceCheckUtils]: 49: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,935 INFO L290 TraceCheckUtils]: 50: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,935 INFO L290 TraceCheckUtils]: 51: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,935 INFO L290 TraceCheckUtils]: 52: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,935 INFO L290 TraceCheckUtils]: 53: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,936 INFO L290 TraceCheckUtils]: 54: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,936 INFO L290 TraceCheckUtils]: 55: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,936 INFO L290 TraceCheckUtils]: 56: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,936 INFO L290 TraceCheckUtils]: 57: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,937 INFO L290 TraceCheckUtils]: 58: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,937 INFO L290 TraceCheckUtils]: 59: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,937 INFO L290 TraceCheckUtils]: 60: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,937 INFO L290 TraceCheckUtils]: 61: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,938 INFO L290 TraceCheckUtils]: 62: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,938 INFO L290 TraceCheckUtils]: 63: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,938 INFO L290 TraceCheckUtils]: 64: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,938 INFO L290 TraceCheckUtils]: 65: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,939 INFO L290 TraceCheckUtils]: 66: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,939 INFO L290 TraceCheckUtils]: 67: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,939 INFO L290 TraceCheckUtils]: 68: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,939 INFO L290 TraceCheckUtils]: 69: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,940 INFO L290 TraceCheckUtils]: 70: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,940 INFO L290 TraceCheckUtils]: 71: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,940 INFO L290 TraceCheckUtils]: 72: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,940 INFO L290 TraceCheckUtils]: 73: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,941 INFO L290 TraceCheckUtils]: 74: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,941 INFO L290 TraceCheckUtils]: 75: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,941 INFO L290 TraceCheckUtils]: 76: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,941 INFO L290 TraceCheckUtils]: 77: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,942 INFO L290 TraceCheckUtils]: 78: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,942 INFO L290 TraceCheckUtils]: 79: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,942 INFO L290 TraceCheckUtils]: 80: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,942 INFO L290 TraceCheckUtils]: 81: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,943 INFO L290 TraceCheckUtils]: 82: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,943 INFO L290 TraceCheckUtils]: 83: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,943 INFO L290 TraceCheckUtils]: 84: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,943 INFO L290 TraceCheckUtils]: 85: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,944 INFO L290 TraceCheckUtils]: 86: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,944 INFO L290 TraceCheckUtils]: 87: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,944 INFO L290 TraceCheckUtils]: 88: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,944 INFO L290 TraceCheckUtils]: 89: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,945 INFO L290 TraceCheckUtils]: 90: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,945 INFO L290 TraceCheckUtils]: 91: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,945 INFO L290 TraceCheckUtils]: 92: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,945 INFO L290 TraceCheckUtils]: 93: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,946 INFO L290 TraceCheckUtils]: 94: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,946 INFO L290 TraceCheckUtils]: 95: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,946 INFO L290 TraceCheckUtils]: 96: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,946 INFO L290 TraceCheckUtils]: 97: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,947 INFO L290 TraceCheckUtils]: 98: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,947 INFO L290 TraceCheckUtils]: 99: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,947 INFO L290 TraceCheckUtils]: 100: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,947 INFO L290 TraceCheckUtils]: 101: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,948 INFO L290 TraceCheckUtils]: 102: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,948 INFO L290 TraceCheckUtils]: 103: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,948 INFO L290 TraceCheckUtils]: 104: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {50458#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:11,948 INFO L290 TraceCheckUtils]: 105: Hoare triple {50458#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 106: Hoare triple {50457#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 107: Hoare triple {50457#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 108: Hoare triple {50457#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 109: Hoare triple {50457#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 110: Hoare triple {50457#false} assume 1 == ~E_M~0;~E_M~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 111: Hoare triple {50457#false} assume 1 == ~E_1~0;~E_1~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 112: Hoare triple {50457#false} assume 1 == ~E_2~0;~E_2~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 113: Hoare triple {50457#false} assume !(1 == ~E_3~0); {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 114: Hoare triple {50457#false} assume 1 == ~E_4~0;~E_4~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,949 INFO L290 TraceCheckUtils]: 115: Hoare triple {50457#false} assume 1 == ~E_5~0;~E_5~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 116: Hoare triple {50457#false} assume 1 == ~E_6~0;~E_6~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 117: Hoare triple {50457#false} assume 1 == ~E_7~0;~E_7~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 118: Hoare triple {50457#false} assume 1 == ~E_8~0;~E_8~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 119: Hoare triple {50457#false} assume 1 == ~E_9~0;~E_9~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 120: Hoare triple {50457#false} assume 1 == ~E_10~0;~E_10~0 := 2; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 121: Hoare triple {50457#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 122: Hoare triple {50457#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 123: Hoare triple {50457#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 124: Hoare triple {50457#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {50457#false} is VALID [2022-02-21 04:23:11,950 INFO L290 TraceCheckUtils]: 125: Hoare triple {50457#false} assume !(0 == start_simulation_~tmp~3#1); {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 126: Hoare triple {50457#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 127: Hoare triple {50457#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 128: Hoare triple {50457#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 129: Hoare triple {50457#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 130: Hoare triple {50457#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 131: Hoare triple {50457#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 132: Hoare triple {50457#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {50457#false} is VALID [2022-02-21 04:23:11,951 INFO L290 TraceCheckUtils]: 133: Hoare triple {50457#false} assume !(0 != start_simulation_~tmp___0~1#1); {50457#false} is VALID [2022-02-21 04:23:11,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:11,952 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:11,952 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231203481] [2022-02-21 04:23:11,952 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231203481] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:11,952 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:11,952 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:11,952 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127573662] [2022-02-21 04:23:11,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:11,953 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:11,953 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:11,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:11,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:11,954 INFO L87 Difference]: Start difference. First operand 1361 states and 2015 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,405 INFO L93 Difference]: Finished difference Result 2504 states and 3694 transitions. [2022-02-21 04:23:14,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:14,406 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,459 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:14,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2504 states and 3694 transitions. [2022-02-21 04:23:14,606 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2022-02-21 04:23:14,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2504 states to 2504 states and 3694 transitions. [2022-02-21 04:23:14,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2504 [2022-02-21 04:23:14,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2504 [2022-02-21 04:23:14,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2504 states and 3694 transitions. [2022-02-21 04:23:14,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:14,757 INFO L681 BuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-02-21 04:23:14,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2504 states and 3694 transitions. [2022-02-21 04:23:14,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2504 to 2504. [2022-02-21 04:23:14,783 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:14,786 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2504 states and 3694 transitions. Second operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,788 INFO L74 IsIncluded]: Start isIncluded. First operand 2504 states and 3694 transitions. Second operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,790 INFO L87 Difference]: Start difference. First operand 2504 states and 3694 transitions. Second operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,915 INFO L93 Difference]: Finished difference Result 2504 states and 3694 transitions. [2022-02-21 04:23:14,915 INFO L276 IsEmpty]: Start isEmpty. Operand 2504 states and 3694 transitions. [2022-02-21 04:23:14,917 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,917 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,920 INFO L74 IsIncluded]: Start isIncluded. First operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2504 states and 3694 transitions. [2022-02-21 04:23:14,922 INFO L87 Difference]: Start difference. First operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2504 states and 3694 transitions. [2022-02-21 04:23:15,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,068 INFO L93 Difference]: Finished difference Result 2504 states and 3694 transitions. [2022-02-21 04:23:15,068 INFO L276 IsEmpty]: Start isEmpty. Operand 2504 states and 3694 transitions. [2022-02-21 04:23:15,070 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:15,070 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:15,070 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:15,070 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:15,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2504 states to 2504 states and 3694 transitions. [2022-02-21 04:23:15,198 INFO L704 BuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-02-21 04:23:15,198 INFO L587 BuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-02-21 04:23:15,198 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:15,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2504 states and 3694 transitions. [2022-02-21 04:23:15,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2022-02-21 04:23:15,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:15,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:15,203 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,203 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,204 INFO L791 eck$LassoCheckResult]: Stem: 53978#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 53979#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 53014#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53015#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53908#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 53608#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53609#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53889#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54046#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53775#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53776#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53663#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53664#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54006#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53968#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53894#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53895#L1024 assume !(0 == ~M_E~0); 54147#L1024-2 assume !(0 == ~T1_E~0); 53343#L1029-1 assume !(0 == ~T2_E~0); 53344#L1034-1 assume !(0 == ~T3_E~0); 53450#L1039-1 assume !(0 == ~T4_E~0); 54268#L1044-1 assume !(0 == ~T5_E~0); 53686#L1049-1 assume !(0 == ~T6_E~0); 53687#L1054-1 assume !(0 == ~T7_E~0); 53916#L1059-1 assume !(0 == ~T8_E~0); 53390#L1064-1 assume !(0 == ~T9_E~0); 53391#L1069-1 assume !(0 == ~T10_E~0); 54113#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 54182#L1079-1 assume !(0 == ~E_1~0); 54149#L1084-1 assume !(0 == ~E_2~0); 54150#L1089-1 assume !(0 == ~E_3~0); 54201#L1094-1 assume !(0 == ~E_4~0); 53765#L1099-1 assume !(0 == ~E_5~0); 53766#L1104-1 assume !(0 == ~E_6~0); 54024#L1109-1 assume !(0 == ~E_7~0); 53564#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 53565#L1119-1 assume !(0 == ~E_9~0); 53619#L1124-1 assume !(0 == ~E_10~0); 53047#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53048#L502 assume 1 == ~m_pc~0; 53914#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53176#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53177#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53963#L1273 assume !(0 != activate_threads_~tmp~1#1); 53964#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54314#L521 assume !(1 == ~t1_pc~0); 54234#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53107#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53108#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53250#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 53089#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53090#L540 assume 1 == ~t2_pc~0; 54164#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53878#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54167#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54180#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 54228#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53365#L559 assume 1 == ~t3_pc~0; 53366#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53644#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53645#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53790#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 53194#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53195#L578 assume !(1 == ~t4_pc~0); 53315#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53314#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53083#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53084#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53946#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53947#L597 assume 1 == ~t5_pc~0; 54338#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53128#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53129#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53732#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 53896#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53897#L616 assume !(1 == ~t6_pc~0); 53912#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53911#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54290#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53820#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 53757#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53758#L635 assume 1 == ~t7_pc~0; 53951#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53097#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53470#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54122#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 53890#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53891#L654 assume !(1 == ~t8_pc~0); 53712#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 53713#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54229#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54110#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 54111#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53341#L673 assume 1 == ~t9_pc~0; 53342#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53038#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54310#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54078#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 54033#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54034#L692 assume !(1 == ~t10_pc~0); 53982#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53981#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53900#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53769#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 53770#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54090#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 53254#L1142-2 assume !(1 == ~T1_E~0); 53255#L1147-1 assume !(1 == ~T2_E~0); 54079#L1152-1 assume !(1 == ~T3_E~0); 53651#L1157-1 assume !(1 == ~T4_E~0); 53652#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54494#L1167-1 assume !(1 == ~T6_E~0); 54483#L1172-1 assume !(1 == ~T7_E~0); 54481#L1177-1 assume !(1 == ~T8_E~0); 54479#L1182-1 assume !(1 == ~T9_E~0); 54477#L1187-1 assume !(1 == ~T10_E~0); 54443#L1192-1 assume !(1 == ~E_M~0); 54442#L1197-1 assume !(1 == ~E_1~0); 54441#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 53881#L1207-1 assume !(1 == ~E_3~0); 53860#L1212-1 assume !(1 == ~E_4~0); 53113#L1217-1 assume !(1 == ~E_5~0); 53114#L1222-1 assume !(1 == ~E_6~0); 53856#L1227-1 assume !(1 == ~E_7~0); 53857#L1232-1 assume !(1 == ~E_8~0); 52979#L1237-1 assume !(1 == ~E_9~0); 52980#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 53915#L1247-1 assume { :end_inline_reset_delta_events } true; 53153#L1553-2 [2022-02-21 04:23:15,204 INFO L793 eck$LassoCheckResult]: Loop: 53153#L1553-2 assume !false; 53154#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54068#L999 assume !false; 54117#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 53238#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 53131#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 53628#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54372#L854 assume !(0 != eval_~tmp~0#1); 54371#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54370#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54369#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54257#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53756#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53725#L1034-3 assume !(0 == ~T3_E~0); 53726#L1039-3 assume !(0 == ~T4_E~0); 54051#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53335#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53336#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53109#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53110#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53697#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53698#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54029#L1079-3 assume !(0 == ~E_1~0); 53926#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53813#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53814#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53742#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53743#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54049#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54037#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54038#L1119-3 assume !(0 == ~E_9~0); 54349#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 54359#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54303#L502-36 assume 1 == ~m_pc~0; 54052#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52965#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52966#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53392#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53393#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53668#L521-36 assume 1 == ~t1_pc~0; 53669#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53681#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53849#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53886#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54115#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54116#L540-36 assume 1 == ~t2_pc~0; 54306#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53055#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53471#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54360#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53789#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52976#L559-36 assume 1 == ~t3_pc~0; 52977#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53435#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53283#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53284#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53935#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54177#L578-36 assume 1 == ~t4_pc~0; 53906#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53867#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54207#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54208#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53703#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53704#L597-36 assume !(1 == ~t5_pc~0); 53924#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 54288#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53847#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53848#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 53517#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53518#L616-36 assume 1 == ~t6_pc~0; 54307#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53043#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53044#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53648#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53751#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54067#L635-36 assume 1 == ~t7_pc~0; 54260#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54128#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53796#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53797#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53738#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53739#L654-36 assume 1 == ~t8_pc~0; 54352#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54265#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54363#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54342#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54316#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53420#L673-36 assume !(1 == ~t9_pc~0); 53421#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 53777#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53778#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55360#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55359#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55358#L692-36 assume 1 == ~t10_pc~0; 55356#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55355#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55354#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55353#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55352#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55351#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53898#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55350#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55349#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54292#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55348#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55347#L1167-3 assume !(1 == ~T6_E~0); 55346#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55345#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55344#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55343#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55342#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55341#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55340#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55339#L1207-3 assume !(1 == ~E_3~0); 55338#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55337#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55336#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55335#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 55334#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 55333#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55332#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 55331#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 55320#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 55120#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 55119#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 55118#L1572 assume !(0 == start_simulation_~tmp~3#1); 53522#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 54358#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 53000#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 54296#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 54298#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52969#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52970#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 54133#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 53153#L1553-2 [2022-02-21 04:23:15,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,205 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2022-02-21 04:23:15,205 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,205 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248383667] [2022-02-21 04:23:15,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 0: Hoare triple {60480#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 1: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 2: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 3: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 4: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 5: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 6: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 7: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 8: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 9: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 10: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 11: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 12: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 13: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 14: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 15: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {60482#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 16: Hoare triple {60482#(= ~E_M~0 ~M_E~0)} assume !(0 == ~M_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,231 INFO L290 TraceCheckUtils]: 17: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T1_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,231 INFO L290 TraceCheckUtils]: 18: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T2_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,231 INFO L290 TraceCheckUtils]: 19: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T3_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,231 INFO L290 TraceCheckUtils]: 20: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T4_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,232 INFO L290 TraceCheckUtils]: 21: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T5_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,232 INFO L290 TraceCheckUtils]: 22: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T6_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,232 INFO L290 TraceCheckUtils]: 23: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T7_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,232 INFO L290 TraceCheckUtils]: 24: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T8_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,233 INFO L290 TraceCheckUtils]: 25: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T9_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,233 INFO L290 TraceCheckUtils]: 26: Hoare triple {60483#(not (= ~E_M~0 0))} assume !(0 == ~T10_E~0); {60483#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:23:15,233 INFO L290 TraceCheckUtils]: 27: Hoare triple {60483#(not (= ~E_M~0 0))} assume 0 == ~E_M~0;~E_M~0 := 1; {60481#false} is VALID [2022-02-21 04:23:15,233 INFO L290 TraceCheckUtils]: 28: Hoare triple {60481#false} assume !(0 == ~E_1~0); {60481#false} is VALID [2022-02-21 04:23:15,233 INFO L290 TraceCheckUtils]: 29: Hoare triple {60481#false} assume !(0 == ~E_2~0); {60481#false} is VALID [2022-02-21 04:23:15,233 INFO L290 TraceCheckUtils]: 30: Hoare triple {60481#false} assume !(0 == ~E_3~0); {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 31: Hoare triple {60481#false} assume !(0 == ~E_4~0); {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 32: Hoare triple {60481#false} assume !(0 == ~E_5~0); {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 33: Hoare triple {60481#false} assume !(0 == ~E_6~0); {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 34: Hoare triple {60481#false} assume !(0 == ~E_7~0); {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 35: Hoare triple {60481#false} assume 0 == ~E_8~0;~E_8~0 := 1; {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 36: Hoare triple {60481#false} assume !(0 == ~E_9~0); {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 37: Hoare triple {60481#false} assume !(0 == ~E_10~0); {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 38: Hoare triple {60481#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {60481#false} is VALID [2022-02-21 04:23:15,234 INFO L290 TraceCheckUtils]: 39: Hoare triple {60481#false} assume 1 == ~m_pc~0; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 40: Hoare triple {60481#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 41: Hoare triple {60481#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 42: Hoare triple {60481#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 43: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp~1#1); {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 44: Hoare triple {60481#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 45: Hoare triple {60481#false} assume !(1 == ~t1_pc~0); {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 46: Hoare triple {60481#false} is_transmit1_triggered_~__retres1~1#1 := 0; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 47: Hoare triple {60481#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 48: Hoare triple {60481#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {60481#false} is VALID [2022-02-21 04:23:15,235 INFO L290 TraceCheckUtils]: 49: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___0~0#1); {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 50: Hoare triple {60481#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 51: Hoare triple {60481#false} assume 1 == ~t2_pc~0; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 52: Hoare triple {60481#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 53: Hoare triple {60481#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 54: Hoare triple {60481#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 55: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___1~0#1); {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 56: Hoare triple {60481#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 57: Hoare triple {60481#false} assume 1 == ~t3_pc~0; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 58: Hoare triple {60481#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {60481#false} is VALID [2022-02-21 04:23:15,236 INFO L290 TraceCheckUtils]: 59: Hoare triple {60481#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 60: Hoare triple {60481#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 61: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___2~0#1); {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 62: Hoare triple {60481#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 63: Hoare triple {60481#false} assume !(1 == ~t4_pc~0); {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 64: Hoare triple {60481#false} is_transmit4_triggered_~__retres1~4#1 := 0; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 65: Hoare triple {60481#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 66: Hoare triple {60481#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 67: Hoare triple {60481#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 68: Hoare triple {60481#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {60481#false} is VALID [2022-02-21 04:23:15,237 INFO L290 TraceCheckUtils]: 69: Hoare triple {60481#false} assume 1 == ~t5_pc~0; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 70: Hoare triple {60481#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 71: Hoare triple {60481#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 72: Hoare triple {60481#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 73: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___4~0#1); {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 74: Hoare triple {60481#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 75: Hoare triple {60481#false} assume !(1 == ~t6_pc~0); {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 76: Hoare triple {60481#false} is_transmit6_triggered_~__retres1~6#1 := 0; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 77: Hoare triple {60481#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 78: Hoare triple {60481#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {60481#false} is VALID [2022-02-21 04:23:15,238 INFO L290 TraceCheckUtils]: 79: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___5~0#1); {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 80: Hoare triple {60481#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 81: Hoare triple {60481#false} assume 1 == ~t7_pc~0; {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 82: Hoare triple {60481#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 83: Hoare triple {60481#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 84: Hoare triple {60481#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 85: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___6~0#1); {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 86: Hoare triple {60481#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 87: Hoare triple {60481#false} assume !(1 == ~t8_pc~0); {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 88: Hoare triple {60481#false} is_transmit8_triggered_~__retres1~8#1 := 0; {60481#false} is VALID [2022-02-21 04:23:15,239 INFO L290 TraceCheckUtils]: 89: Hoare triple {60481#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 90: Hoare triple {60481#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 91: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___7~0#1); {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 92: Hoare triple {60481#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 93: Hoare triple {60481#false} assume 1 == ~t9_pc~0; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 94: Hoare triple {60481#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 95: Hoare triple {60481#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 96: Hoare triple {60481#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 97: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___8~0#1); {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 98: Hoare triple {60481#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {60481#false} is VALID [2022-02-21 04:23:15,240 INFO L290 TraceCheckUtils]: 99: Hoare triple {60481#false} assume !(1 == ~t10_pc~0); {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 100: Hoare triple {60481#false} is_transmit10_triggered_~__retres1~10#1 := 0; {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 101: Hoare triple {60481#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 102: Hoare triple {60481#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 103: Hoare triple {60481#false} assume !(0 != activate_threads_~tmp___9~0#1); {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 104: Hoare triple {60481#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 105: Hoare triple {60481#false} assume 1 == ~M_E~0;~M_E~0 := 2; {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 106: Hoare triple {60481#false} assume !(1 == ~T1_E~0); {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 107: Hoare triple {60481#false} assume !(1 == ~T2_E~0); {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 108: Hoare triple {60481#false} assume !(1 == ~T3_E~0); {60481#false} is VALID [2022-02-21 04:23:15,241 INFO L290 TraceCheckUtils]: 109: Hoare triple {60481#false} assume !(1 == ~T4_E~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 110: Hoare triple {60481#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 111: Hoare triple {60481#false} assume !(1 == ~T6_E~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 112: Hoare triple {60481#false} assume !(1 == ~T7_E~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 113: Hoare triple {60481#false} assume !(1 == ~T8_E~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 114: Hoare triple {60481#false} assume !(1 == ~T9_E~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 115: Hoare triple {60481#false} assume !(1 == ~T10_E~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 116: Hoare triple {60481#false} assume !(1 == ~E_M~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 117: Hoare triple {60481#false} assume !(1 == ~E_1~0); {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 118: Hoare triple {60481#false} assume 1 == ~E_2~0;~E_2~0 := 2; {60481#false} is VALID [2022-02-21 04:23:15,242 INFO L290 TraceCheckUtils]: 119: Hoare triple {60481#false} assume !(1 == ~E_3~0); {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 120: Hoare triple {60481#false} assume !(1 == ~E_4~0); {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 121: Hoare triple {60481#false} assume !(1 == ~E_5~0); {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 122: Hoare triple {60481#false} assume !(1 == ~E_6~0); {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 123: Hoare triple {60481#false} assume !(1 == ~E_7~0); {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 124: Hoare triple {60481#false} assume !(1 == ~E_8~0); {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 125: Hoare triple {60481#false} assume !(1 == ~E_9~0); {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 126: Hoare triple {60481#false} assume 1 == ~E_10~0;~E_10~0 := 2; {60481#false} is VALID [2022-02-21 04:23:15,243 INFO L290 TraceCheckUtils]: 127: Hoare triple {60481#false} assume { :end_inline_reset_delta_events } true; {60481#false} is VALID [2022-02-21 04:23:15,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,244 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,244 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248383667] [2022-02-21 04:23:15,244 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248383667] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,244 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,244 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,244 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068809090] [2022-02-21 04:23:15,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,245 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:15,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1340179659, now seen corresponding path program 1 times [2022-02-21 04:23:15,245 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,245 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201174694] [2022-02-21 04:23:15,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 0: Hoare triple {60484#true} assume !false; {60484#true} is VALID [2022-02-21 04:23:15,269 INFO L290 TraceCheckUtils]: 1: Hoare triple {60484#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 2: Hoare triple {60484#true} assume !false; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 3: Hoare triple {60484#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 4: Hoare triple {60484#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 5: Hoare triple {60484#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 6: Hoare triple {60484#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 7: Hoare triple {60484#true} assume !(0 != eval_~tmp~0#1); {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 8: Hoare triple {60484#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 9: Hoare triple {60484#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {60484#true} is VALID [2022-02-21 04:23:15,270 INFO L290 TraceCheckUtils]: 10: Hoare triple {60484#true} assume 0 == ~M_E~0;~M_E~0 := 1; {60484#true} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 11: Hoare triple {60484#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {60484#true} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 12: Hoare triple {60484#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {60484#true} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 13: Hoare triple {60484#true} assume !(0 == ~T3_E~0); {60484#true} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 14: Hoare triple {60484#true} assume !(0 == ~T4_E~0); {60484#true} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 15: Hoare triple {60484#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {60484#true} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 16: Hoare triple {60484#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,271 INFO L290 TraceCheckUtils]: 17: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 18: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 19: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 20: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,272 INFO L290 TraceCheckUtils]: 21: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 22: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 23: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,273 INFO L290 TraceCheckUtils]: 24: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 25: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 26: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 27: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,274 INFO L290 TraceCheckUtils]: 28: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 29: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 30: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 31: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,275 INFO L290 TraceCheckUtils]: 32: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 33: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 34: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 35: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,276 INFO L290 TraceCheckUtils]: 36: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 37: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 38: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 39: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,277 INFO L290 TraceCheckUtils]: 40: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 41: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 42: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 43: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,278 INFO L290 TraceCheckUtils]: 44: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 45: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 46: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 47: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,279 INFO L290 TraceCheckUtils]: 48: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 49: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 50: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 51: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,280 INFO L290 TraceCheckUtils]: 52: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,281 INFO L290 TraceCheckUtils]: 53: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,281 INFO L290 TraceCheckUtils]: 54: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,281 INFO L290 TraceCheckUtils]: 55: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,281 INFO L290 TraceCheckUtils]: 56: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,282 INFO L290 TraceCheckUtils]: 57: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,282 INFO L290 TraceCheckUtils]: 58: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,282 INFO L290 TraceCheckUtils]: 59: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,282 INFO L290 TraceCheckUtils]: 60: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,283 INFO L290 TraceCheckUtils]: 61: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,283 INFO L290 TraceCheckUtils]: 62: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,283 INFO L290 TraceCheckUtils]: 63: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,283 INFO L290 TraceCheckUtils]: 64: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,284 INFO L290 TraceCheckUtils]: 65: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,284 INFO L290 TraceCheckUtils]: 66: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,284 INFO L290 TraceCheckUtils]: 67: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,284 INFO L290 TraceCheckUtils]: 68: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,285 INFO L290 TraceCheckUtils]: 69: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,285 INFO L290 TraceCheckUtils]: 70: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,285 INFO L290 TraceCheckUtils]: 71: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,285 INFO L290 TraceCheckUtils]: 72: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,286 INFO L290 TraceCheckUtils]: 73: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,286 INFO L290 TraceCheckUtils]: 74: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,286 INFO L290 TraceCheckUtils]: 75: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,286 INFO L290 TraceCheckUtils]: 76: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,287 INFO L290 TraceCheckUtils]: 77: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,287 INFO L290 TraceCheckUtils]: 78: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,287 INFO L290 TraceCheckUtils]: 79: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,287 INFO L290 TraceCheckUtils]: 80: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,288 INFO L290 TraceCheckUtils]: 81: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,288 INFO L290 TraceCheckUtils]: 82: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,288 INFO L290 TraceCheckUtils]: 83: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,288 INFO L290 TraceCheckUtils]: 84: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,289 INFO L290 TraceCheckUtils]: 85: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,289 INFO L290 TraceCheckUtils]: 86: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,289 INFO L290 TraceCheckUtils]: 87: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,289 INFO L290 TraceCheckUtils]: 88: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,290 INFO L290 TraceCheckUtils]: 89: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,290 INFO L290 TraceCheckUtils]: 90: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,290 INFO L290 TraceCheckUtils]: 91: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,290 INFO L290 TraceCheckUtils]: 92: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,291 INFO L290 TraceCheckUtils]: 93: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,291 INFO L290 TraceCheckUtils]: 94: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,291 INFO L290 TraceCheckUtils]: 95: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,291 INFO L290 TraceCheckUtils]: 96: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,292 INFO L290 TraceCheckUtils]: 97: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,292 INFO L290 TraceCheckUtils]: 98: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,292 INFO L290 TraceCheckUtils]: 99: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,292 INFO L290 TraceCheckUtils]: 100: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,293 INFO L290 TraceCheckUtils]: 101: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,293 INFO L290 TraceCheckUtils]: 102: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,293 INFO L290 TraceCheckUtils]: 103: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,293 INFO L290 TraceCheckUtils]: 104: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {60486#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 105: Hoare triple {60486#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 106: Hoare triple {60485#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 107: Hoare triple {60485#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 108: Hoare triple {60485#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 109: Hoare triple {60485#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 110: Hoare triple {60485#false} assume 1 == ~E_M~0;~E_M~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 111: Hoare triple {60485#false} assume 1 == ~E_1~0;~E_1~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 112: Hoare triple {60485#false} assume 1 == ~E_2~0;~E_2~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 113: Hoare triple {60485#false} assume !(1 == ~E_3~0); {60485#false} is VALID [2022-02-21 04:23:15,294 INFO L290 TraceCheckUtils]: 114: Hoare triple {60485#false} assume 1 == ~E_4~0;~E_4~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 115: Hoare triple {60485#false} assume 1 == ~E_5~0;~E_5~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 116: Hoare triple {60485#false} assume 1 == ~E_6~0;~E_6~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 117: Hoare triple {60485#false} assume 1 == ~E_7~0;~E_7~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 118: Hoare triple {60485#false} assume 1 == ~E_8~0;~E_8~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 119: Hoare triple {60485#false} assume 1 == ~E_9~0;~E_9~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 120: Hoare triple {60485#false} assume 1 == ~E_10~0;~E_10~0 := 2; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 121: Hoare triple {60485#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 122: Hoare triple {60485#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 123: Hoare triple {60485#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {60485#false} is VALID [2022-02-21 04:23:15,295 INFO L290 TraceCheckUtils]: 124: Hoare triple {60485#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 125: Hoare triple {60485#false} assume !(0 == start_simulation_~tmp~3#1); {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 126: Hoare triple {60485#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 127: Hoare triple {60485#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 128: Hoare triple {60485#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 129: Hoare triple {60485#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 130: Hoare triple {60485#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 131: Hoare triple {60485#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 132: Hoare triple {60485#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {60485#false} is VALID [2022-02-21 04:23:15,296 INFO L290 TraceCheckUtils]: 133: Hoare triple {60485#false} assume !(0 != start_simulation_~tmp___0~1#1); {60485#false} is VALID [2022-02-21 04:23:15,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,297 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,297 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201174694] [2022-02-21 04:23:15,297 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201174694] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,297 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,297 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,297 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [730063468] [2022-02-21 04:23:15,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,298 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:15,298 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:15,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:15,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:15,299 INFO L87 Difference]: Start difference. First operand 2504 states and 3694 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,434 INFO L93 Difference]: Finished difference Result 4620 states and 6803 transitions. [2022-02-21 04:23:17,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:17,435 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,500 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:17,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4620 states and 6803 transitions. [2022-02-21 04:23:17,946 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2022-02-21 04:23:18,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4620 states to 4620 states and 6803 transitions. [2022-02-21 04:23:18,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4620 [2022-02-21 04:23:18,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4620 [2022-02-21 04:23:18,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4620 states and 6803 transitions. [2022-02-21 04:23:18,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:18,420 INFO L681 BuchiCegarLoop]: Abstraction has 4620 states and 6803 transitions. [2022-02-21 04:23:18,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4620 states and 6803 transitions. [2022-02-21 04:23:18,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4620 to 4618. [2022-02-21 04:23:18,465 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:18,471 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4620 states and 6803 transitions. Second operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,475 INFO L74 IsIncluded]: Start isIncluded. First operand 4620 states and 6803 transitions. Second operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,481 INFO L87 Difference]: Start difference. First operand 4620 states and 6803 transitions. Second operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,921 INFO L93 Difference]: Finished difference Result 4620 states and 6803 transitions. [2022-02-21 04:23:18,921 INFO L276 IsEmpty]: Start isEmpty. Operand 4620 states and 6803 transitions. [2022-02-21 04:23:18,925 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:18,925 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:18,930 INFO L74 IsIncluded]: Start isIncluded. First operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4620 states and 6803 transitions. [2022-02-21 04:23:18,933 INFO L87 Difference]: Start difference. First operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4620 states and 6803 transitions. [2022-02-21 04:23:19,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,364 INFO L93 Difference]: Finished difference Result 4620 states and 6803 transitions. [2022-02-21 04:23:19,364 INFO L276 IsEmpty]: Start isEmpty. Operand 4620 states and 6803 transitions. [2022-02-21 04:23:19,416 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,416 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,416 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:19,416 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:19,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4618 states to 4618 states and 6801 transitions. [2022-02-21 04:23:19,840 INFO L704 BuchiCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2022-02-21 04:23:19,840 INFO L587 BuchiCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2022-02-21 04:23:19,840 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:19,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4618 states and 6801 transitions. [2022-02-21 04:23:19,848 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2022-02-21 04:23:19,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:19,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:19,849 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:19,850 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:19,850 INFO L791 eck$LassoCheckResult]: Stem: 66121#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 66122#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 65158#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65159#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66051#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 65750#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65751#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66032#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66192#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65917#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65918#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65805#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65806#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66150#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66111#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 66037#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66038#L1024 assume !(0 == ~M_E~0); 66291#L1024-2 assume !(0 == ~T1_E~0); 65485#L1029-1 assume !(0 == ~T2_E~0); 65486#L1034-1 assume !(0 == ~T3_E~0); 65592#L1039-1 assume !(0 == ~T4_E~0); 66412#L1044-1 assume !(0 == ~T5_E~0); 65828#L1049-1 assume !(0 == ~T6_E~0); 65829#L1054-1 assume !(0 == ~T7_E~0); 66059#L1059-1 assume !(0 == ~T8_E~0); 65532#L1064-1 assume !(0 == ~T9_E~0); 65533#L1069-1 assume !(0 == ~T10_E~0); 66258#L1074-1 assume !(0 == ~E_M~0); 66326#L1079-1 assume !(0 == ~E_1~0); 66293#L1084-1 assume !(0 == ~E_2~0); 66294#L1089-1 assume !(0 == ~E_3~0); 66346#L1094-1 assume !(0 == ~E_4~0); 65907#L1099-1 assume !(0 == ~E_5~0); 65908#L1104-1 assume !(0 == ~E_6~0); 66169#L1109-1 assume !(0 == ~E_7~0); 65706#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 65707#L1119-1 assume !(0 == ~E_9~0); 65761#L1124-1 assume !(0 == ~E_10~0); 65191#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65192#L502 assume 1 == ~m_pc~0; 66057#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65320#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65321#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 66106#L1273 assume !(0 != activate_threads_~tmp~1#1); 66107#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66451#L521 assume !(1 == ~t1_pc~0); 66379#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65251#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65252#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65394#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 65233#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65234#L540 assume 1 == ~t2_pc~0; 66307#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66021#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66310#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66324#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 66372#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65507#L559 assume 1 == ~t3_pc~0; 65508#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65786#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65787#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65933#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 65338#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65339#L578 assume !(1 == ~t4_pc~0); 65457#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65456#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65227#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65228#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66089#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66090#L597 assume 1 == ~t5_pc~0; 66466#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65272#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65273#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65874#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 66039#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66040#L616 assume !(1 == ~t6_pc~0); 66055#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66054#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66430#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65963#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 65898#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65899#L635 assume 1 == ~t7_pc~0; 66094#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65241#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65612#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66268#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 66033#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66034#L654 assume !(1 == ~t8_pc~0); 65854#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65855#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66373#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66255#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 66256#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65483#L673 assume 1 == ~t9_pc~0; 65484#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65182#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66447#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66224#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 66178#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66179#L692 assume !(1 == ~t10_pc~0); 66125#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66124#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66043#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65911#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 65912#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66235#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 66490#L1142-2 assume !(1 == ~T1_E~0); 69611#L1147-1 assume !(1 == ~T2_E~0); 69610#L1152-1 assume !(1 == ~T3_E~0); 69609#L1157-1 assume !(1 == ~T4_E~0); 69607#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69605#L1167-1 assume !(1 == ~T6_E~0); 69603#L1172-1 assume !(1 == ~T7_E~0); 69601#L1177-1 assume !(1 == ~T8_E~0); 69599#L1182-1 assume !(1 == ~T9_E~0); 69597#L1187-1 assume !(1 == ~T10_E~0); 66575#L1192-1 assume !(1 == ~E_M~0); 66572#L1197-1 assume !(1 == ~E_1~0); 66570#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 66569#L1207-1 assume !(1 == ~E_3~0); 66557#L1212-1 assume !(1 == ~E_4~0); 66555#L1217-1 assume !(1 == ~E_5~0); 66553#L1222-1 assume !(1 == ~E_6~0); 66551#L1227-1 assume !(1 == ~E_7~0); 66549#L1232-1 assume !(1 == ~E_8~0); 66547#L1237-1 assume !(1 == ~E_9~0); 66543#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 66533#L1247-1 assume { :end_inline_reset_delta_events } true; 66526#L1553-2 [2022-02-21 04:23:19,850 INFO L793 eck$LassoCheckResult]: Loop: 66526#L1553-2 assume !false; 66520#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66515#L999 assume !false; 66514#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 66513#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 66502#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 66501#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 66499#L854 assume !(0 != eval_~tmp~0#1); 66498#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66497#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66495#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 66496#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67179#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67176#L1034-3 assume !(0 == ~T3_E~0); 67173#L1039-3 assume !(0 == ~T4_E~0); 67170#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67167#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67164#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67161#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67158#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67155#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67152#L1074-3 assume !(0 == ~E_M~0); 67149#L1079-3 assume !(0 == ~E_1~0); 67146#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67143#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67140#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67137#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67134#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67131#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67128#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67125#L1119-3 assume !(0 == ~E_9~0); 67122#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67119#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67116#L502-36 assume 1 == ~m_pc~0; 67113#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 67107#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67104#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 67101#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67098#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67095#L521-36 assume 1 == ~t1_pc~0; 67091#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67086#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67083#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67080#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67077#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67074#L540-36 assume 1 == ~t2_pc~0; 67071#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67065#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67062#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67059#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67056#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67053#L559-36 assume 1 == ~t3_pc~0; 67049#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 67044#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67041#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67038#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67035#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67032#L578-36 assume 1 == ~t4_pc~0; 67029#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67023#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67020#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67017#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67014#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67011#L597-36 assume !(1 == ~t5_pc~0); 67008#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 67002#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66999#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66996#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 66993#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66990#L616-36 assume 1 == ~t6_pc~0; 66985#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66978#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66974#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66970#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66966#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66962#L635-36 assume 1 == ~t7_pc~0; 66957#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66950#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66946#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66942#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66938#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66934#L654-36 assume 1 == ~t8_pc~0; 66929#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66922#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66918#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66914#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66910#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66906#L673-36 assume !(1 == ~t9_pc~0); 66901#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 66894#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66890#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66886#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66882#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66878#L692-36 assume 1 == ~t10_pc~0; 66873#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66866#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66862#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66858#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66854#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66850#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 66041#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66842#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66838#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66432#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66831#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66828#L1167-3 assume !(1 == ~T6_E~0); 66825#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66821#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66818#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66815#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 66812#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66808#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66806#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66803#L1207-3 assume !(1 == ~E_3~0); 66801#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66799#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66797#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66795#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66793#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66790#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66788#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 66786#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 66774#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 66772#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 66770#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 66767#L1572 assume !(0 == start_simulation_~tmp~3#1); 65664#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 66567#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 66556#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 66554#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 66552#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66550#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66548#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 66534#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 66526#L1553-2 [2022-02-21 04:23:19,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:19,851 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2022-02-21 04:23:19,851 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:19,852 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145465859] [2022-02-21 04:23:19,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:19,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:19,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 0: Hoare triple {78970#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 1: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 2: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 3: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 4: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 5: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 6: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 7: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 8: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,881 INFO L290 TraceCheckUtils]: 9: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,881 INFO L290 TraceCheckUtils]: 10: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,881 INFO L290 TraceCheckUtils]: 11: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,882 INFO L290 TraceCheckUtils]: 12: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,882 INFO L290 TraceCheckUtils]: 13: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,882 INFO L290 TraceCheckUtils]: 14: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,882 INFO L290 TraceCheckUtils]: 15: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {78972#(= ~E_8~0 ~M_E~0)} is VALID [2022-02-21 04:23:19,883 INFO L290 TraceCheckUtils]: 16: Hoare triple {78972#(= ~E_8~0 ~M_E~0)} assume !(0 == ~M_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,883 INFO L290 TraceCheckUtils]: 17: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T1_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,883 INFO L290 TraceCheckUtils]: 18: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T2_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,884 INFO L290 TraceCheckUtils]: 19: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T3_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,884 INFO L290 TraceCheckUtils]: 20: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T4_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,884 INFO L290 TraceCheckUtils]: 21: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T5_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,884 INFO L290 TraceCheckUtils]: 22: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T6_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,885 INFO L290 TraceCheckUtils]: 23: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T7_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,885 INFO L290 TraceCheckUtils]: 24: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T8_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,885 INFO L290 TraceCheckUtils]: 25: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T9_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,885 INFO L290 TraceCheckUtils]: 26: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~T10_E~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,886 INFO L290 TraceCheckUtils]: 27: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_M~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,886 INFO L290 TraceCheckUtils]: 28: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_1~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,886 INFO L290 TraceCheckUtils]: 29: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_2~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,886 INFO L290 TraceCheckUtils]: 30: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_3~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,887 INFO L290 TraceCheckUtils]: 31: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_4~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,887 INFO L290 TraceCheckUtils]: 32: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_5~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,887 INFO L290 TraceCheckUtils]: 33: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_6~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 34: Hoare triple {78973#(not (= ~E_8~0 0))} assume !(0 == ~E_7~0); {78973#(not (= ~E_8~0 0))} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 35: Hoare triple {78973#(not (= ~E_8~0 0))} assume 0 == ~E_8~0;~E_8~0 := 1; {78971#false} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 36: Hoare triple {78971#false} assume !(0 == ~E_9~0); {78971#false} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 37: Hoare triple {78971#false} assume !(0 == ~E_10~0); {78971#false} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 38: Hoare triple {78971#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {78971#false} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 39: Hoare triple {78971#false} assume 1 == ~m_pc~0; {78971#false} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 40: Hoare triple {78971#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {78971#false} is VALID [2022-02-21 04:23:19,888 INFO L290 TraceCheckUtils]: 41: Hoare triple {78971#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 42: Hoare triple {78971#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 43: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp~1#1); {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 44: Hoare triple {78971#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 45: Hoare triple {78971#false} assume !(1 == ~t1_pc~0); {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 46: Hoare triple {78971#false} is_transmit1_triggered_~__retres1~1#1 := 0; {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 47: Hoare triple {78971#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 48: Hoare triple {78971#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 49: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___0~0#1); {78971#false} is VALID [2022-02-21 04:23:19,889 INFO L290 TraceCheckUtils]: 50: Hoare triple {78971#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 51: Hoare triple {78971#false} assume 1 == ~t2_pc~0; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 52: Hoare triple {78971#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 53: Hoare triple {78971#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 54: Hoare triple {78971#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 55: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___1~0#1); {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 56: Hoare triple {78971#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 57: Hoare triple {78971#false} assume 1 == ~t3_pc~0; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 58: Hoare triple {78971#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {78971#false} is VALID [2022-02-21 04:23:19,890 INFO L290 TraceCheckUtils]: 59: Hoare triple {78971#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 60: Hoare triple {78971#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 61: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___2~0#1); {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 62: Hoare triple {78971#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 63: Hoare triple {78971#false} assume !(1 == ~t4_pc~0); {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 64: Hoare triple {78971#false} is_transmit4_triggered_~__retres1~4#1 := 0; {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 65: Hoare triple {78971#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 66: Hoare triple {78971#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {78971#false} is VALID [2022-02-21 04:23:19,891 INFO L290 TraceCheckUtils]: 67: Hoare triple {78971#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 68: Hoare triple {78971#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 69: Hoare triple {78971#false} assume 1 == ~t5_pc~0; {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 70: Hoare triple {78971#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 71: Hoare triple {78971#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 72: Hoare triple {78971#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 73: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___4~0#1); {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 74: Hoare triple {78971#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 75: Hoare triple {78971#false} assume !(1 == ~t6_pc~0); {78971#false} is VALID [2022-02-21 04:23:19,892 INFO L290 TraceCheckUtils]: 76: Hoare triple {78971#false} is_transmit6_triggered_~__retres1~6#1 := 0; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 77: Hoare triple {78971#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 78: Hoare triple {78971#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 79: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___5~0#1); {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 80: Hoare triple {78971#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 81: Hoare triple {78971#false} assume 1 == ~t7_pc~0; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 82: Hoare triple {78971#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 83: Hoare triple {78971#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 84: Hoare triple {78971#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {78971#false} is VALID [2022-02-21 04:23:19,893 INFO L290 TraceCheckUtils]: 85: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___6~0#1); {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 86: Hoare triple {78971#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 87: Hoare triple {78971#false} assume !(1 == ~t8_pc~0); {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 88: Hoare triple {78971#false} is_transmit8_triggered_~__retres1~8#1 := 0; {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 89: Hoare triple {78971#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 90: Hoare triple {78971#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 91: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___7~0#1); {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 92: Hoare triple {78971#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 93: Hoare triple {78971#false} assume 1 == ~t9_pc~0; {78971#false} is VALID [2022-02-21 04:23:19,894 INFO L290 TraceCheckUtils]: 94: Hoare triple {78971#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 95: Hoare triple {78971#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 96: Hoare triple {78971#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 97: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___8~0#1); {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 98: Hoare triple {78971#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 99: Hoare triple {78971#false} assume !(1 == ~t10_pc~0); {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 100: Hoare triple {78971#false} is_transmit10_triggered_~__retres1~10#1 := 0; {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 101: Hoare triple {78971#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 102: Hoare triple {78971#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {78971#false} is VALID [2022-02-21 04:23:19,895 INFO L290 TraceCheckUtils]: 103: Hoare triple {78971#false} assume !(0 != activate_threads_~tmp___9~0#1); {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 104: Hoare triple {78971#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 105: Hoare triple {78971#false} assume 1 == ~M_E~0;~M_E~0 := 2; {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 106: Hoare triple {78971#false} assume !(1 == ~T1_E~0); {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 107: Hoare triple {78971#false} assume !(1 == ~T2_E~0); {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 108: Hoare triple {78971#false} assume !(1 == ~T3_E~0); {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 109: Hoare triple {78971#false} assume !(1 == ~T4_E~0); {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 110: Hoare triple {78971#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {78971#false} is VALID [2022-02-21 04:23:19,896 INFO L290 TraceCheckUtils]: 111: Hoare triple {78971#false} assume !(1 == ~T6_E~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 112: Hoare triple {78971#false} assume !(1 == ~T7_E~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 113: Hoare triple {78971#false} assume !(1 == ~T8_E~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 114: Hoare triple {78971#false} assume !(1 == ~T9_E~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 115: Hoare triple {78971#false} assume !(1 == ~T10_E~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 116: Hoare triple {78971#false} assume !(1 == ~E_M~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 117: Hoare triple {78971#false} assume !(1 == ~E_1~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 118: Hoare triple {78971#false} assume 1 == ~E_2~0;~E_2~0 := 2; {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 119: Hoare triple {78971#false} assume !(1 == ~E_3~0); {78971#false} is VALID [2022-02-21 04:23:19,897 INFO L290 TraceCheckUtils]: 120: Hoare triple {78971#false} assume !(1 == ~E_4~0); {78971#false} is VALID [2022-02-21 04:23:19,898 INFO L290 TraceCheckUtils]: 121: Hoare triple {78971#false} assume !(1 == ~E_5~0); {78971#false} is VALID [2022-02-21 04:23:19,898 INFO L290 TraceCheckUtils]: 122: Hoare triple {78971#false} assume !(1 == ~E_6~0); {78971#false} is VALID [2022-02-21 04:23:19,898 INFO L290 TraceCheckUtils]: 123: Hoare triple {78971#false} assume !(1 == ~E_7~0); {78971#false} is VALID [2022-02-21 04:23:19,898 INFO L290 TraceCheckUtils]: 124: Hoare triple {78971#false} assume !(1 == ~E_8~0); {78971#false} is VALID [2022-02-21 04:23:19,898 INFO L290 TraceCheckUtils]: 125: Hoare triple {78971#false} assume !(1 == ~E_9~0); {78971#false} is VALID [2022-02-21 04:23:19,898 INFO L290 TraceCheckUtils]: 126: Hoare triple {78971#false} assume 1 == ~E_10~0;~E_10~0 := 2; {78971#false} is VALID [2022-02-21 04:23:19,898 INFO L290 TraceCheckUtils]: 127: Hoare triple {78971#false} assume { :end_inline_reset_delta_events } true; {78971#false} is VALID [2022-02-21 04:23:19,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,899 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,899 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145465859] [2022-02-21 04:23:19,899 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145465859] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,900 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,901 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,901 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412690170] [2022-02-21 04:23:19,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,901 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:19,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:19,902 INFO L85 PathProgramCache]: Analyzing trace with hash 386965303, now seen corresponding path program 1 times [2022-02-21 04:23:19,902 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:19,902 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691673827] [2022-02-21 04:23:19,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:19,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:19,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,923 INFO L290 TraceCheckUtils]: 0: Hoare triple {78974#true} assume !false; {78974#true} is VALID [2022-02-21 04:23:19,923 INFO L290 TraceCheckUtils]: 1: Hoare triple {78974#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {78974#true} is VALID [2022-02-21 04:23:19,923 INFO L290 TraceCheckUtils]: 2: Hoare triple {78974#true} assume !false; {78974#true} is VALID [2022-02-21 04:23:19,923 INFO L290 TraceCheckUtils]: 3: Hoare triple {78974#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {78974#true} is VALID [2022-02-21 04:23:19,923 INFO L290 TraceCheckUtils]: 4: Hoare triple {78974#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {78974#true} is VALID [2022-02-21 04:23:19,923 INFO L290 TraceCheckUtils]: 5: Hoare triple {78974#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 6: Hoare triple {78974#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 7: Hoare triple {78974#true} assume !(0 != eval_~tmp~0#1); {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 8: Hoare triple {78974#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 9: Hoare triple {78974#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 10: Hoare triple {78974#true} assume 0 == ~M_E~0;~M_E~0 := 1; {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 11: Hoare triple {78974#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 12: Hoare triple {78974#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 13: Hoare triple {78974#true} assume !(0 == ~T3_E~0); {78974#true} is VALID [2022-02-21 04:23:19,924 INFO L290 TraceCheckUtils]: 14: Hoare triple {78974#true} assume !(0 == ~T4_E~0); {78974#true} is VALID [2022-02-21 04:23:19,925 INFO L290 TraceCheckUtils]: 15: Hoare triple {78974#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {78974#true} is VALID [2022-02-21 04:23:19,925 INFO L290 TraceCheckUtils]: 16: Hoare triple {78974#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,925 INFO L290 TraceCheckUtils]: 17: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,925 INFO L290 TraceCheckUtils]: 18: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,926 INFO L290 TraceCheckUtils]: 19: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,926 INFO L290 TraceCheckUtils]: 20: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,926 INFO L290 TraceCheckUtils]: 21: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,926 INFO L290 TraceCheckUtils]: 22: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,927 INFO L290 TraceCheckUtils]: 23: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,927 INFO L290 TraceCheckUtils]: 24: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,927 INFO L290 TraceCheckUtils]: 25: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,928 INFO L290 TraceCheckUtils]: 26: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,928 INFO L290 TraceCheckUtils]: 27: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,928 INFO L290 TraceCheckUtils]: 28: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,928 INFO L290 TraceCheckUtils]: 29: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,929 INFO L290 TraceCheckUtils]: 30: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,929 INFO L290 TraceCheckUtils]: 31: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,929 INFO L290 TraceCheckUtils]: 32: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,929 INFO L290 TraceCheckUtils]: 33: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,930 INFO L290 TraceCheckUtils]: 34: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,930 INFO L290 TraceCheckUtils]: 35: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,930 INFO L290 TraceCheckUtils]: 36: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,931 INFO L290 TraceCheckUtils]: 37: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,931 INFO L290 TraceCheckUtils]: 38: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,931 INFO L290 TraceCheckUtils]: 39: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,931 INFO L290 TraceCheckUtils]: 40: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,932 INFO L290 TraceCheckUtils]: 41: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,932 INFO L290 TraceCheckUtils]: 42: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,932 INFO L290 TraceCheckUtils]: 43: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,932 INFO L290 TraceCheckUtils]: 44: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,933 INFO L290 TraceCheckUtils]: 45: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,933 INFO L290 TraceCheckUtils]: 46: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,933 INFO L290 TraceCheckUtils]: 47: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,934 INFO L290 TraceCheckUtils]: 48: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,934 INFO L290 TraceCheckUtils]: 49: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,934 INFO L290 TraceCheckUtils]: 50: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,934 INFO L290 TraceCheckUtils]: 51: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,935 INFO L290 TraceCheckUtils]: 52: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,935 INFO L290 TraceCheckUtils]: 53: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,935 INFO L290 TraceCheckUtils]: 54: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,935 INFO L290 TraceCheckUtils]: 55: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,936 INFO L290 TraceCheckUtils]: 56: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,936 INFO L290 TraceCheckUtils]: 57: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,936 INFO L290 TraceCheckUtils]: 58: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,937 INFO L290 TraceCheckUtils]: 59: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,937 INFO L290 TraceCheckUtils]: 60: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,937 INFO L290 TraceCheckUtils]: 61: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,937 INFO L290 TraceCheckUtils]: 62: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,938 INFO L290 TraceCheckUtils]: 63: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,938 INFO L290 TraceCheckUtils]: 64: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,938 INFO L290 TraceCheckUtils]: 65: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,938 INFO L290 TraceCheckUtils]: 66: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,939 INFO L290 TraceCheckUtils]: 67: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,939 INFO L290 TraceCheckUtils]: 68: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,939 INFO L290 TraceCheckUtils]: 69: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,939 INFO L290 TraceCheckUtils]: 70: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,940 INFO L290 TraceCheckUtils]: 71: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,940 INFO L290 TraceCheckUtils]: 72: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,940 INFO L290 TraceCheckUtils]: 73: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,941 INFO L290 TraceCheckUtils]: 74: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,941 INFO L290 TraceCheckUtils]: 75: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,941 INFO L290 TraceCheckUtils]: 76: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,941 INFO L290 TraceCheckUtils]: 77: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,942 INFO L290 TraceCheckUtils]: 78: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,942 INFO L290 TraceCheckUtils]: 79: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,942 INFO L290 TraceCheckUtils]: 80: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,942 INFO L290 TraceCheckUtils]: 81: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,943 INFO L290 TraceCheckUtils]: 82: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,943 INFO L290 TraceCheckUtils]: 83: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,943 INFO L290 TraceCheckUtils]: 84: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,944 INFO L290 TraceCheckUtils]: 85: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,944 INFO L290 TraceCheckUtils]: 86: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,944 INFO L290 TraceCheckUtils]: 87: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,944 INFO L290 TraceCheckUtils]: 88: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,945 INFO L290 TraceCheckUtils]: 89: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,945 INFO L290 TraceCheckUtils]: 90: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,945 INFO L290 TraceCheckUtils]: 91: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,945 INFO L290 TraceCheckUtils]: 92: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,946 INFO L290 TraceCheckUtils]: 93: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,946 INFO L290 TraceCheckUtils]: 94: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,946 INFO L290 TraceCheckUtils]: 95: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,946 INFO L290 TraceCheckUtils]: 96: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,947 INFO L290 TraceCheckUtils]: 97: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,947 INFO L290 TraceCheckUtils]: 98: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,947 INFO L290 TraceCheckUtils]: 99: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,948 INFO L290 TraceCheckUtils]: 100: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,948 INFO L290 TraceCheckUtils]: 101: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,948 INFO L290 TraceCheckUtils]: 102: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,948 INFO L290 TraceCheckUtils]: 103: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,949 INFO L290 TraceCheckUtils]: 104: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {78976#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,949 INFO L290 TraceCheckUtils]: 105: Hoare triple {78976#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {78975#false} is VALID [2022-02-21 04:23:19,949 INFO L290 TraceCheckUtils]: 106: Hoare triple {78975#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,949 INFO L290 TraceCheckUtils]: 107: Hoare triple {78975#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,949 INFO L290 TraceCheckUtils]: 108: Hoare triple {78975#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,949 INFO L290 TraceCheckUtils]: 109: Hoare triple {78975#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,949 INFO L290 TraceCheckUtils]: 110: Hoare triple {78975#false} assume 1 == ~E_M~0;~E_M~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 111: Hoare triple {78975#false} assume 1 == ~E_1~0;~E_1~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 112: Hoare triple {78975#false} assume 1 == ~E_2~0;~E_2~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 113: Hoare triple {78975#false} assume !(1 == ~E_3~0); {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 114: Hoare triple {78975#false} assume 1 == ~E_4~0;~E_4~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 115: Hoare triple {78975#false} assume 1 == ~E_5~0;~E_5~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 116: Hoare triple {78975#false} assume 1 == ~E_6~0;~E_6~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 117: Hoare triple {78975#false} assume 1 == ~E_7~0;~E_7~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 118: Hoare triple {78975#false} assume 1 == ~E_8~0;~E_8~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,950 INFO L290 TraceCheckUtils]: 119: Hoare triple {78975#false} assume 1 == ~E_9~0;~E_9~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 120: Hoare triple {78975#false} assume 1 == ~E_10~0;~E_10~0 := 2; {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 121: Hoare triple {78975#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 122: Hoare triple {78975#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 123: Hoare triple {78975#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 124: Hoare triple {78975#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 125: Hoare triple {78975#false} assume !(0 == start_simulation_~tmp~3#1); {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 126: Hoare triple {78975#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {78975#false} is VALID [2022-02-21 04:23:19,951 INFO L290 TraceCheckUtils]: 127: Hoare triple {78975#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {78975#false} is VALID [2022-02-21 04:23:19,952 INFO L290 TraceCheckUtils]: 128: Hoare triple {78975#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {78975#false} is VALID [2022-02-21 04:23:19,952 INFO L290 TraceCheckUtils]: 129: Hoare triple {78975#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {78975#false} is VALID [2022-02-21 04:23:19,952 INFO L290 TraceCheckUtils]: 130: Hoare triple {78975#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {78975#false} is VALID [2022-02-21 04:23:19,952 INFO L290 TraceCheckUtils]: 131: Hoare triple {78975#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {78975#false} is VALID [2022-02-21 04:23:19,952 INFO L290 TraceCheckUtils]: 132: Hoare triple {78975#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {78975#false} is VALID [2022-02-21 04:23:19,952 INFO L290 TraceCheckUtils]: 133: Hoare triple {78975#false} assume !(0 != start_simulation_~tmp___0~1#1); {78975#false} is VALID [2022-02-21 04:23:19,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,953 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,953 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691673827] [2022-02-21 04:23:19,953 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691673827] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,953 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,953 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,953 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918046060] [2022-02-21 04:23:19,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,954 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:19,954 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:19,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:19,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:19,954 INFO L87 Difference]: Start difference. First operand 4618 states and 6801 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:23,534 INFO L93 Difference]: Finished difference Result 8652 states and 12712 transitions. [2022-02-21 04:23:23,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:23,535 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,603 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:23,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8652 states and 12712 transitions. [2022-02-21 04:23:25,082 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2022-02-21 04:23:26,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8652 states to 8652 states and 12712 transitions. [2022-02-21 04:23:26,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8652 [2022-02-21 04:23:26,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8652 [2022-02-21 04:23:26,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8652 states and 12712 transitions. [2022-02-21 04:23:26,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:26,594 INFO L681 BuchiCegarLoop]: Abstraction has 8652 states and 12712 transitions. [2022-02-21 04:23:26,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8652 states and 12712 transitions. [2022-02-21 04:23:26,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8652 to 8648. [2022-02-21 04:23:26,676 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:26,683 INFO L82 GeneralOperation]: Start isEquivalent. First operand 8652 states and 12712 transitions. Second operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,688 INFO L74 IsIncluded]: Start isIncluded. First operand 8652 states and 12712 transitions. Second operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,694 INFO L87 Difference]: Start difference. First operand 8652 states and 12712 transitions. Second operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,232 INFO L93 Difference]: Finished difference Result 8652 states and 12712 transitions. [2022-02-21 04:23:28,232 INFO L276 IsEmpty]: Start isEmpty. Operand 8652 states and 12712 transitions. [2022-02-21 04:23:28,240 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:28,241 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:28,288 INFO L74 IsIncluded]: Start isIncluded. First operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8652 states and 12712 transitions. [2022-02-21 04:23:28,294 INFO L87 Difference]: Start difference. First operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8652 states and 12712 transitions. [2022-02-21 04:23:29,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,845 INFO L93 Difference]: Finished difference Result 8652 states and 12712 transitions. [2022-02-21 04:23:29,845 INFO L276 IsEmpty]: Start isEmpty. Operand 8652 states and 12712 transitions. [2022-02-21 04:23:29,853 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,854 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,854 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:29,854 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:29,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:31,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8648 states to 8648 states and 12708 transitions. [2022-02-21 04:23:31,316 INFO L704 BuchiCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2022-02-21 04:23:31,316 INFO L587 BuchiCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2022-02-21 04:23:31,316 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:31,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8648 states and 12708 transitions. [2022-02-21 04:23:31,332 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2022-02-21 04:23:31,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:31,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:31,334 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,334 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:31,335 INFO L791 eck$LassoCheckResult]: Stem: 88652#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 88653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 87680#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87681#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88577#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 88276#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88277#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88558#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88728#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88445#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88446#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88335#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88336#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 88685#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 88641#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 88565#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88566#L1024 assume !(0 == ~M_E~0); 88834#L1024-2 assume !(0 == ~T1_E~0); 88007#L1029-1 assume !(0 == ~T2_E~0); 88008#L1034-1 assume !(0 == ~T3_E~0); 88115#L1039-1 assume !(0 == ~T4_E~0); 88965#L1044-1 assume !(0 == ~T5_E~0); 88355#L1049-1 assume !(0 == ~T6_E~0); 88356#L1054-1 assume !(0 == ~T7_E~0); 88587#L1059-1 assume !(0 == ~T8_E~0); 88054#L1064-1 assume !(0 == ~T9_E~0); 88055#L1069-1 assume !(0 == ~T10_E~0); 88799#L1074-1 assume !(0 == ~E_M~0); 88872#L1079-1 assume !(0 == ~E_1~0); 88836#L1084-1 assume !(0 == ~E_2~0); 88837#L1089-1 assume !(0 == ~E_3~0); 88894#L1094-1 assume !(0 == ~E_4~0); 88433#L1099-1 assume !(0 == ~E_5~0); 88434#L1104-1 assume !(0 == ~E_6~0); 88703#L1109-1 assume !(0 == ~E_7~0); 88231#L1114-1 assume !(0 == ~E_8~0); 88232#L1119-1 assume !(0 == ~E_9~0); 88290#L1124-1 assume !(0 == ~E_10~0); 87713#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87714#L502 assume 1 == ~m_pc~0; 88585#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 87842#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87843#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88637#L1273 assume !(0 != activate_threads_~tmp~1#1); 88638#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89009#L521 assume !(1 == ~t1_pc~0); 88929#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87773#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87774#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87917#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 87757#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87758#L540 assume 1 == ~t2_pc~0; 88851#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88547#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88856#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88870#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 88922#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88029#L559 assume 1 == ~t3_pc~0; 88030#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88312#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88313#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88458#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 87860#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87861#L578 assume !(1 == ~t4_pc~0); 87981#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87980#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87749#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87750#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88620#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88621#L597 assume 1 == ~t5_pc~0; 89029#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87794#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87795#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88406#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 88567#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88568#L616 assume !(1 == ~t6_pc~0); 88584#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 88583#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88984#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88489#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 88425#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88426#L635 assume 1 == ~t7_pc~0; 88625#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 87763#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88135#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88810#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 88559#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88560#L654 assume !(1 == ~t8_pc~0); 88379#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 88380#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88923#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88796#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 88797#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88005#L673 assume 1 == ~t9_pc~0; 88006#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87704#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89004#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88762#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 88713#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88714#L692 assume !(1 == ~t10_pc~0); 88656#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 88655#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88569#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88437#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 88438#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88775#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 89057#L1142-2 assume !(1 == ~T1_E~0); 88763#L1147-1 assume !(1 == ~T2_E~0); 88764#L1152-1 assume !(1 == ~T3_E~0); 89193#L1157-1 assume !(1 == ~T4_E~0); 89191#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89189#L1167-1 assume !(1 == ~T6_E~0); 89186#L1172-1 assume !(1 == ~T7_E~0); 89184#L1177-1 assume !(1 == ~T8_E~0); 89182#L1182-1 assume !(1 == ~T9_E~0); 89180#L1187-1 assume !(1 == ~T10_E~0); 89178#L1192-1 assume !(1 == ~E_M~0); 89176#L1197-1 assume !(1 == ~E_1~0); 89173#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 89171#L1207-1 assume !(1 == ~E_3~0); 89169#L1212-1 assume !(1 == ~E_4~0); 89163#L1217-1 assume !(1 == ~E_5~0); 89161#L1222-1 assume !(1 == ~E_6~0); 89159#L1227-1 assume !(1 == ~E_7~0); 89154#L1232-1 assume !(1 == ~E_8~0); 89148#L1237-1 assume !(1 == ~E_9~0); 89143#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 89100#L1247-1 assume { :end_inline_reset_delta_events } true; 89093#L1553-2 [2022-02-21 04:23:31,335 INFO L793 eck$LassoCheckResult]: Loop: 89093#L1553-2 assume !false; 89087#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89082#L999 assume !false; 89081#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 89080#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 89069#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 89068#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 89066#L854 assume !(0 != eval_~tmp~0#1); 89065#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89064#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89063#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 88952#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88953#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 95425#L1034-3 assume !(0 == ~T3_E~0); 95419#L1039-3 assume !(0 == ~T4_E~0); 88773#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87999#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88000#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87775#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 87776#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 88364#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88365#L1074-3 assume !(0 == ~E_M~0); 88709#L1079-3 assume !(0 == ~E_1~0); 88598#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88481#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88482#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88411#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88412#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88732#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 95245#L1114-3 assume !(0 == ~E_8~0); 95243#L1119-3 assume !(0 == ~E_9~0); 95241#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 95238#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95233#L502-36 assume !(1 == ~m_pc~0); 95227#L502-38 is_master_triggered_~__retres1~0#1 := 0; 95222#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95216#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 91939#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91936#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91934#L521-36 assume 1 == ~t1_pc~0; 91931#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 91929#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89679#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89677#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89653#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89478#L540-36 assume !(1 == ~t2_pc~0); 89473#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 89471#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89469#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89468#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 89467#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89466#L559-36 assume 1 == ~t3_pc~0; 89463#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 89460#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89458#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89456#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89454#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89452#L578-36 assume !(1 == ~t4_pc~0); 89449#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 89446#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89444#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89442#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89440#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89438#L597-36 assume 1 == ~t5_pc~0; 89435#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89432#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89430#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89428#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 89426#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 89424#L616-36 assume 1 == ~t6_pc~0; 89421#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 89418#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 89416#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89414#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 89412#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89410#L635-36 assume !(1 == ~t7_pc~0); 89408#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 89404#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89402#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89400#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 89398#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89396#L654-36 assume 1 == ~t8_pc~0; 89393#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 89390#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89388#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89386#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 89384#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89382#L673-36 assume !(1 == ~t9_pc~0); 89379#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 89376#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89374#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89372#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 89370#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89368#L692-36 assume 1 == ~t10_pc~0; 89365#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 89362#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89360#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89358#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 89356#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89354#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88563#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89350#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 89348#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89344#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89342#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89338#L1167-3 assume !(1 == ~T6_E~0); 89328#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 89322#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 89316#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89310#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89303#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 89295#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89290#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 89286#L1207-3 assume !(1 == ~E_3~0); 89282#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89278#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89273#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89269#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89264#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89259#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89257#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89248#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 89235#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 89233#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 89231#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 89229#L1572 assume !(0 == start_simulation_~tmp~3#1); 88187#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 89223#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 89167#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 89160#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 89155#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89149#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89144#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 89101#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 89093#L1553-2 [2022-02-21 04:23:31,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,336 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2022-02-21 04:23:31,336 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,336 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919188578] [2022-02-21 04:23:31,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,357 INFO L290 TraceCheckUtils]: 0: Hoare triple {113586#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,358 INFO L290 TraceCheckUtils]: 1: Hoare triple {113588#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,358 INFO L290 TraceCheckUtils]: 2: Hoare triple {113588#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,358 INFO L290 TraceCheckUtils]: 3: Hoare triple {113588#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,359 INFO L290 TraceCheckUtils]: 4: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,359 INFO L290 TraceCheckUtils]: 5: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,359 INFO L290 TraceCheckUtils]: 6: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,359 INFO L290 TraceCheckUtils]: 7: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,360 INFO L290 TraceCheckUtils]: 8: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,360 INFO L290 TraceCheckUtils]: 9: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,360 INFO L290 TraceCheckUtils]: 10: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,361 INFO L290 TraceCheckUtils]: 11: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,361 INFO L290 TraceCheckUtils]: 12: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,361 INFO L290 TraceCheckUtils]: 13: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,361 INFO L290 TraceCheckUtils]: 14: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,362 INFO L290 TraceCheckUtils]: 15: Hoare triple {113588#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,362 INFO L290 TraceCheckUtils]: 16: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,362 INFO L290 TraceCheckUtils]: 17: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,362 INFO L290 TraceCheckUtils]: 18: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,363 INFO L290 TraceCheckUtils]: 19: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,363 INFO L290 TraceCheckUtils]: 20: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,363 INFO L290 TraceCheckUtils]: 21: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,363 INFO L290 TraceCheckUtils]: 22: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,364 INFO L290 TraceCheckUtils]: 23: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T7_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,364 INFO L290 TraceCheckUtils]: 24: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T8_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,364 INFO L290 TraceCheckUtils]: 25: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T9_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,364 INFO L290 TraceCheckUtils]: 26: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~T10_E~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,365 INFO L290 TraceCheckUtils]: 27: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,365 INFO L290 TraceCheckUtils]: 28: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,365 INFO L290 TraceCheckUtils]: 29: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,365 INFO L290 TraceCheckUtils]: 30: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,366 INFO L290 TraceCheckUtils]: 31: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,366 INFO L290 TraceCheckUtils]: 32: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,366 INFO L290 TraceCheckUtils]: 33: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,366 INFO L290 TraceCheckUtils]: 34: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_7~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,367 INFO L290 TraceCheckUtils]: 35: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_8~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,367 INFO L290 TraceCheckUtils]: 36: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_9~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,367 INFO L290 TraceCheckUtils]: 37: Hoare triple {113588#(= ~m_pc~0 0)} assume !(0 == ~E_10~0); {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,367 INFO L290 TraceCheckUtils]: 38: Hoare triple {113588#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {113588#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 39: Hoare triple {113588#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 40: Hoare triple {113587#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 41: Hoare triple {113587#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 42: Hoare triple {113587#false} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 43: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp~1#1); {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 44: Hoare triple {113587#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 45: Hoare triple {113587#false} assume !(1 == ~t1_pc~0); {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 46: Hoare triple {113587#false} is_transmit1_triggered_~__retres1~1#1 := 0; {113587#false} is VALID [2022-02-21 04:23:31,368 INFO L290 TraceCheckUtils]: 47: Hoare triple {113587#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 48: Hoare triple {113587#false} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 49: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___0~0#1); {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 50: Hoare triple {113587#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 51: Hoare triple {113587#false} assume 1 == ~t2_pc~0; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 52: Hoare triple {113587#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 53: Hoare triple {113587#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 54: Hoare triple {113587#false} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 55: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___1~0#1); {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 56: Hoare triple {113587#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {113587#false} is VALID [2022-02-21 04:23:31,369 INFO L290 TraceCheckUtils]: 57: Hoare triple {113587#false} assume 1 == ~t3_pc~0; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 58: Hoare triple {113587#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 59: Hoare triple {113587#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 60: Hoare triple {113587#false} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 61: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___2~0#1); {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 62: Hoare triple {113587#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 63: Hoare triple {113587#false} assume !(1 == ~t4_pc~0); {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 64: Hoare triple {113587#false} is_transmit4_triggered_~__retres1~4#1 := 0; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 65: Hoare triple {113587#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 66: Hoare triple {113587#false} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {113587#false} is VALID [2022-02-21 04:23:31,370 INFO L290 TraceCheckUtils]: 67: Hoare triple {113587#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 68: Hoare triple {113587#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 69: Hoare triple {113587#false} assume 1 == ~t5_pc~0; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 70: Hoare triple {113587#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 71: Hoare triple {113587#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 72: Hoare triple {113587#false} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 73: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___4~0#1); {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 74: Hoare triple {113587#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 75: Hoare triple {113587#false} assume !(1 == ~t6_pc~0); {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 76: Hoare triple {113587#false} is_transmit6_triggered_~__retres1~6#1 := 0; {113587#false} is VALID [2022-02-21 04:23:31,371 INFO L290 TraceCheckUtils]: 77: Hoare triple {113587#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 78: Hoare triple {113587#false} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 79: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___5~0#1); {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 80: Hoare triple {113587#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 81: Hoare triple {113587#false} assume 1 == ~t7_pc~0; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 82: Hoare triple {113587#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 83: Hoare triple {113587#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 84: Hoare triple {113587#false} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 85: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___6~0#1); {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 86: Hoare triple {113587#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {113587#false} is VALID [2022-02-21 04:23:31,372 INFO L290 TraceCheckUtils]: 87: Hoare triple {113587#false} assume !(1 == ~t8_pc~0); {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 88: Hoare triple {113587#false} is_transmit8_triggered_~__retres1~8#1 := 0; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 89: Hoare triple {113587#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 90: Hoare triple {113587#false} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 91: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___7~0#1); {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 92: Hoare triple {113587#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 93: Hoare triple {113587#false} assume 1 == ~t9_pc~0; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 94: Hoare triple {113587#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 95: Hoare triple {113587#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 96: Hoare triple {113587#false} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {113587#false} is VALID [2022-02-21 04:23:31,373 INFO L290 TraceCheckUtils]: 97: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___8~0#1); {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 98: Hoare triple {113587#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 99: Hoare triple {113587#false} assume !(1 == ~t10_pc~0); {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 100: Hoare triple {113587#false} is_transmit10_triggered_~__retres1~10#1 := 0; {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 101: Hoare triple {113587#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 102: Hoare triple {113587#false} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 103: Hoare triple {113587#false} assume !(0 != activate_threads_~tmp___9~0#1); {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 104: Hoare triple {113587#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 105: Hoare triple {113587#false} assume 1 == ~M_E~0;~M_E~0 := 2; {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 106: Hoare triple {113587#false} assume !(1 == ~T1_E~0); {113587#false} is VALID [2022-02-21 04:23:31,374 INFO L290 TraceCheckUtils]: 107: Hoare triple {113587#false} assume !(1 == ~T2_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 108: Hoare triple {113587#false} assume !(1 == ~T3_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 109: Hoare triple {113587#false} assume !(1 == ~T4_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 110: Hoare triple {113587#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 111: Hoare triple {113587#false} assume !(1 == ~T6_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 112: Hoare triple {113587#false} assume !(1 == ~T7_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 113: Hoare triple {113587#false} assume !(1 == ~T8_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 114: Hoare triple {113587#false} assume !(1 == ~T9_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 115: Hoare triple {113587#false} assume !(1 == ~T10_E~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 116: Hoare triple {113587#false} assume !(1 == ~E_M~0); {113587#false} is VALID [2022-02-21 04:23:31,375 INFO L290 TraceCheckUtils]: 117: Hoare triple {113587#false} assume !(1 == ~E_1~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 118: Hoare triple {113587#false} assume 1 == ~E_2~0;~E_2~0 := 2; {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 119: Hoare triple {113587#false} assume !(1 == ~E_3~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 120: Hoare triple {113587#false} assume !(1 == ~E_4~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 121: Hoare triple {113587#false} assume !(1 == ~E_5~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 122: Hoare triple {113587#false} assume !(1 == ~E_6~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 123: Hoare triple {113587#false} assume !(1 == ~E_7~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 124: Hoare triple {113587#false} assume !(1 == ~E_8~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 125: Hoare triple {113587#false} assume !(1 == ~E_9~0); {113587#false} is VALID [2022-02-21 04:23:31,376 INFO L290 TraceCheckUtils]: 126: Hoare triple {113587#false} assume 1 == ~E_10~0;~E_10~0 := 2; {113587#false} is VALID [2022-02-21 04:23:31,377 INFO L290 TraceCheckUtils]: 127: Hoare triple {113587#false} assume { :end_inline_reset_delta_events } true; {113587#false} is VALID [2022-02-21 04:23:31,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,377 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,377 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919188578] [2022-02-21 04:23:31,377 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919188578] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,377 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,377 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:31,377 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357375608] [2022-02-21 04:23:31,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,378 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:31,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:31,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1465377660, now seen corresponding path program 1 times [2022-02-21 04:23:31,379 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:31,379 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978257281] [2022-02-21 04:23:31,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:31,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:31,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:31,416 INFO L290 TraceCheckUtils]: 0: Hoare triple {113589#true} assume !false; {113589#true} is VALID [2022-02-21 04:23:31,416 INFO L290 TraceCheckUtils]: 1: Hoare triple {113589#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {113589#true} is VALID [2022-02-21 04:23:31,416 INFO L290 TraceCheckUtils]: 2: Hoare triple {113589#true} assume !false; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 3: Hoare triple {113589#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 4: Hoare triple {113589#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 5: Hoare triple {113589#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 6: Hoare triple {113589#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 7: Hoare triple {113589#true} assume !(0 != eval_~tmp~0#1); {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 8: Hoare triple {113589#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 9: Hoare triple {113589#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 10: Hoare triple {113589#true} assume 0 == ~M_E~0;~M_E~0 := 1; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 11: Hoare triple {113589#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {113589#true} is VALID [2022-02-21 04:23:31,417 INFO L290 TraceCheckUtils]: 12: Hoare triple {113589#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {113589#true} is VALID [2022-02-21 04:23:31,418 INFO L290 TraceCheckUtils]: 13: Hoare triple {113589#true} assume !(0 == ~T3_E~0); {113589#true} is VALID [2022-02-21 04:23:31,418 INFO L290 TraceCheckUtils]: 14: Hoare triple {113589#true} assume !(0 == ~T4_E~0); {113589#true} is VALID [2022-02-21 04:23:31,418 INFO L290 TraceCheckUtils]: 15: Hoare triple {113589#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {113589#true} is VALID [2022-02-21 04:23:31,418 INFO L290 TraceCheckUtils]: 16: Hoare triple {113589#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,418 INFO L290 TraceCheckUtils]: 17: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,419 INFO L290 TraceCheckUtils]: 18: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,419 INFO L290 TraceCheckUtils]: 19: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,419 INFO L290 TraceCheckUtils]: 20: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,419 INFO L290 TraceCheckUtils]: 21: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,420 INFO L290 TraceCheckUtils]: 22: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_1~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,420 INFO L290 TraceCheckUtils]: 23: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,420 INFO L290 TraceCheckUtils]: 24: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,420 INFO L290 TraceCheckUtils]: 25: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,421 INFO L290 TraceCheckUtils]: 26: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,421 INFO L290 TraceCheckUtils]: 27: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,421 INFO L290 TraceCheckUtils]: 28: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,421 INFO L290 TraceCheckUtils]: 29: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,422 INFO L290 TraceCheckUtils]: 30: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_9~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,422 INFO L290 TraceCheckUtils]: 31: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,422 INFO L290 TraceCheckUtils]: 32: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,422 INFO L290 TraceCheckUtils]: 33: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,423 INFO L290 TraceCheckUtils]: 34: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,423 INFO L290 TraceCheckUtils]: 35: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,423 INFO L290 TraceCheckUtils]: 36: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,423 INFO L290 TraceCheckUtils]: 37: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,424 INFO L290 TraceCheckUtils]: 38: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,424 INFO L290 TraceCheckUtils]: 39: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,424 INFO L290 TraceCheckUtils]: 40: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,425 INFO L290 TraceCheckUtils]: 41: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,425 INFO L290 TraceCheckUtils]: 42: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,425 INFO L290 TraceCheckUtils]: 43: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,425 INFO L290 TraceCheckUtils]: 44: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,426 INFO L290 TraceCheckUtils]: 45: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,426 INFO L290 TraceCheckUtils]: 46: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,426 INFO L290 TraceCheckUtils]: 47: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,426 INFO L290 TraceCheckUtils]: 48: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,427 INFO L290 TraceCheckUtils]: 49: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,427 INFO L290 TraceCheckUtils]: 50: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,427 INFO L290 TraceCheckUtils]: 51: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,427 INFO L290 TraceCheckUtils]: 52: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,428 INFO L290 TraceCheckUtils]: 53: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,428 INFO L290 TraceCheckUtils]: 54: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,428 INFO L290 TraceCheckUtils]: 55: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,428 INFO L290 TraceCheckUtils]: 56: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,429 INFO L290 TraceCheckUtils]: 57: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,429 INFO L290 TraceCheckUtils]: 58: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,429 INFO L290 TraceCheckUtils]: 59: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,429 INFO L290 TraceCheckUtils]: 60: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,430 INFO L290 TraceCheckUtils]: 61: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,430 INFO L290 TraceCheckUtils]: 62: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,430 INFO L290 TraceCheckUtils]: 63: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,430 INFO L290 TraceCheckUtils]: 64: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,431 INFO L290 TraceCheckUtils]: 65: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,431 INFO L290 TraceCheckUtils]: 66: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,431 INFO L290 TraceCheckUtils]: 67: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,431 INFO L290 TraceCheckUtils]: 68: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,432 INFO L290 TraceCheckUtils]: 69: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,432 INFO L290 TraceCheckUtils]: 70: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,432 INFO L290 TraceCheckUtils]: 71: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,432 INFO L290 TraceCheckUtils]: 72: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,433 INFO L290 TraceCheckUtils]: 73: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,433 INFO L290 TraceCheckUtils]: 74: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,433 INFO L290 TraceCheckUtils]: 75: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,433 INFO L290 TraceCheckUtils]: 76: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,434 INFO L290 TraceCheckUtils]: 77: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,434 INFO L290 TraceCheckUtils]: 78: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,434 INFO L290 TraceCheckUtils]: 79: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,434 INFO L290 TraceCheckUtils]: 80: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,435 INFO L290 TraceCheckUtils]: 81: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,435 INFO L290 TraceCheckUtils]: 82: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,435 INFO L290 TraceCheckUtils]: 83: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,435 INFO L290 TraceCheckUtils]: 84: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,436 INFO L290 TraceCheckUtils]: 85: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,436 INFO L290 TraceCheckUtils]: 86: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,436 INFO L290 TraceCheckUtils]: 87: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,437 INFO L290 TraceCheckUtils]: 88: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,437 INFO L290 TraceCheckUtils]: 89: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,437 INFO L290 TraceCheckUtils]: 90: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,437 INFO L290 TraceCheckUtils]: 91: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,438 INFO L290 TraceCheckUtils]: 92: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,438 INFO L290 TraceCheckUtils]: 93: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,438 INFO L290 TraceCheckUtils]: 94: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,438 INFO L290 TraceCheckUtils]: 95: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,439 INFO L290 TraceCheckUtils]: 96: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,439 INFO L290 TraceCheckUtils]: 97: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,439 INFO L290 TraceCheckUtils]: 98: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,439 INFO L290 TraceCheckUtils]: 99: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,440 INFO L290 TraceCheckUtils]: 100: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,440 INFO L290 TraceCheckUtils]: 101: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,440 INFO L290 TraceCheckUtils]: 102: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,440 INFO L290 TraceCheckUtils]: 103: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,441 INFO L290 TraceCheckUtils]: 104: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {113591#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:31,441 INFO L290 TraceCheckUtils]: 105: Hoare triple {113591#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {113590#false} is VALID [2022-02-21 04:23:31,441 INFO L290 TraceCheckUtils]: 106: Hoare triple {113590#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,441 INFO L290 TraceCheckUtils]: 107: Hoare triple {113590#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,441 INFO L290 TraceCheckUtils]: 108: Hoare triple {113590#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,441 INFO L290 TraceCheckUtils]: 109: Hoare triple {113590#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,441 INFO L290 TraceCheckUtils]: 110: Hoare triple {113590#false} assume 1 == ~E_M~0;~E_M~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 111: Hoare triple {113590#false} assume 1 == ~E_1~0;~E_1~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 112: Hoare triple {113590#false} assume 1 == ~E_2~0;~E_2~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 113: Hoare triple {113590#false} assume !(1 == ~E_3~0); {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 114: Hoare triple {113590#false} assume 1 == ~E_4~0;~E_4~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 115: Hoare triple {113590#false} assume 1 == ~E_5~0;~E_5~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 116: Hoare triple {113590#false} assume 1 == ~E_6~0;~E_6~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 117: Hoare triple {113590#false} assume 1 == ~E_7~0;~E_7~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 118: Hoare triple {113590#false} assume 1 == ~E_8~0;~E_8~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 119: Hoare triple {113590#false} assume 1 == ~E_9~0;~E_9~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,442 INFO L290 TraceCheckUtils]: 120: Hoare triple {113590#false} assume 1 == ~E_10~0;~E_10~0 := 2; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 121: Hoare triple {113590#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 122: Hoare triple {113590#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 123: Hoare triple {113590#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 124: Hoare triple {113590#false} start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 125: Hoare triple {113590#false} assume !(0 == start_simulation_~tmp~3#1); {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 126: Hoare triple {113590#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 127: Hoare triple {113590#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 128: Hoare triple {113590#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 129: Hoare triple {113590#false} stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; {113590#false} is VALID [2022-02-21 04:23:31,443 INFO L290 TraceCheckUtils]: 130: Hoare triple {113590#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {113590#false} is VALID [2022-02-21 04:23:31,444 INFO L290 TraceCheckUtils]: 131: Hoare triple {113590#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {113590#false} is VALID [2022-02-21 04:23:31,444 INFO L290 TraceCheckUtils]: 132: Hoare triple {113590#false} start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; {113590#false} is VALID [2022-02-21 04:23:31,444 INFO L290 TraceCheckUtils]: 133: Hoare triple {113590#false} assume !(0 != start_simulation_~tmp___0~1#1); {113590#false} is VALID [2022-02-21 04:23:31,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:31,444 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:31,444 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978257281] [2022-02-21 04:23:31,444 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978257281] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:31,445 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:31,445 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:31,445 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588393702] [2022-02-21 04:23:31,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:31,445 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:31,445 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:31,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:31,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:31,446 INFO L87 Difference]: Start difference. First operand 8648 states and 12708 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,650 INFO L93 Difference]: Finished difference Result 16971 states and 24755 transitions. [2022-02-21 04:23:38,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:38,650 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,726 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 128 edges. 128 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:38,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16971 states and 24755 transitions. [2022-02-21 04:23:44,814 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16753 [2022-02-21 04:23:50,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16971 states to 16971 states and 24755 transitions. [2022-02-21 04:23:50,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16971 [2022-02-21 04:23:50,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16971 [2022-02-21 04:23:50,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16971 states and 24755 transitions. [2022-02-21 04:23:51,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:51,065 INFO L681 BuchiCegarLoop]: Abstraction has 16971 states and 24755 transitions. [2022-02-21 04:23:51,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16971 states and 24755 transitions. [2022-02-21 04:23:51,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16971 to 16363. [2022-02-21 04:23:51,246 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:51,265 INFO L82 GeneralOperation]: Start isEquivalent. First operand 16971 states and 24755 transitions. Second operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:51,284 INFO L74 IsIncluded]: Start isIncluded. First operand 16971 states and 24755 transitions. Second operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:51,304 INFO L87 Difference]: Start difference. First operand 16971 states and 24755 transitions. Second operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:57,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:57,924 INFO L93 Difference]: Finished difference Result 16971 states and 24755 transitions. [2022-02-21 04:23:57,924 INFO L276 IsEmpty]: Start isEmpty. Operand 16971 states and 24755 transitions. [2022-02-21 04:23:57,940 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:57,940 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:57,959 INFO L74 IsIncluded]: Start isIncluded. First operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 16971 states and 24755 transitions. [2022-02-21 04:23:57,977 INFO L87 Difference]: Start difference. First operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 16971 states and 24755 transitions. [2022-02-21 04:24:03,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:03,700 INFO L93 Difference]: Finished difference Result 16971 states and 24755 transitions. [2022-02-21 04:24:03,701 INFO L276 IsEmpty]: Start isEmpty. Operand 16971 states and 24755 transitions. [2022-02-21 04:24:03,712 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:03,712 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:03,713 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:03,713 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:03,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)