./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:22:56,812 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:22:56,814 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:22:56,846 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:22:56,847 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:22:56,850 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:22:56,851 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:22:56,853 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:22:56,855 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:22:56,859 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:22:56,860 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:22:56,861 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:22:56,861 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:22:56,863 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:22:56,864 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:22:56,866 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:22:56,867 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:22:56,867 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:22:56,869 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:22:56,874 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:22:56,875 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:22:56,876 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:22:56,877 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:22:56,878 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:22:56,883 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:22:56,883 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:22:56,883 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:22:56,885 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:22:56,885 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:22:56,886 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:22:56,886 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:22:56,887 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:22:56,888 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:22:56,889 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:22:56,889 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:22:56,890 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:22:56,890 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:22:56,890 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:22:56,890 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:22:56,891 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:22:56,891 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:22:56,893 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:22:56,917 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:22:56,917 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:22:56,917 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:22:56,917 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:22:56,918 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:22:56,919 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:22:56,919 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:22:56,919 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:22:56,919 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:22:56,919 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:22:56,920 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:22:56,920 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:22:56,920 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:22:56,920 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:22:56,920 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:22:56,920 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:22:56,921 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:22:56,922 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:22:56,922 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:22:56,922 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:22:56,922 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:22:56,922 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:22:56,922 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:22:56,923 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:22:56,924 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:22:56,924 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2022-02-21 04:22:57,142 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:22:57,168 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:22:57,169 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:22:57,170 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:22:57,171 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:22:57,172 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2022-02-21 04:22:57,239 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/11f1382e1/85d9457159c34ad8bc5710f794e15e20/FLAG6bf49b20b [2022-02-21 04:22:57,669 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:22:57,680 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2022-02-21 04:22:57,696 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/11f1382e1/85d9457159c34ad8bc5710f794e15e20/FLAG6bf49b20b [2022-02-21 04:22:57,709 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/11f1382e1/85d9457159c34ad8bc5710f794e15e20 [2022-02-21 04:22:57,711 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:22:57,712 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:22:57,714 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:57,715 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:22:57,717 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:22:57,719 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:57" (1/1) ... [2022-02-21 04:22:57,720 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ecbeb8e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:57, skipping insertion in model container [2022-02-21 04:22:57,720 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:22:57" (1/1) ... [2022-02-21 04:22:57,725 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:22:57,766 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:22:57,926 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2022-02-21 04:22:58,051 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:58,066 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:22:58,082 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2022-02-21 04:22:58,117 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:22:58,129 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:22:58,130 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58 WrapperNode [2022-02-21 04:22:58,130 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:22:58,131 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:58,131 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:22:58,131 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:22:58,136 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,154 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,280 INFO L137 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 238, statements flattened = 3645 [2022-02-21 04:22:58,281 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:22:58,282 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:22:58,282 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:22:58,282 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:22:58,288 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,288 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,298 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,298 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,338 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,368 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,374 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,387 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:22:58,388 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:22:58,388 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:22:58,388 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:22:58,390 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (1/1) ... [2022-02-21 04:22:58,395 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:22:58,402 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:22:58,414 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:22:58,433 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:22:58,451 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:22:58,452 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:22:58,452 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:22:58,452 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:22:58,537 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:22:58,538 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:23:00,185 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:23:00,199 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:23:00,200 INFO L299 CfgBuilder]: Removed 14 assume(true) statements. [2022-02-21 04:23:00,202 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:00 BoogieIcfgContainer [2022-02-21 04:23:00,202 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:23:00,203 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:23:00,203 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:23:00,206 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:23:00,206 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:00,206 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:22:57" (1/3) ... [2022-02-21 04:23:00,207 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@88967a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:00, skipping insertion in model container [2022-02-21 04:23:00,207 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:00,207 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:22:58" (2/3) ... [2022-02-21 04:23:00,208 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@88967a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:00, skipping insertion in model container [2022-02-21 04:23:00,208 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:00,208 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:00" (3/3) ... [2022-02-21 04:23:00,209 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2022-02-21 04:23:00,237 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:23:00,237 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:23:00,237 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:23:00,237 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:23:00,237 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:23:00,238 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:23:00,238 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:23:00,238 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:23:00,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2022-02-21 04:23:00,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:00,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:00,521 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,522 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:23:00,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:00,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2022-02-21 04:23:00,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:00,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:00,645 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,645 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:00,652 INFO L791 eck$LassoCheckResult]: Stem: 395#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1507#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1131#L1641true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1514#L773true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1152#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1400#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1084#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1398#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 303#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 572#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1095#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1031#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 255#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 727#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 195#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 928#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1453#L1109true assume !(0 == ~M_E~0); 963#L1109-2true assume !(0 == ~T1_E~0); 199#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1523#L1119-1true assume !(0 == ~T3_E~0); 1036#L1124-1true assume !(0 == ~T4_E~0); 27#L1129-1true assume !(0 == ~T5_E~0); 350#L1134-1true assume !(0 == ~T6_E~0); 945#L1139-1true assume !(0 == ~T7_E~0); 1021#L1144-1true assume !(0 == ~T8_E~0); 784#L1149-1true assume !(0 == ~T9_E~0); 75#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 920#L1159-1true assume !(0 == ~T11_E~0); 769#L1164-1true assume !(0 == ~E_M~0); 282#L1169-1true assume !(0 == ~E_1~0); 224#L1174-1true assume !(0 == ~E_2~0); 155#L1179-1true assume !(0 == ~E_3~0); 116#L1184-1true assume !(0 == ~E_4~0); 134#L1189-1true assume !(0 == ~E_5~0); 180#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 791#L1199-1true assume !(0 == ~E_7~0); 969#L1204-1true assume !(0 == ~E_8~0); 723#L1209-1true assume !(0 == ~E_9~0); 1177#L1214-1true assume !(0 == ~E_10~0); 1526#L1219-1true assume !(0 == ~E_11~0); 1470#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293#L544true assume 1 == ~m_pc~0; 1029#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1188#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 798#L556true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96#L1379true assume !(0 != activate_threads_~tmp~1#1); 1393#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 557#L563true assume !(1 == ~t1_pc~0); 1184#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 32#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1107#L575true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 665#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 30#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405#L582true assume 1 == ~t2_pc~0; 886#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 675#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 783#L594true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 843#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 46#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 757#L601true assume !(1 == ~t3_pc~0); 463#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1016#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1219#L613true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 706#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1410#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 655#L620true assume 1 == ~t4_pc~0; 37#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 364#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 329#L632true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 569#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 759#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 740#L639true assume 1 == ~t5_pc~0; 630#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 183#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 590#L651true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 584#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 849#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 529#L658true assume !(1 == ~t6_pc~0); 291#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 697#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1136#L670true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1477#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 710#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 205#L677true assume 1 == ~t7_pc~0; 1245#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 889#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1341#L689true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1071#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1230#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1304#L696true assume !(1 == ~t8_pc~0); 324#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1150#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1196#L708true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1347#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1521#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 618#L715true assume 1 == ~t9_pc~0; 1222#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 381#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 323#L727true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 605#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1391#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 887#L734true assume !(1 == ~t10_pc~0); 1038#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 268#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 277#L746true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 813#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1257#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 311#L753true assume 1 == ~t11_pc~0; 716#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1570#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 377#L765true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 475#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 777#L1467-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 514#L1237true assume !(1 == ~M_E~0); 1299#L1237-2true assume !(1 == ~T1_E~0); 1420#L1242-1true assume !(1 == ~T2_E~0); 361#L1247-1true assume !(1 == ~T3_E~0); 1067#L1252-1true assume !(1 == ~T4_E~0); 235#L1257-1true assume !(1 == ~T5_E~0); 908#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1054#L1267-1true assume !(1 == ~T7_E~0); 1055#L1272-1true assume !(1 == ~T8_E~0); 411#L1277-1true assume !(1 == ~T9_E~0); 823#L1282-1true assume !(1 == ~T10_E~0); 751#L1287-1true assume !(1 == ~T11_E~0); 792#L1292-1true assume !(1 == ~E_M~0); 709#L1297-1true assume !(1 == ~E_1~0); 307#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1040#L1307-1true assume !(1 == ~E_3~0); 1357#L1312-1true assume !(1 == ~E_4~0); 438#L1317-1true assume !(1 == ~E_5~0); 613#L1322-1true assume !(1 == ~E_6~0); 275#L1327-1true assume !(1 == ~E_7~0); 664#L1332-1true assume !(1 == ~E_8~0); 1336#L1337-1true assume !(1 == ~E_9~0); 609#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1234#L1347-1true assume !(1 == ~E_11~0); 1039#L1352-1true assume { :end_inline_reset_delta_events } true; 1564#L1678-2true [2022-02-21 04:23:00,654 INFO L793 eck$LassoCheckResult]: Loop: 1564#L1678-2true assume !false; 656#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 817#L1084true assume !true; 171#L1099true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105#L773-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1423#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 38#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1215#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 711#L1119-3true assume !(0 == ~T3_E~0); 1559#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 736#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 954#L1134-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1115#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1027#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 298#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1551#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 443#L1159-3true assume !(0 == ~T11_E~0); 1538#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 652#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 986#L1174-3true assume 0 == ~E_2~0;~E_2~0 := 1; 699#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1306#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 870#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 551#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 168#L1199-3true assume !(0 == ~E_7~0); 794#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 288#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 15#L1214-3true assume 0 == ~E_10~0;~E_10~0 := 1; 602#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 386#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 644#L544-39true assume !(1 == ~m_pc~0); 5#L544-41true is_master_triggered_~__retres1~0#1 := 0; 738#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124#L556-13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 209#L1379-39true assume !(0 != activate_threads_~tmp~1#1); 848#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1317#L563-39true assume !(1 == ~t1_pc~0); 73#L563-41true is_transmit1_triggered_~__retres1~1#1 := 0; 1539#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 625#L575-13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1434#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1446#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1003#L582-39true assume 1 == ~t2_pc~0; 243#L583-13true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 761#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 667#L594-13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 971#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 120#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20#L601-39true assume 1 == ~t3_pc~0; 1236#L602-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 807#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 985#L613-13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1492#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 856#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527#L620-39true assume 1 == ~t4_pc~0; 695#L621-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 940#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1500#L632-13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 821#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1546#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1543#L639-39true assume 1 == ~t5_pc~0; 978#L640-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 365#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127#L651-13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33#L1419-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1380#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 555#L658-39true assume 1 == ~t6_pc~0; 540#L659-13true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1065#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10#L670-13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 720#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 692#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238#L677-39true assume 1 == ~t7_pc~0; 659#L678-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 992#L689-13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 145#L1435-39true assume !(0 != activate_threads_~tmp___6~0#1); 1369#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 477#L696-39true assume !(1 == ~t8_pc~0); 781#L696-41true is_transmit8_triggered_~__retres1~8#1 := 0; 375#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1495#L708-13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 578#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 547#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 461#L715-39true assume !(1 == ~t9_pc~0); 1058#L715-41true is_transmit9_triggered_~__retres1~9#1 := 0; 815#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1569#L727-13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1568#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 742#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1141#L734-39true assume !(1 == ~t10_pc~0); 281#L734-41true is_transmit10_triggered_~__retres1~10#1 := 0; 478#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 746#L746-13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1460#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1091#L753-39true assume !(1 == ~t11_pc~0); 56#L753-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1019#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1147#L765-13true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 455#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 750#L1467-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 525#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1086#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 773#L1242-3true assume !(1 == ~T2_E~0); 1511#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1053#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 689#L1257-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1022#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1098#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1528#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1334#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 130#L1282-3true assume !(1 == ~T10_E~0); 666#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 82#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1489#L1297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 900#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1227#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1509#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1503#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 795#L1322-3true assume !(1 == ~E_6~0); 1556#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 112#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 99#L1337-3true assume 1 == ~E_9~0;~E_9~0 := 2; 504#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 943#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 604#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 891#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 214#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 698#L911-1true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 741#L1697true assume !(0 == start_simulation_~tmp~3#1); 520#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1309#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 857#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 619#L911-2true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1119#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 574#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#L1660true start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 888#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1564#L1678-2true [2022-02-21 04:23:00,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:00,674 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2022-02-21 04:23:00,680 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:00,681 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348915071] [2022-02-21 04:23:00,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:00,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:00,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:00,868 INFO L290 TraceCheckUtils]: 0: Hoare triple {1576#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {1576#true} is VALID [2022-02-21 04:23:00,869 INFO L290 TraceCheckUtils]: 1: Hoare triple {1576#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {1578#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:00,870 INFO L290 TraceCheckUtils]: 2: Hoare triple {1578#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1578#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:00,871 INFO L290 TraceCheckUtils]: 3: Hoare triple {1578#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1578#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:00,871 INFO L290 TraceCheckUtils]: 4: Hoare triple {1578#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,871 INFO L290 TraceCheckUtils]: 5: Hoare triple {1577#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1577#false} is VALID [2022-02-21 04:23:00,871 INFO L290 TraceCheckUtils]: 6: Hoare triple {1577#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,872 INFO L290 TraceCheckUtils]: 7: Hoare triple {1577#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,872 INFO L290 TraceCheckUtils]: 8: Hoare triple {1577#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,872 INFO L290 TraceCheckUtils]: 9: Hoare triple {1577#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,873 INFO L290 TraceCheckUtils]: 10: Hoare triple {1577#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,873 INFO L290 TraceCheckUtils]: 11: Hoare triple {1577#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,873 INFO L290 TraceCheckUtils]: 12: Hoare triple {1577#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,873 INFO L290 TraceCheckUtils]: 13: Hoare triple {1577#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1577#false} is VALID [2022-02-21 04:23:00,873 INFO L290 TraceCheckUtils]: 14: Hoare triple {1577#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,874 INFO L290 TraceCheckUtils]: 15: Hoare triple {1577#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,874 INFO L290 TraceCheckUtils]: 16: Hoare triple {1577#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1577#false} is VALID [2022-02-21 04:23:00,874 INFO L290 TraceCheckUtils]: 17: Hoare triple {1577#false} assume !(0 == ~M_E~0); {1577#false} is VALID [2022-02-21 04:23:00,874 INFO L290 TraceCheckUtils]: 18: Hoare triple {1577#false} assume !(0 == ~T1_E~0); {1577#false} is VALID [2022-02-21 04:23:00,874 INFO L290 TraceCheckUtils]: 19: Hoare triple {1577#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1577#false} is VALID [2022-02-21 04:23:00,875 INFO L290 TraceCheckUtils]: 20: Hoare triple {1577#false} assume !(0 == ~T3_E~0); {1577#false} is VALID [2022-02-21 04:23:00,875 INFO L290 TraceCheckUtils]: 21: Hoare triple {1577#false} assume !(0 == ~T4_E~0); {1577#false} is VALID [2022-02-21 04:23:00,875 INFO L290 TraceCheckUtils]: 22: Hoare triple {1577#false} assume !(0 == ~T5_E~0); {1577#false} is VALID [2022-02-21 04:23:00,876 INFO L290 TraceCheckUtils]: 23: Hoare triple {1577#false} assume !(0 == ~T6_E~0); {1577#false} is VALID [2022-02-21 04:23:00,876 INFO L290 TraceCheckUtils]: 24: Hoare triple {1577#false} assume !(0 == ~T7_E~0); {1577#false} is VALID [2022-02-21 04:23:00,877 INFO L290 TraceCheckUtils]: 25: Hoare triple {1577#false} assume !(0 == ~T8_E~0); {1577#false} is VALID [2022-02-21 04:23:00,877 INFO L290 TraceCheckUtils]: 26: Hoare triple {1577#false} assume !(0 == ~T9_E~0); {1577#false} is VALID [2022-02-21 04:23:00,877 INFO L290 TraceCheckUtils]: 27: Hoare triple {1577#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1577#false} is VALID [2022-02-21 04:23:00,877 INFO L290 TraceCheckUtils]: 28: Hoare triple {1577#false} assume !(0 == ~T11_E~0); {1577#false} is VALID [2022-02-21 04:23:00,878 INFO L290 TraceCheckUtils]: 29: Hoare triple {1577#false} assume !(0 == ~E_M~0); {1577#false} is VALID [2022-02-21 04:23:00,878 INFO L290 TraceCheckUtils]: 30: Hoare triple {1577#false} assume !(0 == ~E_1~0); {1577#false} is VALID [2022-02-21 04:23:00,878 INFO L290 TraceCheckUtils]: 31: Hoare triple {1577#false} assume !(0 == ~E_2~0); {1577#false} is VALID [2022-02-21 04:23:00,878 INFO L290 TraceCheckUtils]: 32: Hoare triple {1577#false} assume !(0 == ~E_3~0); {1577#false} is VALID [2022-02-21 04:23:00,878 INFO L290 TraceCheckUtils]: 33: Hoare triple {1577#false} assume !(0 == ~E_4~0); {1577#false} is VALID [2022-02-21 04:23:00,879 INFO L290 TraceCheckUtils]: 34: Hoare triple {1577#false} assume !(0 == ~E_5~0); {1577#false} is VALID [2022-02-21 04:23:00,879 INFO L290 TraceCheckUtils]: 35: Hoare triple {1577#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1577#false} is VALID [2022-02-21 04:23:00,879 INFO L290 TraceCheckUtils]: 36: Hoare triple {1577#false} assume !(0 == ~E_7~0); {1577#false} is VALID [2022-02-21 04:23:00,879 INFO L290 TraceCheckUtils]: 37: Hoare triple {1577#false} assume !(0 == ~E_8~0); {1577#false} is VALID [2022-02-21 04:23:00,879 INFO L290 TraceCheckUtils]: 38: Hoare triple {1577#false} assume !(0 == ~E_9~0); {1577#false} is VALID [2022-02-21 04:23:00,880 INFO L290 TraceCheckUtils]: 39: Hoare triple {1577#false} assume !(0 == ~E_10~0); {1577#false} is VALID [2022-02-21 04:23:00,880 INFO L290 TraceCheckUtils]: 40: Hoare triple {1577#false} assume !(0 == ~E_11~0); {1577#false} is VALID [2022-02-21 04:23:00,880 INFO L290 TraceCheckUtils]: 41: Hoare triple {1577#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1577#false} is VALID [2022-02-21 04:23:00,881 INFO L290 TraceCheckUtils]: 42: Hoare triple {1577#false} assume 1 == ~m_pc~0; {1577#false} is VALID [2022-02-21 04:23:00,881 INFO L290 TraceCheckUtils]: 43: Hoare triple {1577#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1577#false} is VALID [2022-02-21 04:23:00,881 INFO L290 TraceCheckUtils]: 44: Hoare triple {1577#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1577#false} is VALID [2022-02-21 04:23:00,882 INFO L290 TraceCheckUtils]: 45: Hoare triple {1577#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1577#false} is VALID [2022-02-21 04:23:00,882 INFO L290 TraceCheckUtils]: 46: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp~1#1); {1577#false} is VALID [2022-02-21 04:23:00,882 INFO L290 TraceCheckUtils]: 47: Hoare triple {1577#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1577#false} is VALID [2022-02-21 04:23:00,882 INFO L290 TraceCheckUtils]: 48: Hoare triple {1577#false} assume !(1 == ~t1_pc~0); {1577#false} is VALID [2022-02-21 04:23:00,882 INFO L290 TraceCheckUtils]: 49: Hoare triple {1577#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1577#false} is VALID [2022-02-21 04:23:00,885 INFO L290 TraceCheckUtils]: 50: Hoare triple {1577#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1577#false} is VALID [2022-02-21 04:23:00,885 INFO L290 TraceCheckUtils]: 51: Hoare triple {1577#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1577#false} is VALID [2022-02-21 04:23:00,886 INFO L290 TraceCheckUtils]: 52: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___0~0#1); {1577#false} is VALID [2022-02-21 04:23:00,886 INFO L290 TraceCheckUtils]: 53: Hoare triple {1577#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1577#false} is VALID [2022-02-21 04:23:00,886 INFO L290 TraceCheckUtils]: 54: Hoare triple {1577#false} assume 1 == ~t2_pc~0; {1577#false} is VALID [2022-02-21 04:23:00,888 INFO L290 TraceCheckUtils]: 55: Hoare triple {1577#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1577#false} is VALID [2022-02-21 04:23:00,889 INFO L290 TraceCheckUtils]: 56: Hoare triple {1577#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1577#false} is VALID [2022-02-21 04:23:00,889 INFO L290 TraceCheckUtils]: 57: Hoare triple {1577#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1577#false} is VALID [2022-02-21 04:23:00,889 INFO L290 TraceCheckUtils]: 58: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___1~0#1); {1577#false} is VALID [2022-02-21 04:23:00,889 INFO L290 TraceCheckUtils]: 59: Hoare triple {1577#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1577#false} is VALID [2022-02-21 04:23:00,890 INFO L290 TraceCheckUtils]: 60: Hoare triple {1577#false} assume !(1 == ~t3_pc~0); {1577#false} is VALID [2022-02-21 04:23:00,890 INFO L290 TraceCheckUtils]: 61: Hoare triple {1577#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1577#false} is VALID [2022-02-21 04:23:00,891 INFO L290 TraceCheckUtils]: 62: Hoare triple {1577#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1577#false} is VALID [2022-02-21 04:23:00,892 INFO L290 TraceCheckUtils]: 63: Hoare triple {1577#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1577#false} is VALID [2022-02-21 04:23:00,892 INFO L290 TraceCheckUtils]: 64: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___2~0#1); {1577#false} is VALID [2022-02-21 04:23:00,894 INFO L290 TraceCheckUtils]: 65: Hoare triple {1577#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1577#false} is VALID [2022-02-21 04:23:00,894 INFO L290 TraceCheckUtils]: 66: Hoare triple {1577#false} assume 1 == ~t4_pc~0; {1577#false} is VALID [2022-02-21 04:23:00,894 INFO L290 TraceCheckUtils]: 67: Hoare triple {1577#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1577#false} is VALID [2022-02-21 04:23:00,895 INFO L290 TraceCheckUtils]: 68: Hoare triple {1577#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1577#false} is VALID [2022-02-21 04:23:00,895 INFO L290 TraceCheckUtils]: 69: Hoare triple {1577#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1577#false} is VALID [2022-02-21 04:23:00,896 INFO L290 TraceCheckUtils]: 70: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___3~0#1); {1577#false} is VALID [2022-02-21 04:23:00,896 INFO L290 TraceCheckUtils]: 71: Hoare triple {1577#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1577#false} is VALID [2022-02-21 04:23:00,896 INFO L290 TraceCheckUtils]: 72: Hoare triple {1577#false} assume 1 == ~t5_pc~0; {1577#false} is VALID [2022-02-21 04:23:00,896 INFO L290 TraceCheckUtils]: 73: Hoare triple {1577#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1577#false} is VALID [2022-02-21 04:23:00,900 INFO L290 TraceCheckUtils]: 74: Hoare triple {1577#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1577#false} is VALID [2022-02-21 04:23:00,901 INFO L290 TraceCheckUtils]: 75: Hoare triple {1577#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1577#false} is VALID [2022-02-21 04:23:00,901 INFO L290 TraceCheckUtils]: 76: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___4~0#1); {1577#false} is VALID [2022-02-21 04:23:00,901 INFO L290 TraceCheckUtils]: 77: Hoare triple {1577#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1577#false} is VALID [2022-02-21 04:23:00,901 INFO L290 TraceCheckUtils]: 78: Hoare triple {1577#false} assume !(1 == ~t6_pc~0); {1577#false} is VALID [2022-02-21 04:23:00,901 INFO L290 TraceCheckUtils]: 79: Hoare triple {1577#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1577#false} is VALID [2022-02-21 04:23:00,902 INFO L290 TraceCheckUtils]: 80: Hoare triple {1577#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1577#false} is VALID [2022-02-21 04:23:00,902 INFO L290 TraceCheckUtils]: 81: Hoare triple {1577#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1577#false} is VALID [2022-02-21 04:23:00,902 INFO L290 TraceCheckUtils]: 82: Hoare triple {1577#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1577#false} is VALID [2022-02-21 04:23:00,902 INFO L290 TraceCheckUtils]: 83: Hoare triple {1577#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1577#false} is VALID [2022-02-21 04:23:00,902 INFO L290 TraceCheckUtils]: 84: Hoare triple {1577#false} assume 1 == ~t7_pc~0; {1577#false} is VALID [2022-02-21 04:23:00,903 INFO L290 TraceCheckUtils]: 85: Hoare triple {1577#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1577#false} is VALID [2022-02-21 04:23:00,903 INFO L290 TraceCheckUtils]: 86: Hoare triple {1577#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1577#false} is VALID [2022-02-21 04:23:00,903 INFO L290 TraceCheckUtils]: 87: Hoare triple {1577#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1577#false} is VALID [2022-02-21 04:23:00,903 INFO L290 TraceCheckUtils]: 88: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___6~0#1); {1577#false} is VALID [2022-02-21 04:23:00,903 INFO L290 TraceCheckUtils]: 89: Hoare triple {1577#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1577#false} is VALID [2022-02-21 04:23:00,904 INFO L290 TraceCheckUtils]: 90: Hoare triple {1577#false} assume !(1 == ~t8_pc~0); {1577#false} is VALID [2022-02-21 04:23:00,904 INFO L290 TraceCheckUtils]: 91: Hoare triple {1577#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1577#false} is VALID [2022-02-21 04:23:00,904 INFO L290 TraceCheckUtils]: 92: Hoare triple {1577#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1577#false} is VALID [2022-02-21 04:23:00,904 INFO L290 TraceCheckUtils]: 93: Hoare triple {1577#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1577#false} is VALID [2022-02-21 04:23:00,904 INFO L290 TraceCheckUtils]: 94: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___7~0#1); {1577#false} is VALID [2022-02-21 04:23:00,904 INFO L290 TraceCheckUtils]: 95: Hoare triple {1577#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1577#false} is VALID [2022-02-21 04:23:00,905 INFO L290 TraceCheckUtils]: 96: Hoare triple {1577#false} assume 1 == ~t9_pc~0; {1577#false} is VALID [2022-02-21 04:23:00,905 INFO L290 TraceCheckUtils]: 97: Hoare triple {1577#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1577#false} is VALID [2022-02-21 04:23:00,905 INFO L290 TraceCheckUtils]: 98: Hoare triple {1577#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1577#false} is VALID [2022-02-21 04:23:00,905 INFO L290 TraceCheckUtils]: 99: Hoare triple {1577#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1577#false} is VALID [2022-02-21 04:23:00,905 INFO L290 TraceCheckUtils]: 100: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___8~0#1); {1577#false} is VALID [2022-02-21 04:23:00,906 INFO L290 TraceCheckUtils]: 101: Hoare triple {1577#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1577#false} is VALID [2022-02-21 04:23:00,906 INFO L290 TraceCheckUtils]: 102: Hoare triple {1577#false} assume !(1 == ~t10_pc~0); {1577#false} is VALID [2022-02-21 04:23:00,906 INFO L290 TraceCheckUtils]: 103: Hoare triple {1577#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1577#false} is VALID [2022-02-21 04:23:00,906 INFO L290 TraceCheckUtils]: 104: Hoare triple {1577#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1577#false} is VALID [2022-02-21 04:23:00,907 INFO L290 TraceCheckUtils]: 105: Hoare triple {1577#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1577#false} is VALID [2022-02-21 04:23:00,909 INFO L290 TraceCheckUtils]: 106: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___9~0#1); {1577#false} is VALID [2022-02-21 04:23:00,909 INFO L290 TraceCheckUtils]: 107: Hoare triple {1577#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1577#false} is VALID [2022-02-21 04:23:00,909 INFO L290 TraceCheckUtils]: 108: Hoare triple {1577#false} assume 1 == ~t11_pc~0; {1577#false} is VALID [2022-02-21 04:23:00,909 INFO L290 TraceCheckUtils]: 109: Hoare triple {1577#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {1577#false} is VALID [2022-02-21 04:23:00,909 INFO L290 TraceCheckUtils]: 110: Hoare triple {1577#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1577#false} is VALID [2022-02-21 04:23:00,910 INFO L290 TraceCheckUtils]: 111: Hoare triple {1577#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1577#false} is VALID [2022-02-21 04:23:00,910 INFO L290 TraceCheckUtils]: 112: Hoare triple {1577#false} assume !(0 != activate_threads_~tmp___10~0#1); {1577#false} is VALID [2022-02-21 04:23:00,910 INFO L290 TraceCheckUtils]: 113: Hoare triple {1577#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1577#false} is VALID [2022-02-21 04:23:00,911 INFO L290 TraceCheckUtils]: 114: Hoare triple {1577#false} assume !(1 == ~M_E~0); {1577#false} is VALID [2022-02-21 04:23:00,912 INFO L290 TraceCheckUtils]: 115: Hoare triple {1577#false} assume !(1 == ~T1_E~0); {1577#false} is VALID [2022-02-21 04:23:00,912 INFO L290 TraceCheckUtils]: 116: Hoare triple {1577#false} assume !(1 == ~T2_E~0); {1577#false} is VALID [2022-02-21 04:23:00,913 INFO L290 TraceCheckUtils]: 117: Hoare triple {1577#false} assume !(1 == ~T3_E~0); {1577#false} is VALID [2022-02-21 04:23:00,913 INFO L290 TraceCheckUtils]: 118: Hoare triple {1577#false} assume !(1 == ~T4_E~0); {1577#false} is VALID [2022-02-21 04:23:00,920 INFO L290 TraceCheckUtils]: 119: Hoare triple {1577#false} assume !(1 == ~T5_E~0); {1577#false} is VALID [2022-02-21 04:23:00,920 INFO L290 TraceCheckUtils]: 120: Hoare triple {1577#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,922 INFO L290 TraceCheckUtils]: 121: Hoare triple {1577#false} assume !(1 == ~T7_E~0); {1577#false} is VALID [2022-02-21 04:23:00,922 INFO L290 TraceCheckUtils]: 122: Hoare triple {1577#false} assume !(1 == ~T8_E~0); {1577#false} is VALID [2022-02-21 04:23:00,923 INFO L290 TraceCheckUtils]: 123: Hoare triple {1577#false} assume !(1 == ~T9_E~0); {1577#false} is VALID [2022-02-21 04:23:00,923 INFO L290 TraceCheckUtils]: 124: Hoare triple {1577#false} assume !(1 == ~T10_E~0); {1577#false} is VALID [2022-02-21 04:23:00,923 INFO L290 TraceCheckUtils]: 125: Hoare triple {1577#false} assume !(1 == ~T11_E~0); {1577#false} is VALID [2022-02-21 04:23:00,923 INFO L290 TraceCheckUtils]: 126: Hoare triple {1577#false} assume !(1 == ~E_M~0); {1577#false} is VALID [2022-02-21 04:23:00,924 INFO L290 TraceCheckUtils]: 127: Hoare triple {1577#false} assume !(1 == ~E_1~0); {1577#false} is VALID [2022-02-21 04:23:00,924 INFO L290 TraceCheckUtils]: 128: Hoare triple {1577#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,924 INFO L290 TraceCheckUtils]: 129: Hoare triple {1577#false} assume !(1 == ~E_3~0); {1577#false} is VALID [2022-02-21 04:23:00,925 INFO L290 TraceCheckUtils]: 130: Hoare triple {1577#false} assume !(1 == ~E_4~0); {1577#false} is VALID [2022-02-21 04:23:00,925 INFO L290 TraceCheckUtils]: 131: Hoare triple {1577#false} assume !(1 == ~E_5~0); {1577#false} is VALID [2022-02-21 04:23:00,925 INFO L290 TraceCheckUtils]: 132: Hoare triple {1577#false} assume !(1 == ~E_6~0); {1577#false} is VALID [2022-02-21 04:23:00,925 INFO L290 TraceCheckUtils]: 133: Hoare triple {1577#false} assume !(1 == ~E_7~0); {1577#false} is VALID [2022-02-21 04:23:00,925 INFO L290 TraceCheckUtils]: 134: Hoare triple {1577#false} assume !(1 == ~E_8~0); {1577#false} is VALID [2022-02-21 04:23:00,925 INFO L290 TraceCheckUtils]: 135: Hoare triple {1577#false} assume !(1 == ~E_9~0); {1577#false} is VALID [2022-02-21 04:23:00,926 INFO L290 TraceCheckUtils]: 136: Hoare triple {1577#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1577#false} is VALID [2022-02-21 04:23:00,926 INFO L290 TraceCheckUtils]: 137: Hoare triple {1577#false} assume !(1 == ~E_11~0); {1577#false} is VALID [2022-02-21 04:23:00,927 INFO L290 TraceCheckUtils]: 138: Hoare triple {1577#false} assume { :end_inline_reset_delta_events } true; {1577#false} is VALID [2022-02-21 04:23:00,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:00,929 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:00,929 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348915071] [2022-02-21 04:23:00,930 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348915071] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:00,931 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:00,931 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:00,932 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887905818] [2022-02-21 04:23:00,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:00,936 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:00,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:00,938 INFO L85 PathProgramCache]: Analyzing trace with hash -356606326, now seen corresponding path program 1 times [2022-02-21 04:23:00,938 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:00,938 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669479972] [2022-02-21 04:23:00,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:00,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:00,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:01,005 INFO L290 TraceCheckUtils]: 0: Hoare triple {1579#true} assume !false; {1579#true} is VALID [2022-02-21 04:23:01,006 INFO L290 TraceCheckUtils]: 1: Hoare triple {1579#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1579#true} is VALID [2022-02-21 04:23:01,006 INFO L290 TraceCheckUtils]: 2: Hoare triple {1579#true} assume !true; {1580#false} is VALID [2022-02-21 04:23:01,006 INFO L290 TraceCheckUtils]: 3: Hoare triple {1580#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1580#false} is VALID [2022-02-21 04:23:01,006 INFO L290 TraceCheckUtils]: 4: Hoare triple {1580#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1580#false} is VALID [2022-02-21 04:23:01,007 INFO L290 TraceCheckUtils]: 5: Hoare triple {1580#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,007 INFO L290 TraceCheckUtils]: 6: Hoare triple {1580#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,007 INFO L290 TraceCheckUtils]: 7: Hoare triple {1580#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,007 INFO L290 TraceCheckUtils]: 8: Hoare triple {1580#false} assume !(0 == ~T3_E~0); {1580#false} is VALID [2022-02-21 04:23:01,007 INFO L290 TraceCheckUtils]: 9: Hoare triple {1580#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,007 INFO L290 TraceCheckUtils]: 10: Hoare triple {1580#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,008 INFO L290 TraceCheckUtils]: 11: Hoare triple {1580#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,008 INFO L290 TraceCheckUtils]: 12: Hoare triple {1580#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,008 INFO L290 TraceCheckUtils]: 13: Hoare triple {1580#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,008 INFO L290 TraceCheckUtils]: 14: Hoare triple {1580#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,008 INFO L290 TraceCheckUtils]: 15: Hoare triple {1580#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,008 INFO L290 TraceCheckUtils]: 16: Hoare triple {1580#false} assume !(0 == ~T11_E~0); {1580#false} is VALID [2022-02-21 04:23:01,009 INFO L290 TraceCheckUtils]: 17: Hoare triple {1580#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,009 INFO L290 TraceCheckUtils]: 18: Hoare triple {1580#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,009 INFO L290 TraceCheckUtils]: 19: Hoare triple {1580#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,009 INFO L290 TraceCheckUtils]: 20: Hoare triple {1580#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,009 INFO L290 TraceCheckUtils]: 21: Hoare triple {1580#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,010 INFO L290 TraceCheckUtils]: 22: Hoare triple {1580#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,010 INFO L290 TraceCheckUtils]: 23: Hoare triple {1580#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,010 INFO L290 TraceCheckUtils]: 24: Hoare triple {1580#false} assume !(0 == ~E_7~0); {1580#false} is VALID [2022-02-21 04:23:01,010 INFO L290 TraceCheckUtils]: 25: Hoare triple {1580#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,010 INFO L290 TraceCheckUtils]: 26: Hoare triple {1580#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,010 INFO L290 TraceCheckUtils]: 27: Hoare triple {1580#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,011 INFO L290 TraceCheckUtils]: 28: Hoare triple {1580#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1580#false} is VALID [2022-02-21 04:23:01,011 INFO L290 TraceCheckUtils]: 29: Hoare triple {1580#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1580#false} is VALID [2022-02-21 04:23:01,011 INFO L290 TraceCheckUtils]: 30: Hoare triple {1580#false} assume !(1 == ~m_pc~0); {1580#false} is VALID [2022-02-21 04:23:01,011 INFO L290 TraceCheckUtils]: 31: Hoare triple {1580#false} is_master_triggered_~__retres1~0#1 := 0; {1580#false} is VALID [2022-02-21 04:23:01,011 INFO L290 TraceCheckUtils]: 32: Hoare triple {1580#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1580#false} is VALID [2022-02-21 04:23:01,012 INFO L290 TraceCheckUtils]: 33: Hoare triple {1580#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1580#false} is VALID [2022-02-21 04:23:01,012 INFO L290 TraceCheckUtils]: 34: Hoare triple {1580#false} assume !(0 != activate_threads_~tmp~1#1); {1580#false} is VALID [2022-02-21 04:23:01,012 INFO L290 TraceCheckUtils]: 35: Hoare triple {1580#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1580#false} is VALID [2022-02-21 04:23:01,013 INFO L290 TraceCheckUtils]: 36: Hoare triple {1580#false} assume !(1 == ~t1_pc~0); {1580#false} is VALID [2022-02-21 04:23:01,016 INFO L290 TraceCheckUtils]: 37: Hoare triple {1580#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1580#false} is VALID [2022-02-21 04:23:01,016 INFO L290 TraceCheckUtils]: 38: Hoare triple {1580#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1580#false} is VALID [2022-02-21 04:23:01,016 INFO L290 TraceCheckUtils]: 39: Hoare triple {1580#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1580#false} is VALID [2022-02-21 04:23:01,016 INFO L290 TraceCheckUtils]: 40: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,016 INFO L290 TraceCheckUtils]: 41: Hoare triple {1580#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1580#false} is VALID [2022-02-21 04:23:01,017 INFO L290 TraceCheckUtils]: 42: Hoare triple {1580#false} assume 1 == ~t2_pc~0; {1580#false} is VALID [2022-02-21 04:23:01,017 INFO L290 TraceCheckUtils]: 43: Hoare triple {1580#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,017 INFO L290 TraceCheckUtils]: 44: Hoare triple {1580#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1580#false} is VALID [2022-02-21 04:23:01,017 INFO L290 TraceCheckUtils]: 45: Hoare triple {1580#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1580#false} is VALID [2022-02-21 04:23:01,018 INFO L290 TraceCheckUtils]: 46: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,018 INFO L290 TraceCheckUtils]: 47: Hoare triple {1580#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1580#false} is VALID [2022-02-21 04:23:01,019 INFO L290 TraceCheckUtils]: 48: Hoare triple {1580#false} assume 1 == ~t3_pc~0; {1580#false} is VALID [2022-02-21 04:23:01,019 INFO L290 TraceCheckUtils]: 49: Hoare triple {1580#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,019 INFO L290 TraceCheckUtils]: 50: Hoare triple {1580#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1580#false} is VALID [2022-02-21 04:23:01,019 INFO L290 TraceCheckUtils]: 51: Hoare triple {1580#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1580#false} is VALID [2022-02-21 04:23:01,020 INFO L290 TraceCheckUtils]: 52: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,020 INFO L290 TraceCheckUtils]: 53: Hoare triple {1580#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1580#false} is VALID [2022-02-21 04:23:01,020 INFO L290 TraceCheckUtils]: 54: Hoare triple {1580#false} assume 1 == ~t4_pc~0; {1580#false} is VALID [2022-02-21 04:23:01,020 INFO L290 TraceCheckUtils]: 55: Hoare triple {1580#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,021 INFO L290 TraceCheckUtils]: 56: Hoare triple {1580#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1580#false} is VALID [2022-02-21 04:23:01,021 INFO L290 TraceCheckUtils]: 57: Hoare triple {1580#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1580#false} is VALID [2022-02-21 04:23:01,021 INFO L290 TraceCheckUtils]: 58: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,021 INFO L290 TraceCheckUtils]: 59: Hoare triple {1580#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1580#false} is VALID [2022-02-21 04:23:01,021 INFO L290 TraceCheckUtils]: 60: Hoare triple {1580#false} assume 1 == ~t5_pc~0; {1580#false} is VALID [2022-02-21 04:23:01,021 INFO L290 TraceCheckUtils]: 61: Hoare triple {1580#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,022 INFO L290 TraceCheckUtils]: 62: Hoare triple {1580#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1580#false} is VALID [2022-02-21 04:23:01,022 INFO L290 TraceCheckUtils]: 63: Hoare triple {1580#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1580#false} is VALID [2022-02-21 04:23:01,022 INFO L290 TraceCheckUtils]: 64: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,025 INFO L290 TraceCheckUtils]: 65: Hoare triple {1580#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1580#false} is VALID [2022-02-21 04:23:01,025 INFO L290 TraceCheckUtils]: 66: Hoare triple {1580#false} assume 1 == ~t6_pc~0; {1580#false} is VALID [2022-02-21 04:23:01,025 INFO L290 TraceCheckUtils]: 67: Hoare triple {1580#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,025 INFO L290 TraceCheckUtils]: 68: Hoare triple {1580#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1580#false} is VALID [2022-02-21 04:23:01,026 INFO L290 TraceCheckUtils]: 69: Hoare triple {1580#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1580#false} is VALID [2022-02-21 04:23:01,026 INFO L290 TraceCheckUtils]: 70: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,026 INFO L290 TraceCheckUtils]: 71: Hoare triple {1580#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1580#false} is VALID [2022-02-21 04:23:01,026 INFO L290 TraceCheckUtils]: 72: Hoare triple {1580#false} assume 1 == ~t7_pc~0; {1580#false} is VALID [2022-02-21 04:23:01,026 INFO L290 TraceCheckUtils]: 73: Hoare triple {1580#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,027 INFO L290 TraceCheckUtils]: 74: Hoare triple {1580#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1580#false} is VALID [2022-02-21 04:23:01,027 INFO L290 TraceCheckUtils]: 75: Hoare triple {1580#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1580#false} is VALID [2022-02-21 04:23:01,027 INFO L290 TraceCheckUtils]: 76: Hoare triple {1580#false} assume !(0 != activate_threads_~tmp___6~0#1); {1580#false} is VALID [2022-02-21 04:23:01,027 INFO L290 TraceCheckUtils]: 77: Hoare triple {1580#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1580#false} is VALID [2022-02-21 04:23:01,027 INFO L290 TraceCheckUtils]: 78: Hoare triple {1580#false} assume !(1 == ~t8_pc~0); {1580#false} is VALID [2022-02-21 04:23:01,027 INFO L290 TraceCheckUtils]: 79: Hoare triple {1580#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1580#false} is VALID [2022-02-21 04:23:01,028 INFO L290 TraceCheckUtils]: 80: Hoare triple {1580#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1580#false} is VALID [2022-02-21 04:23:01,028 INFO L290 TraceCheckUtils]: 81: Hoare triple {1580#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1580#false} is VALID [2022-02-21 04:23:01,028 INFO L290 TraceCheckUtils]: 82: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,028 INFO L290 TraceCheckUtils]: 83: Hoare triple {1580#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1580#false} is VALID [2022-02-21 04:23:01,028 INFO L290 TraceCheckUtils]: 84: Hoare triple {1580#false} assume !(1 == ~t9_pc~0); {1580#false} is VALID [2022-02-21 04:23:01,028 INFO L290 TraceCheckUtils]: 85: Hoare triple {1580#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1580#false} is VALID [2022-02-21 04:23:01,029 INFO L290 TraceCheckUtils]: 86: Hoare triple {1580#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1580#false} is VALID [2022-02-21 04:23:01,029 INFO L290 TraceCheckUtils]: 87: Hoare triple {1580#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1580#false} is VALID [2022-02-21 04:23:01,029 INFO L290 TraceCheckUtils]: 88: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,029 INFO L290 TraceCheckUtils]: 89: Hoare triple {1580#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1580#false} is VALID [2022-02-21 04:23:01,029 INFO L290 TraceCheckUtils]: 90: Hoare triple {1580#false} assume !(1 == ~t10_pc~0); {1580#false} is VALID [2022-02-21 04:23:01,030 INFO L290 TraceCheckUtils]: 91: Hoare triple {1580#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1580#false} is VALID [2022-02-21 04:23:01,030 INFO L290 TraceCheckUtils]: 92: Hoare triple {1580#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1580#false} is VALID [2022-02-21 04:23:01,031 INFO L290 TraceCheckUtils]: 93: Hoare triple {1580#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1580#false} is VALID [2022-02-21 04:23:01,031 INFO L290 TraceCheckUtils]: 94: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,031 INFO L290 TraceCheckUtils]: 95: Hoare triple {1580#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1580#false} is VALID [2022-02-21 04:23:01,031 INFO L290 TraceCheckUtils]: 96: Hoare triple {1580#false} assume !(1 == ~t11_pc~0); {1580#false} is VALID [2022-02-21 04:23:01,031 INFO L290 TraceCheckUtils]: 97: Hoare triple {1580#false} is_transmit11_triggered_~__retres1~11#1 := 0; {1580#false} is VALID [2022-02-21 04:23:01,031 INFO L290 TraceCheckUtils]: 98: Hoare triple {1580#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1580#false} is VALID [2022-02-21 04:23:01,032 INFO L290 TraceCheckUtils]: 99: Hoare triple {1580#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1580#false} is VALID [2022-02-21 04:23:01,032 INFO L290 TraceCheckUtils]: 100: Hoare triple {1580#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {1580#false} is VALID [2022-02-21 04:23:01,032 INFO L290 TraceCheckUtils]: 101: Hoare triple {1580#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1580#false} is VALID [2022-02-21 04:23:01,032 INFO L290 TraceCheckUtils]: 102: Hoare triple {1580#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,036 INFO L290 TraceCheckUtils]: 103: Hoare triple {1580#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,037 INFO L290 TraceCheckUtils]: 104: Hoare triple {1580#false} assume !(1 == ~T2_E~0); {1580#false} is VALID [2022-02-21 04:23:01,037 INFO L290 TraceCheckUtils]: 105: Hoare triple {1580#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,038 INFO L290 TraceCheckUtils]: 106: Hoare triple {1580#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,041 INFO L290 TraceCheckUtils]: 107: Hoare triple {1580#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 108: Hoare triple {1580#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,042 INFO L290 TraceCheckUtils]: 109: Hoare triple {1580#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,044 INFO L290 TraceCheckUtils]: 110: Hoare triple {1580#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,044 INFO L290 TraceCheckUtils]: 111: Hoare triple {1580#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,044 INFO L290 TraceCheckUtils]: 112: Hoare triple {1580#false} assume !(1 == ~T10_E~0); {1580#false} is VALID [2022-02-21 04:23:01,045 INFO L290 TraceCheckUtils]: 113: Hoare triple {1580#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,045 INFO L290 TraceCheckUtils]: 114: Hoare triple {1580#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,046 INFO L290 TraceCheckUtils]: 115: Hoare triple {1580#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,048 INFO L290 TraceCheckUtils]: 116: Hoare triple {1580#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,048 INFO L290 TraceCheckUtils]: 117: Hoare triple {1580#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 118: Hoare triple {1580#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 119: Hoare triple {1580#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 120: Hoare triple {1580#false} assume !(1 == ~E_6~0); {1580#false} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 121: Hoare triple {1580#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 122: Hoare triple {1580#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 123: Hoare triple {1580#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,049 INFO L290 TraceCheckUtils]: 124: Hoare triple {1580#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 125: Hoare triple {1580#false} assume 1 == ~E_11~0;~E_11~0 := 2; {1580#false} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 126: Hoare triple {1580#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {1580#false} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 127: Hoare triple {1580#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 128: Hoare triple {1580#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {1580#false} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 129: Hoare triple {1580#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {1580#false} is VALID [2022-02-21 04:23:01,050 INFO L290 TraceCheckUtils]: 130: Hoare triple {1580#false} assume !(0 == start_simulation_~tmp~3#1); {1580#false} is VALID [2022-02-21 04:23:01,051 INFO L290 TraceCheckUtils]: 131: Hoare triple {1580#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {1580#false} is VALID [2022-02-21 04:23:01,051 INFO L290 TraceCheckUtils]: 132: Hoare triple {1580#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {1580#false} is VALID [2022-02-21 04:23:01,051 INFO L290 TraceCheckUtils]: 133: Hoare triple {1580#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {1580#false} is VALID [2022-02-21 04:23:01,051 INFO L290 TraceCheckUtils]: 134: Hoare triple {1580#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {1580#false} is VALID [2022-02-21 04:23:01,051 INFO L290 TraceCheckUtils]: 135: Hoare triple {1580#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1580#false} is VALID [2022-02-21 04:23:01,051 INFO L290 TraceCheckUtils]: 136: Hoare triple {1580#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1580#false} is VALID [2022-02-21 04:23:01,052 INFO L290 TraceCheckUtils]: 137: Hoare triple {1580#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {1580#false} is VALID [2022-02-21 04:23:01,052 INFO L290 TraceCheckUtils]: 138: Hoare triple {1580#false} assume !(0 != start_simulation_~tmp___0~1#1); {1580#false} is VALID [2022-02-21 04:23:01,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:01,055 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:01,056 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669479972] [2022-02-21 04:23:01,056 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669479972] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:01,056 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:01,056 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:01,057 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344448192] [2022-02-21 04:23:01,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:01,059 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:01,060 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:01,081 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:23:01,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:23:01,087 INFO L87 Difference]: Start difference. First operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:01,851 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2022-02-21 04:23:01,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:23:01,853 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:01,947 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:01,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2022-02-21 04:23:02,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:02,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1566 states and 2325 transitions. [2022-02-21 04:23:02,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:02,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:02,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2325 transitions. [2022-02-21 04:23:02,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:02,113 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-02-21 04:23:02,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2325 transitions. [2022-02-21 04:23:02,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:02,171 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:02,178 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2325 transitions. Second operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,184 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2325 transitions. Second operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,189 INFO L87 Difference]: Start difference. First operand 1566 states and 2325 transitions. Second operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,250 INFO L93 Difference]: Finished difference Result 1566 states and 2325 transitions. [2022-02-21 04:23:02,250 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2325 transitions. [2022-02-21 04:23:02,255 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:02,255 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:02,259 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2325 transitions. [2022-02-21 04:23:02,261 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2325 transitions. [2022-02-21 04:23:02,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:02,338 INFO L93 Difference]: Finished difference Result 1566 states and 2325 transitions. [2022-02-21 04:23:02,339 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2325 transitions. [2022-02-21 04:23:02,341 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:02,341 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:02,341 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:02,341 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:02,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:02,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2325 transitions. [2022-02-21 04:23:02,402 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-02-21 04:23:02,403 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-02-21 04:23:02,403 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:02,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2325 transitions. [2022-02-21 04:23:02,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:02,408 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:02,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:02,412 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,413 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:02,413 INFO L791 eck$LassoCheckResult]: Stem: 3887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4616#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4617#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3390#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3391#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4626#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4591#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4592#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3739#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3740#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4146#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4564#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3651#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3652#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3537#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3538#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4490#L1109 assume !(0 == ~M_E~0); 4512#L1109-2 assume !(0 == ~T1_E~0); 3544#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3545#L1119-1 assume !(0 == ~T3_E~0); 4568#L1124-1 assume !(0 == ~T4_E~0); 3205#L1129-1 assume !(0 == ~T5_E~0); 3206#L1134-1 assume !(0 == ~T6_E~0); 3819#L1139-1 assume !(0 == ~T7_E~0); 4496#L1144-1 assume !(0 == ~T8_E~0); 4368#L1149-1 assume !(0 == ~T9_E~0); 3312#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3313#L1159-1 assume !(0 == ~T11_E~0); 4354#L1164-1 assume !(0 == ~E_M~0); 3705#L1169-1 assume !(0 == ~E_1~0); 3594#L1174-1 assume !(0 == ~E_2~0); 3467#L1179-1 assume !(0 == ~E_3~0); 3394#L1184-1 assume !(0 == ~E_4~0); 3395#L1189-1 assume !(0 == ~E_5~0); 3426#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3513#L1199-1 assume !(0 == ~E_7~0); 4376#L1204-1 assume !(0 == ~E_8~0); 4312#L1209-1 assume !(0 == ~E_9~0); 4313#L1214-1 assume !(0 == ~E_10~0); 4638#L1219-1 assume !(0 == ~E_11~0); 4711#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3722#L544 assume 1 == ~m_pc~0; 3723#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4555#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4383#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3356#L1379 assume !(0 != activate_threads_~tmp~1#1); 3357#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4129#L563 assume !(1 == ~t1_pc~0); 3929#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3215#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4252#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3211#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3212#L582 assume 1 == ~t2_pc~0; 3907#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4262#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4263#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4367#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3244#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3245#L601 assume !(1 == ~t3_pc~0); 3923#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3922#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4556#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4298#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4299#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4242#L620 assume 1 == ~t4_pc~0; 3225#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3226#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3787#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3788#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4143#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4330#L639 assume 1 == ~t5_pc~0; 4213#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3517#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3518#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4164#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4165#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4094#L658 assume !(1 == ~t6_pc~0); 3719#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3720#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4288#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4618#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4302#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3557#L677 assume 1 == ~t7_pc~0; 3558#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3460#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4461#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4585#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4586#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4657#L696 assume !(1 == ~t8_pc~0); 3777#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3778#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4625#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4646#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4692#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4196#L715 assume 1 == ~t9_pc~0; 4197#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3867#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3775#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3776#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4185#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4457#L734 assume !(1 == ~t10_pc~0); 4458#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3677#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3678#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3696#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4401#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3753#L753 assume 1 == ~t11_pc~0; 3754#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4307#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3862#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3863#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4012#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4069#L1237 assume !(1 == ~M_E~0); 4070#L1237-2 assume !(1 == ~T1_E~0); 4682#L1242-1 assume !(1 == ~T2_E~0); 3833#L1247-1 assume !(1 == ~T3_E~0); 3834#L1252-1 assume !(1 == ~T4_E~0); 3617#L1257-1 assume !(1 == ~T5_E~0); 3618#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4473#L1267-1 assume !(1 == ~T7_E~0); 4578#L1272-1 assume !(1 == ~T8_E~0); 3916#L1277-1 assume !(1 == ~T9_E~0); 3917#L1282-1 assume !(1 == ~T10_E~0); 4339#L1287-1 assume !(1 == ~T11_E~0); 4340#L1292-1 assume !(1 == ~E_M~0); 4301#L1297-1 assume !(1 == ~E_1~0); 3748#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3749#L1307-1 assume !(1 == ~E_3~0); 4571#L1312-1 assume !(1 == ~E_4~0); 3959#L1317-1 assume !(1 == ~E_5~0); 3960#L1322-1 assume !(1 == ~E_6~0); 3692#L1327-1 assume !(1 == ~E_7~0); 3693#L1332-1 assume !(1 == ~E_8~0); 4251#L1337-1 assume !(1 == ~E_9~0); 4188#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4189#L1347-1 assume !(1 == ~E_11~0); 4570#L1352-1 assume { :end_inline_reset_delta_events } true; 4460#L1678-2 [2022-02-21 04:23:02,414 INFO L793 eck$LassoCheckResult]: Loop: 4460#L1678-2 assume !false; 4243#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4244#L1084 assume !false; 4027#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4028#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3331#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4345#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3257#L925 assume !(0 != eval_~tmp~0#1); 3259#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3373#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3374#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3228#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3229#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4303#L1119-3 assume !(0 == ~T3_E~0); 4304#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4325#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4326#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4504#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4562#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3732#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3733#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3968#L1159-3 assume !(0 == ~T11_E~0); 3969#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4239#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4240#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4290#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4291#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4446#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4123#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3490#L1199-3 assume !(0 == ~E_7~0); 3491#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3714#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3176#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3177#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3875#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3876#L544-39 assume !(1 == ~m_pc~0); 3157#L544-41 is_master_triggered_~__retres1~0#1 := 0; 3158#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3408#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3409#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 3565#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4433#L563-39 assume 1 == ~t1_pc~0; 4439#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3308#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4207#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4208#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4705#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4548#L582-39 assume !(1 == ~t2_pc~0); 3632#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 3633#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4253#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4254#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3401#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3188#L601-39 assume 1 == ~t3_pc~0; 3189#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3239#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4397#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4533#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4437#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4089#L620-39 assume !(1 == ~t4_pc~0); 4090#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4287#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4495#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4410#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4411#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4716#L639-39 assume 1 == ~t5_pc~0; 4523#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3837#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3414#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3217#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3218#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4126#L658-39 assume 1 == ~t6_pc~0; 4108#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4109#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3167#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3168#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4283#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4284#L677-39 assume 1 == ~t7_pc~0; 4246#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3392#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3393#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3448#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 3449#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4014#L696-39 assume 1 == ~t8_pc~0; 3979#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3859#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3860#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4155#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4119#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3994#L715-39 assume 1 == ~t9_pc~0; 3193#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3194#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4403#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4717#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4332#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4333#L734-39 assume 1 == ~t10_pc~0; 4258#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3704#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4015#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3346#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3347#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4595#L753-39 assume !(1 == ~t11_pc~0); 3266#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 3267#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4559#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3984#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3985#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4086#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4087#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4357#L1242-3 assume !(1 == ~T2_E~0); 4358#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4577#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4277#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4278#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4560#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4601#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4689#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3418#L1282-3 assume !(1 == ~T10_E~0); 3419#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3328#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3329#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4466#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4467#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4655#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4379#L1322-3 assume !(1 == ~E_6~0); 4380#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3387#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3362#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3363#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4055#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4183#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4184#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3310#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3575#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4289#L1697 assume !(0 == start_simulation_~tmp~3#1); 4076#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4077#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3434#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4199#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 4200#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4149#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3746#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3747#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4460#L1678-2 [2022-02-21 04:23:02,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,416 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2022-02-21 04:23:02,416 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,416 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654310698] [2022-02-21 04:23:02,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:02,484 INFO L290 TraceCheckUtils]: 0: Hoare triple {7853#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {7853#true} is VALID [2022-02-21 04:23:02,491 INFO L290 TraceCheckUtils]: 1: Hoare triple {7853#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {7855#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:02,492 INFO L290 TraceCheckUtils]: 2: Hoare triple {7855#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {7855#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:02,493 INFO L290 TraceCheckUtils]: 3: Hoare triple {7855#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {7855#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:02,494 INFO L290 TraceCheckUtils]: 4: Hoare triple {7855#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,494 INFO L290 TraceCheckUtils]: 5: Hoare triple {7854#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {7854#false} is VALID [2022-02-21 04:23:02,494 INFO L290 TraceCheckUtils]: 6: Hoare triple {7854#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,494 INFO L290 TraceCheckUtils]: 7: Hoare triple {7854#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,494 INFO L290 TraceCheckUtils]: 8: Hoare triple {7854#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 9: Hoare triple {7854#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 10: Hoare triple {7854#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 11: Hoare triple {7854#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 12: Hoare triple {7854#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 13: Hoare triple {7854#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 14: Hoare triple {7854#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 15: Hoare triple {7854#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,495 INFO L290 TraceCheckUtils]: 16: Hoare triple {7854#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 17: Hoare triple {7854#false} assume !(0 == ~M_E~0); {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 18: Hoare triple {7854#false} assume !(0 == ~T1_E~0); {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 19: Hoare triple {7854#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 20: Hoare triple {7854#false} assume !(0 == ~T3_E~0); {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 21: Hoare triple {7854#false} assume !(0 == ~T4_E~0); {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 22: Hoare triple {7854#false} assume !(0 == ~T5_E~0); {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 23: Hoare triple {7854#false} assume !(0 == ~T6_E~0); {7854#false} is VALID [2022-02-21 04:23:02,496 INFO L290 TraceCheckUtils]: 24: Hoare triple {7854#false} assume !(0 == ~T7_E~0); {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 25: Hoare triple {7854#false} assume !(0 == ~T8_E~0); {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 26: Hoare triple {7854#false} assume !(0 == ~T9_E~0); {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 27: Hoare triple {7854#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 28: Hoare triple {7854#false} assume !(0 == ~T11_E~0); {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 29: Hoare triple {7854#false} assume !(0 == ~E_M~0); {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 30: Hoare triple {7854#false} assume !(0 == ~E_1~0); {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 31: Hoare triple {7854#false} assume !(0 == ~E_2~0); {7854#false} is VALID [2022-02-21 04:23:02,497 INFO L290 TraceCheckUtils]: 32: Hoare triple {7854#false} assume !(0 == ~E_3~0); {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 33: Hoare triple {7854#false} assume !(0 == ~E_4~0); {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 34: Hoare triple {7854#false} assume !(0 == ~E_5~0); {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 35: Hoare triple {7854#false} assume 0 == ~E_6~0;~E_6~0 := 1; {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 36: Hoare triple {7854#false} assume !(0 == ~E_7~0); {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 37: Hoare triple {7854#false} assume !(0 == ~E_8~0); {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 38: Hoare triple {7854#false} assume !(0 == ~E_9~0); {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 39: Hoare triple {7854#false} assume !(0 == ~E_10~0); {7854#false} is VALID [2022-02-21 04:23:02,498 INFO L290 TraceCheckUtils]: 40: Hoare triple {7854#false} assume !(0 == ~E_11~0); {7854#false} is VALID [2022-02-21 04:23:02,499 INFO L290 TraceCheckUtils]: 41: Hoare triple {7854#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7854#false} is VALID [2022-02-21 04:23:02,499 INFO L290 TraceCheckUtils]: 42: Hoare triple {7854#false} assume 1 == ~m_pc~0; {7854#false} is VALID [2022-02-21 04:23:02,499 INFO L290 TraceCheckUtils]: 43: Hoare triple {7854#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {7854#false} is VALID [2022-02-21 04:23:02,500 INFO L290 TraceCheckUtils]: 44: Hoare triple {7854#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7854#false} is VALID [2022-02-21 04:23:02,500 INFO L290 TraceCheckUtils]: 45: Hoare triple {7854#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {7854#false} is VALID [2022-02-21 04:23:02,500 INFO L290 TraceCheckUtils]: 46: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp~1#1); {7854#false} is VALID [2022-02-21 04:23:02,500 INFO L290 TraceCheckUtils]: 47: Hoare triple {7854#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7854#false} is VALID [2022-02-21 04:23:02,500 INFO L290 TraceCheckUtils]: 48: Hoare triple {7854#false} assume !(1 == ~t1_pc~0); {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 49: Hoare triple {7854#false} is_transmit1_triggered_~__retres1~1#1 := 0; {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 50: Hoare triple {7854#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 51: Hoare triple {7854#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 52: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___0~0#1); {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 53: Hoare triple {7854#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 54: Hoare triple {7854#false} assume 1 == ~t2_pc~0; {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 55: Hoare triple {7854#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {7854#false} is VALID [2022-02-21 04:23:02,501 INFO L290 TraceCheckUtils]: 56: Hoare triple {7854#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7854#false} is VALID [2022-02-21 04:23:02,502 INFO L290 TraceCheckUtils]: 57: Hoare triple {7854#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {7854#false} is VALID [2022-02-21 04:23:02,502 INFO L290 TraceCheckUtils]: 58: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___1~0#1); {7854#false} is VALID [2022-02-21 04:23:02,502 INFO L290 TraceCheckUtils]: 59: Hoare triple {7854#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7854#false} is VALID [2022-02-21 04:23:02,502 INFO L290 TraceCheckUtils]: 60: Hoare triple {7854#false} assume !(1 == ~t3_pc~0); {7854#false} is VALID [2022-02-21 04:23:02,502 INFO L290 TraceCheckUtils]: 61: Hoare triple {7854#false} is_transmit3_triggered_~__retres1~3#1 := 0; {7854#false} is VALID [2022-02-21 04:23:02,502 INFO L290 TraceCheckUtils]: 62: Hoare triple {7854#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7854#false} is VALID [2022-02-21 04:23:02,503 INFO L290 TraceCheckUtils]: 63: Hoare triple {7854#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {7854#false} is VALID [2022-02-21 04:23:02,505 INFO L290 TraceCheckUtils]: 64: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___2~0#1); {7854#false} is VALID [2022-02-21 04:23:02,505 INFO L290 TraceCheckUtils]: 65: Hoare triple {7854#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7854#false} is VALID [2022-02-21 04:23:02,505 INFO L290 TraceCheckUtils]: 66: Hoare triple {7854#false} assume 1 == ~t4_pc~0; {7854#false} is VALID [2022-02-21 04:23:02,505 INFO L290 TraceCheckUtils]: 67: Hoare triple {7854#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {7854#false} is VALID [2022-02-21 04:23:02,505 INFO L290 TraceCheckUtils]: 68: Hoare triple {7854#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 69: Hoare triple {7854#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 70: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___3~0#1); {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 71: Hoare triple {7854#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 72: Hoare triple {7854#false} assume 1 == ~t5_pc~0; {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 73: Hoare triple {7854#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 74: Hoare triple {7854#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 75: Hoare triple {7854#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {7854#false} is VALID [2022-02-21 04:23:02,506 INFO L290 TraceCheckUtils]: 76: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___4~0#1); {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 77: Hoare triple {7854#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 78: Hoare triple {7854#false} assume !(1 == ~t6_pc~0); {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 79: Hoare triple {7854#false} is_transmit6_triggered_~__retres1~6#1 := 0; {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 80: Hoare triple {7854#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 81: Hoare triple {7854#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 82: Hoare triple {7854#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 83: Hoare triple {7854#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {7854#false} is VALID [2022-02-21 04:23:02,507 INFO L290 TraceCheckUtils]: 84: Hoare triple {7854#false} assume 1 == ~t7_pc~0; {7854#false} is VALID [2022-02-21 04:23:02,508 INFO L290 TraceCheckUtils]: 85: Hoare triple {7854#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {7854#false} is VALID [2022-02-21 04:23:02,508 INFO L290 TraceCheckUtils]: 86: Hoare triple {7854#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {7854#false} is VALID [2022-02-21 04:23:02,508 INFO L290 TraceCheckUtils]: 87: Hoare triple {7854#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {7854#false} is VALID [2022-02-21 04:23:02,508 INFO L290 TraceCheckUtils]: 88: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___6~0#1); {7854#false} is VALID [2022-02-21 04:23:02,508 INFO L290 TraceCheckUtils]: 89: Hoare triple {7854#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {7854#false} is VALID [2022-02-21 04:23:02,508 INFO L290 TraceCheckUtils]: 90: Hoare triple {7854#false} assume !(1 == ~t8_pc~0); {7854#false} is VALID [2022-02-21 04:23:02,508 INFO L290 TraceCheckUtils]: 91: Hoare triple {7854#false} is_transmit8_triggered_~__retres1~8#1 := 0; {7854#false} is VALID [2022-02-21 04:23:02,509 INFO L290 TraceCheckUtils]: 92: Hoare triple {7854#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {7854#false} is VALID [2022-02-21 04:23:02,509 INFO L290 TraceCheckUtils]: 93: Hoare triple {7854#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {7854#false} is VALID [2022-02-21 04:23:02,510 INFO L290 TraceCheckUtils]: 94: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___7~0#1); {7854#false} is VALID [2022-02-21 04:23:02,510 INFO L290 TraceCheckUtils]: 95: Hoare triple {7854#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {7854#false} is VALID [2022-02-21 04:23:02,512 INFO L290 TraceCheckUtils]: 96: Hoare triple {7854#false} assume 1 == ~t9_pc~0; {7854#false} is VALID [2022-02-21 04:23:02,512 INFO L290 TraceCheckUtils]: 97: Hoare triple {7854#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {7854#false} is VALID [2022-02-21 04:23:02,512 INFO L290 TraceCheckUtils]: 98: Hoare triple {7854#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {7854#false} is VALID [2022-02-21 04:23:02,512 INFO L290 TraceCheckUtils]: 99: Hoare triple {7854#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {7854#false} is VALID [2022-02-21 04:23:02,512 INFO L290 TraceCheckUtils]: 100: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___8~0#1); {7854#false} is VALID [2022-02-21 04:23:02,513 INFO L290 TraceCheckUtils]: 101: Hoare triple {7854#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {7854#false} is VALID [2022-02-21 04:23:02,513 INFO L290 TraceCheckUtils]: 102: Hoare triple {7854#false} assume !(1 == ~t10_pc~0); {7854#false} is VALID [2022-02-21 04:23:02,513 INFO L290 TraceCheckUtils]: 103: Hoare triple {7854#false} is_transmit10_triggered_~__retres1~10#1 := 0; {7854#false} is VALID [2022-02-21 04:23:02,514 INFO L290 TraceCheckUtils]: 104: Hoare triple {7854#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {7854#false} is VALID [2022-02-21 04:23:02,514 INFO L290 TraceCheckUtils]: 105: Hoare triple {7854#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {7854#false} is VALID [2022-02-21 04:23:02,514 INFO L290 TraceCheckUtils]: 106: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___9~0#1); {7854#false} is VALID [2022-02-21 04:23:02,514 INFO L290 TraceCheckUtils]: 107: Hoare triple {7854#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {7854#false} is VALID [2022-02-21 04:23:02,514 INFO L290 TraceCheckUtils]: 108: Hoare triple {7854#false} assume 1 == ~t11_pc~0; {7854#false} is VALID [2022-02-21 04:23:02,514 INFO L290 TraceCheckUtils]: 109: Hoare triple {7854#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {7854#false} is VALID [2022-02-21 04:23:02,515 INFO L290 TraceCheckUtils]: 110: Hoare triple {7854#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {7854#false} is VALID [2022-02-21 04:23:02,515 INFO L290 TraceCheckUtils]: 111: Hoare triple {7854#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {7854#false} is VALID [2022-02-21 04:23:02,515 INFO L290 TraceCheckUtils]: 112: Hoare triple {7854#false} assume !(0 != activate_threads_~tmp___10~0#1); {7854#false} is VALID [2022-02-21 04:23:02,515 INFO L290 TraceCheckUtils]: 113: Hoare triple {7854#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7854#false} is VALID [2022-02-21 04:23:02,515 INFO L290 TraceCheckUtils]: 114: Hoare triple {7854#false} assume !(1 == ~M_E~0); {7854#false} is VALID [2022-02-21 04:23:02,515 INFO L290 TraceCheckUtils]: 115: Hoare triple {7854#false} assume !(1 == ~T1_E~0); {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 116: Hoare triple {7854#false} assume !(1 == ~T2_E~0); {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 117: Hoare triple {7854#false} assume !(1 == ~T3_E~0); {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 118: Hoare triple {7854#false} assume !(1 == ~T4_E~0); {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 119: Hoare triple {7854#false} assume !(1 == ~T5_E~0); {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 120: Hoare triple {7854#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 121: Hoare triple {7854#false} assume !(1 == ~T7_E~0); {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 122: Hoare triple {7854#false} assume !(1 == ~T8_E~0); {7854#false} is VALID [2022-02-21 04:23:02,516 INFO L290 TraceCheckUtils]: 123: Hoare triple {7854#false} assume !(1 == ~T9_E~0); {7854#false} is VALID [2022-02-21 04:23:02,517 INFO L290 TraceCheckUtils]: 124: Hoare triple {7854#false} assume !(1 == ~T10_E~0); {7854#false} is VALID [2022-02-21 04:23:02,517 INFO L290 TraceCheckUtils]: 125: Hoare triple {7854#false} assume !(1 == ~T11_E~0); {7854#false} is VALID [2022-02-21 04:23:02,517 INFO L290 TraceCheckUtils]: 126: Hoare triple {7854#false} assume !(1 == ~E_M~0); {7854#false} is VALID [2022-02-21 04:23:02,517 INFO L290 TraceCheckUtils]: 127: Hoare triple {7854#false} assume !(1 == ~E_1~0); {7854#false} is VALID [2022-02-21 04:23:02,519 INFO L290 TraceCheckUtils]: 128: Hoare triple {7854#false} assume 1 == ~E_2~0;~E_2~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,519 INFO L290 TraceCheckUtils]: 129: Hoare triple {7854#false} assume !(1 == ~E_3~0); {7854#false} is VALID [2022-02-21 04:23:02,519 INFO L290 TraceCheckUtils]: 130: Hoare triple {7854#false} assume !(1 == ~E_4~0); {7854#false} is VALID [2022-02-21 04:23:02,519 INFO L290 TraceCheckUtils]: 131: Hoare triple {7854#false} assume !(1 == ~E_5~0); {7854#false} is VALID [2022-02-21 04:23:02,519 INFO L290 TraceCheckUtils]: 132: Hoare triple {7854#false} assume !(1 == ~E_6~0); {7854#false} is VALID [2022-02-21 04:23:02,520 INFO L290 TraceCheckUtils]: 133: Hoare triple {7854#false} assume !(1 == ~E_7~0); {7854#false} is VALID [2022-02-21 04:23:02,520 INFO L290 TraceCheckUtils]: 134: Hoare triple {7854#false} assume !(1 == ~E_8~0); {7854#false} is VALID [2022-02-21 04:23:02,520 INFO L290 TraceCheckUtils]: 135: Hoare triple {7854#false} assume !(1 == ~E_9~0); {7854#false} is VALID [2022-02-21 04:23:02,520 INFO L290 TraceCheckUtils]: 136: Hoare triple {7854#false} assume 1 == ~E_10~0;~E_10~0 := 2; {7854#false} is VALID [2022-02-21 04:23:02,520 INFO L290 TraceCheckUtils]: 137: Hoare triple {7854#false} assume !(1 == ~E_11~0); {7854#false} is VALID [2022-02-21 04:23:02,520 INFO L290 TraceCheckUtils]: 138: Hoare triple {7854#false} assume { :end_inline_reset_delta_events } true; {7854#false} is VALID [2022-02-21 04:23:02,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:02,522 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:02,523 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654310698] [2022-02-21 04:23:02,523 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654310698] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:02,523 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:02,523 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:02,523 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545530631] [2022-02-21 04:23:02,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:02,524 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:02,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:02,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1065978444, now seen corresponding path program 1 times [2022-02-21 04:23:02,525 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:02,526 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309030476] [2022-02-21 04:23:02,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:02,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:02,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:02,608 INFO L290 TraceCheckUtils]: 0: Hoare triple {7856#true} assume !false; {7856#true} is VALID [2022-02-21 04:23:02,608 INFO L290 TraceCheckUtils]: 1: Hoare triple {7856#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {7856#true} is VALID [2022-02-21 04:23:02,608 INFO L290 TraceCheckUtils]: 2: Hoare triple {7856#true} assume !false; {7856#true} is VALID [2022-02-21 04:23:02,608 INFO L290 TraceCheckUtils]: 3: Hoare triple {7856#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {7856#true} is VALID [2022-02-21 04:23:02,608 INFO L290 TraceCheckUtils]: 4: Hoare triple {7856#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {7856#true} is VALID [2022-02-21 04:23:02,608 INFO L290 TraceCheckUtils]: 5: Hoare triple {7856#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {7856#true} is VALID [2022-02-21 04:23:02,608 INFO L290 TraceCheckUtils]: 6: Hoare triple {7856#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {7856#true} is VALID [2022-02-21 04:23:02,609 INFO L290 TraceCheckUtils]: 7: Hoare triple {7856#true} assume !(0 != eval_~tmp~0#1); {7856#true} is VALID [2022-02-21 04:23:02,609 INFO L290 TraceCheckUtils]: 8: Hoare triple {7856#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {7856#true} is VALID [2022-02-21 04:23:02,609 INFO L290 TraceCheckUtils]: 9: Hoare triple {7856#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {7856#true} is VALID [2022-02-21 04:23:02,609 INFO L290 TraceCheckUtils]: 10: Hoare triple {7856#true} assume 0 == ~M_E~0;~M_E~0 := 1; {7856#true} is VALID [2022-02-21 04:23:02,609 INFO L290 TraceCheckUtils]: 11: Hoare triple {7856#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {7856#true} is VALID [2022-02-21 04:23:02,609 INFO L290 TraceCheckUtils]: 12: Hoare triple {7856#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,609 INFO L290 TraceCheckUtils]: 13: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,610 INFO L290 TraceCheckUtils]: 14: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,610 INFO L290 TraceCheckUtils]: 15: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,610 INFO L290 TraceCheckUtils]: 16: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,610 INFO L290 TraceCheckUtils]: 17: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,611 INFO L290 TraceCheckUtils]: 18: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,611 INFO L290 TraceCheckUtils]: 19: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,611 INFO L290 TraceCheckUtils]: 20: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,611 INFO L290 TraceCheckUtils]: 21: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,612 INFO L290 TraceCheckUtils]: 22: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,612 INFO L290 TraceCheckUtils]: 23: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,612 INFO L290 TraceCheckUtils]: 24: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,612 INFO L290 TraceCheckUtils]: 25: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,613 INFO L290 TraceCheckUtils]: 26: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,613 INFO L290 TraceCheckUtils]: 27: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,613 INFO L290 TraceCheckUtils]: 28: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,613 INFO L290 TraceCheckUtils]: 29: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,614 INFO L290 TraceCheckUtils]: 30: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,614 INFO L290 TraceCheckUtils]: 31: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,614 INFO L290 TraceCheckUtils]: 32: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,615 INFO L290 TraceCheckUtils]: 33: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,615 INFO L290 TraceCheckUtils]: 34: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,615 INFO L290 TraceCheckUtils]: 35: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,615 INFO L290 TraceCheckUtils]: 36: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,616 INFO L290 TraceCheckUtils]: 37: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,616 INFO L290 TraceCheckUtils]: 38: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,616 INFO L290 TraceCheckUtils]: 39: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,616 INFO L290 TraceCheckUtils]: 40: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,617 INFO L290 TraceCheckUtils]: 41: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,617 INFO L290 TraceCheckUtils]: 42: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,617 INFO L290 TraceCheckUtils]: 43: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,618 INFO L290 TraceCheckUtils]: 44: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,618 INFO L290 TraceCheckUtils]: 45: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,618 INFO L290 TraceCheckUtils]: 46: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,618 INFO L290 TraceCheckUtils]: 47: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,619 INFO L290 TraceCheckUtils]: 48: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,619 INFO L290 TraceCheckUtils]: 49: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,619 INFO L290 TraceCheckUtils]: 50: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,619 INFO L290 TraceCheckUtils]: 51: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,620 INFO L290 TraceCheckUtils]: 52: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,620 INFO L290 TraceCheckUtils]: 53: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,620 INFO L290 TraceCheckUtils]: 54: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,620 INFO L290 TraceCheckUtils]: 55: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,621 INFO L290 TraceCheckUtils]: 56: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,621 INFO L290 TraceCheckUtils]: 57: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,621 INFO L290 TraceCheckUtils]: 58: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,622 INFO L290 TraceCheckUtils]: 59: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,622 INFO L290 TraceCheckUtils]: 60: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,622 INFO L290 TraceCheckUtils]: 61: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,622 INFO L290 TraceCheckUtils]: 62: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,623 INFO L290 TraceCheckUtils]: 63: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,623 INFO L290 TraceCheckUtils]: 64: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,623 INFO L290 TraceCheckUtils]: 65: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,623 INFO L290 TraceCheckUtils]: 66: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,624 INFO L290 TraceCheckUtils]: 67: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,624 INFO L290 TraceCheckUtils]: 68: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,624 INFO L290 TraceCheckUtils]: 69: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,624 INFO L290 TraceCheckUtils]: 70: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,625 INFO L290 TraceCheckUtils]: 71: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,625 INFO L290 TraceCheckUtils]: 72: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,625 INFO L290 TraceCheckUtils]: 73: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,625 INFO L290 TraceCheckUtils]: 74: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,626 INFO L290 TraceCheckUtils]: 75: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,626 INFO L290 TraceCheckUtils]: 76: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,626 INFO L290 TraceCheckUtils]: 77: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,626 INFO L290 TraceCheckUtils]: 78: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,627 INFO L290 TraceCheckUtils]: 79: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,627 INFO L290 TraceCheckUtils]: 80: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,627 INFO L290 TraceCheckUtils]: 81: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,628 INFO L290 TraceCheckUtils]: 82: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,628 INFO L290 TraceCheckUtils]: 83: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,628 INFO L290 TraceCheckUtils]: 84: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,628 INFO L290 TraceCheckUtils]: 85: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,629 INFO L290 TraceCheckUtils]: 86: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,631 INFO L290 TraceCheckUtils]: 87: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,631 INFO L290 TraceCheckUtils]: 88: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,632 INFO L290 TraceCheckUtils]: 89: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,632 INFO L290 TraceCheckUtils]: 90: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,632 INFO L290 TraceCheckUtils]: 91: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,632 INFO L290 TraceCheckUtils]: 92: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,633 INFO L290 TraceCheckUtils]: 93: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,633 INFO L290 TraceCheckUtils]: 94: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,633 INFO L290 TraceCheckUtils]: 95: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,633 INFO L290 TraceCheckUtils]: 96: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,634 INFO L290 TraceCheckUtils]: 97: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,634 INFO L290 TraceCheckUtils]: 98: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,635 INFO L290 TraceCheckUtils]: 99: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,635 INFO L290 TraceCheckUtils]: 100: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,635 INFO L290 TraceCheckUtils]: 101: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,635 INFO L290 TraceCheckUtils]: 102: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,636 INFO L290 TraceCheckUtils]: 103: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,636 INFO L290 TraceCheckUtils]: 104: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,636 INFO L290 TraceCheckUtils]: 105: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 106: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 107: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 108: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {7858#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 109: Hoare triple {7858#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {7857#false} is VALID [2022-02-21 04:23:02,637 INFO L290 TraceCheckUtils]: 110: Hoare triple {7857#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 111: Hoare triple {7857#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 112: Hoare triple {7857#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 113: Hoare triple {7857#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 114: Hoare triple {7857#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 115: Hoare triple {7857#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 116: Hoare triple {7857#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 117: Hoare triple {7857#false} assume !(1 == ~T10_E~0); {7857#false} is VALID [2022-02-21 04:23:02,638 INFO L290 TraceCheckUtils]: 118: Hoare triple {7857#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 119: Hoare triple {7857#false} assume 1 == ~E_M~0;~E_M~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 120: Hoare triple {7857#false} assume 1 == ~E_1~0;~E_1~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 121: Hoare triple {7857#false} assume 1 == ~E_2~0;~E_2~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 122: Hoare triple {7857#false} assume 1 == ~E_3~0;~E_3~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 123: Hoare triple {7857#false} assume 1 == ~E_4~0;~E_4~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 124: Hoare triple {7857#false} assume 1 == ~E_5~0;~E_5~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 125: Hoare triple {7857#false} assume !(1 == ~E_6~0); {7857#false} is VALID [2022-02-21 04:23:02,639 INFO L290 TraceCheckUtils]: 126: Hoare triple {7857#false} assume 1 == ~E_7~0;~E_7~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 127: Hoare triple {7857#false} assume 1 == ~E_8~0;~E_8~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 128: Hoare triple {7857#false} assume 1 == ~E_9~0;~E_9~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 129: Hoare triple {7857#false} assume 1 == ~E_10~0;~E_10~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 130: Hoare triple {7857#false} assume 1 == ~E_11~0;~E_11~0 := 2; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 131: Hoare triple {7857#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 132: Hoare triple {7857#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 133: Hoare triple {7857#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {7857#false} is VALID [2022-02-21 04:23:02,640 INFO L290 TraceCheckUtils]: 134: Hoare triple {7857#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 135: Hoare triple {7857#false} assume !(0 == start_simulation_~tmp~3#1); {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 136: Hoare triple {7857#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 137: Hoare triple {7857#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 138: Hoare triple {7857#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 139: Hoare triple {7857#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 140: Hoare triple {7857#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 141: Hoare triple {7857#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 142: Hoare triple {7857#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {7857#false} is VALID [2022-02-21 04:23:02,641 INFO L290 TraceCheckUtils]: 143: Hoare triple {7857#false} assume !(0 != start_simulation_~tmp___0~1#1); {7857#false} is VALID [2022-02-21 04:23:02,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:02,642 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:02,642 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309030476] [2022-02-21 04:23:02,643 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309030476] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:02,643 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:02,643 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:02,643 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109594490] [2022-02-21 04:23:02,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:02,644 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:02,644 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:02,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:02,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:02,645 INFO L87 Difference]: Start difference. First operand 1566 states and 2325 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:03,800 INFO L93 Difference]: Finished difference Result 1566 states and 2324 transitions. [2022-02-21 04:23:03,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:03,800 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:03,874 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:03,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2324 transitions. [2022-02-21 04:23:03,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:03,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2324 transitions. [2022-02-21 04:23:03,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:03,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:03,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2324 transitions. [2022-02-21 04:23:03,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:03,992 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-02-21 04:23:03,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2324 transitions. [2022-02-21 04:23:04,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:04,007 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:04,010 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2324 transitions. Second operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,012 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2324 transitions. Second operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,014 INFO L87 Difference]: Start difference. First operand 1566 states and 2324 transitions. Second operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,073 INFO L93 Difference]: Finished difference Result 1566 states and 2324 transitions. [2022-02-21 04:23:04,073 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2324 transitions. [2022-02-21 04:23:04,075 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,076 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,079 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2324 transitions. [2022-02-21 04:23:04,081 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2324 transitions. [2022-02-21 04:23:04,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:04,139 INFO L93 Difference]: Finished difference Result 1566 states and 2324 transitions. [2022-02-21 04:23:04,139 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2324 transitions. [2022-02-21 04:23:04,141 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:04,142 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:04,142 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:04,142 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:04,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2324 transitions. [2022-02-21 04:23:04,201 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-02-21 04:23:04,201 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-02-21 04:23:04,201 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:04,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2324 transitions. [2022-02-21 04:23:04,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:04,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:04,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:04,208 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,208 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,208 INFO L791 eck$LassoCheckResult]: Stem: 10160#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 10161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10889#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10890#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9663#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9664#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10899#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 10864#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10865#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10012#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10013#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10419#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10837#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9924#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9925#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9810#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9811#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10765#L1109 assume !(0 == ~M_E~0); 10785#L1109-2 assume !(0 == ~T1_E~0); 9817#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9818#L1119-1 assume !(0 == ~T3_E~0); 10841#L1124-1 assume !(0 == ~T4_E~0); 9480#L1129-1 assume !(0 == ~T5_E~0); 9481#L1134-1 assume !(0 == ~T6_E~0); 10092#L1139-1 assume !(0 == ~T7_E~0); 10769#L1144-1 assume !(0 == ~T8_E~0); 10641#L1149-1 assume !(0 == ~T9_E~0); 9587#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9588#L1159-1 assume !(0 == ~T11_E~0); 10627#L1164-1 assume !(0 == ~E_M~0); 9978#L1169-1 assume !(0 == ~E_1~0); 9867#L1174-1 assume !(0 == ~E_2~0); 9743#L1179-1 assume !(0 == ~E_3~0); 9667#L1184-1 assume !(0 == ~E_4~0); 9668#L1189-1 assume !(0 == ~E_5~0); 9699#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9788#L1199-1 assume !(0 == ~E_7~0); 10649#L1204-1 assume !(0 == ~E_8~0); 10586#L1209-1 assume !(0 == ~E_9~0); 10587#L1214-1 assume !(0 == ~E_10~0); 10911#L1219-1 assume !(0 == ~E_11~0); 10984#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9997#L544 assume 1 == ~m_pc~0; 9998#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10828#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10658#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9629#L1379 assume !(0 != activate_threads_~tmp~1#1); 9630#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10405#L563 assume !(1 == ~t1_pc~0); 10202#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9488#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9489#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10525#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9484#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9485#L582 assume 1 == ~t2_pc~0; 10180#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10535#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10536#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10640#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9517#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9518#L601 assume !(1 == ~t3_pc~0); 10196#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10195#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10829#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10571#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10572#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10515#L620 assume 1 == ~t4_pc~0; 9498#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9499#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10060#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10061#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10416#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10604#L639 assume 1 == ~t5_pc~0; 10489#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9790#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9791#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10437#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10438#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10369#L658 assume !(1 == ~t6_pc~0); 9992#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9993#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10562#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10891#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10575#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9832#L677 assume 1 == ~t7_pc~0; 9833#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9736#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10734#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10858#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10859#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10930#L696 assume !(1 == ~t8_pc~0); 10051#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10052#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10898#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10919#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 10965#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10469#L715 assume 1 == ~t9_pc~0; 10470#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10140#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10048#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10049#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10458#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10731#L734 assume !(1 == ~t10_pc~0); 10732#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9950#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9951#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9971#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10674#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10026#L753 assume 1 == ~t11_pc~0; 10027#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10580#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10135#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10136#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10287#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10344#L1237 assume !(1 == ~M_E~0); 10345#L1237-2 assume !(1 == ~T1_E~0); 10956#L1242-1 assume !(1 == ~T2_E~0); 10106#L1247-1 assume !(1 == ~T3_E~0); 10107#L1252-1 assume !(1 == ~T4_E~0); 9890#L1257-1 assume !(1 == ~T5_E~0); 9891#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10747#L1267-1 assume !(1 == ~T7_E~0); 10851#L1272-1 assume !(1 == ~T8_E~0); 10189#L1277-1 assume !(1 == ~T9_E~0); 10190#L1282-1 assume !(1 == ~T10_E~0); 10612#L1287-1 assume !(1 == ~T11_E~0); 10613#L1292-1 assume !(1 == ~E_M~0); 10574#L1297-1 assume !(1 == ~E_1~0); 10021#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10022#L1307-1 assume !(1 == ~E_3~0); 10844#L1312-1 assume !(1 == ~E_4~0); 10232#L1317-1 assume !(1 == ~E_5~0); 10233#L1322-1 assume !(1 == ~E_6~0); 9965#L1327-1 assume !(1 == ~E_7~0); 9966#L1332-1 assume !(1 == ~E_8~0); 10524#L1337-1 assume !(1 == ~E_9~0); 10461#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10462#L1347-1 assume !(1 == ~E_11~0); 10843#L1352-1 assume { :end_inline_reset_delta_events } true; 10730#L1678-2 [2022-02-21 04:23:04,208 INFO L793 eck$LassoCheckResult]: Loop: 10730#L1678-2 assume !false; 10517#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10518#L1084 assume !false; 10301#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10302#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9604#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10619#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9530#L925 assume !(0 != eval_~tmp~0#1); 9532#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9646#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9647#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9501#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9502#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10576#L1119-3 assume !(0 == ~T3_E~0); 10577#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10598#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10599#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10777#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10835#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10005#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10006#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10243#L1159-3 assume !(0 == ~T11_E~0); 10244#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10512#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10513#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10563#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10564#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10719#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10396#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9763#L1199-3 assume !(0 == ~E_7~0); 9764#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9987#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9449#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9450#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10148#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10149#L544-39 assume !(1 == ~m_pc~0); 9430#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9431#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9679#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9680#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 9838#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10706#L563-39 assume 1 == ~t1_pc~0; 10712#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9581#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10480#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10481#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10978#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10821#L582-39 assume 1 == ~t2_pc~0; 9904#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9906#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10526#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10527#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9674#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9461#L601-39 assume 1 == ~t3_pc~0; 9462#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9512#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10670#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10806#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10710#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10362#L620-39 assume !(1 == ~t4_pc~0); 10363#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10560#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10768#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10683#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10684#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10989#L639-39 assume 1 == ~t5_pc~0; 10796#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10110#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9687#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9490#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9491#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10399#L658-39 assume 1 == ~t6_pc~0; 10381#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10382#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9440#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9441#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10556#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10557#L677-39 assume 1 == ~t7_pc~0; 10519#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9665#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9666#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9721#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 9722#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10286#L696-39 assume 1 == ~t8_pc~0; 10252#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10132#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10133#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10428#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10392#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10267#L715-39 assume 1 == ~t9_pc~0; 9466#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9467#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10676#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10990#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10605#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10606#L734-39 assume 1 == ~t10_pc~0; 10531#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9977#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10288#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9619#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9620#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10868#L753-39 assume !(1 == ~t11_pc~0); 9539#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9540#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10832#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10257#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10258#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10359#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10360#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10630#L1242-3 assume !(1 == ~T2_E~0); 10631#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10850#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10550#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10551#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10833#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10874#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10962#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9691#L1282-3 assume !(1 == ~T10_E~0); 9692#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9601#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9602#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10739#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10740#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10928#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10986#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10652#L1322-3 assume !(1 == ~E_6~0); 10653#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9660#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9635#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9636#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10328#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10456#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10457#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9583#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9848#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 10561#L1697 assume !(0 == start_simulation_~tmp~3#1); 10349#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10350#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9707#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10472#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 10473#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10422#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10019#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10020#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10730#L1678-2 [2022-02-21 04:23:04,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,209 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2022-02-21 04:23:04,209 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,209 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439942485] [2022-02-21 04:23:04,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,236 INFO L290 TraceCheckUtils]: 0: Hoare triple {14126#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {14126#true} is VALID [2022-02-21 04:23:04,236 INFO L290 TraceCheckUtils]: 1: Hoare triple {14126#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {14128#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:04,237 INFO L290 TraceCheckUtils]: 2: Hoare triple {14128#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {14128#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:04,237 INFO L290 TraceCheckUtils]: 3: Hoare triple {14128#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {14128#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:04,237 INFO L290 TraceCheckUtils]: 4: Hoare triple {14128#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {14128#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:04,237 INFO L290 TraceCheckUtils]: 5: Hoare triple {14128#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {14128#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 6: Hoare triple {14128#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 7: Hoare triple {14127#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 8: Hoare triple {14127#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 9: Hoare triple {14127#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 10: Hoare triple {14127#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 11: Hoare triple {14127#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 12: Hoare triple {14127#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,238 INFO L290 TraceCheckUtils]: 13: Hoare triple {14127#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 14: Hoare triple {14127#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 15: Hoare triple {14127#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 16: Hoare triple {14127#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 17: Hoare triple {14127#false} assume !(0 == ~M_E~0); {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 18: Hoare triple {14127#false} assume !(0 == ~T1_E~0); {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 19: Hoare triple {14127#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 20: Hoare triple {14127#false} assume !(0 == ~T3_E~0); {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 21: Hoare triple {14127#false} assume !(0 == ~T4_E~0); {14127#false} is VALID [2022-02-21 04:23:04,239 INFO L290 TraceCheckUtils]: 22: Hoare triple {14127#false} assume !(0 == ~T5_E~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 23: Hoare triple {14127#false} assume !(0 == ~T6_E~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 24: Hoare triple {14127#false} assume !(0 == ~T7_E~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 25: Hoare triple {14127#false} assume !(0 == ~T8_E~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 26: Hoare triple {14127#false} assume !(0 == ~T9_E~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 27: Hoare triple {14127#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 28: Hoare triple {14127#false} assume !(0 == ~T11_E~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 29: Hoare triple {14127#false} assume !(0 == ~E_M~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 30: Hoare triple {14127#false} assume !(0 == ~E_1~0); {14127#false} is VALID [2022-02-21 04:23:04,240 INFO L290 TraceCheckUtils]: 31: Hoare triple {14127#false} assume !(0 == ~E_2~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 32: Hoare triple {14127#false} assume !(0 == ~E_3~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 33: Hoare triple {14127#false} assume !(0 == ~E_4~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 34: Hoare triple {14127#false} assume !(0 == ~E_5~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 35: Hoare triple {14127#false} assume 0 == ~E_6~0;~E_6~0 := 1; {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 36: Hoare triple {14127#false} assume !(0 == ~E_7~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 37: Hoare triple {14127#false} assume !(0 == ~E_8~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 38: Hoare triple {14127#false} assume !(0 == ~E_9~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 39: Hoare triple {14127#false} assume !(0 == ~E_10~0); {14127#false} is VALID [2022-02-21 04:23:04,241 INFO L290 TraceCheckUtils]: 40: Hoare triple {14127#false} assume !(0 == ~E_11~0); {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 41: Hoare triple {14127#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 42: Hoare triple {14127#false} assume 1 == ~m_pc~0; {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 43: Hoare triple {14127#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 44: Hoare triple {14127#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 45: Hoare triple {14127#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 46: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp~1#1); {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 47: Hoare triple {14127#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 48: Hoare triple {14127#false} assume !(1 == ~t1_pc~0); {14127#false} is VALID [2022-02-21 04:23:04,242 INFO L290 TraceCheckUtils]: 49: Hoare triple {14127#false} is_transmit1_triggered_~__retres1~1#1 := 0; {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 50: Hoare triple {14127#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 51: Hoare triple {14127#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 52: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___0~0#1); {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 53: Hoare triple {14127#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 54: Hoare triple {14127#false} assume 1 == ~t2_pc~0; {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 55: Hoare triple {14127#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 56: Hoare triple {14127#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14127#false} is VALID [2022-02-21 04:23:04,243 INFO L290 TraceCheckUtils]: 57: Hoare triple {14127#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 58: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___1~0#1); {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 59: Hoare triple {14127#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 60: Hoare triple {14127#false} assume !(1 == ~t3_pc~0); {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 61: Hoare triple {14127#false} is_transmit3_triggered_~__retres1~3#1 := 0; {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 62: Hoare triple {14127#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 63: Hoare triple {14127#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 64: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___2~0#1); {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 65: Hoare triple {14127#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14127#false} is VALID [2022-02-21 04:23:04,244 INFO L290 TraceCheckUtils]: 66: Hoare triple {14127#false} assume 1 == ~t4_pc~0; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 67: Hoare triple {14127#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 68: Hoare triple {14127#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 69: Hoare triple {14127#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 70: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___3~0#1); {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 71: Hoare triple {14127#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 72: Hoare triple {14127#false} assume 1 == ~t5_pc~0; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 73: Hoare triple {14127#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 74: Hoare triple {14127#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14127#false} is VALID [2022-02-21 04:23:04,245 INFO L290 TraceCheckUtils]: 75: Hoare triple {14127#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 76: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___4~0#1); {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 77: Hoare triple {14127#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 78: Hoare triple {14127#false} assume !(1 == ~t6_pc~0); {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 79: Hoare triple {14127#false} is_transmit6_triggered_~__retres1~6#1 := 0; {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 80: Hoare triple {14127#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 81: Hoare triple {14127#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 82: Hoare triple {14127#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 83: Hoare triple {14127#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14127#false} is VALID [2022-02-21 04:23:04,246 INFO L290 TraceCheckUtils]: 84: Hoare triple {14127#false} assume 1 == ~t7_pc~0; {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 85: Hoare triple {14127#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 86: Hoare triple {14127#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 87: Hoare triple {14127#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 88: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___6~0#1); {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 89: Hoare triple {14127#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 90: Hoare triple {14127#false} assume !(1 == ~t8_pc~0); {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 91: Hoare triple {14127#false} is_transmit8_triggered_~__retres1~8#1 := 0; {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 92: Hoare triple {14127#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {14127#false} is VALID [2022-02-21 04:23:04,247 INFO L290 TraceCheckUtils]: 93: Hoare triple {14127#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 94: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___7~0#1); {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 95: Hoare triple {14127#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 96: Hoare triple {14127#false} assume 1 == ~t9_pc~0; {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 97: Hoare triple {14127#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 98: Hoare triple {14127#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 99: Hoare triple {14127#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 100: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___8~0#1); {14127#false} is VALID [2022-02-21 04:23:04,248 INFO L290 TraceCheckUtils]: 101: Hoare triple {14127#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 102: Hoare triple {14127#false} assume !(1 == ~t10_pc~0); {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 103: Hoare triple {14127#false} is_transmit10_triggered_~__retres1~10#1 := 0; {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 104: Hoare triple {14127#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 105: Hoare triple {14127#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 106: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___9~0#1); {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 107: Hoare triple {14127#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 108: Hoare triple {14127#false} assume 1 == ~t11_pc~0; {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 109: Hoare triple {14127#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {14127#false} is VALID [2022-02-21 04:23:04,249 INFO L290 TraceCheckUtils]: 110: Hoare triple {14127#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 111: Hoare triple {14127#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 112: Hoare triple {14127#false} assume !(0 != activate_threads_~tmp___10~0#1); {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 113: Hoare triple {14127#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 114: Hoare triple {14127#false} assume !(1 == ~M_E~0); {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 115: Hoare triple {14127#false} assume !(1 == ~T1_E~0); {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 116: Hoare triple {14127#false} assume !(1 == ~T2_E~0); {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 117: Hoare triple {14127#false} assume !(1 == ~T3_E~0); {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 118: Hoare triple {14127#false} assume !(1 == ~T4_E~0); {14127#false} is VALID [2022-02-21 04:23:04,250 INFO L290 TraceCheckUtils]: 119: Hoare triple {14127#false} assume !(1 == ~T5_E~0); {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 120: Hoare triple {14127#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 121: Hoare triple {14127#false} assume !(1 == ~T7_E~0); {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 122: Hoare triple {14127#false} assume !(1 == ~T8_E~0); {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 123: Hoare triple {14127#false} assume !(1 == ~T9_E~0); {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 124: Hoare triple {14127#false} assume !(1 == ~T10_E~0); {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 125: Hoare triple {14127#false} assume !(1 == ~T11_E~0); {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 126: Hoare triple {14127#false} assume !(1 == ~E_M~0); {14127#false} is VALID [2022-02-21 04:23:04,251 INFO L290 TraceCheckUtils]: 127: Hoare triple {14127#false} assume !(1 == ~E_1~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 128: Hoare triple {14127#false} assume 1 == ~E_2~0;~E_2~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 129: Hoare triple {14127#false} assume !(1 == ~E_3~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 130: Hoare triple {14127#false} assume !(1 == ~E_4~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 131: Hoare triple {14127#false} assume !(1 == ~E_5~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 132: Hoare triple {14127#false} assume !(1 == ~E_6~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 133: Hoare triple {14127#false} assume !(1 == ~E_7~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 134: Hoare triple {14127#false} assume !(1 == ~E_8~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 135: Hoare triple {14127#false} assume !(1 == ~E_9~0); {14127#false} is VALID [2022-02-21 04:23:04,252 INFO L290 TraceCheckUtils]: 136: Hoare triple {14127#false} assume 1 == ~E_10~0;~E_10~0 := 2; {14127#false} is VALID [2022-02-21 04:23:04,253 INFO L290 TraceCheckUtils]: 137: Hoare triple {14127#false} assume !(1 == ~E_11~0); {14127#false} is VALID [2022-02-21 04:23:04,253 INFO L290 TraceCheckUtils]: 138: Hoare triple {14127#false} assume { :end_inline_reset_delta_events } true; {14127#false} is VALID [2022-02-21 04:23:04,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,253 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,253 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439942485] [2022-02-21 04:23:04,253 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439942485] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,254 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,254 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:04,254 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044577303] [2022-02-21 04:23:04,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,254 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:04,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1367576821, now seen corresponding path program 1 times [2022-02-21 04:23:04,255 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,255 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671882762] [2022-02-21 04:23:04,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,296 INFO L290 TraceCheckUtils]: 0: Hoare triple {14129#true} assume !false; {14129#true} is VALID [2022-02-21 04:23:04,296 INFO L290 TraceCheckUtils]: 1: Hoare triple {14129#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {14129#true} is VALID [2022-02-21 04:23:04,296 INFO L290 TraceCheckUtils]: 2: Hoare triple {14129#true} assume !false; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 3: Hoare triple {14129#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 4: Hoare triple {14129#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 5: Hoare triple {14129#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 6: Hoare triple {14129#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 7: Hoare triple {14129#true} assume !(0 != eval_~tmp~0#1); {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 8: Hoare triple {14129#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 9: Hoare triple {14129#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 10: Hoare triple {14129#true} assume 0 == ~M_E~0;~M_E~0 := 1; {14129#true} is VALID [2022-02-21 04:23:04,297 INFO L290 TraceCheckUtils]: 11: Hoare triple {14129#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {14129#true} is VALID [2022-02-21 04:23:04,298 INFO L290 TraceCheckUtils]: 12: Hoare triple {14129#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,298 INFO L290 TraceCheckUtils]: 13: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,298 INFO L290 TraceCheckUtils]: 14: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,299 INFO L290 TraceCheckUtils]: 15: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,299 INFO L290 TraceCheckUtils]: 16: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,299 INFO L290 TraceCheckUtils]: 17: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,300 INFO L290 TraceCheckUtils]: 18: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,300 INFO L290 TraceCheckUtils]: 19: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,300 INFO L290 TraceCheckUtils]: 20: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,300 INFO L290 TraceCheckUtils]: 21: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,301 INFO L290 TraceCheckUtils]: 22: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,301 INFO L290 TraceCheckUtils]: 23: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,301 INFO L290 TraceCheckUtils]: 24: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,301 INFO L290 TraceCheckUtils]: 25: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,302 INFO L290 TraceCheckUtils]: 26: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,302 INFO L290 TraceCheckUtils]: 27: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,302 INFO L290 TraceCheckUtils]: 28: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,302 INFO L290 TraceCheckUtils]: 29: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,303 INFO L290 TraceCheckUtils]: 30: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,303 INFO L290 TraceCheckUtils]: 31: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,303 INFO L290 TraceCheckUtils]: 32: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,304 INFO L290 TraceCheckUtils]: 33: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,304 INFO L290 TraceCheckUtils]: 34: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,304 INFO L290 TraceCheckUtils]: 35: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,304 INFO L290 TraceCheckUtils]: 36: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,305 INFO L290 TraceCheckUtils]: 37: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,305 INFO L290 TraceCheckUtils]: 38: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,305 INFO L290 TraceCheckUtils]: 39: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,305 INFO L290 TraceCheckUtils]: 40: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,306 INFO L290 TraceCheckUtils]: 41: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,306 INFO L290 TraceCheckUtils]: 42: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,306 INFO L290 TraceCheckUtils]: 43: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,307 INFO L290 TraceCheckUtils]: 44: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,307 INFO L290 TraceCheckUtils]: 45: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,307 INFO L290 TraceCheckUtils]: 46: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,307 INFO L290 TraceCheckUtils]: 47: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,308 INFO L290 TraceCheckUtils]: 48: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,308 INFO L290 TraceCheckUtils]: 49: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,308 INFO L290 TraceCheckUtils]: 50: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,309 INFO L290 TraceCheckUtils]: 51: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,309 INFO L290 TraceCheckUtils]: 52: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,309 INFO L290 TraceCheckUtils]: 53: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,309 INFO L290 TraceCheckUtils]: 54: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,310 INFO L290 TraceCheckUtils]: 55: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,310 INFO L290 TraceCheckUtils]: 56: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,310 INFO L290 TraceCheckUtils]: 57: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,310 INFO L290 TraceCheckUtils]: 58: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 59: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 60: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 61: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,311 INFO L290 TraceCheckUtils]: 62: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 63: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 64: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,312 INFO L290 TraceCheckUtils]: 65: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 66: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 67: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 68: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,313 INFO L290 TraceCheckUtils]: 69: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,314 INFO L290 TraceCheckUtils]: 70: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,314 INFO L290 TraceCheckUtils]: 71: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,314 INFO L290 TraceCheckUtils]: 72: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,314 INFO L290 TraceCheckUtils]: 73: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,315 INFO L290 TraceCheckUtils]: 74: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,315 INFO L290 TraceCheckUtils]: 75: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,315 INFO L290 TraceCheckUtils]: 76: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,316 INFO L290 TraceCheckUtils]: 77: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,316 INFO L290 TraceCheckUtils]: 78: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,316 INFO L290 TraceCheckUtils]: 79: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,316 INFO L290 TraceCheckUtils]: 80: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 81: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 82: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 83: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,317 INFO L290 TraceCheckUtils]: 84: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,318 INFO L290 TraceCheckUtils]: 85: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,318 INFO L290 TraceCheckUtils]: 86: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,318 INFO L290 TraceCheckUtils]: 87: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,318 INFO L290 TraceCheckUtils]: 88: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,319 INFO L290 TraceCheckUtils]: 89: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,319 INFO L290 TraceCheckUtils]: 90: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,319 INFO L290 TraceCheckUtils]: 91: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,320 INFO L290 TraceCheckUtils]: 92: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,320 INFO L290 TraceCheckUtils]: 93: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,320 INFO L290 TraceCheckUtils]: 94: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,320 INFO L290 TraceCheckUtils]: 95: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,321 INFO L290 TraceCheckUtils]: 96: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,321 INFO L290 TraceCheckUtils]: 97: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,321 INFO L290 TraceCheckUtils]: 98: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,322 INFO L290 TraceCheckUtils]: 99: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,322 INFO L290 TraceCheckUtils]: 100: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,322 INFO L290 TraceCheckUtils]: 101: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,322 INFO L290 TraceCheckUtils]: 102: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 103: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 104: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 105: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,323 INFO L290 TraceCheckUtils]: 106: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 107: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 108: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {14131#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 109: Hoare triple {14131#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {14130#false} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 110: Hoare triple {14130#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,324 INFO L290 TraceCheckUtils]: 111: Hoare triple {14130#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 112: Hoare triple {14130#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 113: Hoare triple {14130#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 114: Hoare triple {14130#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 115: Hoare triple {14130#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 116: Hoare triple {14130#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 117: Hoare triple {14130#false} assume !(1 == ~T10_E~0); {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 118: Hoare triple {14130#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,325 INFO L290 TraceCheckUtils]: 119: Hoare triple {14130#false} assume 1 == ~E_M~0;~E_M~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 120: Hoare triple {14130#false} assume 1 == ~E_1~0;~E_1~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 121: Hoare triple {14130#false} assume 1 == ~E_2~0;~E_2~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 122: Hoare triple {14130#false} assume 1 == ~E_3~0;~E_3~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 123: Hoare triple {14130#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 124: Hoare triple {14130#false} assume 1 == ~E_5~0;~E_5~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 125: Hoare triple {14130#false} assume !(1 == ~E_6~0); {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 126: Hoare triple {14130#false} assume 1 == ~E_7~0;~E_7~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 127: Hoare triple {14130#false} assume 1 == ~E_8~0;~E_8~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,326 INFO L290 TraceCheckUtils]: 128: Hoare triple {14130#false} assume 1 == ~E_9~0;~E_9~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 129: Hoare triple {14130#false} assume 1 == ~E_10~0;~E_10~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 130: Hoare triple {14130#false} assume 1 == ~E_11~0;~E_11~0 := 2; {14130#false} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 131: Hoare triple {14130#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {14130#false} is VALID [2022-02-21 04:23:04,327 INFO L290 TraceCheckUtils]: 132: Hoare triple {14130#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 133: Hoare triple {14130#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 134: Hoare triple {14130#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 135: Hoare triple {14130#false} assume !(0 == start_simulation_~tmp~3#1); {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 136: Hoare triple {14130#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 137: Hoare triple {14130#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 138: Hoare triple {14130#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 139: Hoare triple {14130#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {14130#false} is VALID [2022-02-21 04:23:04,339 INFO L290 TraceCheckUtils]: 140: Hoare triple {14130#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {14130#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 141: Hoare triple {14130#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14130#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 142: Hoare triple {14130#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {14130#false} is VALID [2022-02-21 04:23:04,340 INFO L290 TraceCheckUtils]: 143: Hoare triple {14130#false} assume !(0 != start_simulation_~tmp___0~1#1); {14130#false} is VALID [2022-02-21 04:23:04,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,340 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,341 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671882762] [2022-02-21 04:23:04,341 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671882762] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,341 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,341 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:04,341 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107044840] [2022-02-21 04:23:04,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,342 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:04,342 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:04,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:04,342 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:04,343 INFO L87 Difference]: Start difference. First operand 1566 states and 2324 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,440 INFO L93 Difference]: Finished difference Result 1566 states and 2323 transitions. [2022-02-21 04:23:05,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:05,440 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,521 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:05,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:05,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2323 transitions. [2022-02-21 04:23:05,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:05,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:05,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:05,643 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-02-21 04:23:05,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:05,659 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:05,662 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2323 transitions. Second operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,664 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2323 transitions. Second operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,667 INFO L87 Difference]: Start difference. First operand 1566 states and 2323 transitions. Second operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,726 INFO L93 Difference]: Finished difference Result 1566 states and 2323 transitions. [2022-02-21 04:23:05,726 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,728 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:05,729 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:05,731 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,733 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:05,788 INFO L93 Difference]: Finished difference Result 1566 states and 2323 transitions. [2022-02-21 04:23:05,788 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,790 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:05,790 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:05,791 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:05,791 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:05,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2323 transitions. [2022-02-21 04:23:05,846 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-02-21 04:23:05,846 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-02-21 04:23:05,846 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:05,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2323 transitions. [2022-02-21 04:23:05,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:05,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:05,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:05,852 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,853 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,853 INFO L791 eck$LassoCheckResult]: Stem: 16433#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 17162#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17163#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15936#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 15937#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17172#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17137#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 17138#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16285#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16286#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16692#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17110#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16197#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16198#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16083#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16084#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17036#L1109 assume !(0 == ~M_E~0); 17058#L1109-2 assume !(0 == ~T1_E~0); 16090#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16091#L1119-1 assume !(0 == ~T3_E~0); 17114#L1124-1 assume !(0 == ~T4_E~0); 15751#L1129-1 assume !(0 == ~T5_E~0); 15752#L1134-1 assume !(0 == ~T6_E~0); 16365#L1139-1 assume !(0 == ~T7_E~0); 17042#L1144-1 assume !(0 == ~T8_E~0); 16914#L1149-1 assume !(0 == ~T9_E~0); 15858#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15859#L1159-1 assume !(0 == ~T11_E~0); 16900#L1164-1 assume !(0 == ~E_M~0); 16251#L1169-1 assume !(0 == ~E_1~0); 16140#L1174-1 assume !(0 == ~E_2~0); 16013#L1179-1 assume !(0 == ~E_3~0); 15940#L1184-1 assume !(0 == ~E_4~0); 15941#L1189-1 assume !(0 == ~E_5~0); 15972#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16059#L1199-1 assume !(0 == ~E_7~0); 16922#L1204-1 assume !(0 == ~E_8~0); 16858#L1209-1 assume !(0 == ~E_9~0); 16859#L1214-1 assume !(0 == ~E_10~0); 17184#L1219-1 assume !(0 == ~E_11~0); 17257#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16268#L544 assume 1 == ~m_pc~0; 16269#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17101#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16929#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15902#L1379 assume !(0 != activate_threads_~tmp~1#1); 15903#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16675#L563 assume !(1 == ~t1_pc~0); 16475#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15761#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15762#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16798#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15757#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15758#L582 assume 1 == ~t2_pc~0; 16453#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16808#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16809#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16913#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15790#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15791#L601 assume !(1 == ~t3_pc~0); 16469#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16468#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17102#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16844#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16845#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16788#L620 assume 1 == ~t4_pc~0; 15771#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15772#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16333#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16334#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16689#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16876#L639 assume 1 == ~t5_pc~0; 16759#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16063#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16064#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16710#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16711#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16640#L658 assume !(1 == ~t6_pc~0); 16265#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16266#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16834#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17164#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16848#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16103#L677 assume 1 == ~t7_pc~0; 16104#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16006#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17007#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17131#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17132#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17203#L696 assume !(1 == ~t8_pc~0); 16323#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16324#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17171#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17192#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17238#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16742#L715 assume 1 == ~t9_pc~0; 16743#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16413#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16321#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16322#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16731#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17003#L734 assume !(1 == ~t10_pc~0); 17004#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16223#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16224#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16242#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 16947#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16299#L753 assume 1 == ~t11_pc~0; 16300#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16853#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16408#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16409#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16558#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16615#L1237 assume !(1 == ~M_E~0); 16616#L1237-2 assume !(1 == ~T1_E~0); 17228#L1242-1 assume !(1 == ~T2_E~0); 16379#L1247-1 assume !(1 == ~T3_E~0); 16380#L1252-1 assume !(1 == ~T4_E~0); 16163#L1257-1 assume !(1 == ~T5_E~0); 16164#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17019#L1267-1 assume !(1 == ~T7_E~0); 17124#L1272-1 assume !(1 == ~T8_E~0); 16462#L1277-1 assume !(1 == ~T9_E~0); 16463#L1282-1 assume !(1 == ~T10_E~0); 16885#L1287-1 assume !(1 == ~T11_E~0); 16886#L1292-1 assume !(1 == ~E_M~0); 16847#L1297-1 assume !(1 == ~E_1~0); 16294#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16295#L1307-1 assume !(1 == ~E_3~0); 17117#L1312-1 assume !(1 == ~E_4~0); 16505#L1317-1 assume !(1 == ~E_5~0); 16506#L1322-1 assume !(1 == ~E_6~0); 16238#L1327-1 assume !(1 == ~E_7~0); 16239#L1332-1 assume !(1 == ~E_8~0); 16797#L1337-1 assume !(1 == ~E_9~0); 16734#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16735#L1347-1 assume !(1 == ~E_11~0); 17116#L1352-1 assume { :end_inline_reset_delta_events } true; 17006#L1678-2 [2022-02-21 04:23:05,853 INFO L793 eck$LassoCheckResult]: Loop: 17006#L1678-2 assume !false; 16789#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16790#L1084 assume !false; 16573#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16574#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15877#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16891#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15803#L925 assume !(0 != eval_~tmp~0#1); 15805#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15919#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15920#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15774#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15775#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16849#L1119-3 assume !(0 == ~T3_E~0); 16850#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16871#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16872#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17050#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17108#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16278#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16279#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16514#L1159-3 assume !(0 == ~T11_E~0); 16515#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16785#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16786#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16836#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16837#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16992#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16669#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16036#L1199-3 assume !(0 == ~E_7~0); 16037#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16260#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15722#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15723#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16421#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16422#L544-39 assume !(1 == ~m_pc~0); 15703#L544-41 is_master_triggered_~__retres1~0#1 := 0; 15704#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15954#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15955#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 16111#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16979#L563-39 assume 1 == ~t1_pc~0; 16985#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15854#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16753#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16754#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17251#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17094#L582-39 assume 1 == ~t2_pc~0; 16177#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16179#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16799#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16800#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15947#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15734#L601-39 assume 1 == ~t3_pc~0; 15735#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15785#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16943#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17079#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16983#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16635#L620-39 assume !(1 == ~t4_pc~0); 16636#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 16833#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17041#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16956#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16957#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17262#L639-39 assume 1 == ~t5_pc~0; 17069#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16383#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15960#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15763#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15764#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16672#L658-39 assume !(1 == ~t6_pc~0); 16656#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 16655#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15713#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15714#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16829#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16830#L677-39 assume 1 == ~t7_pc~0; 16792#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15938#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15939#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15994#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 15995#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16560#L696-39 assume 1 == ~t8_pc~0; 16525#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16405#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16406#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16701#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16665#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16540#L715-39 assume 1 == ~t9_pc~0; 15739#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15740#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16949#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17263#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16878#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16879#L734-39 assume 1 == ~t10_pc~0; 16804#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16250#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16561#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15892#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 15893#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17141#L753-39 assume !(1 == ~t11_pc~0); 15812#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15813#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17105#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16530#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16531#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16632#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16633#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16903#L1242-3 assume !(1 == ~T2_E~0); 16904#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17123#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16823#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16824#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17106#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17147#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17235#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15964#L1282-3 assume !(1 == ~T10_E~0); 15965#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15874#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15875#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17012#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17013#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17201#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17259#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16925#L1322-3 assume !(1 == ~E_6~0); 16926#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15933#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15908#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15909#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16601#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16729#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16730#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15856#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16121#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16835#L1697 assume !(0 == start_simulation_~tmp~3#1); 16622#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16623#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15980#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16745#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 16746#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16695#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16292#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 16293#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17006#L1678-2 [2022-02-21 04:23:05,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:05,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2022-02-21 04:23:05,854 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:05,854 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418779003] [2022-02-21 04:23:05,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:05,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:05,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,900 INFO L290 TraceCheckUtils]: 0: Hoare triple {20399#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {20399#true} is VALID [2022-02-21 04:23:05,901 INFO L290 TraceCheckUtils]: 1: Hoare triple {20399#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {20401#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:05,901 INFO L290 TraceCheckUtils]: 2: Hoare triple {20401#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {20401#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:05,901 INFO L290 TraceCheckUtils]: 3: Hoare triple {20401#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {20401#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:05,901 INFO L290 TraceCheckUtils]: 4: Hoare triple {20401#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {20401#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:05,902 INFO L290 TraceCheckUtils]: 5: Hoare triple {20401#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {20401#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:05,902 INFO L290 TraceCheckUtils]: 6: Hoare triple {20401#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {20401#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:05,902 INFO L290 TraceCheckUtils]: 7: Hoare triple {20401#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,902 INFO L290 TraceCheckUtils]: 8: Hoare triple {20400#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,902 INFO L290 TraceCheckUtils]: 9: Hoare triple {20400#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,902 INFO L290 TraceCheckUtils]: 10: Hoare triple {20400#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,902 INFO L290 TraceCheckUtils]: 11: Hoare triple {20400#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 12: Hoare triple {20400#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 13: Hoare triple {20400#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 14: Hoare triple {20400#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 15: Hoare triple {20400#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 16: Hoare triple {20400#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 17: Hoare triple {20400#false} assume !(0 == ~M_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 18: Hoare triple {20400#false} assume !(0 == ~T1_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 19: Hoare triple {20400#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 20: Hoare triple {20400#false} assume !(0 == ~T3_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 21: Hoare triple {20400#false} assume !(0 == ~T4_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 22: Hoare triple {20400#false} assume !(0 == ~T5_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 23: Hoare triple {20400#false} assume !(0 == ~T6_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 24: Hoare triple {20400#false} assume !(0 == ~T7_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 25: Hoare triple {20400#false} assume !(0 == ~T8_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 26: Hoare triple {20400#false} assume !(0 == ~T9_E~0); {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 27: Hoare triple {20400#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {20400#false} is VALID [2022-02-21 04:23:05,903 INFO L290 TraceCheckUtils]: 28: Hoare triple {20400#false} assume !(0 == ~T11_E~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 29: Hoare triple {20400#false} assume !(0 == ~E_M~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 30: Hoare triple {20400#false} assume !(0 == ~E_1~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 31: Hoare triple {20400#false} assume !(0 == ~E_2~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 32: Hoare triple {20400#false} assume !(0 == ~E_3~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 33: Hoare triple {20400#false} assume !(0 == ~E_4~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 34: Hoare triple {20400#false} assume !(0 == ~E_5~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 35: Hoare triple {20400#false} assume 0 == ~E_6~0;~E_6~0 := 1; {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 36: Hoare triple {20400#false} assume !(0 == ~E_7~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 37: Hoare triple {20400#false} assume !(0 == ~E_8~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 38: Hoare triple {20400#false} assume !(0 == ~E_9~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 39: Hoare triple {20400#false} assume !(0 == ~E_10~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 40: Hoare triple {20400#false} assume !(0 == ~E_11~0); {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 41: Hoare triple {20400#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 42: Hoare triple {20400#false} assume 1 == ~m_pc~0; {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 43: Hoare triple {20400#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 44: Hoare triple {20400#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 45: Hoare triple {20400#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20400#false} is VALID [2022-02-21 04:23:05,904 INFO L290 TraceCheckUtils]: 46: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp~1#1); {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 47: Hoare triple {20400#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 48: Hoare triple {20400#false} assume !(1 == ~t1_pc~0); {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 49: Hoare triple {20400#false} is_transmit1_triggered_~__retres1~1#1 := 0; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 50: Hoare triple {20400#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 51: Hoare triple {20400#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 52: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___0~0#1); {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 53: Hoare triple {20400#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 54: Hoare triple {20400#false} assume 1 == ~t2_pc~0; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 55: Hoare triple {20400#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 56: Hoare triple {20400#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 57: Hoare triple {20400#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 58: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___1~0#1); {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 59: Hoare triple {20400#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 60: Hoare triple {20400#false} assume !(1 == ~t3_pc~0); {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 61: Hoare triple {20400#false} is_transmit3_triggered_~__retres1~3#1 := 0; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 62: Hoare triple {20400#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 63: Hoare triple {20400#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20400#false} is VALID [2022-02-21 04:23:05,905 INFO L290 TraceCheckUtils]: 64: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___2~0#1); {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 65: Hoare triple {20400#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 66: Hoare triple {20400#false} assume 1 == ~t4_pc~0; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 67: Hoare triple {20400#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 68: Hoare triple {20400#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 69: Hoare triple {20400#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 70: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___3~0#1); {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 71: Hoare triple {20400#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 72: Hoare triple {20400#false} assume 1 == ~t5_pc~0; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 73: Hoare triple {20400#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 74: Hoare triple {20400#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 75: Hoare triple {20400#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 76: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___4~0#1); {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 77: Hoare triple {20400#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 78: Hoare triple {20400#false} assume !(1 == ~t6_pc~0); {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 79: Hoare triple {20400#false} is_transmit6_triggered_~__retres1~6#1 := 0; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 80: Hoare triple {20400#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 81: Hoare triple {20400#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {20400#false} is VALID [2022-02-21 04:23:05,906 INFO L290 TraceCheckUtils]: 82: Hoare triple {20400#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 83: Hoare triple {20400#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 84: Hoare triple {20400#false} assume 1 == ~t7_pc~0; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 85: Hoare triple {20400#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 86: Hoare triple {20400#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 87: Hoare triple {20400#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 88: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___6~0#1); {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 89: Hoare triple {20400#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 90: Hoare triple {20400#false} assume !(1 == ~t8_pc~0); {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 91: Hoare triple {20400#false} is_transmit8_triggered_~__retres1~8#1 := 0; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 92: Hoare triple {20400#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 93: Hoare triple {20400#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 94: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___7~0#1); {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 95: Hoare triple {20400#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 96: Hoare triple {20400#false} assume 1 == ~t9_pc~0; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 97: Hoare triple {20400#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 98: Hoare triple {20400#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {20400#false} is VALID [2022-02-21 04:23:05,907 INFO L290 TraceCheckUtils]: 99: Hoare triple {20400#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 100: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___8~0#1); {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 101: Hoare triple {20400#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 102: Hoare triple {20400#false} assume !(1 == ~t10_pc~0); {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 103: Hoare triple {20400#false} is_transmit10_triggered_~__retres1~10#1 := 0; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 104: Hoare triple {20400#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 105: Hoare triple {20400#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 106: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___9~0#1); {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 107: Hoare triple {20400#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 108: Hoare triple {20400#false} assume 1 == ~t11_pc~0; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 109: Hoare triple {20400#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 110: Hoare triple {20400#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 111: Hoare triple {20400#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 112: Hoare triple {20400#false} assume !(0 != activate_threads_~tmp___10~0#1); {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 113: Hoare triple {20400#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 114: Hoare triple {20400#false} assume !(1 == ~M_E~0); {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 115: Hoare triple {20400#false} assume !(1 == ~T1_E~0); {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 116: Hoare triple {20400#false} assume !(1 == ~T2_E~0); {20400#false} is VALID [2022-02-21 04:23:05,908 INFO L290 TraceCheckUtils]: 117: Hoare triple {20400#false} assume !(1 == ~T3_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 118: Hoare triple {20400#false} assume !(1 == ~T4_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 119: Hoare triple {20400#false} assume !(1 == ~T5_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 120: Hoare triple {20400#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 121: Hoare triple {20400#false} assume !(1 == ~T7_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 122: Hoare triple {20400#false} assume !(1 == ~T8_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 123: Hoare triple {20400#false} assume !(1 == ~T9_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 124: Hoare triple {20400#false} assume !(1 == ~T10_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 125: Hoare triple {20400#false} assume !(1 == ~T11_E~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 126: Hoare triple {20400#false} assume !(1 == ~E_M~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 127: Hoare triple {20400#false} assume !(1 == ~E_1~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 128: Hoare triple {20400#false} assume 1 == ~E_2~0;~E_2~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 129: Hoare triple {20400#false} assume !(1 == ~E_3~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 130: Hoare triple {20400#false} assume !(1 == ~E_4~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 131: Hoare triple {20400#false} assume !(1 == ~E_5~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 132: Hoare triple {20400#false} assume !(1 == ~E_6~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 133: Hoare triple {20400#false} assume !(1 == ~E_7~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 134: Hoare triple {20400#false} assume !(1 == ~E_8~0); {20400#false} is VALID [2022-02-21 04:23:05,909 INFO L290 TraceCheckUtils]: 135: Hoare triple {20400#false} assume !(1 == ~E_9~0); {20400#false} is VALID [2022-02-21 04:23:05,910 INFO L290 TraceCheckUtils]: 136: Hoare triple {20400#false} assume 1 == ~E_10~0;~E_10~0 := 2; {20400#false} is VALID [2022-02-21 04:23:05,910 INFO L290 TraceCheckUtils]: 137: Hoare triple {20400#false} assume !(1 == ~E_11~0); {20400#false} is VALID [2022-02-21 04:23:05,910 INFO L290 TraceCheckUtils]: 138: Hoare triple {20400#false} assume { :end_inline_reset_delta_events } true; {20400#false} is VALID [2022-02-21 04:23:05,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:05,910 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:05,910 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418779003] [2022-02-21 04:23:05,910 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418779003] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:05,910 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:05,910 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:05,910 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768875335] [2022-02-21 04:23:05,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:05,911 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:05,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:05,911 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 1 times [2022-02-21 04:23:05,911 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:05,911 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126223321] [2022-02-21 04:23:05,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:05,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:05,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 0: Hoare triple {20402#true} assume !false; {20402#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 1: Hoare triple {20402#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {20402#true} is VALID [2022-02-21 04:23:05,973 INFO L290 TraceCheckUtils]: 2: Hoare triple {20402#true} assume !false; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 3: Hoare triple {20402#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 4: Hoare triple {20402#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 5: Hoare triple {20402#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 6: Hoare triple {20402#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 7: Hoare triple {20402#true} assume !(0 != eval_~tmp~0#1); {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 8: Hoare triple {20402#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 9: Hoare triple {20402#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 10: Hoare triple {20402#true} assume 0 == ~M_E~0;~M_E~0 := 1; {20402#true} is VALID [2022-02-21 04:23:05,974 INFO L290 TraceCheckUtils]: 11: Hoare triple {20402#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {20402#true} is VALID [2022-02-21 04:23:05,975 INFO L290 TraceCheckUtils]: 12: Hoare triple {20402#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,975 INFO L290 TraceCheckUtils]: 13: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,975 INFO L290 TraceCheckUtils]: 14: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,976 INFO L290 TraceCheckUtils]: 15: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,976 INFO L290 TraceCheckUtils]: 16: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,976 INFO L290 TraceCheckUtils]: 17: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,976 INFO L290 TraceCheckUtils]: 18: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,977 INFO L290 TraceCheckUtils]: 19: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,977 INFO L290 TraceCheckUtils]: 20: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,977 INFO L290 TraceCheckUtils]: 21: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 22: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 23: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 24: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,978 INFO L290 TraceCheckUtils]: 25: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,979 INFO L290 TraceCheckUtils]: 26: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,979 INFO L290 TraceCheckUtils]: 27: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,979 INFO L290 TraceCheckUtils]: 28: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,979 INFO L290 TraceCheckUtils]: 29: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,980 INFO L290 TraceCheckUtils]: 30: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,980 INFO L290 TraceCheckUtils]: 31: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,980 INFO L290 TraceCheckUtils]: 32: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,981 INFO L290 TraceCheckUtils]: 33: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,981 INFO L290 TraceCheckUtils]: 34: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,981 INFO L290 TraceCheckUtils]: 35: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,981 INFO L290 TraceCheckUtils]: 36: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,982 INFO L290 TraceCheckUtils]: 37: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,982 INFO L290 TraceCheckUtils]: 38: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,982 INFO L290 TraceCheckUtils]: 39: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,982 INFO L290 TraceCheckUtils]: 40: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,983 INFO L290 TraceCheckUtils]: 41: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,983 INFO L290 TraceCheckUtils]: 42: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,983 INFO L290 TraceCheckUtils]: 43: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,984 INFO L290 TraceCheckUtils]: 44: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,984 INFO L290 TraceCheckUtils]: 45: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,984 INFO L290 TraceCheckUtils]: 46: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,984 INFO L290 TraceCheckUtils]: 47: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,985 INFO L290 TraceCheckUtils]: 48: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,985 INFO L290 TraceCheckUtils]: 49: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,985 INFO L290 TraceCheckUtils]: 50: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,985 INFO L290 TraceCheckUtils]: 51: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,986 INFO L290 TraceCheckUtils]: 52: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,986 INFO L290 TraceCheckUtils]: 53: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,986 INFO L290 TraceCheckUtils]: 54: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 55: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 56: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 57: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,987 INFO L290 TraceCheckUtils]: 58: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 59: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 60: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,988 INFO L290 TraceCheckUtils]: 61: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,990 INFO L290 TraceCheckUtils]: 62: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,990 INFO L290 TraceCheckUtils]: 63: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,990 INFO L290 TraceCheckUtils]: 64: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,990 INFO L290 TraceCheckUtils]: 65: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,991 INFO L290 TraceCheckUtils]: 66: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,991 INFO L290 TraceCheckUtils]: 67: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,991 INFO L290 TraceCheckUtils]: 68: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,991 INFO L290 TraceCheckUtils]: 69: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,992 INFO L290 TraceCheckUtils]: 70: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,992 INFO L290 TraceCheckUtils]: 71: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,992 INFO L290 TraceCheckUtils]: 72: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,993 INFO L290 TraceCheckUtils]: 73: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,993 INFO L290 TraceCheckUtils]: 74: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,993 INFO L290 TraceCheckUtils]: 75: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,993 INFO L290 TraceCheckUtils]: 76: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,994 INFO L290 TraceCheckUtils]: 77: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,994 INFO L290 TraceCheckUtils]: 78: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,994 INFO L290 TraceCheckUtils]: 79: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,994 INFO L290 TraceCheckUtils]: 80: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,995 INFO L290 TraceCheckUtils]: 81: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,995 INFO L290 TraceCheckUtils]: 82: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,995 INFO L290 TraceCheckUtils]: 83: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,996 INFO L290 TraceCheckUtils]: 84: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,996 INFO L290 TraceCheckUtils]: 85: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,996 INFO L290 TraceCheckUtils]: 86: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,996 INFO L290 TraceCheckUtils]: 87: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,997 INFO L290 TraceCheckUtils]: 88: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,997 INFO L290 TraceCheckUtils]: 89: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,997 INFO L290 TraceCheckUtils]: 90: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,997 INFO L290 TraceCheckUtils]: 91: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,998 INFO L290 TraceCheckUtils]: 92: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,998 INFO L290 TraceCheckUtils]: 93: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,998 INFO L290 TraceCheckUtils]: 94: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,999 INFO L290 TraceCheckUtils]: 95: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,999 INFO L290 TraceCheckUtils]: 96: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,999 INFO L290 TraceCheckUtils]: 97: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:05,999 INFO L290 TraceCheckUtils]: 98: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,000 INFO L290 TraceCheckUtils]: 99: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,000 INFO L290 TraceCheckUtils]: 100: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,000 INFO L290 TraceCheckUtils]: 101: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,000 INFO L290 TraceCheckUtils]: 102: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,001 INFO L290 TraceCheckUtils]: 103: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,001 INFO L290 TraceCheckUtils]: 104: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,001 INFO L290 TraceCheckUtils]: 105: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,002 INFO L290 TraceCheckUtils]: 106: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,002 INFO L290 TraceCheckUtils]: 107: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,002 INFO L290 TraceCheckUtils]: 108: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {20404#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:06,002 INFO L290 TraceCheckUtils]: 109: Hoare triple {20404#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {20403#false} is VALID [2022-02-21 04:23:06,002 INFO L290 TraceCheckUtils]: 110: Hoare triple {20403#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 111: Hoare triple {20403#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 112: Hoare triple {20403#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 113: Hoare triple {20403#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 114: Hoare triple {20403#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 115: Hoare triple {20403#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 116: Hoare triple {20403#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 117: Hoare triple {20403#false} assume !(1 == ~T10_E~0); {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 118: Hoare triple {20403#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,003 INFO L290 TraceCheckUtils]: 119: Hoare triple {20403#false} assume 1 == ~E_M~0;~E_M~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 120: Hoare triple {20403#false} assume 1 == ~E_1~0;~E_1~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 121: Hoare triple {20403#false} assume 1 == ~E_2~0;~E_2~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 122: Hoare triple {20403#false} assume 1 == ~E_3~0;~E_3~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 123: Hoare triple {20403#false} assume 1 == ~E_4~0;~E_4~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 124: Hoare triple {20403#false} assume 1 == ~E_5~0;~E_5~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 125: Hoare triple {20403#false} assume !(1 == ~E_6~0); {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 126: Hoare triple {20403#false} assume 1 == ~E_7~0;~E_7~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 127: Hoare triple {20403#false} assume 1 == ~E_8~0;~E_8~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,004 INFO L290 TraceCheckUtils]: 128: Hoare triple {20403#false} assume 1 == ~E_9~0;~E_9~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 129: Hoare triple {20403#false} assume 1 == ~E_10~0;~E_10~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 130: Hoare triple {20403#false} assume 1 == ~E_11~0;~E_11~0 := 2; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 131: Hoare triple {20403#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 132: Hoare triple {20403#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 133: Hoare triple {20403#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 134: Hoare triple {20403#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 135: Hoare triple {20403#false} assume !(0 == start_simulation_~tmp~3#1); {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 136: Hoare triple {20403#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {20403#false} is VALID [2022-02-21 04:23:06,005 INFO L290 TraceCheckUtils]: 137: Hoare triple {20403#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {20403#false} is VALID [2022-02-21 04:23:06,006 INFO L290 TraceCheckUtils]: 138: Hoare triple {20403#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {20403#false} is VALID [2022-02-21 04:23:06,006 INFO L290 TraceCheckUtils]: 139: Hoare triple {20403#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {20403#false} is VALID [2022-02-21 04:23:06,006 INFO L290 TraceCheckUtils]: 140: Hoare triple {20403#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {20403#false} is VALID [2022-02-21 04:23:06,006 INFO L290 TraceCheckUtils]: 141: Hoare triple {20403#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {20403#false} is VALID [2022-02-21 04:23:06,006 INFO L290 TraceCheckUtils]: 142: Hoare triple {20403#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {20403#false} is VALID [2022-02-21 04:23:06,006 INFO L290 TraceCheckUtils]: 143: Hoare triple {20403#false} assume !(0 != start_simulation_~tmp___0~1#1); {20403#false} is VALID [2022-02-21 04:23:06,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:06,007 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:06,007 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126223321] [2022-02-21 04:23:06,007 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126223321] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:06,008 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:06,008 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:06,008 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641522874] [2022-02-21 04:23:06,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:06,008 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:06,008 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:06,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:06,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:06,009 INFO L87 Difference]: Start difference. First operand 1566 states and 2323 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,101 INFO L93 Difference]: Finished difference Result 1566 states and 2322 transitions. [2022-02-21 04:23:07,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:07,101 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,210 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:07,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:07,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2322 transitions. [2022-02-21 04:23:07,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:07,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:07,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:07,326 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-02-21 04:23:07,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:07,342 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:07,344 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2322 transitions. Second operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,346 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2322 transitions. Second operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,348 INFO L87 Difference]: Start difference. First operand 1566 states and 2322 transitions. Second operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,401 INFO L93 Difference]: Finished difference Result 1566 states and 2322 transitions. [2022-02-21 04:23:07,401 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,403 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,403 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,405 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,407 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,460 INFO L93 Difference]: Finished difference Result 1566 states and 2322 transitions. [2022-02-21 04:23:07,460 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,462 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,462 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,462 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:07,462 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:07,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2322 transitions. [2022-02-21 04:23:07,518 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-02-21 04:23:07,518 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-02-21 04:23:07,518 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:07,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2322 transitions. [2022-02-21 04:23:07,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:07,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:07,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:07,524 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,524 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,524 INFO L791 eck$LassoCheckResult]: Stem: 22706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23435#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23436#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22209#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22210#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23445#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23410#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23411#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 22558#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22559#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22965#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23383#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22470#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22471#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22356#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22357#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23311#L1109 assume !(0 == ~M_E~0); 23332#L1109-2 assume !(0 == ~T1_E~0); 22363#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22364#L1119-1 assume !(0 == ~T3_E~0); 23387#L1124-1 assume !(0 == ~T4_E~0); 22026#L1129-1 assume !(0 == ~T5_E~0); 22027#L1134-1 assume !(0 == ~T6_E~0); 22638#L1139-1 assume !(0 == ~T7_E~0); 23315#L1144-1 assume !(0 == ~T8_E~0); 23187#L1149-1 assume !(0 == ~T9_E~0); 22133#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22134#L1159-1 assume !(0 == ~T11_E~0); 23173#L1164-1 assume !(0 == ~E_M~0); 22524#L1169-1 assume !(0 == ~E_1~0); 22413#L1174-1 assume !(0 == ~E_2~0); 22289#L1179-1 assume !(0 == ~E_3~0); 22213#L1184-1 assume !(0 == ~E_4~0); 22214#L1189-1 assume !(0 == ~E_5~0); 22245#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22334#L1199-1 assume !(0 == ~E_7~0); 23195#L1204-1 assume !(0 == ~E_8~0); 23132#L1209-1 assume !(0 == ~E_9~0); 23133#L1214-1 assume !(0 == ~E_10~0); 23457#L1219-1 assume !(0 == ~E_11~0); 23530#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22543#L544 assume 1 == ~m_pc~0; 22544#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23374#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23204#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22177#L1379 assume !(0 != activate_threads_~tmp~1#1); 22178#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22951#L563 assume !(1 == ~t1_pc~0); 22748#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22034#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22035#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23071#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22030#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22031#L582 assume 1 == ~t2_pc~0; 22726#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23082#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23083#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23186#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22063#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22064#L601 assume !(1 == ~t3_pc~0); 22742#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22741#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23376#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23117#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23118#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23061#L620 assume 1 == ~t4_pc~0; 22046#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22047#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22607#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22608#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 22962#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23149#L639 assume 1 == ~t5_pc~0; 23032#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22336#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22337#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22983#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 22984#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22913#L658 assume !(1 == ~t6_pc~0); 22538#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22539#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23107#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23437#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23121#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22376#L677 assume 1 == ~t7_pc~0; 22377#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22279#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23280#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23404#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23405#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23476#L696 assume !(1 == ~t8_pc~0); 22596#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22597#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23444#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23465#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23511#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23015#L715 assume 1 == ~t9_pc~0; 23016#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22686#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22594#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22595#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23004#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23276#L734 assume !(1 == ~t10_pc~0); 23277#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22496#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22497#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22515#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23220#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22572#L753 assume 1 == ~t11_pc~0; 22573#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23126#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22681#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22682#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 22831#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22888#L1237 assume !(1 == ~M_E~0); 22889#L1237-2 assume !(1 == ~T1_E~0); 23501#L1242-1 assume !(1 == ~T2_E~0); 22652#L1247-1 assume !(1 == ~T3_E~0); 22653#L1252-1 assume !(1 == ~T4_E~0); 22436#L1257-1 assume !(1 == ~T5_E~0); 22437#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23292#L1267-1 assume !(1 == ~T7_E~0); 23397#L1272-1 assume !(1 == ~T8_E~0); 22735#L1277-1 assume !(1 == ~T9_E~0); 22736#L1282-1 assume !(1 == ~T10_E~0); 23158#L1287-1 assume !(1 == ~T11_E~0); 23159#L1292-1 assume !(1 == ~E_M~0); 23120#L1297-1 assume !(1 == ~E_1~0); 22567#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22568#L1307-1 assume !(1 == ~E_3~0); 23390#L1312-1 assume !(1 == ~E_4~0); 22778#L1317-1 assume !(1 == ~E_5~0); 22779#L1322-1 assume !(1 == ~E_6~0); 22511#L1327-1 assume !(1 == ~E_7~0); 22512#L1332-1 assume !(1 == ~E_8~0); 23070#L1337-1 assume !(1 == ~E_9~0); 23007#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23008#L1347-1 assume !(1 == ~E_11~0); 23389#L1352-1 assume { :end_inline_reset_delta_events } true; 23279#L1678-2 [2022-02-21 04:23:07,524 INFO L793 eck$LassoCheckResult]: Loop: 23279#L1678-2 assume !false; 23062#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23063#L1084 assume !false; 22846#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22847#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22150#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23164#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22076#L925 assume !(0 != eval_~tmp~0#1); 22078#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22192#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22193#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22044#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22045#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23122#L1119-3 assume !(0 == ~T3_E~0); 23123#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23144#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23145#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23323#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23381#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22551#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22552#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22787#L1159-3 assume !(0 == ~T11_E~0); 22788#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23058#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23059#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23109#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23110#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23265#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22942#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22309#L1199-3 assume !(0 == ~E_7~0); 22310#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22533#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21995#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21996#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22694#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22695#L544-39 assume !(1 == ~m_pc~0); 21976#L544-41 is_master_triggered_~__retres1~0#1 := 0; 21977#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22227#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22228#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 22384#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23252#L563-39 assume 1 == ~t1_pc~0; 23258#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22127#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23026#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23027#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23524#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23367#L582-39 assume 1 == ~t2_pc~0; 22450#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22452#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23072#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23073#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22220#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22007#L601-39 assume 1 == ~t3_pc~0; 22008#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22058#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23216#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23352#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23256#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22908#L620-39 assume !(1 == ~t4_pc~0); 22909#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 23106#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23314#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23229#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23230#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23535#L639-39 assume 1 == ~t5_pc~0; 23342#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22656#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22233#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22036#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22037#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22945#L658-39 assume !(1 == ~t6_pc~0); 22929#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22928#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21986#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21987#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23102#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23103#L677-39 assume 1 == ~t7_pc~0; 23065#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22211#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22212#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22267#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 22268#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22833#L696-39 assume 1 == ~t8_pc~0; 22798#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22678#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22679#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22974#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22938#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22813#L715-39 assume 1 == ~t9_pc~0; 22012#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22013#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23222#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23536#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23151#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23152#L734-39 assume 1 == ~t10_pc~0; 23077#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22523#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22834#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22165#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22166#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23414#L753-39 assume !(1 == ~t11_pc~0); 22085#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 22086#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23378#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22803#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22804#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22905#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22906#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23176#L1242-3 assume !(1 == ~T2_E~0); 23177#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23396#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23096#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23097#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23379#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23420#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23508#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22237#L1282-3 assume !(1 == ~T10_E~0); 22238#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22147#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22148#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23285#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23286#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23474#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23532#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23198#L1322-3 assume !(1 == ~E_6~0); 23199#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22206#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22181#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22182#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22874#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23002#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23003#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22129#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22394#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23108#L1697 assume !(0 == start_simulation_~tmp~3#1); 22895#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22896#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22253#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23018#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 23019#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22968#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22565#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22566#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23279#L1678-2 [2022-02-21 04:23:07,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:07,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2022-02-21 04:23:07,525 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:07,525 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112537127] [2022-02-21 04:23:07,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:07,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:07,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:07,546 INFO L290 TraceCheckUtils]: 0: Hoare triple {26672#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {26672#true} is VALID [2022-02-21 04:23:07,547 INFO L290 TraceCheckUtils]: 1: Hoare triple {26672#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {26674#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:07,547 INFO L290 TraceCheckUtils]: 2: Hoare triple {26674#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26674#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:07,547 INFO L290 TraceCheckUtils]: 3: Hoare triple {26674#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26674#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:07,547 INFO L290 TraceCheckUtils]: 4: Hoare triple {26674#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {26674#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:07,548 INFO L290 TraceCheckUtils]: 5: Hoare triple {26674#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26674#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:07,548 INFO L290 TraceCheckUtils]: 6: Hoare triple {26674#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26674#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:07,548 INFO L290 TraceCheckUtils]: 7: Hoare triple {26674#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {26674#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:07,548 INFO L290 TraceCheckUtils]: 8: Hoare triple {26674#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,548 INFO L290 TraceCheckUtils]: 9: Hoare triple {26673#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 10: Hoare triple {26673#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 11: Hoare triple {26673#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 12: Hoare triple {26673#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 13: Hoare triple {26673#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 14: Hoare triple {26673#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 15: Hoare triple {26673#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 16: Hoare triple {26673#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 17: Hoare triple {26673#false} assume !(0 == ~M_E~0); {26673#false} is VALID [2022-02-21 04:23:07,549 INFO L290 TraceCheckUtils]: 18: Hoare triple {26673#false} assume !(0 == ~T1_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 19: Hoare triple {26673#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 20: Hoare triple {26673#false} assume !(0 == ~T3_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 21: Hoare triple {26673#false} assume !(0 == ~T4_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 22: Hoare triple {26673#false} assume !(0 == ~T5_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 23: Hoare triple {26673#false} assume !(0 == ~T6_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 24: Hoare triple {26673#false} assume !(0 == ~T7_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 25: Hoare triple {26673#false} assume !(0 == ~T8_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 26: Hoare triple {26673#false} assume !(0 == ~T9_E~0); {26673#false} is VALID [2022-02-21 04:23:07,550 INFO L290 TraceCheckUtils]: 27: Hoare triple {26673#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 28: Hoare triple {26673#false} assume !(0 == ~T11_E~0); {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 29: Hoare triple {26673#false} assume !(0 == ~E_M~0); {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 30: Hoare triple {26673#false} assume !(0 == ~E_1~0); {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 31: Hoare triple {26673#false} assume !(0 == ~E_2~0); {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 32: Hoare triple {26673#false} assume !(0 == ~E_3~0); {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 33: Hoare triple {26673#false} assume !(0 == ~E_4~0); {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 34: Hoare triple {26673#false} assume !(0 == ~E_5~0); {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 35: Hoare triple {26673#false} assume 0 == ~E_6~0;~E_6~0 := 1; {26673#false} is VALID [2022-02-21 04:23:07,551 INFO L290 TraceCheckUtils]: 36: Hoare triple {26673#false} assume !(0 == ~E_7~0); {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 37: Hoare triple {26673#false} assume !(0 == ~E_8~0); {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 38: Hoare triple {26673#false} assume !(0 == ~E_9~0); {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 39: Hoare triple {26673#false} assume !(0 == ~E_10~0); {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 40: Hoare triple {26673#false} assume !(0 == ~E_11~0); {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 41: Hoare triple {26673#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 42: Hoare triple {26673#false} assume 1 == ~m_pc~0; {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 43: Hoare triple {26673#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 44: Hoare triple {26673#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26673#false} is VALID [2022-02-21 04:23:07,552 INFO L290 TraceCheckUtils]: 45: Hoare triple {26673#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 46: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp~1#1); {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 47: Hoare triple {26673#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 48: Hoare triple {26673#false} assume !(1 == ~t1_pc~0); {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 49: Hoare triple {26673#false} is_transmit1_triggered_~__retres1~1#1 := 0; {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 50: Hoare triple {26673#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 51: Hoare triple {26673#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 52: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___0~0#1); {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 53: Hoare triple {26673#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26673#false} is VALID [2022-02-21 04:23:07,553 INFO L290 TraceCheckUtils]: 54: Hoare triple {26673#false} assume 1 == ~t2_pc~0; {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 55: Hoare triple {26673#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 56: Hoare triple {26673#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 57: Hoare triple {26673#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 58: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___1~0#1); {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 59: Hoare triple {26673#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 60: Hoare triple {26673#false} assume !(1 == ~t3_pc~0); {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 61: Hoare triple {26673#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 62: Hoare triple {26673#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26673#false} is VALID [2022-02-21 04:23:07,554 INFO L290 TraceCheckUtils]: 63: Hoare triple {26673#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 64: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___2~0#1); {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 65: Hoare triple {26673#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 66: Hoare triple {26673#false} assume 1 == ~t4_pc~0; {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 67: Hoare triple {26673#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 68: Hoare triple {26673#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 69: Hoare triple {26673#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 70: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___3~0#1); {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 71: Hoare triple {26673#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26673#false} is VALID [2022-02-21 04:23:07,555 INFO L290 TraceCheckUtils]: 72: Hoare triple {26673#false} assume 1 == ~t5_pc~0; {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 73: Hoare triple {26673#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 74: Hoare triple {26673#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 75: Hoare triple {26673#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 76: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___4~0#1); {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 77: Hoare triple {26673#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 78: Hoare triple {26673#false} assume !(1 == ~t6_pc~0); {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 79: Hoare triple {26673#false} is_transmit6_triggered_~__retres1~6#1 := 0; {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 80: Hoare triple {26673#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26673#false} is VALID [2022-02-21 04:23:07,556 INFO L290 TraceCheckUtils]: 81: Hoare triple {26673#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 82: Hoare triple {26673#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 83: Hoare triple {26673#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 84: Hoare triple {26673#false} assume 1 == ~t7_pc~0; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 85: Hoare triple {26673#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 86: Hoare triple {26673#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 87: Hoare triple {26673#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 88: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___6~0#1); {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 89: Hoare triple {26673#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26673#false} is VALID [2022-02-21 04:23:07,557 INFO L290 TraceCheckUtils]: 90: Hoare triple {26673#false} assume !(1 == ~t8_pc~0); {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 91: Hoare triple {26673#false} is_transmit8_triggered_~__retres1~8#1 := 0; {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 92: Hoare triple {26673#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 93: Hoare triple {26673#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 94: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___7~0#1); {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 95: Hoare triple {26673#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 96: Hoare triple {26673#false} assume 1 == ~t9_pc~0; {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 97: Hoare triple {26673#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 98: Hoare triple {26673#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26673#false} is VALID [2022-02-21 04:23:07,558 INFO L290 TraceCheckUtils]: 99: Hoare triple {26673#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 100: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___8~0#1); {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 101: Hoare triple {26673#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 102: Hoare triple {26673#false} assume !(1 == ~t10_pc~0); {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 103: Hoare triple {26673#false} is_transmit10_triggered_~__retres1~10#1 := 0; {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 104: Hoare triple {26673#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 105: Hoare triple {26673#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 106: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___9~0#1); {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 107: Hoare triple {26673#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26673#false} is VALID [2022-02-21 04:23:07,559 INFO L290 TraceCheckUtils]: 108: Hoare triple {26673#false} assume 1 == ~t11_pc~0; {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 109: Hoare triple {26673#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 110: Hoare triple {26673#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 111: Hoare triple {26673#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 112: Hoare triple {26673#false} assume !(0 != activate_threads_~tmp___10~0#1); {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 113: Hoare triple {26673#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 114: Hoare triple {26673#false} assume !(1 == ~M_E~0); {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 115: Hoare triple {26673#false} assume !(1 == ~T1_E~0); {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 116: Hoare triple {26673#false} assume !(1 == ~T2_E~0); {26673#false} is VALID [2022-02-21 04:23:07,560 INFO L290 TraceCheckUtils]: 117: Hoare triple {26673#false} assume !(1 == ~T3_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 118: Hoare triple {26673#false} assume !(1 == ~T4_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 119: Hoare triple {26673#false} assume !(1 == ~T5_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 120: Hoare triple {26673#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 121: Hoare triple {26673#false} assume !(1 == ~T7_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 122: Hoare triple {26673#false} assume !(1 == ~T8_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 123: Hoare triple {26673#false} assume !(1 == ~T9_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 124: Hoare triple {26673#false} assume !(1 == ~T10_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 125: Hoare triple {26673#false} assume !(1 == ~T11_E~0); {26673#false} is VALID [2022-02-21 04:23:07,561 INFO L290 TraceCheckUtils]: 126: Hoare triple {26673#false} assume !(1 == ~E_M~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 127: Hoare triple {26673#false} assume !(1 == ~E_1~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 128: Hoare triple {26673#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 129: Hoare triple {26673#false} assume !(1 == ~E_3~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 130: Hoare triple {26673#false} assume !(1 == ~E_4~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 131: Hoare triple {26673#false} assume !(1 == ~E_5~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 132: Hoare triple {26673#false} assume !(1 == ~E_6~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 133: Hoare triple {26673#false} assume !(1 == ~E_7~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 134: Hoare triple {26673#false} assume !(1 == ~E_8~0); {26673#false} is VALID [2022-02-21 04:23:07,562 INFO L290 TraceCheckUtils]: 135: Hoare triple {26673#false} assume !(1 == ~E_9~0); {26673#false} is VALID [2022-02-21 04:23:07,563 INFO L290 TraceCheckUtils]: 136: Hoare triple {26673#false} assume 1 == ~E_10~0;~E_10~0 := 2; {26673#false} is VALID [2022-02-21 04:23:07,563 INFO L290 TraceCheckUtils]: 137: Hoare triple {26673#false} assume !(1 == ~E_11~0); {26673#false} is VALID [2022-02-21 04:23:07,563 INFO L290 TraceCheckUtils]: 138: Hoare triple {26673#false} assume { :end_inline_reset_delta_events } true; {26673#false} is VALID [2022-02-21 04:23:07,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:07,563 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:07,563 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112537127] [2022-02-21 04:23:07,564 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112537127] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:07,564 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:07,564 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:07,564 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946037986] [2022-02-21 04:23:07,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:07,564 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:07,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:07,565 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 2 times [2022-02-21 04:23:07,565 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:07,565 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434032489] [2022-02-21 04:23:07,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:07,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:07,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:07,590 INFO L290 TraceCheckUtils]: 0: Hoare triple {26675#true} assume !false; {26675#true} is VALID [2022-02-21 04:23:07,590 INFO L290 TraceCheckUtils]: 1: Hoare triple {26675#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26675#true} is VALID [2022-02-21 04:23:07,590 INFO L290 TraceCheckUtils]: 2: Hoare triple {26675#true} assume !false; {26675#true} is VALID [2022-02-21 04:23:07,590 INFO L290 TraceCheckUtils]: 3: Hoare triple {26675#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {26675#true} is VALID [2022-02-21 04:23:07,590 INFO L290 TraceCheckUtils]: 4: Hoare triple {26675#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {26675#true} is VALID [2022-02-21 04:23:07,591 INFO L290 TraceCheckUtils]: 5: Hoare triple {26675#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {26675#true} is VALID [2022-02-21 04:23:07,591 INFO L290 TraceCheckUtils]: 6: Hoare triple {26675#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {26675#true} is VALID [2022-02-21 04:23:07,591 INFO L290 TraceCheckUtils]: 7: Hoare triple {26675#true} assume !(0 != eval_~tmp~0#1); {26675#true} is VALID [2022-02-21 04:23:07,591 INFO L290 TraceCheckUtils]: 8: Hoare triple {26675#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26675#true} is VALID [2022-02-21 04:23:07,591 INFO L290 TraceCheckUtils]: 9: Hoare triple {26675#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26675#true} is VALID [2022-02-21 04:23:07,591 INFO L290 TraceCheckUtils]: 10: Hoare triple {26675#true} assume 0 == ~M_E~0;~M_E~0 := 1; {26675#true} is VALID [2022-02-21 04:23:07,591 INFO L290 TraceCheckUtils]: 11: Hoare triple {26675#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26675#true} is VALID [2022-02-21 04:23:07,592 INFO L290 TraceCheckUtils]: 12: Hoare triple {26675#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,592 INFO L290 TraceCheckUtils]: 13: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,592 INFO L290 TraceCheckUtils]: 14: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,592 INFO L290 TraceCheckUtils]: 15: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,593 INFO L290 TraceCheckUtils]: 16: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,593 INFO L290 TraceCheckUtils]: 17: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,593 INFO L290 TraceCheckUtils]: 18: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,593 INFO L290 TraceCheckUtils]: 19: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,594 INFO L290 TraceCheckUtils]: 20: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,594 INFO L290 TraceCheckUtils]: 21: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,594 INFO L290 TraceCheckUtils]: 22: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,594 INFO L290 TraceCheckUtils]: 23: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,595 INFO L290 TraceCheckUtils]: 24: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,595 INFO L290 TraceCheckUtils]: 25: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,595 INFO L290 TraceCheckUtils]: 26: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,595 INFO L290 TraceCheckUtils]: 27: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,596 INFO L290 TraceCheckUtils]: 28: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,596 INFO L290 TraceCheckUtils]: 29: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,596 INFO L290 TraceCheckUtils]: 30: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,596 INFO L290 TraceCheckUtils]: 31: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,597 INFO L290 TraceCheckUtils]: 32: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,597 INFO L290 TraceCheckUtils]: 33: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,597 INFO L290 TraceCheckUtils]: 34: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,598 INFO L290 TraceCheckUtils]: 35: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,598 INFO L290 TraceCheckUtils]: 36: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,598 INFO L290 TraceCheckUtils]: 37: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,598 INFO L290 TraceCheckUtils]: 38: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,599 INFO L290 TraceCheckUtils]: 39: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,599 INFO L290 TraceCheckUtils]: 40: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,599 INFO L290 TraceCheckUtils]: 41: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,599 INFO L290 TraceCheckUtils]: 42: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,600 INFO L290 TraceCheckUtils]: 43: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,600 INFO L290 TraceCheckUtils]: 44: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,600 INFO L290 TraceCheckUtils]: 45: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,600 INFO L290 TraceCheckUtils]: 46: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,601 INFO L290 TraceCheckUtils]: 47: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,601 INFO L290 TraceCheckUtils]: 48: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,601 INFO L290 TraceCheckUtils]: 49: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,601 INFO L290 TraceCheckUtils]: 50: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,602 INFO L290 TraceCheckUtils]: 51: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,602 INFO L290 TraceCheckUtils]: 52: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,602 INFO L290 TraceCheckUtils]: 53: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,602 INFO L290 TraceCheckUtils]: 54: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,603 INFO L290 TraceCheckUtils]: 55: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,603 INFO L290 TraceCheckUtils]: 56: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,603 INFO L290 TraceCheckUtils]: 57: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,603 INFO L290 TraceCheckUtils]: 58: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,604 INFO L290 TraceCheckUtils]: 59: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,604 INFO L290 TraceCheckUtils]: 60: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,604 INFO L290 TraceCheckUtils]: 61: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,604 INFO L290 TraceCheckUtils]: 62: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,605 INFO L290 TraceCheckUtils]: 63: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,605 INFO L290 TraceCheckUtils]: 64: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,605 INFO L290 TraceCheckUtils]: 65: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,606 INFO L290 TraceCheckUtils]: 66: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,606 INFO L290 TraceCheckUtils]: 67: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,606 INFO L290 TraceCheckUtils]: 68: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,606 INFO L290 TraceCheckUtils]: 69: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,607 INFO L290 TraceCheckUtils]: 70: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,607 INFO L290 TraceCheckUtils]: 71: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,607 INFO L290 TraceCheckUtils]: 72: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,607 INFO L290 TraceCheckUtils]: 73: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,608 INFO L290 TraceCheckUtils]: 74: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,608 INFO L290 TraceCheckUtils]: 75: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,608 INFO L290 TraceCheckUtils]: 76: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,608 INFO L290 TraceCheckUtils]: 77: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,609 INFO L290 TraceCheckUtils]: 78: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,609 INFO L290 TraceCheckUtils]: 79: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,609 INFO L290 TraceCheckUtils]: 80: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,609 INFO L290 TraceCheckUtils]: 81: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,610 INFO L290 TraceCheckUtils]: 82: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,610 INFO L290 TraceCheckUtils]: 83: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,610 INFO L290 TraceCheckUtils]: 84: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,610 INFO L290 TraceCheckUtils]: 85: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,611 INFO L290 TraceCheckUtils]: 86: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,611 INFO L290 TraceCheckUtils]: 87: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,611 INFO L290 TraceCheckUtils]: 88: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,612 INFO L290 TraceCheckUtils]: 89: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,612 INFO L290 TraceCheckUtils]: 90: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,612 INFO L290 TraceCheckUtils]: 91: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,612 INFO L290 TraceCheckUtils]: 92: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,613 INFO L290 TraceCheckUtils]: 93: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,613 INFO L290 TraceCheckUtils]: 94: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,613 INFO L290 TraceCheckUtils]: 95: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,613 INFO L290 TraceCheckUtils]: 96: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,614 INFO L290 TraceCheckUtils]: 97: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,614 INFO L290 TraceCheckUtils]: 98: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,614 INFO L290 TraceCheckUtils]: 99: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,614 INFO L290 TraceCheckUtils]: 100: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,615 INFO L290 TraceCheckUtils]: 101: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,615 INFO L290 TraceCheckUtils]: 102: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,615 INFO L290 TraceCheckUtils]: 103: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,615 INFO L290 TraceCheckUtils]: 104: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,616 INFO L290 TraceCheckUtils]: 105: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,616 INFO L290 TraceCheckUtils]: 106: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,616 INFO L290 TraceCheckUtils]: 107: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,616 INFO L290 TraceCheckUtils]: 108: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26677#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:07,617 INFO L290 TraceCheckUtils]: 109: Hoare triple {26677#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {26676#false} is VALID [2022-02-21 04:23:07,617 INFO L290 TraceCheckUtils]: 110: Hoare triple {26676#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,617 INFO L290 TraceCheckUtils]: 111: Hoare triple {26676#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,617 INFO L290 TraceCheckUtils]: 112: Hoare triple {26676#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,617 INFO L290 TraceCheckUtils]: 113: Hoare triple {26676#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,617 INFO L290 TraceCheckUtils]: 114: Hoare triple {26676#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 115: Hoare triple {26676#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 116: Hoare triple {26676#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 117: Hoare triple {26676#false} assume !(1 == ~T10_E~0); {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 118: Hoare triple {26676#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 119: Hoare triple {26676#false} assume 1 == ~E_M~0;~E_M~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 120: Hoare triple {26676#false} assume 1 == ~E_1~0;~E_1~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 121: Hoare triple {26676#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 122: Hoare triple {26676#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,618 INFO L290 TraceCheckUtils]: 123: Hoare triple {26676#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 124: Hoare triple {26676#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 125: Hoare triple {26676#false} assume !(1 == ~E_6~0); {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 126: Hoare triple {26676#false} assume 1 == ~E_7~0;~E_7~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 127: Hoare triple {26676#false} assume 1 == ~E_8~0;~E_8~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 128: Hoare triple {26676#false} assume 1 == ~E_9~0;~E_9~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 129: Hoare triple {26676#false} assume 1 == ~E_10~0;~E_10~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 130: Hoare triple {26676#false} assume 1 == ~E_11~0;~E_11~0 := 2; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 131: Hoare triple {26676#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {26676#false} is VALID [2022-02-21 04:23:07,619 INFO L290 TraceCheckUtils]: 132: Hoare triple {26676#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 133: Hoare triple {26676#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 134: Hoare triple {26676#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 135: Hoare triple {26676#false} assume !(0 == start_simulation_~tmp~3#1); {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 136: Hoare triple {26676#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 137: Hoare triple {26676#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 138: Hoare triple {26676#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 139: Hoare triple {26676#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 140: Hoare triple {26676#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26676#false} is VALID [2022-02-21 04:23:07,620 INFO L290 TraceCheckUtils]: 141: Hoare triple {26676#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26676#false} is VALID [2022-02-21 04:23:07,621 INFO L290 TraceCheckUtils]: 142: Hoare triple {26676#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {26676#false} is VALID [2022-02-21 04:23:07,621 INFO L290 TraceCheckUtils]: 143: Hoare triple {26676#false} assume !(0 != start_simulation_~tmp___0~1#1); {26676#false} is VALID [2022-02-21 04:23:07,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:07,621 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:07,621 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434032489] [2022-02-21 04:23:07,622 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434032489] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:07,622 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:07,622 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:07,622 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295126796] [2022-02-21 04:23:07,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:07,622 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:07,623 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:07,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:07,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:07,623 INFO L87 Difference]: Start difference. First operand 1566 states and 2322 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,686 INFO L93 Difference]: Finished difference Result 1566 states and 2321 transitions. [2022-02-21 04:23:08,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:08,687 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,761 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:08,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2321 transitions. [2022-02-21 04:23:08,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:08,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2321 transitions. [2022-02-21 04:23:08,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:08,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:08,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2321 transitions. [2022-02-21 04:23:08,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:08,880 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-02-21 04:23:08,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2321 transitions. [2022-02-21 04:23:08,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:08,896 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:08,898 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2321 transitions. Second operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,900 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2321 transitions. Second operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,901 INFO L87 Difference]: Start difference. First operand 1566 states and 2321 transitions. Second operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:08,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:08,959 INFO L93 Difference]: Finished difference Result 1566 states and 2321 transitions. [2022-02-21 04:23:08,960 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2321 transitions. [2022-02-21 04:23:08,961 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:08,961 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:08,963 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2321 transitions. [2022-02-21 04:23:08,965 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2321 transitions. [2022-02-21 04:23:09,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:09,019 INFO L93 Difference]: Finished difference Result 1566 states and 2321 transitions. [2022-02-21 04:23:09,019 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2321 transitions. [2022-02-21 04:23:09,020 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:09,020 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:09,021 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:09,021 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:09,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2321 transitions. [2022-02-21 04:23:09,076 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-02-21 04:23:09,076 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-02-21 04:23:09,076 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:09,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2321 transitions. [2022-02-21 04:23:09,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:09,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:09,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:09,083 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,083 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:09,083 INFO L791 eck$LassoCheckResult]: Stem: 28979#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 28980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29708#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29709#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28482#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28483#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29718#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29683#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29684#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28831#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 28832#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 29238#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29656#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28743#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28744#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28629#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28630#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29582#L1109 assume !(0 == ~M_E~0); 29604#L1109-2 assume !(0 == ~T1_E~0); 28636#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28637#L1119-1 assume !(0 == ~T3_E~0); 29660#L1124-1 assume !(0 == ~T4_E~0); 28297#L1129-1 assume !(0 == ~T5_E~0); 28298#L1134-1 assume !(0 == ~T6_E~0); 28911#L1139-1 assume !(0 == ~T7_E~0); 29588#L1144-1 assume !(0 == ~T8_E~0); 29460#L1149-1 assume !(0 == ~T9_E~0); 28404#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28405#L1159-1 assume !(0 == ~T11_E~0); 29446#L1164-1 assume !(0 == ~E_M~0); 28797#L1169-1 assume !(0 == ~E_1~0); 28686#L1174-1 assume !(0 == ~E_2~0); 28559#L1179-1 assume !(0 == ~E_3~0); 28486#L1184-1 assume !(0 == ~E_4~0); 28487#L1189-1 assume !(0 == ~E_5~0); 28518#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28605#L1199-1 assume !(0 == ~E_7~0); 29468#L1204-1 assume !(0 == ~E_8~0); 29404#L1209-1 assume !(0 == ~E_9~0); 29405#L1214-1 assume !(0 == ~E_10~0); 29730#L1219-1 assume !(0 == ~E_11~0); 29803#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28814#L544 assume 1 == ~m_pc~0; 28815#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29647#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29475#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28448#L1379 assume !(0 != activate_threads_~tmp~1#1); 28449#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29221#L563 assume !(1 == ~t1_pc~0); 29021#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28307#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28308#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29344#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28303#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28304#L582 assume 1 == ~t2_pc~0; 28999#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29354#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29355#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29459#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28336#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28337#L601 assume !(1 == ~t3_pc~0); 29015#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29014#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29648#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29390#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29391#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29334#L620 assume 1 == ~t4_pc~0; 28317#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28318#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28879#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28880#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29235#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29422#L639 assume 1 == ~t5_pc~0; 29305#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28609#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28610#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29256#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29257#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29186#L658 assume !(1 == ~t6_pc~0); 28811#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28812#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29380#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29710#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29394#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28649#L677 assume 1 == ~t7_pc~0; 28650#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28552#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29553#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29677#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29678#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29749#L696 assume !(1 == ~t8_pc~0); 28869#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28870#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29717#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29738#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 29784#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29288#L715 assume 1 == ~t9_pc~0; 29289#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28959#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28867#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28868#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29277#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29549#L734 assume !(1 == ~t10_pc~0); 29550#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28769#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28770#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28788#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29493#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28845#L753 assume 1 == ~t11_pc~0; 28846#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29399#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28954#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28955#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29104#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29161#L1237 assume !(1 == ~M_E~0); 29162#L1237-2 assume !(1 == ~T1_E~0); 29774#L1242-1 assume !(1 == ~T2_E~0); 28925#L1247-1 assume !(1 == ~T3_E~0); 28926#L1252-1 assume !(1 == ~T4_E~0); 28709#L1257-1 assume !(1 == ~T5_E~0); 28710#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29565#L1267-1 assume !(1 == ~T7_E~0); 29670#L1272-1 assume !(1 == ~T8_E~0); 29008#L1277-1 assume !(1 == ~T9_E~0); 29009#L1282-1 assume !(1 == ~T10_E~0); 29431#L1287-1 assume !(1 == ~T11_E~0); 29432#L1292-1 assume !(1 == ~E_M~0); 29393#L1297-1 assume !(1 == ~E_1~0); 28840#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28841#L1307-1 assume !(1 == ~E_3~0); 29663#L1312-1 assume !(1 == ~E_4~0); 29051#L1317-1 assume !(1 == ~E_5~0); 29052#L1322-1 assume !(1 == ~E_6~0); 28784#L1327-1 assume !(1 == ~E_7~0); 28785#L1332-1 assume !(1 == ~E_8~0); 29343#L1337-1 assume !(1 == ~E_9~0); 29280#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29281#L1347-1 assume !(1 == ~E_11~0); 29662#L1352-1 assume { :end_inline_reset_delta_events } true; 29552#L1678-2 [2022-02-21 04:23:09,084 INFO L793 eck$LassoCheckResult]: Loop: 29552#L1678-2 assume !false; 29335#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29336#L1084 assume !false; 29119#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29120#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28423#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29437#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28349#L925 assume !(0 != eval_~tmp~0#1); 28351#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28465#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28466#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28320#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28321#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29395#L1119-3 assume !(0 == ~T3_E~0); 29396#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29417#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29418#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29596#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29654#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28824#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28825#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29060#L1159-3 assume !(0 == ~T11_E~0); 29061#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29331#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29332#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29382#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29383#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29538#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29215#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28582#L1199-3 assume !(0 == ~E_7~0); 28583#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28806#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28268#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28269#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28967#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28968#L544-39 assume !(1 == ~m_pc~0); 28249#L544-41 is_master_triggered_~__retres1~0#1 := 0; 28250#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28500#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28501#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 28657#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29525#L563-39 assume 1 == ~t1_pc~0; 29531#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28400#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29299#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29300#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29797#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29640#L582-39 assume 1 == ~t2_pc~0; 28723#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28725#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29345#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29346#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28493#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28280#L601-39 assume 1 == ~t3_pc~0; 28281#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28331#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29489#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29625#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29529#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29181#L620-39 assume !(1 == ~t4_pc~0); 29182#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 29379#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29587#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29502#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29503#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29808#L639-39 assume !(1 == ~t5_pc~0); 29616#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 28929#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28506#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28309#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28310#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29218#L658-39 assume 1 == ~t6_pc~0; 29200#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29201#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28259#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28260#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29375#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29376#L677-39 assume 1 == ~t7_pc~0; 29338#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28484#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28485#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28540#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 28541#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29106#L696-39 assume !(1 == ~t8_pc~0); 29072#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 28951#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28952#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29247#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29211#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29086#L715-39 assume 1 == ~t9_pc~0; 28285#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28286#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29495#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29809#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29424#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29425#L734-39 assume 1 == ~t10_pc~0; 29350#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28796#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29107#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28438#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28439#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29687#L753-39 assume !(1 == ~t11_pc~0); 28358#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28359#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29651#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29076#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29077#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29178#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29179#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29449#L1242-3 assume !(1 == ~T2_E~0); 29450#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29669#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29369#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29370#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29652#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29693#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29781#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28510#L1282-3 assume !(1 == ~T10_E~0); 28511#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28420#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28421#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29558#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29559#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29747#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29805#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29471#L1322-3 assume !(1 == ~E_6~0); 29472#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28479#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28454#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28455#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29147#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29275#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29276#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28402#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28667#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 29381#L1697 assume !(0 == start_simulation_~tmp~3#1); 29168#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29169#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28526#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29291#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 29292#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29241#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28838#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28839#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29552#L1678-2 [2022-02-21 04:23:09,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,084 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2022-02-21 04:23:09,084 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,085 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730140801] [2022-02-21 04:23:09,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,108 INFO L290 TraceCheckUtils]: 0: Hoare triple {32945#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {32945#true} is VALID [2022-02-21 04:23:09,108 INFO L290 TraceCheckUtils]: 1: Hoare triple {32945#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,109 INFO L290 TraceCheckUtils]: 2: Hoare triple {32947#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,109 INFO L290 TraceCheckUtils]: 3: Hoare triple {32947#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,109 INFO L290 TraceCheckUtils]: 4: Hoare triple {32947#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,109 INFO L290 TraceCheckUtils]: 5: Hoare triple {32947#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,110 INFO L290 TraceCheckUtils]: 6: Hoare triple {32947#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,120 INFO L290 TraceCheckUtils]: 7: Hoare triple {32947#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,121 INFO L290 TraceCheckUtils]: 8: Hoare triple {32947#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {32947#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:09,121 INFO L290 TraceCheckUtils]: 9: Hoare triple {32947#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,121 INFO L290 TraceCheckUtils]: 10: Hoare triple {32946#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,121 INFO L290 TraceCheckUtils]: 11: Hoare triple {32946#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,121 INFO L290 TraceCheckUtils]: 12: Hoare triple {32946#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 13: Hoare triple {32946#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 14: Hoare triple {32946#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 15: Hoare triple {32946#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 16: Hoare triple {32946#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 17: Hoare triple {32946#false} assume !(0 == ~M_E~0); {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 18: Hoare triple {32946#false} assume !(0 == ~T1_E~0); {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 19: Hoare triple {32946#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {32946#false} is VALID [2022-02-21 04:23:09,122 INFO L290 TraceCheckUtils]: 20: Hoare triple {32946#false} assume !(0 == ~T3_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 21: Hoare triple {32946#false} assume !(0 == ~T4_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 22: Hoare triple {32946#false} assume !(0 == ~T5_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 23: Hoare triple {32946#false} assume !(0 == ~T6_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 24: Hoare triple {32946#false} assume !(0 == ~T7_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 25: Hoare triple {32946#false} assume !(0 == ~T8_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 26: Hoare triple {32946#false} assume !(0 == ~T9_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 27: Hoare triple {32946#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 28: Hoare triple {32946#false} assume !(0 == ~T11_E~0); {32946#false} is VALID [2022-02-21 04:23:09,123 INFO L290 TraceCheckUtils]: 29: Hoare triple {32946#false} assume !(0 == ~E_M~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 30: Hoare triple {32946#false} assume !(0 == ~E_1~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 31: Hoare triple {32946#false} assume !(0 == ~E_2~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 32: Hoare triple {32946#false} assume !(0 == ~E_3~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 33: Hoare triple {32946#false} assume !(0 == ~E_4~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 34: Hoare triple {32946#false} assume !(0 == ~E_5~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 35: Hoare triple {32946#false} assume 0 == ~E_6~0;~E_6~0 := 1; {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 36: Hoare triple {32946#false} assume !(0 == ~E_7~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 37: Hoare triple {32946#false} assume !(0 == ~E_8~0); {32946#false} is VALID [2022-02-21 04:23:09,124 INFO L290 TraceCheckUtils]: 38: Hoare triple {32946#false} assume !(0 == ~E_9~0); {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 39: Hoare triple {32946#false} assume !(0 == ~E_10~0); {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 40: Hoare triple {32946#false} assume !(0 == ~E_11~0); {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 41: Hoare triple {32946#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 42: Hoare triple {32946#false} assume 1 == ~m_pc~0; {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 43: Hoare triple {32946#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 44: Hoare triple {32946#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 45: Hoare triple {32946#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 46: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp~1#1); {32946#false} is VALID [2022-02-21 04:23:09,125 INFO L290 TraceCheckUtils]: 47: Hoare triple {32946#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 48: Hoare triple {32946#false} assume !(1 == ~t1_pc~0); {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 49: Hoare triple {32946#false} is_transmit1_triggered_~__retres1~1#1 := 0; {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 50: Hoare triple {32946#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 51: Hoare triple {32946#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 52: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___0~0#1); {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 53: Hoare triple {32946#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 54: Hoare triple {32946#false} assume 1 == ~t2_pc~0; {32946#false} is VALID [2022-02-21 04:23:09,126 INFO L290 TraceCheckUtils]: 55: Hoare triple {32946#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 56: Hoare triple {32946#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 57: Hoare triple {32946#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 58: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___1~0#1); {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 59: Hoare triple {32946#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 60: Hoare triple {32946#false} assume !(1 == ~t3_pc~0); {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 61: Hoare triple {32946#false} is_transmit3_triggered_~__retres1~3#1 := 0; {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 62: Hoare triple {32946#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 63: Hoare triple {32946#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32946#false} is VALID [2022-02-21 04:23:09,127 INFO L290 TraceCheckUtils]: 64: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___2~0#1); {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 65: Hoare triple {32946#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 66: Hoare triple {32946#false} assume 1 == ~t4_pc~0; {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 67: Hoare triple {32946#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 68: Hoare triple {32946#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 69: Hoare triple {32946#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 70: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___3~0#1); {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 71: Hoare triple {32946#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 72: Hoare triple {32946#false} assume 1 == ~t5_pc~0; {32946#false} is VALID [2022-02-21 04:23:09,128 INFO L290 TraceCheckUtils]: 73: Hoare triple {32946#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 74: Hoare triple {32946#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 75: Hoare triple {32946#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 76: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___4~0#1); {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 77: Hoare triple {32946#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 78: Hoare triple {32946#false} assume !(1 == ~t6_pc~0); {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 79: Hoare triple {32946#false} is_transmit6_triggered_~__retres1~6#1 := 0; {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 80: Hoare triple {32946#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 81: Hoare triple {32946#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32946#false} is VALID [2022-02-21 04:23:09,129 INFO L290 TraceCheckUtils]: 82: Hoare triple {32946#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 83: Hoare triple {32946#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 84: Hoare triple {32946#false} assume 1 == ~t7_pc~0; {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 85: Hoare triple {32946#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 86: Hoare triple {32946#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 87: Hoare triple {32946#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 88: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___6~0#1); {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 89: Hoare triple {32946#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 90: Hoare triple {32946#false} assume !(1 == ~t8_pc~0); {32946#false} is VALID [2022-02-21 04:23:09,130 INFO L290 TraceCheckUtils]: 91: Hoare triple {32946#false} is_transmit8_triggered_~__retres1~8#1 := 0; {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 92: Hoare triple {32946#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 93: Hoare triple {32946#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 94: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___7~0#1); {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 95: Hoare triple {32946#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 96: Hoare triple {32946#false} assume 1 == ~t9_pc~0; {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 97: Hoare triple {32946#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 98: Hoare triple {32946#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32946#false} is VALID [2022-02-21 04:23:09,131 INFO L290 TraceCheckUtils]: 99: Hoare triple {32946#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 100: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___8~0#1); {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 101: Hoare triple {32946#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 102: Hoare triple {32946#false} assume !(1 == ~t10_pc~0); {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 103: Hoare triple {32946#false} is_transmit10_triggered_~__retres1~10#1 := 0; {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 104: Hoare triple {32946#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 105: Hoare triple {32946#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 106: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___9~0#1); {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 107: Hoare triple {32946#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {32946#false} is VALID [2022-02-21 04:23:09,132 INFO L290 TraceCheckUtils]: 108: Hoare triple {32946#false} assume 1 == ~t11_pc~0; {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 109: Hoare triple {32946#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 110: Hoare triple {32946#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 111: Hoare triple {32946#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 112: Hoare triple {32946#false} assume !(0 != activate_threads_~tmp___10~0#1); {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 113: Hoare triple {32946#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 114: Hoare triple {32946#false} assume !(1 == ~M_E~0); {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 115: Hoare triple {32946#false} assume !(1 == ~T1_E~0); {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 116: Hoare triple {32946#false} assume !(1 == ~T2_E~0); {32946#false} is VALID [2022-02-21 04:23:09,133 INFO L290 TraceCheckUtils]: 117: Hoare triple {32946#false} assume !(1 == ~T3_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 118: Hoare triple {32946#false} assume !(1 == ~T4_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 119: Hoare triple {32946#false} assume !(1 == ~T5_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 120: Hoare triple {32946#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 121: Hoare triple {32946#false} assume !(1 == ~T7_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 122: Hoare triple {32946#false} assume !(1 == ~T8_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 123: Hoare triple {32946#false} assume !(1 == ~T9_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 124: Hoare triple {32946#false} assume !(1 == ~T10_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 125: Hoare triple {32946#false} assume !(1 == ~T11_E~0); {32946#false} is VALID [2022-02-21 04:23:09,134 INFO L290 TraceCheckUtils]: 126: Hoare triple {32946#false} assume !(1 == ~E_M~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 127: Hoare triple {32946#false} assume !(1 == ~E_1~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 128: Hoare triple {32946#false} assume 1 == ~E_2~0;~E_2~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 129: Hoare triple {32946#false} assume !(1 == ~E_3~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 130: Hoare triple {32946#false} assume !(1 == ~E_4~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 131: Hoare triple {32946#false} assume !(1 == ~E_5~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 132: Hoare triple {32946#false} assume !(1 == ~E_6~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 133: Hoare triple {32946#false} assume !(1 == ~E_7~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 134: Hoare triple {32946#false} assume !(1 == ~E_8~0); {32946#false} is VALID [2022-02-21 04:23:09,135 INFO L290 TraceCheckUtils]: 135: Hoare triple {32946#false} assume !(1 == ~E_9~0); {32946#false} is VALID [2022-02-21 04:23:09,136 INFO L290 TraceCheckUtils]: 136: Hoare triple {32946#false} assume 1 == ~E_10~0;~E_10~0 := 2; {32946#false} is VALID [2022-02-21 04:23:09,136 INFO L290 TraceCheckUtils]: 137: Hoare triple {32946#false} assume !(1 == ~E_11~0); {32946#false} is VALID [2022-02-21 04:23:09,136 INFO L290 TraceCheckUtils]: 138: Hoare triple {32946#false} assume { :end_inline_reset_delta_events } true; {32946#false} is VALID [2022-02-21 04:23:09,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,136 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,136 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [730140801] [2022-02-21 04:23:09,137 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [730140801] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,137 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,137 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,137 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846470853] [2022-02-21 04:23:09,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,138 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:09,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:09,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1276071859, now seen corresponding path program 1 times [2022-02-21 04:23:09,138 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:09,141 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953240266] [2022-02-21 04:23:09,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:09,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:09,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 0: Hoare triple {32948#true} assume !false; {32948#true} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 1: Hoare triple {32948#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {32948#true} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 2: Hoare triple {32948#true} assume !false; {32948#true} is VALID [2022-02-21 04:23:09,171 INFO L290 TraceCheckUtils]: 3: Hoare triple {32948#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 4: Hoare triple {32948#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 5: Hoare triple {32948#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 6: Hoare triple {32948#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 7: Hoare triple {32948#true} assume !(0 != eval_~tmp~0#1); {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 8: Hoare triple {32948#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 9: Hoare triple {32948#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 10: Hoare triple {32948#true} assume 0 == ~M_E~0;~M_E~0 := 1; {32948#true} is VALID [2022-02-21 04:23:09,172 INFO L290 TraceCheckUtils]: 11: Hoare triple {32948#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {32948#true} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 12: Hoare triple {32948#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 13: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,173 INFO L290 TraceCheckUtils]: 14: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 15: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 16: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 17: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,174 INFO L290 TraceCheckUtils]: 18: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 19: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 20: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,175 INFO L290 TraceCheckUtils]: 21: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 22: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 23: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 24: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,176 INFO L290 TraceCheckUtils]: 25: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 26: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 27: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 28: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,177 INFO L290 TraceCheckUtils]: 29: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,178 INFO L290 TraceCheckUtils]: 30: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,178 INFO L290 TraceCheckUtils]: 31: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,178 INFO L290 TraceCheckUtils]: 32: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,179 INFO L290 TraceCheckUtils]: 33: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,179 INFO L290 TraceCheckUtils]: 34: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,179 INFO L290 TraceCheckUtils]: 35: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,179 INFO L290 TraceCheckUtils]: 36: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,180 INFO L290 TraceCheckUtils]: 37: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,180 INFO L290 TraceCheckUtils]: 38: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,180 INFO L290 TraceCheckUtils]: 39: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,180 INFO L290 TraceCheckUtils]: 40: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,181 INFO L290 TraceCheckUtils]: 41: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,181 INFO L290 TraceCheckUtils]: 42: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,181 INFO L290 TraceCheckUtils]: 43: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,182 INFO L290 TraceCheckUtils]: 44: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,182 INFO L290 TraceCheckUtils]: 45: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,182 INFO L290 TraceCheckUtils]: 46: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,182 INFO L290 TraceCheckUtils]: 47: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,183 INFO L290 TraceCheckUtils]: 48: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,183 INFO L290 TraceCheckUtils]: 49: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,183 INFO L290 TraceCheckUtils]: 50: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,183 INFO L290 TraceCheckUtils]: 51: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,184 INFO L290 TraceCheckUtils]: 52: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,184 INFO L290 TraceCheckUtils]: 53: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,184 INFO L290 TraceCheckUtils]: 54: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,185 INFO L290 TraceCheckUtils]: 55: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,185 INFO L290 TraceCheckUtils]: 56: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,185 INFO L290 TraceCheckUtils]: 57: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,185 INFO L290 TraceCheckUtils]: 58: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,186 INFO L290 TraceCheckUtils]: 59: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,186 INFO L290 TraceCheckUtils]: 60: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,186 INFO L290 TraceCheckUtils]: 61: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,186 INFO L290 TraceCheckUtils]: 62: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,187 INFO L290 TraceCheckUtils]: 63: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,187 INFO L290 TraceCheckUtils]: 64: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,187 INFO L290 TraceCheckUtils]: 65: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,188 INFO L290 TraceCheckUtils]: 66: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,188 INFO L290 TraceCheckUtils]: 67: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,188 INFO L290 TraceCheckUtils]: 68: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,188 INFO L290 TraceCheckUtils]: 69: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,189 INFO L290 TraceCheckUtils]: 70: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,189 INFO L290 TraceCheckUtils]: 71: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,189 INFO L290 TraceCheckUtils]: 72: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,189 INFO L290 TraceCheckUtils]: 73: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,190 INFO L290 TraceCheckUtils]: 74: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,190 INFO L290 TraceCheckUtils]: 75: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,190 INFO L290 TraceCheckUtils]: 76: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,191 INFO L290 TraceCheckUtils]: 77: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,191 INFO L290 TraceCheckUtils]: 78: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,191 INFO L290 TraceCheckUtils]: 79: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,191 INFO L290 TraceCheckUtils]: 80: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,192 INFO L290 TraceCheckUtils]: 81: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,192 INFO L290 TraceCheckUtils]: 82: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,192 INFO L290 TraceCheckUtils]: 83: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,192 INFO L290 TraceCheckUtils]: 84: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,193 INFO L290 TraceCheckUtils]: 85: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,193 INFO L290 TraceCheckUtils]: 86: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,193 INFO L290 TraceCheckUtils]: 87: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,194 INFO L290 TraceCheckUtils]: 88: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,194 INFO L290 TraceCheckUtils]: 89: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,194 INFO L290 TraceCheckUtils]: 90: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,194 INFO L290 TraceCheckUtils]: 91: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,195 INFO L290 TraceCheckUtils]: 92: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,195 INFO L290 TraceCheckUtils]: 93: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,195 INFO L290 TraceCheckUtils]: 94: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,196 INFO L290 TraceCheckUtils]: 95: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,196 INFO L290 TraceCheckUtils]: 96: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,196 INFO L290 TraceCheckUtils]: 97: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,197 INFO L290 TraceCheckUtils]: 98: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,197 INFO L290 TraceCheckUtils]: 99: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,197 INFO L290 TraceCheckUtils]: 100: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 101: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 102: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 103: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,198 INFO L290 TraceCheckUtils]: 104: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 105: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 106: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 107: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,199 INFO L290 TraceCheckUtils]: 108: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {32950#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 109: Hoare triple {32950#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {32949#false} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 110: Hoare triple {32949#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 111: Hoare triple {32949#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 112: Hoare triple {32949#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 113: Hoare triple {32949#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 114: Hoare triple {32949#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,200 INFO L290 TraceCheckUtils]: 115: Hoare triple {32949#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 116: Hoare triple {32949#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 117: Hoare triple {32949#false} assume !(1 == ~T10_E~0); {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 118: Hoare triple {32949#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 119: Hoare triple {32949#false} assume 1 == ~E_M~0;~E_M~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 120: Hoare triple {32949#false} assume 1 == ~E_1~0;~E_1~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 121: Hoare triple {32949#false} assume 1 == ~E_2~0;~E_2~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 122: Hoare triple {32949#false} assume 1 == ~E_3~0;~E_3~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 123: Hoare triple {32949#false} assume 1 == ~E_4~0;~E_4~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,201 INFO L290 TraceCheckUtils]: 124: Hoare triple {32949#false} assume 1 == ~E_5~0;~E_5~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 125: Hoare triple {32949#false} assume !(1 == ~E_6~0); {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 126: Hoare triple {32949#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 127: Hoare triple {32949#false} assume 1 == ~E_8~0;~E_8~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 128: Hoare triple {32949#false} assume 1 == ~E_9~0;~E_9~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 129: Hoare triple {32949#false} assume 1 == ~E_10~0;~E_10~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 130: Hoare triple {32949#false} assume 1 == ~E_11~0;~E_11~0 := 2; {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 131: Hoare triple {32949#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {32949#false} is VALID [2022-02-21 04:23:09,202 INFO L290 TraceCheckUtils]: 132: Hoare triple {32949#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 133: Hoare triple {32949#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 134: Hoare triple {32949#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 135: Hoare triple {32949#false} assume !(0 == start_simulation_~tmp~3#1); {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 136: Hoare triple {32949#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 137: Hoare triple {32949#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 138: Hoare triple {32949#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 139: Hoare triple {32949#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 140: Hoare triple {32949#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {32949#false} is VALID [2022-02-21 04:23:09,203 INFO L290 TraceCheckUtils]: 141: Hoare triple {32949#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {32949#false} is VALID [2022-02-21 04:23:09,204 INFO L290 TraceCheckUtils]: 142: Hoare triple {32949#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {32949#false} is VALID [2022-02-21 04:23:09,204 INFO L290 TraceCheckUtils]: 143: Hoare triple {32949#false} assume !(0 != start_simulation_~tmp___0~1#1); {32949#false} is VALID [2022-02-21 04:23:09,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:09,204 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:09,204 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953240266] [2022-02-21 04:23:09,205 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953240266] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:09,205 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:09,205 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:09,205 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338274540] [2022-02-21 04:23:09,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:09,206 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:09,206 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:09,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:09,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:09,206 INFO L87 Difference]: Start difference. First operand 1566 states and 2321 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,240 INFO L93 Difference]: Finished difference Result 1566 states and 2320 transitions. [2022-02-21 04:23:10,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:10,240 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,318 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:10,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:10,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2320 transitions. [2022-02-21 04:23:10,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:10,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:10,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:10,432 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-02-21 04:23:10,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:10,447 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:10,449 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2320 transitions. Second operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,450 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2320 transitions. Second operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,452 INFO L87 Difference]: Start difference. First operand 1566 states and 2320 transitions. Second operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,504 INFO L93 Difference]: Finished difference Result 1566 states and 2320 transitions. [2022-02-21 04:23:10,504 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,506 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,506 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,508 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,509 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,562 INFO L93 Difference]: Finished difference Result 1566 states and 2320 transitions. [2022-02-21 04:23:10,562 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,564 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,564 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,564 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:10,564 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:10,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2320 transitions. [2022-02-21 04:23:10,618 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-02-21 04:23:10,618 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-02-21 04:23:10,618 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:10,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2320 transitions. [2022-02-21 04:23:10,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:10,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:10,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:10,622 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,622 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,623 INFO L791 eck$LassoCheckResult]: Stem: 35252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35981#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35982#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34755#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 34756#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35991#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35956#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35957#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35104#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35105#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 35511#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 35929#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 35016#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35017#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 34902#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34903#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35855#L1109 assume !(0 == ~M_E~0); 35877#L1109-2 assume !(0 == ~T1_E~0); 34909#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34910#L1119-1 assume !(0 == ~T3_E~0); 35933#L1124-1 assume !(0 == ~T4_E~0); 34570#L1129-1 assume !(0 == ~T5_E~0); 34571#L1134-1 assume !(0 == ~T6_E~0); 35184#L1139-1 assume !(0 == ~T7_E~0); 35861#L1144-1 assume !(0 == ~T8_E~0); 35733#L1149-1 assume !(0 == ~T9_E~0); 34677#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34678#L1159-1 assume !(0 == ~T11_E~0); 35719#L1164-1 assume !(0 == ~E_M~0); 35070#L1169-1 assume !(0 == ~E_1~0); 34959#L1174-1 assume !(0 == ~E_2~0); 34832#L1179-1 assume !(0 == ~E_3~0); 34759#L1184-1 assume !(0 == ~E_4~0); 34760#L1189-1 assume !(0 == ~E_5~0); 34791#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 34878#L1199-1 assume !(0 == ~E_7~0); 35741#L1204-1 assume !(0 == ~E_8~0); 35677#L1209-1 assume !(0 == ~E_9~0); 35678#L1214-1 assume !(0 == ~E_10~0); 36003#L1219-1 assume !(0 == ~E_11~0); 36076#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35087#L544 assume 1 == ~m_pc~0; 35088#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35920#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35748#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34721#L1379 assume !(0 != activate_threads_~tmp~1#1); 34722#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35494#L563 assume !(1 == ~t1_pc~0); 35294#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34580#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34581#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35617#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34576#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34577#L582 assume 1 == ~t2_pc~0; 35272#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35627#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35628#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35732#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34609#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34610#L601 assume !(1 == ~t3_pc~0); 35288#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35287#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35921#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35663#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35664#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35607#L620 assume 1 == ~t4_pc~0; 34590#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34591#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35152#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35153#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35508#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35695#L639 assume 1 == ~t5_pc~0; 35578#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34882#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34883#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35529#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35530#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35459#L658 assume !(1 == ~t6_pc~0); 35084#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35085#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35653#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35983#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35667#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34922#L677 assume 1 == ~t7_pc~0; 34923#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34825#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35826#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35950#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 35951#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36022#L696 assume !(1 == ~t8_pc~0); 35142#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35143#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35990#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36011#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36057#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35561#L715 assume 1 == ~t9_pc~0; 35562#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35232#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35140#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35141#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35550#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35822#L734 assume !(1 == ~t10_pc~0); 35823#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35042#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35043#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35061#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 35766#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35118#L753 assume 1 == ~t11_pc~0; 35119#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35672#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35227#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35228#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35377#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35434#L1237 assume !(1 == ~M_E~0); 35435#L1237-2 assume !(1 == ~T1_E~0); 36047#L1242-1 assume !(1 == ~T2_E~0); 35198#L1247-1 assume !(1 == ~T3_E~0); 35199#L1252-1 assume !(1 == ~T4_E~0); 34982#L1257-1 assume !(1 == ~T5_E~0); 34983#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35838#L1267-1 assume !(1 == ~T7_E~0); 35943#L1272-1 assume !(1 == ~T8_E~0); 35281#L1277-1 assume !(1 == ~T9_E~0); 35282#L1282-1 assume !(1 == ~T10_E~0); 35704#L1287-1 assume !(1 == ~T11_E~0); 35705#L1292-1 assume !(1 == ~E_M~0); 35666#L1297-1 assume !(1 == ~E_1~0); 35113#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35114#L1307-1 assume !(1 == ~E_3~0); 35936#L1312-1 assume !(1 == ~E_4~0); 35324#L1317-1 assume !(1 == ~E_5~0); 35325#L1322-1 assume !(1 == ~E_6~0); 35057#L1327-1 assume !(1 == ~E_7~0); 35058#L1332-1 assume !(1 == ~E_8~0); 35616#L1337-1 assume !(1 == ~E_9~0); 35553#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35554#L1347-1 assume !(1 == ~E_11~0); 35935#L1352-1 assume { :end_inline_reset_delta_events } true; 35825#L1678-2 [2022-02-21 04:23:10,623 INFO L793 eck$LassoCheckResult]: Loop: 35825#L1678-2 assume !false; 35608#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35609#L1084 assume !false; 35392#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35393#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34696#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35710#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34622#L925 assume !(0 != eval_~tmp~0#1); 34624#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34738#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34739#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34593#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34594#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35668#L1119-3 assume !(0 == ~T3_E~0); 35669#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35690#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35691#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35869#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35927#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35097#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35098#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35333#L1159-3 assume !(0 == ~T11_E~0); 35334#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35604#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35605#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35655#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35656#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35811#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35488#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34855#L1199-3 assume !(0 == ~E_7~0); 34856#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35079#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34541#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34542#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35240#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35241#L544-39 assume !(1 == ~m_pc~0); 34522#L544-41 is_master_triggered_~__retres1~0#1 := 0; 34523#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34773#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34774#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 34930#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35798#L563-39 assume !(1 == ~t1_pc~0); 34672#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 34673#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35572#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35573#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36070#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35913#L582-39 assume 1 == ~t2_pc~0; 34996#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34998#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35618#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35619#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34766#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34553#L601-39 assume 1 == ~t3_pc~0; 34554#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34604#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35762#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35898#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35802#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35454#L620-39 assume 1 == ~t4_pc~0; 35456#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35652#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35860#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35775#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35776#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36081#L639-39 assume 1 == ~t5_pc~0; 35888#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35202#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34779#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34582#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34583#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35491#L658-39 assume 1 == ~t6_pc~0; 35473#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35474#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34532#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34533#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35648#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35649#L677-39 assume 1 == ~t7_pc~0; 35611#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34757#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34758#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34813#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 34814#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35379#L696-39 assume 1 == ~t8_pc~0; 35344#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35224#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35225#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35520#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35484#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35359#L715-39 assume !(1 == ~t9_pc~0); 34560#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 34559#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35768#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36082#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35697#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35698#L734-39 assume 1 == ~t10_pc~0; 35623#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35069#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35380#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34711#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34712#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35960#L753-39 assume !(1 == ~t11_pc~0); 34631#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34632#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35924#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35349#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35350#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35451#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35452#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35722#L1242-3 assume !(1 == ~T2_E~0); 35723#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35942#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35642#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35643#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35925#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35966#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36054#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34783#L1282-3 assume !(1 == ~T10_E~0); 34784#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34693#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34694#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35831#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35832#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36020#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36078#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35744#L1322-3 assume !(1 == ~E_6~0); 35745#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34752#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34727#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34728#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35420#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35548#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35549#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34675#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34940#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 35654#L1697 assume !(0 == start_simulation_~tmp~3#1); 35441#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35442#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34799#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35564#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 35565#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35514#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35111#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 35112#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 35825#L1678-2 [2022-02-21 04:23:10,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,624 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2022-02-21 04:23:10,624 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,624 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340323701] [2022-02-21 04:23:10,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,642 INFO L290 TraceCheckUtils]: 0: Hoare triple {39218#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {39218#true} is VALID [2022-02-21 04:23:10,643 INFO L290 TraceCheckUtils]: 1: Hoare triple {39218#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,643 INFO L290 TraceCheckUtils]: 2: Hoare triple {39220#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,643 INFO L290 TraceCheckUtils]: 3: Hoare triple {39220#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,644 INFO L290 TraceCheckUtils]: 4: Hoare triple {39220#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,644 INFO L290 TraceCheckUtils]: 5: Hoare triple {39220#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,644 INFO L290 TraceCheckUtils]: 6: Hoare triple {39220#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,644 INFO L290 TraceCheckUtils]: 7: Hoare triple {39220#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,645 INFO L290 TraceCheckUtils]: 8: Hoare triple {39220#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,645 INFO L290 TraceCheckUtils]: 9: Hoare triple {39220#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {39220#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:10,645 INFO L290 TraceCheckUtils]: 10: Hoare triple {39220#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,645 INFO L290 TraceCheckUtils]: 11: Hoare triple {39219#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,645 INFO L290 TraceCheckUtils]: 12: Hoare triple {39219#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,645 INFO L290 TraceCheckUtils]: 13: Hoare triple {39219#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 14: Hoare triple {39219#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 15: Hoare triple {39219#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 16: Hoare triple {39219#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 17: Hoare triple {39219#false} assume !(0 == ~M_E~0); {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 18: Hoare triple {39219#false} assume !(0 == ~T1_E~0); {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 19: Hoare triple {39219#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 20: Hoare triple {39219#false} assume !(0 == ~T3_E~0); {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 21: Hoare triple {39219#false} assume !(0 == ~T4_E~0); {39219#false} is VALID [2022-02-21 04:23:10,646 INFO L290 TraceCheckUtils]: 22: Hoare triple {39219#false} assume !(0 == ~T5_E~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 23: Hoare triple {39219#false} assume !(0 == ~T6_E~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 24: Hoare triple {39219#false} assume !(0 == ~T7_E~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 25: Hoare triple {39219#false} assume !(0 == ~T8_E~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 26: Hoare triple {39219#false} assume !(0 == ~T9_E~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 27: Hoare triple {39219#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 28: Hoare triple {39219#false} assume !(0 == ~T11_E~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 29: Hoare triple {39219#false} assume !(0 == ~E_M~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 30: Hoare triple {39219#false} assume !(0 == ~E_1~0); {39219#false} is VALID [2022-02-21 04:23:10,647 INFO L290 TraceCheckUtils]: 31: Hoare triple {39219#false} assume !(0 == ~E_2~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 32: Hoare triple {39219#false} assume !(0 == ~E_3~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 33: Hoare triple {39219#false} assume !(0 == ~E_4~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 34: Hoare triple {39219#false} assume !(0 == ~E_5~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 35: Hoare triple {39219#false} assume 0 == ~E_6~0;~E_6~0 := 1; {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 36: Hoare triple {39219#false} assume !(0 == ~E_7~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 37: Hoare triple {39219#false} assume !(0 == ~E_8~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 38: Hoare triple {39219#false} assume !(0 == ~E_9~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 39: Hoare triple {39219#false} assume !(0 == ~E_10~0); {39219#false} is VALID [2022-02-21 04:23:10,648 INFO L290 TraceCheckUtils]: 40: Hoare triple {39219#false} assume !(0 == ~E_11~0); {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 41: Hoare triple {39219#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 42: Hoare triple {39219#false} assume 1 == ~m_pc~0; {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 43: Hoare triple {39219#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 44: Hoare triple {39219#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 45: Hoare triple {39219#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 46: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp~1#1); {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 47: Hoare triple {39219#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 48: Hoare triple {39219#false} assume !(1 == ~t1_pc~0); {39219#false} is VALID [2022-02-21 04:23:10,649 INFO L290 TraceCheckUtils]: 49: Hoare triple {39219#false} is_transmit1_triggered_~__retres1~1#1 := 0; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 50: Hoare triple {39219#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 51: Hoare triple {39219#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 52: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___0~0#1); {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 53: Hoare triple {39219#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 54: Hoare triple {39219#false} assume 1 == ~t2_pc~0; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 55: Hoare triple {39219#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 56: Hoare triple {39219#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 57: Hoare triple {39219#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {39219#false} is VALID [2022-02-21 04:23:10,650 INFO L290 TraceCheckUtils]: 58: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___1~0#1); {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 59: Hoare triple {39219#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 60: Hoare triple {39219#false} assume !(1 == ~t3_pc~0); {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 61: Hoare triple {39219#false} is_transmit3_triggered_~__retres1~3#1 := 0; {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 62: Hoare triple {39219#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 63: Hoare triple {39219#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 64: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___2~0#1); {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 65: Hoare triple {39219#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39219#false} is VALID [2022-02-21 04:23:10,651 INFO L290 TraceCheckUtils]: 66: Hoare triple {39219#false} assume 1 == ~t4_pc~0; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 67: Hoare triple {39219#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 68: Hoare triple {39219#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 69: Hoare triple {39219#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 70: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___3~0#1); {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 71: Hoare triple {39219#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 72: Hoare triple {39219#false} assume 1 == ~t5_pc~0; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 73: Hoare triple {39219#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 74: Hoare triple {39219#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {39219#false} is VALID [2022-02-21 04:23:10,652 INFO L290 TraceCheckUtils]: 75: Hoare triple {39219#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 76: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___4~0#1); {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 77: Hoare triple {39219#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 78: Hoare triple {39219#false} assume !(1 == ~t6_pc~0); {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 79: Hoare triple {39219#false} is_transmit6_triggered_~__retres1~6#1 := 0; {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 80: Hoare triple {39219#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 81: Hoare triple {39219#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 82: Hoare triple {39219#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 83: Hoare triple {39219#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {39219#false} is VALID [2022-02-21 04:23:10,653 INFO L290 TraceCheckUtils]: 84: Hoare triple {39219#false} assume 1 == ~t7_pc~0; {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 85: Hoare triple {39219#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 86: Hoare triple {39219#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 87: Hoare triple {39219#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 88: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___6~0#1); {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 89: Hoare triple {39219#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 90: Hoare triple {39219#false} assume !(1 == ~t8_pc~0); {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 91: Hoare triple {39219#false} is_transmit8_triggered_~__retres1~8#1 := 0; {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 92: Hoare triple {39219#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {39219#false} is VALID [2022-02-21 04:23:10,654 INFO L290 TraceCheckUtils]: 93: Hoare triple {39219#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 94: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___7~0#1); {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 95: Hoare triple {39219#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 96: Hoare triple {39219#false} assume 1 == ~t9_pc~0; {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 97: Hoare triple {39219#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 98: Hoare triple {39219#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 99: Hoare triple {39219#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 100: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___8~0#1); {39219#false} is VALID [2022-02-21 04:23:10,655 INFO L290 TraceCheckUtils]: 101: Hoare triple {39219#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 102: Hoare triple {39219#false} assume !(1 == ~t10_pc~0); {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 103: Hoare triple {39219#false} is_transmit10_triggered_~__retres1~10#1 := 0; {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 104: Hoare triple {39219#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 105: Hoare triple {39219#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 106: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___9~0#1); {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 107: Hoare triple {39219#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 108: Hoare triple {39219#false} assume 1 == ~t11_pc~0; {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 109: Hoare triple {39219#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {39219#false} is VALID [2022-02-21 04:23:10,656 INFO L290 TraceCheckUtils]: 110: Hoare triple {39219#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 111: Hoare triple {39219#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 112: Hoare triple {39219#false} assume !(0 != activate_threads_~tmp___10~0#1); {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 113: Hoare triple {39219#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 114: Hoare triple {39219#false} assume !(1 == ~M_E~0); {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 115: Hoare triple {39219#false} assume !(1 == ~T1_E~0); {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 116: Hoare triple {39219#false} assume !(1 == ~T2_E~0); {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 117: Hoare triple {39219#false} assume !(1 == ~T3_E~0); {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 118: Hoare triple {39219#false} assume !(1 == ~T4_E~0); {39219#false} is VALID [2022-02-21 04:23:10,657 INFO L290 TraceCheckUtils]: 119: Hoare triple {39219#false} assume !(1 == ~T5_E~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 120: Hoare triple {39219#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 121: Hoare triple {39219#false} assume !(1 == ~T7_E~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 122: Hoare triple {39219#false} assume !(1 == ~T8_E~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 123: Hoare triple {39219#false} assume !(1 == ~T9_E~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 124: Hoare triple {39219#false} assume !(1 == ~T10_E~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 125: Hoare triple {39219#false} assume !(1 == ~T11_E~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 126: Hoare triple {39219#false} assume !(1 == ~E_M~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 127: Hoare triple {39219#false} assume !(1 == ~E_1~0); {39219#false} is VALID [2022-02-21 04:23:10,658 INFO L290 TraceCheckUtils]: 128: Hoare triple {39219#false} assume 1 == ~E_2~0;~E_2~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 129: Hoare triple {39219#false} assume !(1 == ~E_3~0); {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 130: Hoare triple {39219#false} assume !(1 == ~E_4~0); {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 131: Hoare triple {39219#false} assume !(1 == ~E_5~0); {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 132: Hoare triple {39219#false} assume !(1 == ~E_6~0); {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 133: Hoare triple {39219#false} assume !(1 == ~E_7~0); {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 134: Hoare triple {39219#false} assume !(1 == ~E_8~0); {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 135: Hoare triple {39219#false} assume !(1 == ~E_9~0); {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 136: Hoare triple {39219#false} assume 1 == ~E_10~0;~E_10~0 := 2; {39219#false} is VALID [2022-02-21 04:23:10,659 INFO L290 TraceCheckUtils]: 137: Hoare triple {39219#false} assume !(1 == ~E_11~0); {39219#false} is VALID [2022-02-21 04:23:10,660 INFO L290 TraceCheckUtils]: 138: Hoare triple {39219#false} assume { :end_inline_reset_delta_events } true; {39219#false} is VALID [2022-02-21 04:23:10,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,660 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,660 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340323701] [2022-02-21 04:23:10,660 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [340323701] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,660 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,661 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,661 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309452653] [2022-02-21 04:23:10,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,661 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:10,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1056861516, now seen corresponding path program 1 times [2022-02-21 04:23:10,662 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,662 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381187820] [2022-02-21 04:23:10,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,715 INFO L290 TraceCheckUtils]: 0: Hoare triple {39221#true} assume !false; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 1: Hoare triple {39221#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 2: Hoare triple {39221#true} assume !false; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 3: Hoare triple {39221#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 4: Hoare triple {39221#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 5: Hoare triple {39221#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 6: Hoare triple {39221#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 7: Hoare triple {39221#true} assume !(0 != eval_~tmp~0#1); {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 8: Hoare triple {39221#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 9: Hoare triple {39221#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 10: Hoare triple {39221#true} assume 0 == ~M_E~0;~M_E~0 := 1; {39221#true} is VALID [2022-02-21 04:23:10,716 INFO L290 TraceCheckUtils]: 11: Hoare triple {39221#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {39221#true} is VALID [2022-02-21 04:23:10,717 INFO L290 TraceCheckUtils]: 12: Hoare triple {39221#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,717 INFO L290 TraceCheckUtils]: 13: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,717 INFO L290 TraceCheckUtils]: 14: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,717 INFO L290 TraceCheckUtils]: 15: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,718 INFO L290 TraceCheckUtils]: 16: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,718 INFO L290 TraceCheckUtils]: 17: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,718 INFO L290 TraceCheckUtils]: 18: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,718 INFO L290 TraceCheckUtils]: 19: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,719 INFO L290 TraceCheckUtils]: 20: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,719 INFO L290 TraceCheckUtils]: 21: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,719 INFO L290 TraceCheckUtils]: 22: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,719 INFO L290 TraceCheckUtils]: 23: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,720 INFO L290 TraceCheckUtils]: 24: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,720 INFO L290 TraceCheckUtils]: 25: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,720 INFO L290 TraceCheckUtils]: 26: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,720 INFO L290 TraceCheckUtils]: 27: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,721 INFO L290 TraceCheckUtils]: 28: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,721 INFO L290 TraceCheckUtils]: 29: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,721 INFO L290 TraceCheckUtils]: 30: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,721 INFO L290 TraceCheckUtils]: 31: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,722 INFO L290 TraceCheckUtils]: 32: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,722 INFO L290 TraceCheckUtils]: 33: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,722 INFO L290 TraceCheckUtils]: 34: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,722 INFO L290 TraceCheckUtils]: 35: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,723 INFO L290 TraceCheckUtils]: 36: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,723 INFO L290 TraceCheckUtils]: 37: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,723 INFO L290 TraceCheckUtils]: 38: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,723 INFO L290 TraceCheckUtils]: 39: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,724 INFO L290 TraceCheckUtils]: 40: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,724 INFO L290 TraceCheckUtils]: 41: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,724 INFO L290 TraceCheckUtils]: 42: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,724 INFO L290 TraceCheckUtils]: 43: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,725 INFO L290 TraceCheckUtils]: 44: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,725 INFO L290 TraceCheckUtils]: 45: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,725 INFO L290 TraceCheckUtils]: 46: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,725 INFO L290 TraceCheckUtils]: 47: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,726 INFO L290 TraceCheckUtils]: 48: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,726 INFO L290 TraceCheckUtils]: 49: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,726 INFO L290 TraceCheckUtils]: 50: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,726 INFO L290 TraceCheckUtils]: 51: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,727 INFO L290 TraceCheckUtils]: 52: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,727 INFO L290 TraceCheckUtils]: 53: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,727 INFO L290 TraceCheckUtils]: 54: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,727 INFO L290 TraceCheckUtils]: 55: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,728 INFO L290 TraceCheckUtils]: 56: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,728 INFO L290 TraceCheckUtils]: 57: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,728 INFO L290 TraceCheckUtils]: 58: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,728 INFO L290 TraceCheckUtils]: 59: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,729 INFO L290 TraceCheckUtils]: 60: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,729 INFO L290 TraceCheckUtils]: 61: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,729 INFO L290 TraceCheckUtils]: 62: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,730 INFO L290 TraceCheckUtils]: 63: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,730 INFO L290 TraceCheckUtils]: 64: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,730 INFO L290 TraceCheckUtils]: 65: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,730 INFO L290 TraceCheckUtils]: 66: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,731 INFO L290 TraceCheckUtils]: 67: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,731 INFO L290 TraceCheckUtils]: 68: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,731 INFO L290 TraceCheckUtils]: 69: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,731 INFO L290 TraceCheckUtils]: 70: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,732 INFO L290 TraceCheckUtils]: 71: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,732 INFO L290 TraceCheckUtils]: 72: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,732 INFO L290 TraceCheckUtils]: 73: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,732 INFO L290 TraceCheckUtils]: 74: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,733 INFO L290 TraceCheckUtils]: 75: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,733 INFO L290 TraceCheckUtils]: 76: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,733 INFO L290 TraceCheckUtils]: 77: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,733 INFO L290 TraceCheckUtils]: 78: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,734 INFO L290 TraceCheckUtils]: 79: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,734 INFO L290 TraceCheckUtils]: 80: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,734 INFO L290 TraceCheckUtils]: 81: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,734 INFO L290 TraceCheckUtils]: 82: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,735 INFO L290 TraceCheckUtils]: 83: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,735 INFO L290 TraceCheckUtils]: 84: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,735 INFO L290 TraceCheckUtils]: 85: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,735 INFO L290 TraceCheckUtils]: 86: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,736 INFO L290 TraceCheckUtils]: 87: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,736 INFO L290 TraceCheckUtils]: 88: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,736 INFO L290 TraceCheckUtils]: 89: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t9_pc~0); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,736 INFO L290 TraceCheckUtils]: 90: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,737 INFO L290 TraceCheckUtils]: 91: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,737 INFO L290 TraceCheckUtils]: 92: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,737 INFO L290 TraceCheckUtils]: 93: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,737 INFO L290 TraceCheckUtils]: 94: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,738 INFO L290 TraceCheckUtils]: 95: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,738 INFO L290 TraceCheckUtils]: 96: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,738 INFO L290 TraceCheckUtils]: 97: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,738 INFO L290 TraceCheckUtils]: 98: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,739 INFO L290 TraceCheckUtils]: 99: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,739 INFO L290 TraceCheckUtils]: 100: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,739 INFO L290 TraceCheckUtils]: 101: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,739 INFO L290 TraceCheckUtils]: 102: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,740 INFO L290 TraceCheckUtils]: 103: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,740 INFO L290 TraceCheckUtils]: 104: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,740 INFO L290 TraceCheckUtils]: 105: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,740 INFO L290 TraceCheckUtils]: 106: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,741 INFO L290 TraceCheckUtils]: 107: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,741 INFO L290 TraceCheckUtils]: 108: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {39223#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:10,741 INFO L290 TraceCheckUtils]: 109: Hoare triple {39223#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {39222#false} is VALID [2022-02-21 04:23:10,741 INFO L290 TraceCheckUtils]: 110: Hoare triple {39222#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 111: Hoare triple {39222#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 112: Hoare triple {39222#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 113: Hoare triple {39222#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 114: Hoare triple {39222#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 115: Hoare triple {39222#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 116: Hoare triple {39222#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 117: Hoare triple {39222#false} assume !(1 == ~T10_E~0); {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 118: Hoare triple {39222#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,742 INFO L290 TraceCheckUtils]: 119: Hoare triple {39222#false} assume 1 == ~E_M~0;~E_M~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 120: Hoare triple {39222#false} assume 1 == ~E_1~0;~E_1~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 121: Hoare triple {39222#false} assume 1 == ~E_2~0;~E_2~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 122: Hoare triple {39222#false} assume 1 == ~E_3~0;~E_3~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 123: Hoare triple {39222#false} assume 1 == ~E_4~0;~E_4~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 124: Hoare triple {39222#false} assume 1 == ~E_5~0;~E_5~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 125: Hoare triple {39222#false} assume !(1 == ~E_6~0); {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 126: Hoare triple {39222#false} assume 1 == ~E_7~0;~E_7~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 127: Hoare triple {39222#false} assume 1 == ~E_8~0;~E_8~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,743 INFO L290 TraceCheckUtils]: 128: Hoare triple {39222#false} assume 1 == ~E_9~0;~E_9~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 129: Hoare triple {39222#false} assume 1 == ~E_10~0;~E_10~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 130: Hoare triple {39222#false} assume 1 == ~E_11~0;~E_11~0 := 2; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 131: Hoare triple {39222#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 132: Hoare triple {39222#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 133: Hoare triple {39222#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 134: Hoare triple {39222#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 135: Hoare triple {39222#false} assume !(0 == start_simulation_~tmp~3#1); {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 136: Hoare triple {39222#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {39222#false} is VALID [2022-02-21 04:23:10,744 INFO L290 TraceCheckUtils]: 137: Hoare triple {39222#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {39222#false} is VALID [2022-02-21 04:23:10,745 INFO L290 TraceCheckUtils]: 138: Hoare triple {39222#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {39222#false} is VALID [2022-02-21 04:23:10,745 INFO L290 TraceCheckUtils]: 139: Hoare triple {39222#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {39222#false} is VALID [2022-02-21 04:23:10,745 INFO L290 TraceCheckUtils]: 140: Hoare triple {39222#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {39222#false} is VALID [2022-02-21 04:23:10,745 INFO L290 TraceCheckUtils]: 141: Hoare triple {39222#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {39222#false} is VALID [2022-02-21 04:23:10,745 INFO L290 TraceCheckUtils]: 142: Hoare triple {39222#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {39222#false} is VALID [2022-02-21 04:23:10,745 INFO L290 TraceCheckUtils]: 143: Hoare triple {39222#false} assume !(0 != start_simulation_~tmp___0~1#1); {39222#false} is VALID [2022-02-21 04:23:10,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,746 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,746 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381187820] [2022-02-21 04:23:10,746 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381187820] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,746 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,746 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,746 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668453277] [2022-02-21 04:23:10,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,747 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:10,747 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:10,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:10,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:10,748 INFO L87 Difference]: Start difference. First operand 1566 states and 2320 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,743 INFO L93 Difference]: Finished difference Result 1566 states and 2319 transitions. [2022-02-21 04:23:11,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:11,744 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,829 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:11,829 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2319 transitions. [2022-02-21 04:23:11,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:11,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2319 transitions. [2022-02-21 04:23:11,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:11,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:11,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2319 transitions. [2022-02-21 04:23:11,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:11,943 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-02-21 04:23:11,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2319 transitions. [2022-02-21 04:23:11,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:11,960 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:11,962 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2319 transitions. Second operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,963 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2319 transitions. Second operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,965 INFO L87 Difference]: Start difference. First operand 1566 states and 2319 transitions. Second operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:12,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:12,017 INFO L93 Difference]: Finished difference Result 1566 states and 2319 transitions. [2022-02-21 04:23:12,018 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2319 transitions. [2022-02-21 04:23:12,019 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:12,019 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:12,021 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2319 transitions. [2022-02-21 04:23:12,023 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2319 transitions. [2022-02-21 04:23:12,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:12,078 INFO L93 Difference]: Finished difference Result 1566 states and 2319 transitions. [2022-02-21 04:23:12,078 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2319 transitions. [2022-02-21 04:23:12,079 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:12,079 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:12,079 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:12,080 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:12,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:12,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2319 transitions. [2022-02-21 04:23:12,134 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-02-21 04:23:12,134 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-02-21 04:23:12,134 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:12,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2319 transitions. [2022-02-21 04:23:12,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:12,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:12,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:12,139 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:12,139 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:12,139 INFO L791 eck$LassoCheckResult]: Stem: 41525#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 41526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 42254#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42255#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41028#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 41029#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42264#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42229#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42230#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41377#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41378#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41784#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 42202#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 41289#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41290#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 41175#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41176#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42128#L1109 assume !(0 == ~M_E~0); 42150#L1109-2 assume !(0 == ~T1_E~0); 41182#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41183#L1119-1 assume !(0 == ~T3_E~0); 42206#L1124-1 assume !(0 == ~T4_E~0); 40843#L1129-1 assume !(0 == ~T5_E~0); 40844#L1134-1 assume !(0 == ~T6_E~0); 41457#L1139-1 assume !(0 == ~T7_E~0); 42134#L1144-1 assume !(0 == ~T8_E~0); 42006#L1149-1 assume !(0 == ~T9_E~0); 40950#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40951#L1159-1 assume !(0 == ~T11_E~0); 41992#L1164-1 assume !(0 == ~E_M~0); 41343#L1169-1 assume !(0 == ~E_1~0); 41232#L1174-1 assume !(0 == ~E_2~0); 41105#L1179-1 assume !(0 == ~E_3~0); 41032#L1184-1 assume !(0 == ~E_4~0); 41033#L1189-1 assume !(0 == ~E_5~0); 41064#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 41151#L1199-1 assume !(0 == ~E_7~0); 42014#L1204-1 assume !(0 == ~E_8~0); 41950#L1209-1 assume !(0 == ~E_9~0); 41951#L1214-1 assume !(0 == ~E_10~0); 42276#L1219-1 assume !(0 == ~E_11~0); 42349#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41360#L544 assume 1 == ~m_pc~0; 41361#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 42193#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42021#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40994#L1379 assume !(0 != activate_threads_~tmp~1#1); 40995#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41767#L563 assume !(1 == ~t1_pc~0); 41567#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40853#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40854#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41890#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 40849#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40850#L582 assume 1 == ~t2_pc~0; 41545#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41900#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41901#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42005#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 40882#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40883#L601 assume !(1 == ~t3_pc~0); 41561#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41560#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42194#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41936#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 41937#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41880#L620 assume 1 == ~t4_pc~0; 40863#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40864#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41425#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41426#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 41781#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41968#L639 assume 1 == ~t5_pc~0; 41851#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41155#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41156#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41802#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 41803#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41732#L658 assume !(1 == ~t6_pc~0); 41357#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41358#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41926#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42256#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41940#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41195#L677 assume 1 == ~t7_pc~0; 41196#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41098#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42099#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42223#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 42224#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42295#L696 assume !(1 == ~t8_pc~0); 41415#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41416#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42263#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42284#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 42330#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41834#L715 assume 1 == ~t9_pc~0; 41835#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41505#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41413#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41414#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 41823#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42095#L734 assume !(1 == ~t10_pc~0); 42096#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41315#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41316#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41334#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 42039#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41391#L753 assume 1 == ~t11_pc~0; 41392#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41945#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41500#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41501#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 41650#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41707#L1237 assume !(1 == ~M_E~0); 41708#L1237-2 assume !(1 == ~T1_E~0); 42320#L1242-1 assume !(1 == ~T2_E~0); 41471#L1247-1 assume !(1 == ~T3_E~0); 41472#L1252-1 assume !(1 == ~T4_E~0); 41255#L1257-1 assume !(1 == ~T5_E~0); 41256#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42111#L1267-1 assume !(1 == ~T7_E~0); 42216#L1272-1 assume !(1 == ~T8_E~0); 41554#L1277-1 assume !(1 == ~T9_E~0); 41555#L1282-1 assume !(1 == ~T10_E~0); 41977#L1287-1 assume !(1 == ~T11_E~0); 41978#L1292-1 assume !(1 == ~E_M~0); 41939#L1297-1 assume !(1 == ~E_1~0); 41386#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 41387#L1307-1 assume !(1 == ~E_3~0); 42209#L1312-1 assume !(1 == ~E_4~0); 41597#L1317-1 assume !(1 == ~E_5~0); 41598#L1322-1 assume !(1 == ~E_6~0); 41330#L1327-1 assume !(1 == ~E_7~0); 41331#L1332-1 assume !(1 == ~E_8~0); 41889#L1337-1 assume !(1 == ~E_9~0); 41826#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 41827#L1347-1 assume !(1 == ~E_11~0); 42208#L1352-1 assume { :end_inline_reset_delta_events } true; 42098#L1678-2 [2022-02-21 04:23:12,139 INFO L793 eck$LassoCheckResult]: Loop: 42098#L1678-2 assume !false; 41881#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41882#L1084 assume !false; 41665#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41666#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40969#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41983#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40895#L925 assume !(0 != eval_~tmp~0#1); 40897#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41011#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41012#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40866#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40867#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41941#L1119-3 assume !(0 == ~T3_E~0); 41942#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41963#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41964#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42142#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42200#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41370#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41371#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41606#L1159-3 assume !(0 == ~T11_E~0); 41607#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41877#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41878#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41928#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41929#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42084#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41761#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41128#L1199-3 assume !(0 == ~E_7~0); 41129#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41352#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40814#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40815#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41513#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41514#L544-39 assume !(1 == ~m_pc~0); 40795#L544-41 is_master_triggered_~__retres1~0#1 := 0; 40796#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41046#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41047#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 41203#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42071#L563-39 assume !(1 == ~t1_pc~0); 40945#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 40946#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41845#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41846#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42343#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42186#L582-39 assume 1 == ~t2_pc~0; 41269#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41271#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41891#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41892#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41039#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40826#L601-39 assume 1 == ~t3_pc~0; 40827#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40877#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42035#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42171#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42075#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41727#L620-39 assume !(1 == ~t4_pc~0); 41728#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41925#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42133#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42048#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42049#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42354#L639-39 assume 1 == ~t5_pc~0; 42161#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41475#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41052#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40855#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40856#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41764#L658-39 assume 1 == ~t6_pc~0; 41746#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41747#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40805#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40806#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41921#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41922#L677-39 assume !(1 == ~t7_pc~0); 41552#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 41030#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41031#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41086#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 41087#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41652#L696-39 assume 1 == ~t8_pc~0; 41617#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41497#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41498#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41793#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41757#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41632#L715-39 assume !(1 == ~t9_pc~0); 40833#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 40832#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42041#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42355#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41970#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41971#L734-39 assume 1 == ~t10_pc~0; 41896#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41342#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41653#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40984#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40985#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42233#L753-39 assume !(1 == ~t11_pc~0); 40904#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 40905#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42197#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41622#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41623#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41724#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41725#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41995#L1242-3 assume !(1 == ~T2_E~0); 41996#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42215#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41915#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41916#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42198#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42239#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42327#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41056#L1282-3 assume !(1 == ~T10_E~0); 41057#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40966#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40967#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42104#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42105#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42293#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42351#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42017#L1322-3 assume !(1 == ~E_6~0); 42018#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41025#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41000#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41001#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41693#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41821#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41822#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40948#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41213#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41927#L1697 assume !(0 == start_simulation_~tmp~3#1); 41714#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41715#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41072#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41837#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 41838#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41787#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41384#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41385#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 42098#L1678-2 [2022-02-21 04:23:12,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:12,140 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2022-02-21 04:23:12,140 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:12,140 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726217168] [2022-02-21 04:23:12,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:12,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:12,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:12,163 INFO L290 TraceCheckUtils]: 0: Hoare triple {45491#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {45491#true} is VALID [2022-02-21 04:23:12,164 INFO L290 TraceCheckUtils]: 1: Hoare triple {45491#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,164 INFO L290 TraceCheckUtils]: 2: Hoare triple {45493#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,164 INFO L290 TraceCheckUtils]: 3: Hoare triple {45493#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,165 INFO L290 TraceCheckUtils]: 4: Hoare triple {45493#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,165 INFO L290 TraceCheckUtils]: 5: Hoare triple {45493#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,165 INFO L290 TraceCheckUtils]: 6: Hoare triple {45493#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,165 INFO L290 TraceCheckUtils]: 7: Hoare triple {45493#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,166 INFO L290 TraceCheckUtils]: 8: Hoare triple {45493#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,166 INFO L290 TraceCheckUtils]: 9: Hoare triple {45493#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,166 INFO L290 TraceCheckUtils]: 10: Hoare triple {45493#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {45493#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:12,166 INFO L290 TraceCheckUtils]: 11: Hoare triple {45493#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {45492#false} is VALID [2022-02-21 04:23:12,166 INFO L290 TraceCheckUtils]: 12: Hoare triple {45492#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 13: Hoare triple {45492#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 14: Hoare triple {45492#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 15: Hoare triple {45492#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 16: Hoare triple {45492#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 17: Hoare triple {45492#false} assume !(0 == ~M_E~0); {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 18: Hoare triple {45492#false} assume !(0 == ~T1_E~0); {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 19: Hoare triple {45492#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 20: Hoare triple {45492#false} assume !(0 == ~T3_E~0); {45492#false} is VALID [2022-02-21 04:23:12,167 INFO L290 TraceCheckUtils]: 21: Hoare triple {45492#false} assume !(0 == ~T4_E~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 22: Hoare triple {45492#false} assume !(0 == ~T5_E~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 23: Hoare triple {45492#false} assume !(0 == ~T6_E~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 24: Hoare triple {45492#false} assume !(0 == ~T7_E~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 25: Hoare triple {45492#false} assume !(0 == ~T8_E~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 26: Hoare triple {45492#false} assume !(0 == ~T9_E~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 27: Hoare triple {45492#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 28: Hoare triple {45492#false} assume !(0 == ~T11_E~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 29: Hoare triple {45492#false} assume !(0 == ~E_M~0); {45492#false} is VALID [2022-02-21 04:23:12,168 INFO L290 TraceCheckUtils]: 30: Hoare triple {45492#false} assume !(0 == ~E_1~0); {45492#false} is VALID [2022-02-21 04:23:12,169 INFO L290 TraceCheckUtils]: 31: Hoare triple {45492#false} assume !(0 == ~E_2~0); {45492#false} is VALID [2022-02-21 04:23:12,169 INFO L290 TraceCheckUtils]: 32: Hoare triple {45492#false} assume !(0 == ~E_3~0); {45492#false} is VALID [2022-02-21 04:23:12,169 INFO L290 TraceCheckUtils]: 33: Hoare triple {45492#false} assume !(0 == ~E_4~0); {45492#false} is VALID [2022-02-21 04:23:12,169 INFO L290 TraceCheckUtils]: 34: Hoare triple {45492#false} assume !(0 == ~E_5~0); {45492#false} is VALID [2022-02-21 04:23:12,169 INFO L290 TraceCheckUtils]: 35: Hoare triple {45492#false} assume 0 == ~E_6~0;~E_6~0 := 1; {45492#false} is VALID [2022-02-21 04:23:12,169 INFO L290 TraceCheckUtils]: 36: Hoare triple {45492#false} assume !(0 == ~E_7~0); {45492#false} is VALID [2022-02-21 04:23:12,173 INFO L290 TraceCheckUtils]: 37: Hoare triple {45492#false} assume !(0 == ~E_8~0); {45492#false} is VALID [2022-02-21 04:23:12,174 INFO L290 TraceCheckUtils]: 38: Hoare triple {45492#false} assume !(0 == ~E_9~0); {45492#false} is VALID [2022-02-21 04:23:12,174 INFO L290 TraceCheckUtils]: 39: Hoare triple {45492#false} assume !(0 == ~E_10~0); {45492#false} is VALID [2022-02-21 04:23:12,174 INFO L290 TraceCheckUtils]: 40: Hoare triple {45492#false} assume !(0 == ~E_11~0); {45492#false} is VALID [2022-02-21 04:23:12,174 INFO L290 TraceCheckUtils]: 41: Hoare triple {45492#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {45492#false} is VALID [2022-02-21 04:23:12,174 INFO L290 TraceCheckUtils]: 42: Hoare triple {45492#false} assume 1 == ~m_pc~0; {45492#false} is VALID [2022-02-21 04:23:12,174 INFO L290 TraceCheckUtils]: 43: Hoare triple {45492#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 44: Hoare triple {45492#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 45: Hoare triple {45492#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 46: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp~1#1); {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 47: Hoare triple {45492#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 48: Hoare triple {45492#false} assume !(1 == ~t1_pc~0); {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 49: Hoare triple {45492#false} is_transmit1_triggered_~__retres1~1#1 := 0; {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 50: Hoare triple {45492#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 51: Hoare triple {45492#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {45492#false} is VALID [2022-02-21 04:23:12,175 INFO L290 TraceCheckUtils]: 52: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___0~0#1); {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 53: Hoare triple {45492#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 54: Hoare triple {45492#false} assume 1 == ~t2_pc~0; {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 55: Hoare triple {45492#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 56: Hoare triple {45492#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 57: Hoare triple {45492#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 58: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___1~0#1); {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 59: Hoare triple {45492#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {45492#false} is VALID [2022-02-21 04:23:12,176 INFO L290 TraceCheckUtils]: 60: Hoare triple {45492#false} assume !(1 == ~t3_pc~0); {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 61: Hoare triple {45492#false} is_transmit3_triggered_~__retres1~3#1 := 0; {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 62: Hoare triple {45492#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 63: Hoare triple {45492#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 64: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___2~0#1); {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 65: Hoare triple {45492#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 66: Hoare triple {45492#false} assume 1 == ~t4_pc~0; {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 67: Hoare triple {45492#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 68: Hoare triple {45492#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {45492#false} is VALID [2022-02-21 04:23:12,177 INFO L290 TraceCheckUtils]: 69: Hoare triple {45492#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 70: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___3~0#1); {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 71: Hoare triple {45492#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 72: Hoare triple {45492#false} assume 1 == ~t5_pc~0; {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 73: Hoare triple {45492#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 74: Hoare triple {45492#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 75: Hoare triple {45492#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 76: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___4~0#1); {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 77: Hoare triple {45492#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {45492#false} is VALID [2022-02-21 04:23:12,178 INFO L290 TraceCheckUtils]: 78: Hoare triple {45492#false} assume !(1 == ~t6_pc~0); {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 79: Hoare triple {45492#false} is_transmit6_triggered_~__retres1~6#1 := 0; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 80: Hoare triple {45492#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 81: Hoare triple {45492#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 82: Hoare triple {45492#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 83: Hoare triple {45492#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 84: Hoare triple {45492#false} assume 1 == ~t7_pc~0; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 85: Hoare triple {45492#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 86: Hoare triple {45492#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {45492#false} is VALID [2022-02-21 04:23:12,179 INFO L290 TraceCheckUtils]: 87: Hoare triple {45492#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 88: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___6~0#1); {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 89: Hoare triple {45492#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 90: Hoare triple {45492#false} assume !(1 == ~t8_pc~0); {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 91: Hoare triple {45492#false} is_transmit8_triggered_~__retres1~8#1 := 0; {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 92: Hoare triple {45492#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 93: Hoare triple {45492#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 94: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___7~0#1); {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 95: Hoare triple {45492#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {45492#false} is VALID [2022-02-21 04:23:12,180 INFO L290 TraceCheckUtils]: 96: Hoare triple {45492#false} assume 1 == ~t9_pc~0; {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 97: Hoare triple {45492#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 98: Hoare triple {45492#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 99: Hoare triple {45492#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 100: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___8~0#1); {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 101: Hoare triple {45492#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 102: Hoare triple {45492#false} assume !(1 == ~t10_pc~0); {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 103: Hoare triple {45492#false} is_transmit10_triggered_~__retres1~10#1 := 0; {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 104: Hoare triple {45492#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {45492#false} is VALID [2022-02-21 04:23:12,181 INFO L290 TraceCheckUtils]: 105: Hoare triple {45492#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 106: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___9~0#1); {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 107: Hoare triple {45492#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 108: Hoare triple {45492#false} assume 1 == ~t11_pc~0; {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 109: Hoare triple {45492#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 110: Hoare triple {45492#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 111: Hoare triple {45492#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 112: Hoare triple {45492#false} assume !(0 != activate_threads_~tmp___10~0#1); {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 113: Hoare triple {45492#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45492#false} is VALID [2022-02-21 04:23:12,182 INFO L290 TraceCheckUtils]: 114: Hoare triple {45492#false} assume !(1 == ~M_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 115: Hoare triple {45492#false} assume !(1 == ~T1_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 116: Hoare triple {45492#false} assume !(1 == ~T2_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 117: Hoare triple {45492#false} assume !(1 == ~T3_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 118: Hoare triple {45492#false} assume !(1 == ~T4_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 119: Hoare triple {45492#false} assume !(1 == ~T5_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 120: Hoare triple {45492#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 121: Hoare triple {45492#false} assume !(1 == ~T7_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 122: Hoare triple {45492#false} assume !(1 == ~T8_E~0); {45492#false} is VALID [2022-02-21 04:23:12,183 INFO L290 TraceCheckUtils]: 123: Hoare triple {45492#false} assume !(1 == ~T9_E~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 124: Hoare triple {45492#false} assume !(1 == ~T10_E~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 125: Hoare triple {45492#false} assume !(1 == ~T11_E~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 126: Hoare triple {45492#false} assume !(1 == ~E_M~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 127: Hoare triple {45492#false} assume !(1 == ~E_1~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 128: Hoare triple {45492#false} assume 1 == ~E_2~0;~E_2~0 := 2; {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 129: Hoare triple {45492#false} assume !(1 == ~E_3~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 130: Hoare triple {45492#false} assume !(1 == ~E_4~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 131: Hoare triple {45492#false} assume !(1 == ~E_5~0); {45492#false} is VALID [2022-02-21 04:23:12,184 INFO L290 TraceCheckUtils]: 132: Hoare triple {45492#false} assume !(1 == ~E_6~0); {45492#false} is VALID [2022-02-21 04:23:12,185 INFO L290 TraceCheckUtils]: 133: Hoare triple {45492#false} assume !(1 == ~E_7~0); {45492#false} is VALID [2022-02-21 04:23:12,185 INFO L290 TraceCheckUtils]: 134: Hoare triple {45492#false} assume !(1 == ~E_8~0); {45492#false} is VALID [2022-02-21 04:23:12,185 INFO L290 TraceCheckUtils]: 135: Hoare triple {45492#false} assume !(1 == ~E_9~0); {45492#false} is VALID [2022-02-21 04:23:12,185 INFO L290 TraceCheckUtils]: 136: Hoare triple {45492#false} assume 1 == ~E_10~0;~E_10~0 := 2; {45492#false} is VALID [2022-02-21 04:23:12,185 INFO L290 TraceCheckUtils]: 137: Hoare triple {45492#false} assume !(1 == ~E_11~0); {45492#false} is VALID [2022-02-21 04:23:12,185 INFO L290 TraceCheckUtils]: 138: Hoare triple {45492#false} assume { :end_inline_reset_delta_events } true; {45492#false} is VALID [2022-02-21 04:23:12,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:12,186 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:12,186 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726217168] [2022-02-21 04:23:12,186 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726217168] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:12,187 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:12,187 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:12,187 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512260568] [2022-02-21 04:23:12,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:12,188 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:12,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:12,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1977169166, now seen corresponding path program 1 times [2022-02-21 04:23:12,188 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:12,191 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698435504] [2022-02-21 04:23:12,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:12,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:12,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:12,222 INFO L290 TraceCheckUtils]: 0: Hoare triple {45494#true} assume !false; {45494#true} is VALID [2022-02-21 04:23:12,223 INFO L290 TraceCheckUtils]: 1: Hoare triple {45494#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {45494#true} is VALID [2022-02-21 04:23:12,223 INFO L290 TraceCheckUtils]: 2: Hoare triple {45494#true} assume !false; {45494#true} is VALID [2022-02-21 04:23:12,223 INFO L290 TraceCheckUtils]: 3: Hoare triple {45494#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {45494#true} is VALID [2022-02-21 04:23:12,223 INFO L290 TraceCheckUtils]: 4: Hoare triple {45494#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {45494#true} is VALID [2022-02-21 04:23:12,223 INFO L290 TraceCheckUtils]: 5: Hoare triple {45494#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {45494#true} is VALID [2022-02-21 04:23:12,223 INFO L290 TraceCheckUtils]: 6: Hoare triple {45494#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {45494#true} is VALID [2022-02-21 04:23:12,223 INFO L290 TraceCheckUtils]: 7: Hoare triple {45494#true} assume !(0 != eval_~tmp~0#1); {45494#true} is VALID [2022-02-21 04:23:12,224 INFO L290 TraceCheckUtils]: 8: Hoare triple {45494#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {45494#true} is VALID [2022-02-21 04:23:12,224 INFO L290 TraceCheckUtils]: 9: Hoare triple {45494#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {45494#true} is VALID [2022-02-21 04:23:12,224 INFO L290 TraceCheckUtils]: 10: Hoare triple {45494#true} assume 0 == ~M_E~0;~M_E~0 := 1; {45494#true} is VALID [2022-02-21 04:23:12,224 INFO L290 TraceCheckUtils]: 11: Hoare triple {45494#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {45494#true} is VALID [2022-02-21 04:23:12,224 INFO L290 TraceCheckUtils]: 12: Hoare triple {45494#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,225 INFO L290 TraceCheckUtils]: 13: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,225 INFO L290 TraceCheckUtils]: 14: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,225 INFO L290 TraceCheckUtils]: 15: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,225 INFO L290 TraceCheckUtils]: 16: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,226 INFO L290 TraceCheckUtils]: 17: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,226 INFO L290 TraceCheckUtils]: 18: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,226 INFO L290 TraceCheckUtils]: 19: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,226 INFO L290 TraceCheckUtils]: 20: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,226 INFO L290 TraceCheckUtils]: 21: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,227 INFO L290 TraceCheckUtils]: 22: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,227 INFO L290 TraceCheckUtils]: 23: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,227 INFO L290 TraceCheckUtils]: 24: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,227 INFO L290 TraceCheckUtils]: 25: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,228 INFO L290 TraceCheckUtils]: 26: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,228 INFO L290 TraceCheckUtils]: 27: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,228 INFO L290 TraceCheckUtils]: 28: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,228 INFO L290 TraceCheckUtils]: 29: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,229 INFO L290 TraceCheckUtils]: 30: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,229 INFO L290 TraceCheckUtils]: 31: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,229 INFO L290 TraceCheckUtils]: 32: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,229 INFO L290 TraceCheckUtils]: 33: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,230 INFO L290 TraceCheckUtils]: 34: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,230 INFO L290 TraceCheckUtils]: 35: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,230 INFO L290 TraceCheckUtils]: 36: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,230 INFO L290 TraceCheckUtils]: 37: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,231 INFO L290 TraceCheckUtils]: 38: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,231 INFO L290 TraceCheckUtils]: 39: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,231 INFO L290 TraceCheckUtils]: 40: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,231 INFO L290 TraceCheckUtils]: 41: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,232 INFO L290 TraceCheckUtils]: 42: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,232 INFO L290 TraceCheckUtils]: 43: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,232 INFO L290 TraceCheckUtils]: 44: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,232 INFO L290 TraceCheckUtils]: 45: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,233 INFO L290 TraceCheckUtils]: 46: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,233 INFO L290 TraceCheckUtils]: 47: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,233 INFO L290 TraceCheckUtils]: 48: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,233 INFO L290 TraceCheckUtils]: 49: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,234 INFO L290 TraceCheckUtils]: 50: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,234 INFO L290 TraceCheckUtils]: 51: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,234 INFO L290 TraceCheckUtils]: 52: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,234 INFO L290 TraceCheckUtils]: 53: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,234 INFO L290 TraceCheckUtils]: 54: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,235 INFO L290 TraceCheckUtils]: 55: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,235 INFO L290 TraceCheckUtils]: 56: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,235 INFO L290 TraceCheckUtils]: 57: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,235 INFO L290 TraceCheckUtils]: 58: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,236 INFO L290 TraceCheckUtils]: 59: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,236 INFO L290 TraceCheckUtils]: 60: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,236 INFO L290 TraceCheckUtils]: 61: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,236 INFO L290 TraceCheckUtils]: 62: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,237 INFO L290 TraceCheckUtils]: 63: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,237 INFO L290 TraceCheckUtils]: 64: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,237 INFO L290 TraceCheckUtils]: 65: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,237 INFO L290 TraceCheckUtils]: 66: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,238 INFO L290 TraceCheckUtils]: 67: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,238 INFO L290 TraceCheckUtils]: 68: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,238 INFO L290 TraceCheckUtils]: 69: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,238 INFO L290 TraceCheckUtils]: 70: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,239 INFO L290 TraceCheckUtils]: 71: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,239 INFO L290 TraceCheckUtils]: 72: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,239 INFO L290 TraceCheckUtils]: 73: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,239 INFO L290 TraceCheckUtils]: 74: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,240 INFO L290 TraceCheckUtils]: 75: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,240 INFO L290 TraceCheckUtils]: 76: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,240 INFO L290 TraceCheckUtils]: 77: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,240 INFO L290 TraceCheckUtils]: 78: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,240 INFO L290 TraceCheckUtils]: 79: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,241 INFO L290 TraceCheckUtils]: 80: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,241 INFO L290 TraceCheckUtils]: 81: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,241 INFO L290 TraceCheckUtils]: 82: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,241 INFO L290 TraceCheckUtils]: 83: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,242 INFO L290 TraceCheckUtils]: 84: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,242 INFO L290 TraceCheckUtils]: 85: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,242 INFO L290 TraceCheckUtils]: 86: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,242 INFO L290 TraceCheckUtils]: 87: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,243 INFO L290 TraceCheckUtils]: 88: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,243 INFO L290 TraceCheckUtils]: 89: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t9_pc~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,243 INFO L290 TraceCheckUtils]: 90: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,243 INFO L290 TraceCheckUtils]: 91: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,244 INFO L290 TraceCheckUtils]: 92: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,244 INFO L290 TraceCheckUtils]: 93: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,244 INFO L290 TraceCheckUtils]: 94: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,244 INFO L290 TraceCheckUtils]: 95: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,245 INFO L290 TraceCheckUtils]: 96: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,245 INFO L290 TraceCheckUtils]: 97: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,245 INFO L290 TraceCheckUtils]: 98: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,245 INFO L290 TraceCheckUtils]: 99: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,246 INFO L290 TraceCheckUtils]: 100: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,246 INFO L290 TraceCheckUtils]: 101: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,246 INFO L290 TraceCheckUtils]: 102: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,246 INFO L290 TraceCheckUtils]: 103: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,247 INFO L290 TraceCheckUtils]: 104: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,247 INFO L290 TraceCheckUtils]: 105: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,247 INFO L290 TraceCheckUtils]: 106: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,247 INFO L290 TraceCheckUtils]: 107: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 108: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {45496#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 109: Hoare triple {45496#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {45495#false} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 110: Hoare triple {45495#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 111: Hoare triple {45495#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 112: Hoare triple {45495#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 113: Hoare triple {45495#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 114: Hoare triple {45495#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,248 INFO L290 TraceCheckUtils]: 115: Hoare triple {45495#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 116: Hoare triple {45495#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 117: Hoare triple {45495#false} assume !(1 == ~T10_E~0); {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 118: Hoare triple {45495#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 119: Hoare triple {45495#false} assume 1 == ~E_M~0;~E_M~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 120: Hoare triple {45495#false} assume 1 == ~E_1~0;~E_1~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 121: Hoare triple {45495#false} assume 1 == ~E_2~0;~E_2~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 122: Hoare triple {45495#false} assume 1 == ~E_3~0;~E_3~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 123: Hoare triple {45495#false} assume 1 == ~E_4~0;~E_4~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,249 INFO L290 TraceCheckUtils]: 124: Hoare triple {45495#false} assume 1 == ~E_5~0;~E_5~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 125: Hoare triple {45495#false} assume !(1 == ~E_6~0); {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 126: Hoare triple {45495#false} assume 1 == ~E_7~0;~E_7~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 127: Hoare triple {45495#false} assume 1 == ~E_8~0;~E_8~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 128: Hoare triple {45495#false} assume 1 == ~E_9~0;~E_9~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 129: Hoare triple {45495#false} assume 1 == ~E_10~0;~E_10~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 130: Hoare triple {45495#false} assume 1 == ~E_11~0;~E_11~0 := 2; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 131: Hoare triple {45495#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 132: Hoare triple {45495#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {45495#false} is VALID [2022-02-21 04:23:12,250 INFO L290 TraceCheckUtils]: 133: Hoare triple {45495#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 134: Hoare triple {45495#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 135: Hoare triple {45495#false} assume !(0 == start_simulation_~tmp~3#1); {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 136: Hoare triple {45495#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 137: Hoare triple {45495#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 138: Hoare triple {45495#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 139: Hoare triple {45495#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 140: Hoare triple {45495#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 141: Hoare triple {45495#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {45495#false} is VALID [2022-02-21 04:23:12,251 INFO L290 TraceCheckUtils]: 142: Hoare triple {45495#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {45495#false} is VALID [2022-02-21 04:23:12,252 INFO L290 TraceCheckUtils]: 143: Hoare triple {45495#false} assume !(0 != start_simulation_~tmp___0~1#1); {45495#false} is VALID [2022-02-21 04:23:12,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:12,252 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:12,254 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698435504] [2022-02-21 04:23:12,263 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698435504] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:12,263 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:12,263 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:12,263 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467863365] [2022-02-21 04:23:12,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:12,264 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:12,264 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:12,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:12,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:12,264 INFO L87 Difference]: Start difference. First operand 1566 states and 2319 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,274 INFO L93 Difference]: Finished difference Result 1566 states and 2318 transitions. [2022-02-21 04:23:13,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:13,274 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,352 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:13,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:13,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2318 transitions. [2022-02-21 04:23:13,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:13,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:13,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:13,467 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-02-21 04:23:13,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:13,480 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:13,482 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2318 transitions. Second operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,483 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2318 transitions. Second operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,484 INFO L87 Difference]: Start difference. First operand 1566 states and 2318 transitions. Second operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,536 INFO L93 Difference]: Finished difference Result 1566 states and 2318 transitions. [2022-02-21 04:23:13,536 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,537 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:13,537 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:13,539 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,540 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,593 INFO L93 Difference]: Finished difference Result 1566 states and 2318 transitions. [2022-02-21 04:23:13,593 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,594 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:13,594 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:13,594 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:13,594 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:13,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2318 transitions. [2022-02-21 04:23:13,648 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-02-21 04:23:13,648 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-02-21 04:23:13,648 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:13,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2318 transitions. [2022-02-21 04:23:13,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:13,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:13,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:13,652 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:13,652 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:13,652 INFO L791 eck$LassoCheckResult]: Stem: 47798#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 47799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48527#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48528#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47301#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 47302#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48537#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48502#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48503#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47650#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47651#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48057#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48475#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 47562#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47563#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 47448#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 47449#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48401#L1109 assume !(0 == ~M_E~0); 48423#L1109-2 assume !(0 == ~T1_E~0); 47455#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47456#L1119-1 assume !(0 == ~T3_E~0); 48479#L1124-1 assume !(0 == ~T4_E~0); 47116#L1129-1 assume !(0 == ~T5_E~0); 47117#L1134-1 assume !(0 == ~T6_E~0); 47730#L1139-1 assume !(0 == ~T7_E~0); 48407#L1144-1 assume !(0 == ~T8_E~0); 48279#L1149-1 assume !(0 == ~T9_E~0); 47223#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47224#L1159-1 assume !(0 == ~T11_E~0); 48265#L1164-1 assume !(0 == ~E_M~0); 47616#L1169-1 assume !(0 == ~E_1~0); 47505#L1174-1 assume !(0 == ~E_2~0); 47378#L1179-1 assume !(0 == ~E_3~0); 47305#L1184-1 assume !(0 == ~E_4~0); 47306#L1189-1 assume !(0 == ~E_5~0); 47337#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 47424#L1199-1 assume !(0 == ~E_7~0); 48287#L1204-1 assume !(0 == ~E_8~0); 48223#L1209-1 assume !(0 == ~E_9~0); 48224#L1214-1 assume !(0 == ~E_10~0); 48549#L1219-1 assume !(0 == ~E_11~0); 48622#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47633#L544 assume 1 == ~m_pc~0; 47634#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48466#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48294#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47267#L1379 assume !(0 != activate_threads_~tmp~1#1); 47268#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48040#L563 assume !(1 == ~t1_pc~0); 47840#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47126#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47127#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48163#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 47122#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47123#L582 assume 1 == ~t2_pc~0; 47818#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48173#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48174#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48278#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 47155#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47156#L601 assume !(1 == ~t3_pc~0); 47834#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47833#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48467#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48209#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 48210#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48153#L620 assume 1 == ~t4_pc~0; 47136#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47137#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47698#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47699#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 48054#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48241#L639 assume 1 == ~t5_pc~0; 48124#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47428#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47429#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48075#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 48076#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48005#L658 assume !(1 == ~t6_pc~0); 47630#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47631#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48199#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48529#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48213#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47468#L677 assume 1 == ~t7_pc~0; 47469#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47371#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48372#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48496#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 48497#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48568#L696 assume !(1 == ~t8_pc~0); 47688#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47689#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48536#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48557#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 48603#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48107#L715 assume 1 == ~t9_pc~0; 48108#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47778#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47686#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47687#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 48096#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48368#L734 assume !(1 == ~t10_pc~0); 48369#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47588#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47589#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47607#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 48312#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47664#L753 assume 1 == ~t11_pc~0; 47665#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48218#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47773#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47774#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 47923#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47980#L1237 assume !(1 == ~M_E~0); 47981#L1237-2 assume !(1 == ~T1_E~0); 48593#L1242-1 assume !(1 == ~T2_E~0); 47744#L1247-1 assume !(1 == ~T3_E~0); 47745#L1252-1 assume !(1 == ~T4_E~0); 47528#L1257-1 assume !(1 == ~T5_E~0); 47529#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48384#L1267-1 assume !(1 == ~T7_E~0); 48489#L1272-1 assume !(1 == ~T8_E~0); 47827#L1277-1 assume !(1 == ~T9_E~0); 47828#L1282-1 assume !(1 == ~T10_E~0); 48250#L1287-1 assume !(1 == ~T11_E~0); 48251#L1292-1 assume !(1 == ~E_M~0); 48212#L1297-1 assume !(1 == ~E_1~0); 47659#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 47660#L1307-1 assume !(1 == ~E_3~0); 48482#L1312-1 assume !(1 == ~E_4~0); 47870#L1317-1 assume !(1 == ~E_5~0); 47871#L1322-1 assume !(1 == ~E_6~0); 47603#L1327-1 assume !(1 == ~E_7~0); 47604#L1332-1 assume !(1 == ~E_8~0); 48162#L1337-1 assume !(1 == ~E_9~0); 48099#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 48100#L1347-1 assume !(1 == ~E_11~0); 48481#L1352-1 assume { :end_inline_reset_delta_events } true; 48371#L1678-2 [2022-02-21 04:23:13,652 INFO L793 eck$LassoCheckResult]: Loop: 48371#L1678-2 assume !false; 48154#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48155#L1084 assume !false; 47938#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47939#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47242#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48256#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 47168#L925 assume !(0 != eval_~tmp~0#1); 47170#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47284#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47285#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47139#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47140#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48214#L1119-3 assume !(0 == ~T3_E~0); 48215#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48236#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48237#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48415#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48473#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47643#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47644#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47879#L1159-3 assume !(0 == ~T11_E~0); 47880#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48150#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48151#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48201#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48202#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48357#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48034#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47401#L1199-3 assume !(0 == ~E_7~0); 47402#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47625#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47087#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47088#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47786#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47787#L544-39 assume !(1 == ~m_pc~0); 47068#L544-41 is_master_triggered_~__retres1~0#1 := 0; 47069#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47319#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47320#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 47476#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48344#L563-39 assume !(1 == ~t1_pc~0); 47218#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 47219#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48118#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48119#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48616#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48459#L582-39 assume 1 == ~t2_pc~0; 47542#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47544#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48164#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48165#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47312#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47099#L601-39 assume 1 == ~t3_pc~0; 47100#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47150#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48308#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48444#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48348#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48000#L620-39 assume !(1 == ~t4_pc~0); 48001#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 48198#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48406#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48321#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48322#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48627#L639-39 assume 1 == ~t5_pc~0; 48434#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47748#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47325#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47128#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47129#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48037#L658-39 assume 1 == ~t6_pc~0; 48019#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48020#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47078#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47079#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48194#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48195#L677-39 assume !(1 == ~t7_pc~0); 47825#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 47303#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47304#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47359#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 47360#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47925#L696-39 assume 1 == ~t8_pc~0; 47890#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47770#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47771#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48066#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48030#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47905#L715-39 assume 1 == ~t9_pc~0; 47104#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47105#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48314#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48628#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48243#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48244#L734-39 assume 1 == ~t10_pc~0; 48169#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47615#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47926#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47257#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47258#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48506#L753-39 assume !(1 == ~t11_pc~0); 47177#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 47178#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48470#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47895#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47896#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47997#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47998#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48268#L1242-3 assume !(1 == ~T2_E~0); 48269#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48488#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48188#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48189#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48471#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48512#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48600#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47329#L1282-3 assume !(1 == ~T10_E~0); 47330#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47239#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47240#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48377#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48378#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48566#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48624#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48290#L1322-3 assume !(1 == ~E_6~0); 48291#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47298#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47273#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47274#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47966#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48094#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 48095#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47221#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 47486#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 48200#L1697 assume !(0 == start_simulation_~tmp~3#1); 47987#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47988#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47345#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48110#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 48111#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48060#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47657#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 47658#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 48371#L1678-2 [2022-02-21 04:23:13,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:13,653 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2022-02-21 04:23:13,653 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:13,653 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980171902] [2022-02-21 04:23:13,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:13,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:13,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:13,671 INFO L290 TraceCheckUtils]: 0: Hoare triple {51764#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {51764#true} is VALID [2022-02-21 04:23:13,671 INFO L290 TraceCheckUtils]: 1: Hoare triple {51764#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,671 INFO L290 TraceCheckUtils]: 2: Hoare triple {51766#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,672 INFO L290 TraceCheckUtils]: 3: Hoare triple {51766#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,672 INFO L290 TraceCheckUtils]: 4: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,672 INFO L290 TraceCheckUtils]: 5: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,672 INFO L290 TraceCheckUtils]: 6: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,673 INFO L290 TraceCheckUtils]: 7: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,673 INFO L290 TraceCheckUtils]: 8: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,673 INFO L290 TraceCheckUtils]: 9: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,673 INFO L290 TraceCheckUtils]: 10: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,674 INFO L290 TraceCheckUtils]: 11: Hoare triple {51766#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {51766#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:13,674 INFO L290 TraceCheckUtils]: 12: Hoare triple {51766#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {51765#false} is VALID [2022-02-21 04:23:13,674 INFO L290 TraceCheckUtils]: 13: Hoare triple {51765#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {51765#false} is VALID [2022-02-21 04:23:13,674 INFO L290 TraceCheckUtils]: 14: Hoare triple {51765#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {51765#false} is VALID [2022-02-21 04:23:13,674 INFO L290 TraceCheckUtils]: 15: Hoare triple {51765#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {51765#false} is VALID [2022-02-21 04:23:13,674 INFO L290 TraceCheckUtils]: 16: Hoare triple {51765#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {51765#false} is VALID [2022-02-21 04:23:13,674 INFO L290 TraceCheckUtils]: 17: Hoare triple {51765#false} assume !(0 == ~M_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 18: Hoare triple {51765#false} assume !(0 == ~T1_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 19: Hoare triple {51765#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 20: Hoare triple {51765#false} assume !(0 == ~T3_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 21: Hoare triple {51765#false} assume !(0 == ~T4_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 22: Hoare triple {51765#false} assume !(0 == ~T5_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 23: Hoare triple {51765#false} assume !(0 == ~T6_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 24: Hoare triple {51765#false} assume !(0 == ~T7_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 25: Hoare triple {51765#false} assume !(0 == ~T8_E~0); {51765#false} is VALID [2022-02-21 04:23:13,675 INFO L290 TraceCheckUtils]: 26: Hoare triple {51765#false} assume !(0 == ~T9_E~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 27: Hoare triple {51765#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 28: Hoare triple {51765#false} assume !(0 == ~T11_E~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 29: Hoare triple {51765#false} assume !(0 == ~E_M~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 30: Hoare triple {51765#false} assume !(0 == ~E_1~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 31: Hoare triple {51765#false} assume !(0 == ~E_2~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 32: Hoare triple {51765#false} assume !(0 == ~E_3~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 33: Hoare triple {51765#false} assume !(0 == ~E_4~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 34: Hoare triple {51765#false} assume !(0 == ~E_5~0); {51765#false} is VALID [2022-02-21 04:23:13,676 INFO L290 TraceCheckUtils]: 35: Hoare triple {51765#false} assume 0 == ~E_6~0;~E_6~0 := 1; {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 36: Hoare triple {51765#false} assume !(0 == ~E_7~0); {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 37: Hoare triple {51765#false} assume !(0 == ~E_8~0); {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 38: Hoare triple {51765#false} assume !(0 == ~E_9~0); {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 39: Hoare triple {51765#false} assume !(0 == ~E_10~0); {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 40: Hoare triple {51765#false} assume !(0 == ~E_11~0); {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 41: Hoare triple {51765#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 42: Hoare triple {51765#false} assume 1 == ~m_pc~0; {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 43: Hoare triple {51765#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {51765#false} is VALID [2022-02-21 04:23:13,677 INFO L290 TraceCheckUtils]: 44: Hoare triple {51765#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 45: Hoare triple {51765#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 46: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp~1#1); {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 47: Hoare triple {51765#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 48: Hoare triple {51765#false} assume !(1 == ~t1_pc~0); {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 49: Hoare triple {51765#false} is_transmit1_triggered_~__retres1~1#1 := 0; {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 50: Hoare triple {51765#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 51: Hoare triple {51765#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 52: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___0~0#1); {51765#false} is VALID [2022-02-21 04:23:13,678 INFO L290 TraceCheckUtils]: 53: Hoare triple {51765#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 54: Hoare triple {51765#false} assume 1 == ~t2_pc~0; {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 55: Hoare triple {51765#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 56: Hoare triple {51765#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 57: Hoare triple {51765#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 58: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___1~0#1); {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 59: Hoare triple {51765#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 60: Hoare triple {51765#false} assume !(1 == ~t3_pc~0); {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 61: Hoare triple {51765#false} is_transmit3_triggered_~__retres1~3#1 := 0; {51765#false} is VALID [2022-02-21 04:23:13,679 INFO L290 TraceCheckUtils]: 62: Hoare triple {51765#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 63: Hoare triple {51765#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 64: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___2~0#1); {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 65: Hoare triple {51765#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 66: Hoare triple {51765#false} assume 1 == ~t4_pc~0; {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 67: Hoare triple {51765#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 68: Hoare triple {51765#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 69: Hoare triple {51765#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 70: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___3~0#1); {51765#false} is VALID [2022-02-21 04:23:13,680 INFO L290 TraceCheckUtils]: 71: Hoare triple {51765#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 72: Hoare triple {51765#false} assume 1 == ~t5_pc~0; {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 73: Hoare triple {51765#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 74: Hoare triple {51765#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 75: Hoare triple {51765#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 76: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___4~0#1); {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 77: Hoare triple {51765#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 78: Hoare triple {51765#false} assume !(1 == ~t6_pc~0); {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 79: Hoare triple {51765#false} is_transmit6_triggered_~__retres1~6#1 := 0; {51765#false} is VALID [2022-02-21 04:23:13,681 INFO L290 TraceCheckUtils]: 80: Hoare triple {51765#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 81: Hoare triple {51765#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 82: Hoare triple {51765#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 83: Hoare triple {51765#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 84: Hoare triple {51765#false} assume 1 == ~t7_pc~0; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 85: Hoare triple {51765#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 86: Hoare triple {51765#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 87: Hoare triple {51765#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 88: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___6~0#1); {51765#false} is VALID [2022-02-21 04:23:13,682 INFO L290 TraceCheckUtils]: 89: Hoare triple {51765#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 90: Hoare triple {51765#false} assume !(1 == ~t8_pc~0); {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 91: Hoare triple {51765#false} is_transmit8_triggered_~__retres1~8#1 := 0; {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 92: Hoare triple {51765#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 93: Hoare triple {51765#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 94: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___7~0#1); {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 95: Hoare triple {51765#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 96: Hoare triple {51765#false} assume 1 == ~t9_pc~0; {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 97: Hoare triple {51765#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51765#false} is VALID [2022-02-21 04:23:13,683 INFO L290 TraceCheckUtils]: 98: Hoare triple {51765#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 99: Hoare triple {51765#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 100: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___8~0#1); {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 101: Hoare triple {51765#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 102: Hoare triple {51765#false} assume !(1 == ~t10_pc~0); {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 103: Hoare triple {51765#false} is_transmit10_triggered_~__retres1~10#1 := 0; {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 104: Hoare triple {51765#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 105: Hoare triple {51765#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 106: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___9~0#1); {51765#false} is VALID [2022-02-21 04:23:13,684 INFO L290 TraceCheckUtils]: 107: Hoare triple {51765#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 108: Hoare triple {51765#false} assume 1 == ~t11_pc~0; {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 109: Hoare triple {51765#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 110: Hoare triple {51765#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 111: Hoare triple {51765#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 112: Hoare triple {51765#false} assume !(0 != activate_threads_~tmp___10~0#1); {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 113: Hoare triple {51765#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 114: Hoare triple {51765#false} assume !(1 == ~M_E~0); {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 115: Hoare triple {51765#false} assume !(1 == ~T1_E~0); {51765#false} is VALID [2022-02-21 04:23:13,685 INFO L290 TraceCheckUtils]: 116: Hoare triple {51765#false} assume !(1 == ~T2_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 117: Hoare triple {51765#false} assume !(1 == ~T3_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 118: Hoare triple {51765#false} assume !(1 == ~T4_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 119: Hoare triple {51765#false} assume !(1 == ~T5_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 120: Hoare triple {51765#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 121: Hoare triple {51765#false} assume !(1 == ~T7_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 122: Hoare triple {51765#false} assume !(1 == ~T8_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 123: Hoare triple {51765#false} assume !(1 == ~T9_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 124: Hoare triple {51765#false} assume !(1 == ~T10_E~0); {51765#false} is VALID [2022-02-21 04:23:13,686 INFO L290 TraceCheckUtils]: 125: Hoare triple {51765#false} assume !(1 == ~T11_E~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 126: Hoare triple {51765#false} assume !(1 == ~E_M~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 127: Hoare triple {51765#false} assume !(1 == ~E_1~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 128: Hoare triple {51765#false} assume 1 == ~E_2~0;~E_2~0 := 2; {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 129: Hoare triple {51765#false} assume !(1 == ~E_3~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 130: Hoare triple {51765#false} assume !(1 == ~E_4~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 131: Hoare triple {51765#false} assume !(1 == ~E_5~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 132: Hoare triple {51765#false} assume !(1 == ~E_6~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 133: Hoare triple {51765#false} assume !(1 == ~E_7~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 134: Hoare triple {51765#false} assume !(1 == ~E_8~0); {51765#false} is VALID [2022-02-21 04:23:13,687 INFO L290 TraceCheckUtils]: 135: Hoare triple {51765#false} assume !(1 == ~E_9~0); {51765#false} is VALID [2022-02-21 04:23:13,688 INFO L290 TraceCheckUtils]: 136: Hoare triple {51765#false} assume 1 == ~E_10~0;~E_10~0 := 2; {51765#false} is VALID [2022-02-21 04:23:13,688 INFO L290 TraceCheckUtils]: 137: Hoare triple {51765#false} assume !(1 == ~E_11~0); {51765#false} is VALID [2022-02-21 04:23:13,688 INFO L290 TraceCheckUtils]: 138: Hoare triple {51765#false} assume { :end_inline_reset_delta_events } true; {51765#false} is VALID [2022-02-21 04:23:13,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:13,688 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:13,688 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980171902] [2022-02-21 04:23:13,689 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1980171902] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:13,689 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:13,689 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:13,689 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474544232] [2022-02-21 04:23:13,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:13,689 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:13,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:13,690 INFO L85 PathProgramCache]: Analyzing trace with hash -1209669491, now seen corresponding path program 1 times [2022-02-21 04:23:13,690 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:13,690 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303419595] [2022-02-21 04:23:13,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:13,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:13,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:13,713 INFO L290 TraceCheckUtils]: 0: Hoare triple {51767#true} assume !false; {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 1: Hoare triple {51767#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 2: Hoare triple {51767#true} assume !false; {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 3: Hoare triple {51767#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 4: Hoare triple {51767#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 5: Hoare triple {51767#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 6: Hoare triple {51767#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 7: Hoare triple {51767#true} assume !(0 != eval_~tmp~0#1); {51767#true} is VALID [2022-02-21 04:23:13,714 INFO L290 TraceCheckUtils]: 8: Hoare triple {51767#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {51767#true} is VALID [2022-02-21 04:23:13,715 INFO L290 TraceCheckUtils]: 9: Hoare triple {51767#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {51767#true} is VALID [2022-02-21 04:23:13,715 INFO L290 TraceCheckUtils]: 10: Hoare triple {51767#true} assume 0 == ~M_E~0;~M_E~0 := 1; {51767#true} is VALID [2022-02-21 04:23:13,715 INFO L290 TraceCheckUtils]: 11: Hoare triple {51767#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {51767#true} is VALID [2022-02-21 04:23:13,715 INFO L290 TraceCheckUtils]: 12: Hoare triple {51767#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,715 INFO L290 TraceCheckUtils]: 13: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,716 INFO L290 TraceCheckUtils]: 14: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,716 INFO L290 TraceCheckUtils]: 15: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,716 INFO L290 TraceCheckUtils]: 16: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,716 INFO L290 TraceCheckUtils]: 17: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,717 INFO L290 TraceCheckUtils]: 18: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,717 INFO L290 TraceCheckUtils]: 19: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,717 INFO L290 TraceCheckUtils]: 20: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,717 INFO L290 TraceCheckUtils]: 21: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,718 INFO L290 TraceCheckUtils]: 22: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,718 INFO L290 TraceCheckUtils]: 23: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,718 INFO L290 TraceCheckUtils]: 24: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,718 INFO L290 TraceCheckUtils]: 25: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,719 INFO L290 TraceCheckUtils]: 26: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,719 INFO L290 TraceCheckUtils]: 27: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,719 INFO L290 TraceCheckUtils]: 28: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,719 INFO L290 TraceCheckUtils]: 29: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,720 INFO L290 TraceCheckUtils]: 30: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,720 INFO L290 TraceCheckUtils]: 31: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,720 INFO L290 TraceCheckUtils]: 32: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,720 INFO L290 TraceCheckUtils]: 33: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,721 INFO L290 TraceCheckUtils]: 34: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,721 INFO L290 TraceCheckUtils]: 35: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,721 INFO L290 TraceCheckUtils]: 36: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,721 INFO L290 TraceCheckUtils]: 37: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,722 INFO L290 TraceCheckUtils]: 38: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,722 INFO L290 TraceCheckUtils]: 39: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,722 INFO L290 TraceCheckUtils]: 40: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,722 INFO L290 TraceCheckUtils]: 41: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,723 INFO L290 TraceCheckUtils]: 42: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,723 INFO L290 TraceCheckUtils]: 43: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,723 INFO L290 TraceCheckUtils]: 44: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,723 INFO L290 TraceCheckUtils]: 45: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,724 INFO L290 TraceCheckUtils]: 46: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,724 INFO L290 TraceCheckUtils]: 47: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,724 INFO L290 TraceCheckUtils]: 48: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,724 INFO L290 TraceCheckUtils]: 49: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,725 INFO L290 TraceCheckUtils]: 50: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,725 INFO L290 TraceCheckUtils]: 51: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,725 INFO L290 TraceCheckUtils]: 52: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,725 INFO L290 TraceCheckUtils]: 53: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,726 INFO L290 TraceCheckUtils]: 54: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,726 INFO L290 TraceCheckUtils]: 55: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,726 INFO L290 TraceCheckUtils]: 56: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,726 INFO L290 TraceCheckUtils]: 57: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,726 INFO L290 TraceCheckUtils]: 58: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,727 INFO L290 TraceCheckUtils]: 59: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,727 INFO L290 TraceCheckUtils]: 60: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,727 INFO L290 TraceCheckUtils]: 61: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,727 INFO L290 TraceCheckUtils]: 62: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,728 INFO L290 TraceCheckUtils]: 63: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,728 INFO L290 TraceCheckUtils]: 64: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,728 INFO L290 TraceCheckUtils]: 65: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,728 INFO L290 TraceCheckUtils]: 66: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,729 INFO L290 TraceCheckUtils]: 67: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,729 INFO L290 TraceCheckUtils]: 68: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,729 INFO L290 TraceCheckUtils]: 69: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,729 INFO L290 TraceCheckUtils]: 70: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,730 INFO L290 TraceCheckUtils]: 71: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,730 INFO L290 TraceCheckUtils]: 72: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,730 INFO L290 TraceCheckUtils]: 73: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,730 INFO L290 TraceCheckUtils]: 74: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,731 INFO L290 TraceCheckUtils]: 75: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,731 INFO L290 TraceCheckUtils]: 76: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,731 INFO L290 TraceCheckUtils]: 77: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,731 INFO L290 TraceCheckUtils]: 78: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,732 INFO L290 TraceCheckUtils]: 79: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,732 INFO L290 TraceCheckUtils]: 80: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,732 INFO L290 TraceCheckUtils]: 81: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,732 INFO L290 TraceCheckUtils]: 82: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,733 INFO L290 TraceCheckUtils]: 83: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,733 INFO L290 TraceCheckUtils]: 84: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,733 INFO L290 TraceCheckUtils]: 85: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,733 INFO L290 TraceCheckUtils]: 86: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,734 INFO L290 TraceCheckUtils]: 87: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,734 INFO L290 TraceCheckUtils]: 88: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,734 INFO L290 TraceCheckUtils]: 89: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,734 INFO L290 TraceCheckUtils]: 90: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,735 INFO L290 TraceCheckUtils]: 91: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,735 INFO L290 TraceCheckUtils]: 92: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,735 INFO L290 TraceCheckUtils]: 93: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,735 INFO L290 TraceCheckUtils]: 94: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,736 INFO L290 TraceCheckUtils]: 95: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,736 INFO L290 TraceCheckUtils]: 96: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,736 INFO L290 TraceCheckUtils]: 97: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,736 INFO L290 TraceCheckUtils]: 98: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,737 INFO L290 TraceCheckUtils]: 99: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,737 INFO L290 TraceCheckUtils]: 100: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,737 INFO L290 TraceCheckUtils]: 101: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,737 INFO L290 TraceCheckUtils]: 102: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,738 INFO L290 TraceCheckUtils]: 103: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,738 INFO L290 TraceCheckUtils]: 104: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,738 INFO L290 TraceCheckUtils]: 105: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,738 INFO L290 TraceCheckUtils]: 106: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,739 INFO L290 TraceCheckUtils]: 107: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,739 INFO L290 TraceCheckUtils]: 108: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {51769#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:13,739 INFO L290 TraceCheckUtils]: 109: Hoare triple {51769#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {51768#false} is VALID [2022-02-21 04:23:13,739 INFO L290 TraceCheckUtils]: 110: Hoare triple {51768#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,739 INFO L290 TraceCheckUtils]: 111: Hoare triple {51768#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,739 INFO L290 TraceCheckUtils]: 112: Hoare triple {51768#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 113: Hoare triple {51768#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 114: Hoare triple {51768#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 115: Hoare triple {51768#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 116: Hoare triple {51768#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 117: Hoare triple {51768#false} assume !(1 == ~T10_E~0); {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 118: Hoare triple {51768#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 119: Hoare triple {51768#false} assume 1 == ~E_M~0;~E_M~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 120: Hoare triple {51768#false} assume 1 == ~E_1~0;~E_1~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 121: Hoare triple {51768#false} assume 1 == ~E_2~0;~E_2~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,740 INFO L290 TraceCheckUtils]: 122: Hoare triple {51768#false} assume 1 == ~E_3~0;~E_3~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 123: Hoare triple {51768#false} assume 1 == ~E_4~0;~E_4~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 124: Hoare triple {51768#false} assume 1 == ~E_5~0;~E_5~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 125: Hoare triple {51768#false} assume !(1 == ~E_6~0); {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 126: Hoare triple {51768#false} assume 1 == ~E_7~0;~E_7~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 127: Hoare triple {51768#false} assume 1 == ~E_8~0;~E_8~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 128: Hoare triple {51768#false} assume 1 == ~E_9~0;~E_9~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 129: Hoare triple {51768#false} assume 1 == ~E_10~0;~E_10~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 130: Hoare triple {51768#false} assume 1 == ~E_11~0;~E_11~0 := 2; {51768#false} is VALID [2022-02-21 04:23:13,741 INFO L290 TraceCheckUtils]: 131: Hoare triple {51768#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 132: Hoare triple {51768#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 133: Hoare triple {51768#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 134: Hoare triple {51768#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 135: Hoare triple {51768#false} assume !(0 == start_simulation_~tmp~3#1); {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 136: Hoare triple {51768#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 137: Hoare triple {51768#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 138: Hoare triple {51768#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 139: Hoare triple {51768#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {51768#false} is VALID [2022-02-21 04:23:13,742 INFO L290 TraceCheckUtils]: 140: Hoare triple {51768#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {51768#false} is VALID [2022-02-21 04:23:13,743 INFO L290 TraceCheckUtils]: 141: Hoare triple {51768#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {51768#false} is VALID [2022-02-21 04:23:13,743 INFO L290 TraceCheckUtils]: 142: Hoare triple {51768#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {51768#false} is VALID [2022-02-21 04:23:13,743 INFO L290 TraceCheckUtils]: 143: Hoare triple {51768#false} assume !(0 != start_simulation_~tmp___0~1#1); {51768#false} is VALID [2022-02-21 04:23:13,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:13,743 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:13,743 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303419595] [2022-02-21 04:23:13,744 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303419595] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:13,744 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:13,744 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:13,744 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689941086] [2022-02-21 04:23:13,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:13,744 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:13,744 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:13,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:13,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:13,746 INFO L87 Difference]: Start difference. First operand 1566 states and 2318 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,766 INFO L93 Difference]: Finished difference Result 1566 states and 2317 transitions. [2022-02-21 04:23:14,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:14,766 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,843 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:14,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2317 transitions. [2022-02-21 04:23:14,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:14,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2317 transitions. [2022-02-21 04:23:14,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:14,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:14,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2317 transitions. [2022-02-21 04:23:14,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:14,953 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-02-21 04:23:14,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2317 transitions. [2022-02-21 04:23:14,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:14,968 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:14,969 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2317 transitions. Second operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,970 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2317 transitions. Second operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,971 INFO L87 Difference]: Start difference. First operand 1566 states and 2317 transitions. Second operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,023 INFO L93 Difference]: Finished difference Result 1566 states and 2317 transitions. [2022-02-21 04:23:15,023 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2317 transitions. [2022-02-21 04:23:15,024 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:15,024 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:15,026 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2317 transitions. [2022-02-21 04:23:15,026 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2317 transitions. [2022-02-21 04:23:15,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,078 INFO L93 Difference]: Finished difference Result 1566 states and 2317 transitions. [2022-02-21 04:23:15,078 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2317 transitions. [2022-02-21 04:23:15,079 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:15,080 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:15,080 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:15,080 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:15,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2317 transitions. [2022-02-21 04:23:15,132 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-02-21 04:23:15,132 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-02-21 04:23:15,132 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:15,132 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2317 transitions. [2022-02-21 04:23:15,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:15,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:15,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:15,136 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,136 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:15,136 INFO L791 eck$LassoCheckResult]: Stem: 54071#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 54072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 54800#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54801#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53574#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 53575#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54810#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54775#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54776#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53923#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53924#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54330#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54748#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53835#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53836#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 53721#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 53722#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54674#L1109 assume !(0 == ~M_E~0); 54696#L1109-2 assume !(0 == ~T1_E~0); 53728#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53729#L1119-1 assume !(0 == ~T3_E~0); 54752#L1124-1 assume !(0 == ~T4_E~0); 53391#L1129-1 assume !(0 == ~T5_E~0); 53392#L1134-1 assume !(0 == ~T6_E~0); 54003#L1139-1 assume !(0 == ~T7_E~0); 54680#L1144-1 assume !(0 == ~T8_E~0); 54552#L1149-1 assume !(0 == ~T9_E~0); 53496#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53497#L1159-1 assume !(0 == ~T11_E~0); 54538#L1164-1 assume !(0 == ~E_M~0); 53889#L1169-1 assume !(0 == ~E_1~0); 53778#L1174-1 assume !(0 == ~E_2~0); 53651#L1179-1 assume !(0 == ~E_3~0); 53578#L1184-1 assume !(0 == ~E_4~0); 53579#L1189-1 assume !(0 == ~E_5~0); 53610#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 53697#L1199-1 assume !(0 == ~E_7~0); 54560#L1204-1 assume !(0 == ~E_8~0); 54496#L1209-1 assume !(0 == ~E_9~0); 54497#L1214-1 assume !(0 == ~E_10~0); 54822#L1219-1 assume !(0 == ~E_11~0); 54895#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53906#L544 assume 1 == ~m_pc~0; 53907#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 54739#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54567#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53540#L1379 assume !(0 != activate_threads_~tmp~1#1); 53541#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54313#L563 assume !(1 == ~t1_pc~0); 54113#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53399#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53400#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54436#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 53395#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53396#L582 assume 1 == ~t2_pc~0; 54091#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54446#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54447#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54551#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 53428#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53429#L601 assume !(1 == ~t3_pc~0); 54107#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54106#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54740#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54482#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 54483#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54426#L620 assume 1 == ~t4_pc~0; 53409#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53410#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53971#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53972#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 54327#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54514#L639 assume 1 == ~t5_pc~0; 54397#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53701#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53702#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54348#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 54349#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54278#L658 assume !(1 == ~t6_pc~0); 53903#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53904#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54472#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54802#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54486#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53741#L677 assume 1 == ~t7_pc~0; 53742#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53644#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54645#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54769#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 54770#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54841#L696 assume !(1 == ~t8_pc~0); 53961#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 53962#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54809#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54830#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 54876#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54380#L715 assume 1 == ~t9_pc~0; 54381#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54051#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53959#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53960#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 54369#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54641#L734 assume !(1 == ~t10_pc~0); 54642#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53861#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53862#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53880#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 54585#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53937#L753 assume 1 == ~t11_pc~0; 53938#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54491#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54046#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54047#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 54196#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54253#L1237 assume !(1 == ~M_E~0); 54254#L1237-2 assume !(1 == ~T1_E~0); 54866#L1242-1 assume !(1 == ~T2_E~0); 54017#L1247-1 assume !(1 == ~T3_E~0); 54018#L1252-1 assume !(1 == ~T4_E~0); 53801#L1257-1 assume !(1 == ~T5_E~0); 53802#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54657#L1267-1 assume !(1 == ~T7_E~0); 54762#L1272-1 assume !(1 == ~T8_E~0); 54100#L1277-1 assume !(1 == ~T9_E~0); 54101#L1282-1 assume !(1 == ~T10_E~0); 54523#L1287-1 assume !(1 == ~T11_E~0); 54524#L1292-1 assume !(1 == ~E_M~0); 54485#L1297-1 assume !(1 == ~E_1~0); 53932#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 53933#L1307-1 assume !(1 == ~E_3~0); 54755#L1312-1 assume !(1 == ~E_4~0); 54143#L1317-1 assume !(1 == ~E_5~0); 54144#L1322-1 assume !(1 == ~E_6~0); 53876#L1327-1 assume !(1 == ~E_7~0); 53877#L1332-1 assume !(1 == ~E_8~0); 54435#L1337-1 assume !(1 == ~E_9~0); 54372#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 54373#L1347-1 assume !(1 == ~E_11~0); 54754#L1352-1 assume { :end_inline_reset_delta_events } true; 54644#L1678-2 [2022-02-21 04:23:15,137 INFO L793 eck$LassoCheckResult]: Loop: 54644#L1678-2 assume !false; 54427#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54428#L1084 assume !false; 54211#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54212#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 53515#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54529#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 53441#L925 assume !(0 != eval_~tmp~0#1); 53443#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53557#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53558#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53412#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53413#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54487#L1119-3 assume !(0 == ~T3_E~0); 54488#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54509#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54510#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54688#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54746#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53916#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53917#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54152#L1159-3 assume !(0 == ~T11_E~0); 54153#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54423#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54424#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54474#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54475#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54630#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54307#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53674#L1199-3 assume !(0 == ~E_7~0); 53675#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53898#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53360#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53361#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54059#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54060#L544-39 assume !(1 == ~m_pc~0); 53341#L544-41 is_master_triggered_~__retres1~0#1 := 0; 53342#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53592#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53593#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 53749#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54617#L563-39 assume !(1 == ~t1_pc~0); 53491#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 53492#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54391#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54392#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54889#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54732#L582-39 assume 1 == ~t2_pc~0; 53815#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53817#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54437#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54438#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53585#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53372#L601-39 assume 1 == ~t3_pc~0; 53373#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53423#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54581#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54717#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54621#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54273#L620-39 assume !(1 == ~t4_pc~0); 54274#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 54471#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54679#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54594#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54595#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54900#L639-39 assume 1 == ~t5_pc~0; 54707#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54021#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53598#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53401#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53402#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54310#L658-39 assume 1 == ~t6_pc~0; 54292#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54293#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53351#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53352#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54467#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54468#L677-39 assume !(1 == ~t7_pc~0); 54098#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 53576#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53577#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53632#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 53633#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54198#L696-39 assume 1 == ~t8_pc~0; 54163#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54043#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54044#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54339#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54303#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54178#L715-39 assume 1 == ~t9_pc~0; 53379#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53380#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54587#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54901#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54516#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54517#L734-39 assume 1 == ~t10_pc~0; 54442#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53888#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54199#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53530#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53531#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54779#L753-39 assume !(1 == ~t11_pc~0); 53450#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 53451#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54743#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54168#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54169#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54270#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54271#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54541#L1242-3 assume !(1 == ~T2_E~0); 54542#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54761#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54461#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54462#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54744#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54785#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54873#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53602#L1282-3 assume !(1 == ~T10_E~0); 53603#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53512#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53513#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54650#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54651#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54839#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54897#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54563#L1322-3 assume !(1 == ~E_6~0); 54564#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53571#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53546#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53547#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54240#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54367#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54368#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 53494#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 53759#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 54473#L1697 assume !(0 == start_simulation_~tmp~3#1); 54260#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54261#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 53618#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54383#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 54384#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54333#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53930#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 53931#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 54644#L1678-2 [2022-02-21 04:23:15,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,137 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2022-02-21 04:23:15,137 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,137 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040641852] [2022-02-21 04:23:15,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,155 INFO L290 TraceCheckUtils]: 0: Hoare triple {58037#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {58037#true} is VALID [2022-02-21 04:23:15,156 INFO L290 TraceCheckUtils]: 1: Hoare triple {58037#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,156 INFO L290 TraceCheckUtils]: 2: Hoare triple {58039#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,156 INFO L290 TraceCheckUtils]: 3: Hoare triple {58039#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,157 INFO L290 TraceCheckUtils]: 4: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,157 INFO L290 TraceCheckUtils]: 5: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,157 INFO L290 TraceCheckUtils]: 6: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,157 INFO L290 TraceCheckUtils]: 7: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,158 INFO L290 TraceCheckUtils]: 8: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,158 INFO L290 TraceCheckUtils]: 9: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,158 INFO L290 TraceCheckUtils]: 10: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,158 INFO L290 TraceCheckUtils]: 11: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,159 INFO L290 TraceCheckUtils]: 12: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,159 INFO L290 TraceCheckUtils]: 13: Hoare triple {58039#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {58039#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:15,159 INFO L290 TraceCheckUtils]: 14: Hoare triple {58039#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {58038#false} is VALID [2022-02-21 04:23:15,159 INFO L290 TraceCheckUtils]: 15: Hoare triple {58038#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {58038#false} is VALID [2022-02-21 04:23:15,159 INFO L290 TraceCheckUtils]: 16: Hoare triple {58038#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {58038#false} is VALID [2022-02-21 04:23:15,159 INFO L290 TraceCheckUtils]: 17: Hoare triple {58038#false} assume !(0 == ~M_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 18: Hoare triple {58038#false} assume !(0 == ~T1_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 19: Hoare triple {58038#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 20: Hoare triple {58038#false} assume !(0 == ~T3_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 21: Hoare triple {58038#false} assume !(0 == ~T4_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 22: Hoare triple {58038#false} assume !(0 == ~T5_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 23: Hoare triple {58038#false} assume !(0 == ~T6_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 24: Hoare triple {58038#false} assume !(0 == ~T7_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 25: Hoare triple {58038#false} assume !(0 == ~T8_E~0); {58038#false} is VALID [2022-02-21 04:23:15,160 INFO L290 TraceCheckUtils]: 26: Hoare triple {58038#false} assume !(0 == ~T9_E~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 27: Hoare triple {58038#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 28: Hoare triple {58038#false} assume !(0 == ~T11_E~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 29: Hoare triple {58038#false} assume !(0 == ~E_M~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 30: Hoare triple {58038#false} assume !(0 == ~E_1~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 31: Hoare triple {58038#false} assume !(0 == ~E_2~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 32: Hoare triple {58038#false} assume !(0 == ~E_3~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 33: Hoare triple {58038#false} assume !(0 == ~E_4~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 34: Hoare triple {58038#false} assume !(0 == ~E_5~0); {58038#false} is VALID [2022-02-21 04:23:15,161 INFO L290 TraceCheckUtils]: 35: Hoare triple {58038#false} assume 0 == ~E_6~0;~E_6~0 := 1; {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 36: Hoare triple {58038#false} assume !(0 == ~E_7~0); {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 37: Hoare triple {58038#false} assume !(0 == ~E_8~0); {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 38: Hoare triple {58038#false} assume !(0 == ~E_9~0); {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 39: Hoare triple {58038#false} assume !(0 == ~E_10~0); {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 40: Hoare triple {58038#false} assume !(0 == ~E_11~0); {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 41: Hoare triple {58038#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 42: Hoare triple {58038#false} assume 1 == ~m_pc~0; {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 43: Hoare triple {58038#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {58038#false} is VALID [2022-02-21 04:23:15,162 INFO L290 TraceCheckUtils]: 44: Hoare triple {58038#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 45: Hoare triple {58038#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 46: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp~1#1); {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 47: Hoare triple {58038#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 48: Hoare triple {58038#false} assume !(1 == ~t1_pc~0); {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 49: Hoare triple {58038#false} is_transmit1_triggered_~__retres1~1#1 := 0; {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 50: Hoare triple {58038#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 51: Hoare triple {58038#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 52: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___0~0#1); {58038#false} is VALID [2022-02-21 04:23:15,163 INFO L290 TraceCheckUtils]: 53: Hoare triple {58038#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 54: Hoare triple {58038#false} assume 1 == ~t2_pc~0; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 55: Hoare triple {58038#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 56: Hoare triple {58038#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 57: Hoare triple {58038#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 58: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___1~0#1); {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 59: Hoare triple {58038#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 60: Hoare triple {58038#false} assume !(1 == ~t3_pc~0); {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 61: Hoare triple {58038#false} is_transmit3_triggered_~__retres1~3#1 := 0; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 62: Hoare triple {58038#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58038#false} is VALID [2022-02-21 04:23:15,164 INFO L290 TraceCheckUtils]: 63: Hoare triple {58038#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 64: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___2~0#1); {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 65: Hoare triple {58038#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 66: Hoare triple {58038#false} assume 1 == ~t4_pc~0; {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 67: Hoare triple {58038#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 68: Hoare triple {58038#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 69: Hoare triple {58038#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 70: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___3~0#1); {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 71: Hoare triple {58038#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58038#false} is VALID [2022-02-21 04:23:15,165 INFO L290 TraceCheckUtils]: 72: Hoare triple {58038#false} assume 1 == ~t5_pc~0; {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 73: Hoare triple {58038#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 74: Hoare triple {58038#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 75: Hoare triple {58038#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 76: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___4~0#1); {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 77: Hoare triple {58038#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 78: Hoare triple {58038#false} assume !(1 == ~t6_pc~0); {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 79: Hoare triple {58038#false} is_transmit6_triggered_~__retres1~6#1 := 0; {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 80: Hoare triple {58038#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58038#false} is VALID [2022-02-21 04:23:15,166 INFO L290 TraceCheckUtils]: 81: Hoare triple {58038#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 82: Hoare triple {58038#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 83: Hoare triple {58038#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 84: Hoare triple {58038#false} assume 1 == ~t7_pc~0; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 85: Hoare triple {58038#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 86: Hoare triple {58038#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 87: Hoare triple {58038#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 88: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___6~0#1); {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 89: Hoare triple {58038#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58038#false} is VALID [2022-02-21 04:23:15,167 INFO L290 TraceCheckUtils]: 90: Hoare triple {58038#false} assume !(1 == ~t8_pc~0); {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 91: Hoare triple {58038#false} is_transmit8_triggered_~__retres1~8#1 := 0; {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 92: Hoare triple {58038#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 93: Hoare triple {58038#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 94: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___7~0#1); {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 95: Hoare triple {58038#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 96: Hoare triple {58038#false} assume 1 == ~t9_pc~0; {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 97: Hoare triple {58038#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 98: Hoare triple {58038#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58038#false} is VALID [2022-02-21 04:23:15,168 INFO L290 TraceCheckUtils]: 99: Hoare triple {58038#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 100: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___8~0#1); {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 101: Hoare triple {58038#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 102: Hoare triple {58038#false} assume !(1 == ~t10_pc~0); {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 103: Hoare triple {58038#false} is_transmit10_triggered_~__retres1~10#1 := 0; {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 104: Hoare triple {58038#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 105: Hoare triple {58038#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 106: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___9~0#1); {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 107: Hoare triple {58038#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58038#false} is VALID [2022-02-21 04:23:15,169 INFO L290 TraceCheckUtils]: 108: Hoare triple {58038#false} assume 1 == ~t11_pc~0; {58038#false} is VALID [2022-02-21 04:23:15,170 INFO L290 TraceCheckUtils]: 109: Hoare triple {58038#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {58038#false} is VALID [2022-02-21 04:23:15,170 INFO L290 TraceCheckUtils]: 110: Hoare triple {58038#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58038#false} is VALID [2022-02-21 04:23:15,170 INFO L290 TraceCheckUtils]: 111: Hoare triple {58038#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58038#false} is VALID [2022-02-21 04:23:15,170 INFO L290 TraceCheckUtils]: 112: Hoare triple {58038#false} assume !(0 != activate_threads_~tmp___10~0#1); {58038#false} is VALID [2022-02-21 04:23:15,172 INFO L290 TraceCheckUtils]: 113: Hoare triple {58038#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58038#false} is VALID [2022-02-21 04:23:15,172 INFO L290 TraceCheckUtils]: 114: Hoare triple {58038#false} assume !(1 == ~M_E~0); {58038#false} is VALID [2022-02-21 04:23:15,172 INFO L290 TraceCheckUtils]: 115: Hoare triple {58038#false} assume !(1 == ~T1_E~0); {58038#false} is VALID [2022-02-21 04:23:15,172 INFO L290 TraceCheckUtils]: 116: Hoare triple {58038#false} assume !(1 == ~T2_E~0); {58038#false} is VALID [2022-02-21 04:23:15,172 INFO L290 TraceCheckUtils]: 117: Hoare triple {58038#false} assume !(1 == ~T3_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 118: Hoare triple {58038#false} assume !(1 == ~T4_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 119: Hoare triple {58038#false} assume !(1 == ~T5_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 120: Hoare triple {58038#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 121: Hoare triple {58038#false} assume !(1 == ~T7_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 122: Hoare triple {58038#false} assume !(1 == ~T8_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 123: Hoare triple {58038#false} assume !(1 == ~T9_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 124: Hoare triple {58038#false} assume !(1 == ~T10_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 125: Hoare triple {58038#false} assume !(1 == ~T11_E~0); {58038#false} is VALID [2022-02-21 04:23:15,173 INFO L290 TraceCheckUtils]: 126: Hoare triple {58038#false} assume !(1 == ~E_M~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 127: Hoare triple {58038#false} assume !(1 == ~E_1~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 128: Hoare triple {58038#false} assume 1 == ~E_2~0;~E_2~0 := 2; {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 129: Hoare triple {58038#false} assume !(1 == ~E_3~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 130: Hoare triple {58038#false} assume !(1 == ~E_4~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 131: Hoare triple {58038#false} assume !(1 == ~E_5~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 132: Hoare triple {58038#false} assume !(1 == ~E_6~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 133: Hoare triple {58038#false} assume !(1 == ~E_7~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 134: Hoare triple {58038#false} assume !(1 == ~E_8~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 135: Hoare triple {58038#false} assume !(1 == ~E_9~0); {58038#false} is VALID [2022-02-21 04:23:15,174 INFO L290 TraceCheckUtils]: 136: Hoare triple {58038#false} assume 1 == ~E_10~0;~E_10~0 := 2; {58038#false} is VALID [2022-02-21 04:23:15,175 INFO L290 TraceCheckUtils]: 137: Hoare triple {58038#false} assume !(1 == ~E_11~0); {58038#false} is VALID [2022-02-21 04:23:15,175 INFO L290 TraceCheckUtils]: 138: Hoare triple {58038#false} assume { :end_inline_reset_delta_events } true; {58038#false} is VALID [2022-02-21 04:23:15,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,175 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,175 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040641852] [2022-02-21 04:23:15,175 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040641852] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,176 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,176 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,176 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862824134] [2022-02-21 04:23:15,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,176 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:15,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:15,177 INFO L85 PathProgramCache]: Analyzing trace with hash -1209669491, now seen corresponding path program 2 times [2022-02-21 04:23:15,177 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:15,177 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530287481] [2022-02-21 04:23:15,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:15,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:15,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:15,200 INFO L290 TraceCheckUtils]: 0: Hoare triple {58040#true} assume !false; {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 1: Hoare triple {58040#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 2: Hoare triple {58040#true} assume !false; {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 3: Hoare triple {58040#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 4: Hoare triple {58040#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 5: Hoare triple {58040#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 6: Hoare triple {58040#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 7: Hoare triple {58040#true} assume !(0 != eval_~tmp~0#1); {58040#true} is VALID [2022-02-21 04:23:15,201 INFO L290 TraceCheckUtils]: 8: Hoare triple {58040#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {58040#true} is VALID [2022-02-21 04:23:15,202 INFO L290 TraceCheckUtils]: 9: Hoare triple {58040#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {58040#true} is VALID [2022-02-21 04:23:15,202 INFO L290 TraceCheckUtils]: 10: Hoare triple {58040#true} assume 0 == ~M_E~0;~M_E~0 := 1; {58040#true} is VALID [2022-02-21 04:23:15,202 INFO L290 TraceCheckUtils]: 11: Hoare triple {58040#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {58040#true} is VALID [2022-02-21 04:23:15,202 INFO L290 TraceCheckUtils]: 12: Hoare triple {58040#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,202 INFO L290 TraceCheckUtils]: 13: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,203 INFO L290 TraceCheckUtils]: 14: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,203 INFO L290 TraceCheckUtils]: 15: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,203 INFO L290 TraceCheckUtils]: 16: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,203 INFO L290 TraceCheckUtils]: 17: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,204 INFO L290 TraceCheckUtils]: 18: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,204 INFO L290 TraceCheckUtils]: 19: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,204 INFO L290 TraceCheckUtils]: 20: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,204 INFO L290 TraceCheckUtils]: 21: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,205 INFO L290 TraceCheckUtils]: 22: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,205 INFO L290 TraceCheckUtils]: 23: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,205 INFO L290 TraceCheckUtils]: 24: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,205 INFO L290 TraceCheckUtils]: 25: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,206 INFO L290 TraceCheckUtils]: 26: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,206 INFO L290 TraceCheckUtils]: 27: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,206 INFO L290 TraceCheckUtils]: 28: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,206 INFO L290 TraceCheckUtils]: 29: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,207 INFO L290 TraceCheckUtils]: 30: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,207 INFO L290 TraceCheckUtils]: 31: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,207 INFO L290 TraceCheckUtils]: 32: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,207 INFO L290 TraceCheckUtils]: 33: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,208 INFO L290 TraceCheckUtils]: 34: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,208 INFO L290 TraceCheckUtils]: 35: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,208 INFO L290 TraceCheckUtils]: 36: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,208 INFO L290 TraceCheckUtils]: 37: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,209 INFO L290 TraceCheckUtils]: 38: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,209 INFO L290 TraceCheckUtils]: 39: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,209 INFO L290 TraceCheckUtils]: 40: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,209 INFO L290 TraceCheckUtils]: 41: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,210 INFO L290 TraceCheckUtils]: 42: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,210 INFO L290 TraceCheckUtils]: 43: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,210 INFO L290 TraceCheckUtils]: 44: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,210 INFO L290 TraceCheckUtils]: 45: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,210 INFO L290 TraceCheckUtils]: 46: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,211 INFO L290 TraceCheckUtils]: 47: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,211 INFO L290 TraceCheckUtils]: 48: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,211 INFO L290 TraceCheckUtils]: 49: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,212 INFO L290 TraceCheckUtils]: 50: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,212 INFO L290 TraceCheckUtils]: 51: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,212 INFO L290 TraceCheckUtils]: 52: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,212 INFO L290 TraceCheckUtils]: 53: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,212 INFO L290 TraceCheckUtils]: 54: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,213 INFO L290 TraceCheckUtils]: 55: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,213 INFO L290 TraceCheckUtils]: 56: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,213 INFO L290 TraceCheckUtils]: 57: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,213 INFO L290 TraceCheckUtils]: 58: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,214 INFO L290 TraceCheckUtils]: 59: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,214 INFO L290 TraceCheckUtils]: 60: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,214 INFO L290 TraceCheckUtils]: 61: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,214 INFO L290 TraceCheckUtils]: 62: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,215 INFO L290 TraceCheckUtils]: 63: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,215 INFO L290 TraceCheckUtils]: 64: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,215 INFO L290 TraceCheckUtils]: 65: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,215 INFO L290 TraceCheckUtils]: 66: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,216 INFO L290 TraceCheckUtils]: 67: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,216 INFO L290 TraceCheckUtils]: 68: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,216 INFO L290 TraceCheckUtils]: 69: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,216 INFO L290 TraceCheckUtils]: 70: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,217 INFO L290 TraceCheckUtils]: 71: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,217 INFO L290 TraceCheckUtils]: 72: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,217 INFO L290 TraceCheckUtils]: 73: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,217 INFO L290 TraceCheckUtils]: 74: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,218 INFO L290 TraceCheckUtils]: 75: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,218 INFO L290 TraceCheckUtils]: 76: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,218 INFO L290 TraceCheckUtils]: 77: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,218 INFO L290 TraceCheckUtils]: 78: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,219 INFO L290 TraceCheckUtils]: 79: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,219 INFO L290 TraceCheckUtils]: 80: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,219 INFO L290 TraceCheckUtils]: 81: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,219 INFO L290 TraceCheckUtils]: 82: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,220 INFO L290 TraceCheckUtils]: 83: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,220 INFO L290 TraceCheckUtils]: 84: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,220 INFO L290 TraceCheckUtils]: 85: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,220 INFO L290 TraceCheckUtils]: 86: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,221 INFO L290 TraceCheckUtils]: 87: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,221 INFO L290 TraceCheckUtils]: 88: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,221 INFO L290 TraceCheckUtils]: 89: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,221 INFO L290 TraceCheckUtils]: 90: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,222 INFO L290 TraceCheckUtils]: 91: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,222 INFO L290 TraceCheckUtils]: 92: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,222 INFO L290 TraceCheckUtils]: 93: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,222 INFO L290 TraceCheckUtils]: 94: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,223 INFO L290 TraceCheckUtils]: 95: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,223 INFO L290 TraceCheckUtils]: 96: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,223 INFO L290 TraceCheckUtils]: 97: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,223 INFO L290 TraceCheckUtils]: 98: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,224 INFO L290 TraceCheckUtils]: 99: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,224 INFO L290 TraceCheckUtils]: 100: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,224 INFO L290 TraceCheckUtils]: 101: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,224 INFO L290 TraceCheckUtils]: 102: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,225 INFO L290 TraceCheckUtils]: 103: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,225 INFO L290 TraceCheckUtils]: 104: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,225 INFO L290 TraceCheckUtils]: 105: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,225 INFO L290 TraceCheckUtils]: 106: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 107: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 108: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {58042#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 109: Hoare triple {58042#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {58041#false} is VALID [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 110: Hoare triple {58041#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 111: Hoare triple {58041#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,226 INFO L290 TraceCheckUtils]: 112: Hoare triple {58041#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 113: Hoare triple {58041#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 114: Hoare triple {58041#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 115: Hoare triple {58041#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 116: Hoare triple {58041#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 117: Hoare triple {58041#false} assume !(1 == ~T10_E~0); {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 118: Hoare triple {58041#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 119: Hoare triple {58041#false} assume 1 == ~E_M~0;~E_M~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 120: Hoare triple {58041#false} assume 1 == ~E_1~0;~E_1~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,227 INFO L290 TraceCheckUtils]: 121: Hoare triple {58041#false} assume 1 == ~E_2~0;~E_2~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 122: Hoare triple {58041#false} assume 1 == ~E_3~0;~E_3~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 123: Hoare triple {58041#false} assume 1 == ~E_4~0;~E_4~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 124: Hoare triple {58041#false} assume 1 == ~E_5~0;~E_5~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 125: Hoare triple {58041#false} assume !(1 == ~E_6~0); {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 126: Hoare triple {58041#false} assume 1 == ~E_7~0;~E_7~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 127: Hoare triple {58041#false} assume 1 == ~E_8~0;~E_8~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 128: Hoare triple {58041#false} assume 1 == ~E_9~0;~E_9~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 129: Hoare triple {58041#false} assume 1 == ~E_10~0;~E_10~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,228 INFO L290 TraceCheckUtils]: 130: Hoare triple {58041#false} assume 1 == ~E_11~0;~E_11~0 := 2; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 131: Hoare triple {58041#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 132: Hoare triple {58041#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 133: Hoare triple {58041#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 134: Hoare triple {58041#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 135: Hoare triple {58041#false} assume !(0 == start_simulation_~tmp~3#1); {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 136: Hoare triple {58041#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 137: Hoare triple {58041#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 138: Hoare triple {58041#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {58041#false} is VALID [2022-02-21 04:23:15,229 INFO L290 TraceCheckUtils]: 139: Hoare triple {58041#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {58041#false} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 140: Hoare triple {58041#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {58041#false} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 141: Hoare triple {58041#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {58041#false} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 142: Hoare triple {58041#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {58041#false} is VALID [2022-02-21 04:23:15,230 INFO L290 TraceCheckUtils]: 143: Hoare triple {58041#false} assume !(0 != start_simulation_~tmp___0~1#1); {58041#false} is VALID [2022-02-21 04:23:15,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:15,230 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:15,231 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1530287481] [2022-02-21 04:23:15,231 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1530287481] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:15,231 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:15,231 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:15,231 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841495911] [2022-02-21 04:23:15,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:15,232 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:15,232 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:15,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:15,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:15,232 INFO L87 Difference]: Start difference. First operand 1566 states and 2317 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,213 INFO L93 Difference]: Finished difference Result 1566 states and 2316 transitions. [2022-02-21 04:23:16,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:16,214 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,308 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:16,309 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:16,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2316 transitions. [2022-02-21 04:23:16,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:16,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:16,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:16,416 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-02-21 04:23:16,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:16,429 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:16,431 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2316 transitions. Second operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,432 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2316 transitions. Second operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,433 INFO L87 Difference]: Start difference. First operand 1566 states and 2316 transitions. Second operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,484 INFO L93 Difference]: Finished difference Result 1566 states and 2316 transitions. [2022-02-21 04:23:16,484 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,485 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:16,485 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:16,487 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,488 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,539 INFO L93 Difference]: Finished difference Result 1566 states and 2316 transitions. [2022-02-21 04:23:16,539 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,541 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:16,541 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:16,541 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:16,541 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:16,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2316 transitions. [2022-02-21 04:23:16,593 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-02-21 04:23:16,593 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-02-21 04:23:16,593 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:16,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2316 transitions. [2022-02-21 04:23:16,596 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:16,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:16,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:16,597 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,597 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,598 INFO L791 eck$LassoCheckResult]: Stem: 60344#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 60345#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 61073#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61074#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59847#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 59848#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61083#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61048#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61049#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60196#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60197#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60603#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61021#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60108#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60109#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59994#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 59995#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60947#L1109 assume !(0 == ~M_E~0); 60969#L1109-2 assume !(0 == ~T1_E~0); 60001#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60002#L1119-1 assume !(0 == ~T3_E~0); 61025#L1124-1 assume !(0 == ~T4_E~0); 59662#L1129-1 assume !(0 == ~T5_E~0); 59663#L1134-1 assume !(0 == ~T6_E~0); 60276#L1139-1 assume !(0 == ~T7_E~0); 60953#L1144-1 assume !(0 == ~T8_E~0); 60825#L1149-1 assume !(0 == ~T9_E~0); 59769#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59770#L1159-1 assume !(0 == ~T11_E~0); 60811#L1164-1 assume !(0 == ~E_M~0); 60162#L1169-1 assume !(0 == ~E_1~0); 60051#L1174-1 assume !(0 == ~E_2~0); 59924#L1179-1 assume !(0 == ~E_3~0); 59851#L1184-1 assume !(0 == ~E_4~0); 59852#L1189-1 assume !(0 == ~E_5~0); 59883#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 59970#L1199-1 assume !(0 == ~E_7~0); 60833#L1204-1 assume !(0 == ~E_8~0); 60769#L1209-1 assume !(0 == ~E_9~0); 60770#L1214-1 assume !(0 == ~E_10~0); 61095#L1219-1 assume !(0 == ~E_11~0); 61168#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60179#L544 assume 1 == ~m_pc~0; 60180#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61012#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60840#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59813#L1379 assume !(0 != activate_threads_~tmp~1#1); 59814#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60586#L563 assume !(1 == ~t1_pc~0); 60386#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 59672#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59673#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60709#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 59668#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59669#L582 assume 1 == ~t2_pc~0; 60364#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60719#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60720#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60824#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 59701#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59702#L601 assume !(1 == ~t3_pc~0); 60380#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60379#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61013#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60755#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 60756#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60699#L620 assume 1 == ~t4_pc~0; 59682#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59683#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60244#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60245#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 60600#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60787#L639 assume 1 == ~t5_pc~0; 60670#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59974#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59975#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60621#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 60622#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60551#L658 assume !(1 == ~t6_pc~0); 60176#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 60177#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60745#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61075#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60759#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60014#L677 assume 1 == ~t7_pc~0; 60015#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59917#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60918#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61042#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 61043#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61114#L696 assume !(1 == ~t8_pc~0); 60234#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 60235#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61082#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61103#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 61149#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60653#L715 assume 1 == ~t9_pc~0; 60654#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60324#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60232#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60233#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 60642#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60914#L734 assume !(1 == ~t10_pc~0); 60915#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 60134#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60135#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60153#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 60858#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60210#L753 assume 1 == ~t11_pc~0; 60211#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60764#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60319#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60320#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 60469#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60526#L1237 assume !(1 == ~M_E~0); 60527#L1237-2 assume !(1 == ~T1_E~0); 61139#L1242-1 assume !(1 == ~T2_E~0); 60290#L1247-1 assume !(1 == ~T3_E~0); 60291#L1252-1 assume !(1 == ~T4_E~0); 60074#L1257-1 assume !(1 == ~T5_E~0); 60075#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60930#L1267-1 assume !(1 == ~T7_E~0); 61035#L1272-1 assume !(1 == ~T8_E~0); 60373#L1277-1 assume !(1 == ~T9_E~0); 60374#L1282-1 assume !(1 == ~T10_E~0); 60796#L1287-1 assume !(1 == ~T11_E~0); 60797#L1292-1 assume !(1 == ~E_M~0); 60758#L1297-1 assume !(1 == ~E_1~0); 60205#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 60206#L1307-1 assume !(1 == ~E_3~0); 61028#L1312-1 assume !(1 == ~E_4~0); 60416#L1317-1 assume !(1 == ~E_5~0); 60417#L1322-1 assume !(1 == ~E_6~0); 60149#L1327-1 assume !(1 == ~E_7~0); 60150#L1332-1 assume !(1 == ~E_8~0); 60708#L1337-1 assume !(1 == ~E_9~0); 60645#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 60646#L1347-1 assume !(1 == ~E_11~0); 61027#L1352-1 assume { :end_inline_reset_delta_events } true; 60917#L1678-2 [2022-02-21 04:23:16,598 INFO L793 eck$LassoCheckResult]: Loop: 60917#L1678-2 assume !false; 60700#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60701#L1084 assume !false; 60484#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 60485#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 59788#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 60802#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 59714#L925 assume !(0 != eval_~tmp~0#1); 59716#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59830#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59831#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59685#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59686#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60760#L1119-3 assume !(0 == ~T3_E~0); 60761#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60782#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60783#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60961#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61019#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60189#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60190#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 60425#L1159-3 assume !(0 == ~T11_E~0); 60426#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60696#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60697#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60747#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60748#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60903#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60580#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59947#L1199-3 assume !(0 == ~E_7~0); 59948#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60171#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59633#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59634#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60332#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60333#L544-39 assume 1 == ~m_pc~0; 60688#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 59615#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59865#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59866#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 60022#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60890#L563-39 assume 1 == ~t1_pc~0; 60896#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59765#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60664#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60665#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61162#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61005#L582-39 assume 1 == ~t2_pc~0; 60088#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60090#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60710#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60711#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59858#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59645#L601-39 assume 1 == ~t3_pc~0; 59646#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 59696#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60854#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60990#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60894#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60546#L620-39 assume !(1 == ~t4_pc~0); 60547#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 60744#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60952#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60867#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60868#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61173#L639-39 assume 1 == ~t5_pc~0; 60980#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60294#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59871#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59674#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59675#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60583#L658-39 assume 1 == ~t6_pc~0; 60565#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60566#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59624#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59625#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60740#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60741#L677-39 assume !(1 == ~t7_pc~0); 60371#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 59849#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59850#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59905#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 59906#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60471#L696-39 assume 1 == ~t8_pc~0; 60436#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60316#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60317#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60612#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60576#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60451#L715-39 assume 1 == ~t9_pc~0; 59650#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59651#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60860#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61174#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60789#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60790#L734-39 assume !(1 == ~t10_pc~0); 60160#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 60161#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60472#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59803#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59804#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61052#L753-39 assume !(1 == ~t11_pc~0); 59723#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 59724#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61016#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60441#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60442#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60543#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60544#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60814#L1242-3 assume !(1 == ~T2_E~0); 60815#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61034#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60734#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60735#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61017#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61058#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61146#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 59875#L1282-3 assume !(1 == ~T10_E~0); 59876#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59785#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59786#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60923#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60924#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61112#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61170#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60836#L1322-3 assume !(1 == ~E_6~0); 60837#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59844#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59819#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59820#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 60512#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60640#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 60641#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 59767#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 60032#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 60746#L1697 assume !(0 == start_simulation_~tmp~3#1); 60533#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 60534#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 59891#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 60656#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 60657#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60606#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60203#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 60204#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 60917#L1678-2 [2022-02-21 04:23:16,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,599 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2022-02-21 04:23:16,599 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,599 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654487244] [2022-02-21 04:23:16,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,631 INFO L290 TraceCheckUtils]: 0: Hoare triple {64310#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {64310#true} is VALID [2022-02-21 04:23:16,631 INFO L290 TraceCheckUtils]: 1: Hoare triple {64310#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,632 INFO L290 TraceCheckUtils]: 2: Hoare triple {64312#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,632 INFO L290 TraceCheckUtils]: 3: Hoare triple {64312#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,632 INFO L290 TraceCheckUtils]: 4: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,632 INFO L290 TraceCheckUtils]: 5: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,633 INFO L290 TraceCheckUtils]: 6: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,633 INFO L290 TraceCheckUtils]: 7: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,633 INFO L290 TraceCheckUtils]: 8: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,633 INFO L290 TraceCheckUtils]: 9: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,634 INFO L290 TraceCheckUtils]: 10: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,634 INFO L290 TraceCheckUtils]: 11: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,634 INFO L290 TraceCheckUtils]: 12: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,634 INFO L290 TraceCheckUtils]: 13: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 14: Hoare triple {64312#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {64312#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 15: Hoare triple {64312#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {64311#false} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 16: Hoare triple {64311#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {64311#false} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 17: Hoare triple {64311#false} assume !(0 == ~M_E~0); {64311#false} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 18: Hoare triple {64311#false} assume !(0 == ~T1_E~0); {64311#false} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 19: Hoare triple {64311#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {64311#false} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 20: Hoare triple {64311#false} assume !(0 == ~T3_E~0); {64311#false} is VALID [2022-02-21 04:23:16,635 INFO L290 TraceCheckUtils]: 21: Hoare triple {64311#false} assume !(0 == ~T4_E~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 22: Hoare triple {64311#false} assume !(0 == ~T5_E~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 23: Hoare triple {64311#false} assume !(0 == ~T6_E~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 24: Hoare triple {64311#false} assume !(0 == ~T7_E~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 25: Hoare triple {64311#false} assume !(0 == ~T8_E~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 26: Hoare triple {64311#false} assume !(0 == ~T9_E~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 27: Hoare triple {64311#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 28: Hoare triple {64311#false} assume !(0 == ~T11_E~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 29: Hoare triple {64311#false} assume !(0 == ~E_M~0); {64311#false} is VALID [2022-02-21 04:23:16,636 INFO L290 TraceCheckUtils]: 30: Hoare triple {64311#false} assume !(0 == ~E_1~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 31: Hoare triple {64311#false} assume !(0 == ~E_2~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 32: Hoare triple {64311#false} assume !(0 == ~E_3~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 33: Hoare triple {64311#false} assume !(0 == ~E_4~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 34: Hoare triple {64311#false} assume !(0 == ~E_5~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 35: Hoare triple {64311#false} assume 0 == ~E_6~0;~E_6~0 := 1; {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 36: Hoare triple {64311#false} assume !(0 == ~E_7~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 37: Hoare triple {64311#false} assume !(0 == ~E_8~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 38: Hoare triple {64311#false} assume !(0 == ~E_9~0); {64311#false} is VALID [2022-02-21 04:23:16,637 INFO L290 TraceCheckUtils]: 39: Hoare triple {64311#false} assume !(0 == ~E_10~0); {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 40: Hoare triple {64311#false} assume !(0 == ~E_11~0); {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 41: Hoare triple {64311#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 42: Hoare triple {64311#false} assume 1 == ~m_pc~0; {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 43: Hoare triple {64311#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 44: Hoare triple {64311#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 45: Hoare triple {64311#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 46: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp~1#1); {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 47: Hoare triple {64311#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {64311#false} is VALID [2022-02-21 04:23:16,638 INFO L290 TraceCheckUtils]: 48: Hoare triple {64311#false} assume !(1 == ~t1_pc~0); {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 49: Hoare triple {64311#false} is_transmit1_triggered_~__retres1~1#1 := 0; {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 50: Hoare triple {64311#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 51: Hoare triple {64311#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 52: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___0~0#1); {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 53: Hoare triple {64311#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 54: Hoare triple {64311#false} assume 1 == ~t2_pc~0; {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 55: Hoare triple {64311#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 56: Hoare triple {64311#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {64311#false} is VALID [2022-02-21 04:23:16,639 INFO L290 TraceCheckUtils]: 57: Hoare triple {64311#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 58: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___1~0#1); {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 59: Hoare triple {64311#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 60: Hoare triple {64311#false} assume !(1 == ~t3_pc~0); {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 61: Hoare triple {64311#false} is_transmit3_triggered_~__retres1~3#1 := 0; {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 62: Hoare triple {64311#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 63: Hoare triple {64311#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 64: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___2~0#1); {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 65: Hoare triple {64311#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {64311#false} is VALID [2022-02-21 04:23:16,640 INFO L290 TraceCheckUtils]: 66: Hoare triple {64311#false} assume 1 == ~t4_pc~0; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 67: Hoare triple {64311#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 68: Hoare triple {64311#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 69: Hoare triple {64311#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 70: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___3~0#1); {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 71: Hoare triple {64311#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 72: Hoare triple {64311#false} assume 1 == ~t5_pc~0; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 73: Hoare triple {64311#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 74: Hoare triple {64311#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {64311#false} is VALID [2022-02-21 04:23:16,641 INFO L290 TraceCheckUtils]: 75: Hoare triple {64311#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 76: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___4~0#1); {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 77: Hoare triple {64311#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 78: Hoare triple {64311#false} assume !(1 == ~t6_pc~0); {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 79: Hoare triple {64311#false} is_transmit6_triggered_~__retres1~6#1 := 0; {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 80: Hoare triple {64311#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 81: Hoare triple {64311#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 82: Hoare triple {64311#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 83: Hoare triple {64311#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {64311#false} is VALID [2022-02-21 04:23:16,642 INFO L290 TraceCheckUtils]: 84: Hoare triple {64311#false} assume 1 == ~t7_pc~0; {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 85: Hoare triple {64311#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 86: Hoare triple {64311#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 87: Hoare triple {64311#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 88: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___6~0#1); {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 89: Hoare triple {64311#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 90: Hoare triple {64311#false} assume !(1 == ~t8_pc~0); {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 91: Hoare triple {64311#false} is_transmit8_triggered_~__retres1~8#1 := 0; {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 92: Hoare triple {64311#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {64311#false} is VALID [2022-02-21 04:23:16,643 INFO L290 TraceCheckUtils]: 93: Hoare triple {64311#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 94: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___7~0#1); {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 95: Hoare triple {64311#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 96: Hoare triple {64311#false} assume 1 == ~t9_pc~0; {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 97: Hoare triple {64311#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 98: Hoare triple {64311#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 99: Hoare triple {64311#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 100: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___8~0#1); {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 101: Hoare triple {64311#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {64311#false} is VALID [2022-02-21 04:23:16,644 INFO L290 TraceCheckUtils]: 102: Hoare triple {64311#false} assume !(1 == ~t10_pc~0); {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 103: Hoare triple {64311#false} is_transmit10_triggered_~__retres1~10#1 := 0; {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 104: Hoare triple {64311#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 105: Hoare triple {64311#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 106: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___9~0#1); {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 107: Hoare triple {64311#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 108: Hoare triple {64311#false} assume 1 == ~t11_pc~0; {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 109: Hoare triple {64311#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 110: Hoare triple {64311#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {64311#false} is VALID [2022-02-21 04:23:16,645 INFO L290 TraceCheckUtils]: 111: Hoare triple {64311#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 112: Hoare triple {64311#false} assume !(0 != activate_threads_~tmp___10~0#1); {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 113: Hoare triple {64311#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 114: Hoare triple {64311#false} assume !(1 == ~M_E~0); {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 115: Hoare triple {64311#false} assume !(1 == ~T1_E~0); {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 116: Hoare triple {64311#false} assume !(1 == ~T2_E~0); {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 117: Hoare triple {64311#false} assume !(1 == ~T3_E~0); {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 118: Hoare triple {64311#false} assume !(1 == ~T4_E~0); {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 119: Hoare triple {64311#false} assume !(1 == ~T5_E~0); {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 120: Hoare triple {64311#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {64311#false} is VALID [2022-02-21 04:23:16,646 INFO L290 TraceCheckUtils]: 121: Hoare triple {64311#false} assume !(1 == ~T7_E~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 122: Hoare triple {64311#false} assume !(1 == ~T8_E~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 123: Hoare triple {64311#false} assume !(1 == ~T9_E~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 124: Hoare triple {64311#false} assume !(1 == ~T10_E~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 125: Hoare triple {64311#false} assume !(1 == ~T11_E~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 126: Hoare triple {64311#false} assume !(1 == ~E_M~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 127: Hoare triple {64311#false} assume !(1 == ~E_1~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 128: Hoare triple {64311#false} assume 1 == ~E_2~0;~E_2~0 := 2; {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 129: Hoare triple {64311#false} assume !(1 == ~E_3~0); {64311#false} is VALID [2022-02-21 04:23:16,647 INFO L290 TraceCheckUtils]: 130: Hoare triple {64311#false} assume !(1 == ~E_4~0); {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 131: Hoare triple {64311#false} assume !(1 == ~E_5~0); {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 132: Hoare triple {64311#false} assume !(1 == ~E_6~0); {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 133: Hoare triple {64311#false} assume !(1 == ~E_7~0); {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 134: Hoare triple {64311#false} assume !(1 == ~E_8~0); {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 135: Hoare triple {64311#false} assume !(1 == ~E_9~0); {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 136: Hoare triple {64311#false} assume 1 == ~E_10~0;~E_10~0 := 2; {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 137: Hoare triple {64311#false} assume !(1 == ~E_11~0); {64311#false} is VALID [2022-02-21 04:23:16,648 INFO L290 TraceCheckUtils]: 138: Hoare triple {64311#false} assume { :end_inline_reset_delta_events } true; {64311#false} is VALID [2022-02-21 04:23:16,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,649 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,649 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654487244] [2022-02-21 04:23:16,649 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654487244] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,649 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,649 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,649 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417709641] [2022-02-21 04:23:16,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,650 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:16,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1092238964, now seen corresponding path program 1 times [2022-02-21 04:23:16,650 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,650 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801577990] [2022-02-21 04:23:16,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,677 INFO L290 TraceCheckUtils]: 0: Hoare triple {64313#true} assume !false; {64313#true} is VALID [2022-02-21 04:23:16,677 INFO L290 TraceCheckUtils]: 1: Hoare triple {64313#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 2: Hoare triple {64313#true} assume !false; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 3: Hoare triple {64313#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 4: Hoare triple {64313#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 5: Hoare triple {64313#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 6: Hoare triple {64313#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 7: Hoare triple {64313#true} assume !(0 != eval_~tmp~0#1); {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 8: Hoare triple {64313#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 9: Hoare triple {64313#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {64313#true} is VALID [2022-02-21 04:23:16,678 INFO L290 TraceCheckUtils]: 10: Hoare triple {64313#true} assume 0 == ~M_E~0;~M_E~0 := 1; {64313#true} is VALID [2022-02-21 04:23:16,679 INFO L290 TraceCheckUtils]: 11: Hoare triple {64313#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {64313#true} is VALID [2022-02-21 04:23:16,679 INFO L290 TraceCheckUtils]: 12: Hoare triple {64313#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,679 INFO L290 TraceCheckUtils]: 13: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,679 INFO L290 TraceCheckUtils]: 14: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,680 INFO L290 TraceCheckUtils]: 15: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,680 INFO L290 TraceCheckUtils]: 16: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,680 INFO L290 TraceCheckUtils]: 17: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,680 INFO L290 TraceCheckUtils]: 18: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,681 INFO L290 TraceCheckUtils]: 19: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,681 INFO L290 TraceCheckUtils]: 20: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,681 INFO L290 TraceCheckUtils]: 21: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,681 INFO L290 TraceCheckUtils]: 22: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,682 INFO L290 TraceCheckUtils]: 23: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,682 INFO L290 TraceCheckUtils]: 24: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,682 INFO L290 TraceCheckUtils]: 25: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,682 INFO L290 TraceCheckUtils]: 26: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,683 INFO L290 TraceCheckUtils]: 27: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,683 INFO L290 TraceCheckUtils]: 28: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,683 INFO L290 TraceCheckUtils]: 29: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,683 INFO L290 TraceCheckUtils]: 30: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,684 INFO L290 TraceCheckUtils]: 31: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,684 INFO L290 TraceCheckUtils]: 32: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,684 INFO L290 TraceCheckUtils]: 33: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,684 INFO L290 TraceCheckUtils]: 34: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,685 INFO L290 TraceCheckUtils]: 35: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,685 INFO L290 TraceCheckUtils]: 36: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,685 INFO L290 TraceCheckUtils]: 37: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,685 INFO L290 TraceCheckUtils]: 38: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,686 INFO L290 TraceCheckUtils]: 39: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,686 INFO L290 TraceCheckUtils]: 40: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,686 INFO L290 TraceCheckUtils]: 41: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,686 INFO L290 TraceCheckUtils]: 42: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,687 INFO L290 TraceCheckUtils]: 43: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,687 INFO L290 TraceCheckUtils]: 44: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,687 INFO L290 TraceCheckUtils]: 45: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,687 INFO L290 TraceCheckUtils]: 46: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,688 INFO L290 TraceCheckUtils]: 47: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,688 INFO L290 TraceCheckUtils]: 48: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,688 INFO L290 TraceCheckUtils]: 49: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,688 INFO L290 TraceCheckUtils]: 50: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,689 INFO L290 TraceCheckUtils]: 51: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,689 INFO L290 TraceCheckUtils]: 52: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,689 INFO L290 TraceCheckUtils]: 53: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,689 INFO L290 TraceCheckUtils]: 54: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,690 INFO L290 TraceCheckUtils]: 55: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,690 INFO L290 TraceCheckUtils]: 56: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,690 INFO L290 TraceCheckUtils]: 57: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,690 INFO L290 TraceCheckUtils]: 58: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,691 INFO L290 TraceCheckUtils]: 59: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,691 INFO L290 TraceCheckUtils]: 60: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,691 INFO L290 TraceCheckUtils]: 61: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,691 INFO L290 TraceCheckUtils]: 62: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,692 INFO L290 TraceCheckUtils]: 63: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,692 INFO L290 TraceCheckUtils]: 64: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,692 INFO L290 TraceCheckUtils]: 65: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,692 INFO L290 TraceCheckUtils]: 66: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,693 INFO L290 TraceCheckUtils]: 67: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,693 INFO L290 TraceCheckUtils]: 68: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,693 INFO L290 TraceCheckUtils]: 69: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,693 INFO L290 TraceCheckUtils]: 70: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,694 INFO L290 TraceCheckUtils]: 71: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,694 INFO L290 TraceCheckUtils]: 72: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,694 INFO L290 TraceCheckUtils]: 73: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,694 INFO L290 TraceCheckUtils]: 74: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,695 INFO L290 TraceCheckUtils]: 75: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,695 INFO L290 TraceCheckUtils]: 76: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,695 INFO L290 TraceCheckUtils]: 77: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,695 INFO L290 TraceCheckUtils]: 78: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,696 INFO L290 TraceCheckUtils]: 79: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,696 INFO L290 TraceCheckUtils]: 80: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,696 INFO L290 TraceCheckUtils]: 81: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,696 INFO L290 TraceCheckUtils]: 82: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,697 INFO L290 TraceCheckUtils]: 83: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,697 INFO L290 TraceCheckUtils]: 84: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,697 INFO L290 TraceCheckUtils]: 85: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,697 INFO L290 TraceCheckUtils]: 86: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,698 INFO L290 TraceCheckUtils]: 87: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,698 INFO L290 TraceCheckUtils]: 88: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,698 INFO L290 TraceCheckUtils]: 89: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,698 INFO L290 TraceCheckUtils]: 90: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,699 INFO L290 TraceCheckUtils]: 91: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,699 INFO L290 TraceCheckUtils]: 92: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,699 INFO L290 TraceCheckUtils]: 93: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,699 INFO L290 TraceCheckUtils]: 94: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,700 INFO L290 TraceCheckUtils]: 95: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,700 INFO L290 TraceCheckUtils]: 96: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,700 INFO L290 TraceCheckUtils]: 97: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,700 INFO L290 TraceCheckUtils]: 98: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,701 INFO L290 TraceCheckUtils]: 99: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,701 INFO L290 TraceCheckUtils]: 100: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,701 INFO L290 TraceCheckUtils]: 101: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,701 INFO L290 TraceCheckUtils]: 102: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,702 INFO L290 TraceCheckUtils]: 103: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,702 INFO L290 TraceCheckUtils]: 104: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,702 INFO L290 TraceCheckUtils]: 105: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,702 INFO L290 TraceCheckUtils]: 106: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,703 INFO L290 TraceCheckUtils]: 107: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,703 INFO L290 TraceCheckUtils]: 108: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {64315#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:16,703 INFO L290 TraceCheckUtils]: 109: Hoare triple {64315#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {64314#false} is VALID [2022-02-21 04:23:16,703 INFO L290 TraceCheckUtils]: 110: Hoare triple {64314#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,703 INFO L290 TraceCheckUtils]: 111: Hoare triple {64314#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,703 INFO L290 TraceCheckUtils]: 112: Hoare triple {64314#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 113: Hoare triple {64314#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 114: Hoare triple {64314#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 115: Hoare triple {64314#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 116: Hoare triple {64314#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 117: Hoare triple {64314#false} assume !(1 == ~T10_E~0); {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 118: Hoare triple {64314#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 119: Hoare triple {64314#false} assume 1 == ~E_M~0;~E_M~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,704 INFO L290 TraceCheckUtils]: 120: Hoare triple {64314#false} assume 1 == ~E_1~0;~E_1~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 121: Hoare triple {64314#false} assume 1 == ~E_2~0;~E_2~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 122: Hoare triple {64314#false} assume 1 == ~E_3~0;~E_3~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 123: Hoare triple {64314#false} assume 1 == ~E_4~0;~E_4~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 124: Hoare triple {64314#false} assume 1 == ~E_5~0;~E_5~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 125: Hoare triple {64314#false} assume !(1 == ~E_6~0); {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 126: Hoare triple {64314#false} assume 1 == ~E_7~0;~E_7~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 127: Hoare triple {64314#false} assume 1 == ~E_8~0;~E_8~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 128: Hoare triple {64314#false} assume 1 == ~E_9~0;~E_9~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 129: Hoare triple {64314#false} assume 1 == ~E_10~0;~E_10~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,705 INFO L290 TraceCheckUtils]: 130: Hoare triple {64314#false} assume 1 == ~E_11~0;~E_11~0 := 2; {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 131: Hoare triple {64314#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 132: Hoare triple {64314#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 133: Hoare triple {64314#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 134: Hoare triple {64314#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 135: Hoare triple {64314#false} assume !(0 == start_simulation_~tmp~3#1); {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 136: Hoare triple {64314#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 137: Hoare triple {64314#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {64314#false} is VALID [2022-02-21 04:23:16,706 INFO L290 TraceCheckUtils]: 138: Hoare triple {64314#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {64314#false} is VALID [2022-02-21 04:23:16,707 INFO L290 TraceCheckUtils]: 139: Hoare triple {64314#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {64314#false} is VALID [2022-02-21 04:23:16,707 INFO L290 TraceCheckUtils]: 140: Hoare triple {64314#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {64314#false} is VALID [2022-02-21 04:23:16,707 INFO L290 TraceCheckUtils]: 141: Hoare triple {64314#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {64314#false} is VALID [2022-02-21 04:23:16,707 INFO L290 TraceCheckUtils]: 142: Hoare triple {64314#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {64314#false} is VALID [2022-02-21 04:23:16,707 INFO L290 TraceCheckUtils]: 143: Hoare triple {64314#false} assume !(0 != start_simulation_~tmp___0~1#1); {64314#false} is VALID [2022-02-21 04:23:16,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,708 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,708 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801577990] [2022-02-21 04:23:16,708 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801577990] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,708 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,708 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,708 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791641314] [2022-02-21 04:23:16,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,709 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:16,709 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:16,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:16,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:16,709 INFO L87 Difference]: Start difference. First operand 1566 states and 2316 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,685 INFO L93 Difference]: Finished difference Result 1566 states and 2315 transitions. [2022-02-21 04:23:17,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:17,685 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,757 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:17,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2315 transitions. [2022-02-21 04:23:17,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:17,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2315 transitions. [2022-02-21 04:23:17,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-02-21 04:23:17,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-02-21 04:23:17,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2315 transitions. [2022-02-21 04:23:17,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:17,872 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-02-21 04:23:17,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2315 transitions. [2022-02-21 04:23:17,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-02-21 04:23:17,884 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:17,885 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1566 states and 2315 transitions. Second operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,886 INFO L74 IsIncluded]: Start isIncluded. First operand 1566 states and 2315 transitions. Second operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,887 INFO L87 Difference]: Start difference. First operand 1566 states and 2315 transitions. Second operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,967 INFO L93 Difference]: Finished difference Result 1566 states and 2315 transitions. [2022-02-21 04:23:17,967 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2315 transitions. [2022-02-21 04:23:17,969 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:17,969 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:17,970 INFO L74 IsIncluded]: Start isIncluded. First operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2315 transitions. [2022-02-21 04:23:17,971 INFO L87 Difference]: Start difference. First operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1566 states and 2315 transitions. [2022-02-21 04:23:18,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:18,026 INFO L93 Difference]: Finished difference Result 1566 states and 2315 transitions. [2022-02-21 04:23:18,026 INFO L276 IsEmpty]: Start isEmpty. Operand 1566 states and 2315 transitions. [2022-02-21 04:23:18,027 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:18,027 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:18,027 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:18,028 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:18,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:18,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2315 transitions. [2022-02-21 04:23:18,079 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-02-21 04:23:18,079 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-02-21 04:23:18,079 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:18,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2315 transitions. [2022-02-21 04:23:18,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-02-21 04:23:18,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:18,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:18,083 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:18,083 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:18,083 INFO L791 eck$LassoCheckResult]: Stem: 66617#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 66618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 67346#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67347#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66120#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 66121#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67356#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67321#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67322#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66469#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66470#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66876#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 67294#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66381#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66382#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 66267#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 66268#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67220#L1109 assume !(0 == ~M_E~0); 67242#L1109-2 assume !(0 == ~T1_E~0); 66274#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66275#L1119-1 assume !(0 == ~T3_E~0); 67298#L1124-1 assume !(0 == ~T4_E~0); 65937#L1129-1 assume !(0 == ~T5_E~0); 65938#L1134-1 assume !(0 == ~T6_E~0); 66549#L1139-1 assume !(0 == ~T7_E~0); 67226#L1144-1 assume !(0 == ~T8_E~0); 67098#L1149-1 assume !(0 == ~T9_E~0); 66042#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66043#L1159-1 assume !(0 == ~T11_E~0); 67084#L1164-1 assume !(0 == ~E_M~0); 66435#L1169-1 assume !(0 == ~E_1~0); 66324#L1174-1 assume !(0 == ~E_2~0); 66197#L1179-1 assume !(0 == ~E_3~0); 66124#L1184-1 assume !(0 == ~E_4~0); 66125#L1189-1 assume !(0 == ~E_5~0); 66156#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 66243#L1199-1 assume !(0 == ~E_7~0); 67106#L1204-1 assume !(0 == ~E_8~0); 67042#L1209-1 assume !(0 == ~E_9~0); 67043#L1214-1 assume !(0 == ~E_10~0); 67368#L1219-1 assume !(0 == ~E_11~0); 67441#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66452#L544 assume 1 == ~m_pc~0; 66453#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 67285#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67113#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66086#L1379 assume !(0 != activate_threads_~tmp~1#1); 66087#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66859#L563 assume !(1 == ~t1_pc~0); 66659#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65945#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65946#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66982#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 65941#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65942#L582 assume 1 == ~t2_pc~0; 66637#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66992#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66993#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67097#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 65974#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65975#L601 assume !(1 == ~t3_pc~0); 66653#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 66652#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67286#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67028#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 67029#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66972#L620 assume 1 == ~t4_pc~0; 65955#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65956#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66517#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66518#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 66873#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67061#L639 assume 1 == ~t5_pc~0; 66944#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66247#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66248#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66894#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 66895#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66824#L658 assume !(1 == ~t6_pc~0); 66449#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66450#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67019#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67348#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 67032#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66287#L677 assume 1 == ~t7_pc~0; 66288#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66190#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67191#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67315#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 67316#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67387#L696 assume !(1 == ~t8_pc~0); 66507#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66508#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67355#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67376#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 67422#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66926#L715 assume 1 == ~t9_pc~0; 66927#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66597#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66505#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66506#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 66915#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67188#L734 assume !(1 == ~t10_pc~0); 67189#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66407#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66408#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66426#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 67131#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66483#L753 assume 1 == ~t11_pc~0; 66484#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 67037#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66592#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66593#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 66743#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66799#L1237 assume !(1 == ~M_E~0); 66800#L1237-2 assume !(1 == ~T1_E~0); 67412#L1242-1 assume !(1 == ~T2_E~0); 66563#L1247-1 assume !(1 == ~T3_E~0); 66564#L1252-1 assume !(1 == ~T4_E~0); 66347#L1257-1 assume !(1 == ~T5_E~0); 66348#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67203#L1267-1 assume !(1 == ~T7_E~0); 67308#L1272-1 assume !(1 == ~T8_E~0); 66646#L1277-1 assume !(1 == ~T9_E~0); 66647#L1282-1 assume !(1 == ~T10_E~0); 67069#L1287-1 assume !(1 == ~T11_E~0); 67070#L1292-1 assume !(1 == ~E_M~0); 67031#L1297-1 assume !(1 == ~E_1~0); 66478#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 66479#L1307-1 assume !(1 == ~E_3~0); 67301#L1312-1 assume !(1 == ~E_4~0); 66689#L1317-1 assume !(1 == ~E_5~0); 66690#L1322-1 assume !(1 == ~E_6~0); 66422#L1327-1 assume !(1 == ~E_7~0); 66423#L1332-1 assume !(1 == ~E_8~0); 66981#L1337-1 assume !(1 == ~E_9~0); 66918#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 66919#L1347-1 assume !(1 == ~E_11~0); 67300#L1352-1 assume { :end_inline_reset_delta_events } true; 67187#L1678-2 [2022-02-21 04:23:18,083 INFO L793 eck$LassoCheckResult]: Loop: 67187#L1678-2 assume !false; 66973#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66974#L1084 assume !false; 66757#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 66758#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 66061#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 67076#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65987#L925 assume !(0 != eval_~tmp~0#1); 65989#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66103#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66104#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65958#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65959#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67033#L1119-3 assume !(0 == ~T3_E~0); 67034#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67055#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67056#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67234#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67292#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66462#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 66463#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66698#L1159-3 assume !(0 == ~T11_E~0); 66699#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66969#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66970#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67020#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67021#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67176#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66853#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 66223#L1199-3 assume !(0 == ~E_7~0); 66224#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66446#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65906#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65907#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66605#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66606#L544-39 assume 1 == ~m_pc~0; 66961#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65888#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66138#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66139#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 66295#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67163#L563-39 assume 1 == ~t1_pc~0; 67169#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 66041#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66937#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66938#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67435#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67278#L582-39 assume 1 == ~t2_pc~0; 66361#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66363#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66983#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66984#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66131#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65918#L601-39 assume !(1 == ~t3_pc~0); 65920#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 65969#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67127#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67263#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67167#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66821#L620-39 assume 1 == ~t4_pc~0; 66823#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67017#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67225#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67140#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67141#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67446#L639-39 assume 1 == ~t5_pc~0; 67253#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66567#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66144#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65947#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65948#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66856#L658-39 assume 1 == ~t6_pc~0; 66838#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66839#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65897#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65898#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 67013#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67014#L677-39 assume 1 == ~t7_pc~0; 66976#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66122#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66123#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66178#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 66179#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66742#L696-39 assume 1 == ~t8_pc~0; 66709#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66589#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66590#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66885#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66849#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66722#L715-39 assume 1 == ~t9_pc~0; 65921#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65922#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67133#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67447#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 67062#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67063#L734-39 assume !(1 == ~t10_pc~0); 66433#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 66434#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66745#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66076#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66077#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67324#L753-39 assume !(1 == ~t11_pc~0); 65996#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 65997#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67289#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66714#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66715#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66812#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 66813#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67087#L1242-3 assume !(1 == ~T2_E~0); 67088#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67307#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67007#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67008#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67290#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 67331#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 67419#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66147#L1282-3 assume !(1 == ~T10_E~0); 66148#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66058#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66059#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67194#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67195#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 67385#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 67443#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67109#L1322-3 assume !(1 == ~E_6~0); 67110#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66117#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66092#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66093#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 66785#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 66913#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 66914#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 66035#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 66305#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 67018#L1697 assume !(0 == start_simulation_~tmp~3#1); 66806#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 66807#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 66164#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 66929#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 66930#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66879#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66474#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 66475#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 67187#L1678-2 [2022-02-21 04:23:18,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:18,084 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2022-02-21 04:23:18,084 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:18,084 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782773449] [2022-02-21 04:23:18,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:18,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:18,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:18,110 INFO L290 TraceCheckUtils]: 0: Hoare triple {70583#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,110 INFO L290 TraceCheckUtils]: 1: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,111 INFO L290 TraceCheckUtils]: 2: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,111 INFO L290 TraceCheckUtils]: 3: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,111 INFO L290 TraceCheckUtils]: 4: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,111 INFO L290 TraceCheckUtils]: 5: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,112 INFO L290 TraceCheckUtils]: 6: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,112 INFO L290 TraceCheckUtils]: 7: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,112 INFO L290 TraceCheckUtils]: 8: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,112 INFO L290 TraceCheckUtils]: 9: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,113 INFO L290 TraceCheckUtils]: 10: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,113 INFO L290 TraceCheckUtils]: 11: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,113 INFO L290 TraceCheckUtils]: 12: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,113 INFO L290 TraceCheckUtils]: 13: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,114 INFO L290 TraceCheckUtils]: 14: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,114 INFO L290 TraceCheckUtils]: 15: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,114 INFO L290 TraceCheckUtils]: 16: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {70585#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:18,115 INFO L290 TraceCheckUtils]: 17: Hoare triple {70585#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {70586#(not (= ~T2_E~0 0))} is VALID [2022-02-21 04:23:18,115 INFO L290 TraceCheckUtils]: 18: Hoare triple {70586#(not (= ~T2_E~0 0))} assume !(0 == ~T1_E~0); {70586#(not (= ~T2_E~0 0))} is VALID [2022-02-21 04:23:18,115 INFO L290 TraceCheckUtils]: 19: Hoare triple {70586#(not (= ~T2_E~0 0))} assume 0 == ~T2_E~0;~T2_E~0 := 1; {70584#false} is VALID [2022-02-21 04:23:18,115 INFO L290 TraceCheckUtils]: 20: Hoare triple {70584#false} assume !(0 == ~T3_E~0); {70584#false} is VALID [2022-02-21 04:23:18,115 INFO L290 TraceCheckUtils]: 21: Hoare triple {70584#false} assume !(0 == ~T4_E~0); {70584#false} is VALID [2022-02-21 04:23:18,115 INFO L290 TraceCheckUtils]: 22: Hoare triple {70584#false} assume !(0 == ~T5_E~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 23: Hoare triple {70584#false} assume !(0 == ~T6_E~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 24: Hoare triple {70584#false} assume !(0 == ~T7_E~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 25: Hoare triple {70584#false} assume !(0 == ~T8_E~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 26: Hoare triple {70584#false} assume !(0 == ~T9_E~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 27: Hoare triple {70584#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 28: Hoare triple {70584#false} assume !(0 == ~T11_E~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 29: Hoare triple {70584#false} assume !(0 == ~E_M~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 30: Hoare triple {70584#false} assume !(0 == ~E_1~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 31: Hoare triple {70584#false} assume !(0 == ~E_2~0); {70584#false} is VALID [2022-02-21 04:23:18,116 INFO L290 TraceCheckUtils]: 32: Hoare triple {70584#false} assume !(0 == ~E_3~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 33: Hoare triple {70584#false} assume !(0 == ~E_4~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 34: Hoare triple {70584#false} assume !(0 == ~E_5~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 35: Hoare triple {70584#false} assume 0 == ~E_6~0;~E_6~0 := 1; {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 36: Hoare triple {70584#false} assume !(0 == ~E_7~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 37: Hoare triple {70584#false} assume !(0 == ~E_8~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 38: Hoare triple {70584#false} assume !(0 == ~E_9~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 39: Hoare triple {70584#false} assume !(0 == ~E_10~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 40: Hoare triple {70584#false} assume !(0 == ~E_11~0); {70584#false} is VALID [2022-02-21 04:23:18,117 INFO L290 TraceCheckUtils]: 41: Hoare triple {70584#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 42: Hoare triple {70584#false} assume 1 == ~m_pc~0; {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 43: Hoare triple {70584#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 44: Hoare triple {70584#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 45: Hoare triple {70584#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 46: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp~1#1); {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 47: Hoare triple {70584#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 48: Hoare triple {70584#false} assume !(1 == ~t1_pc~0); {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 49: Hoare triple {70584#false} is_transmit1_triggered_~__retres1~1#1 := 0; {70584#false} is VALID [2022-02-21 04:23:18,118 INFO L290 TraceCheckUtils]: 50: Hoare triple {70584#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 51: Hoare triple {70584#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 52: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___0~0#1); {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 53: Hoare triple {70584#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 54: Hoare triple {70584#false} assume 1 == ~t2_pc~0; {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 55: Hoare triple {70584#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 56: Hoare triple {70584#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 57: Hoare triple {70584#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 58: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___1~0#1); {70584#false} is VALID [2022-02-21 04:23:18,119 INFO L290 TraceCheckUtils]: 59: Hoare triple {70584#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 60: Hoare triple {70584#false} assume !(1 == ~t3_pc~0); {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 61: Hoare triple {70584#false} is_transmit3_triggered_~__retres1~3#1 := 0; {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 62: Hoare triple {70584#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 63: Hoare triple {70584#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 64: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___2~0#1); {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 65: Hoare triple {70584#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 66: Hoare triple {70584#false} assume 1 == ~t4_pc~0; {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 67: Hoare triple {70584#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {70584#false} is VALID [2022-02-21 04:23:18,120 INFO L290 TraceCheckUtils]: 68: Hoare triple {70584#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 69: Hoare triple {70584#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 70: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___3~0#1); {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 71: Hoare triple {70584#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 72: Hoare triple {70584#false} assume 1 == ~t5_pc~0; {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 73: Hoare triple {70584#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 74: Hoare triple {70584#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 75: Hoare triple {70584#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 76: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___4~0#1); {70584#false} is VALID [2022-02-21 04:23:18,121 INFO L290 TraceCheckUtils]: 77: Hoare triple {70584#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 78: Hoare triple {70584#false} assume !(1 == ~t6_pc~0); {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 79: Hoare triple {70584#false} is_transmit6_triggered_~__retres1~6#1 := 0; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 80: Hoare triple {70584#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 81: Hoare triple {70584#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 82: Hoare triple {70584#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 83: Hoare triple {70584#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 84: Hoare triple {70584#false} assume 1 == ~t7_pc~0; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 85: Hoare triple {70584#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {70584#false} is VALID [2022-02-21 04:23:18,122 INFO L290 TraceCheckUtils]: 86: Hoare triple {70584#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 87: Hoare triple {70584#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 88: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___6~0#1); {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 89: Hoare triple {70584#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 90: Hoare triple {70584#false} assume !(1 == ~t8_pc~0); {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 91: Hoare triple {70584#false} is_transmit8_triggered_~__retres1~8#1 := 0; {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 92: Hoare triple {70584#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 93: Hoare triple {70584#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 94: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___7~0#1); {70584#false} is VALID [2022-02-21 04:23:18,123 INFO L290 TraceCheckUtils]: 95: Hoare triple {70584#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 96: Hoare triple {70584#false} assume 1 == ~t9_pc~0; {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 97: Hoare triple {70584#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 98: Hoare triple {70584#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 99: Hoare triple {70584#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 100: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___8~0#1); {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 101: Hoare triple {70584#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 102: Hoare triple {70584#false} assume !(1 == ~t10_pc~0); {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 103: Hoare triple {70584#false} is_transmit10_triggered_~__retres1~10#1 := 0; {70584#false} is VALID [2022-02-21 04:23:18,124 INFO L290 TraceCheckUtils]: 104: Hoare triple {70584#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 105: Hoare triple {70584#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 106: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___9~0#1); {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 107: Hoare triple {70584#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 108: Hoare triple {70584#false} assume 1 == ~t11_pc~0; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 109: Hoare triple {70584#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 110: Hoare triple {70584#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 111: Hoare triple {70584#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 112: Hoare triple {70584#false} assume !(0 != activate_threads_~tmp___10~0#1); {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 113: Hoare triple {70584#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70584#false} is VALID [2022-02-21 04:23:18,125 INFO L290 TraceCheckUtils]: 114: Hoare triple {70584#false} assume !(1 == ~M_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 115: Hoare triple {70584#false} assume !(1 == ~T1_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 116: Hoare triple {70584#false} assume !(1 == ~T2_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 117: Hoare triple {70584#false} assume !(1 == ~T3_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 118: Hoare triple {70584#false} assume !(1 == ~T4_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 119: Hoare triple {70584#false} assume !(1 == ~T5_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 120: Hoare triple {70584#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 121: Hoare triple {70584#false} assume !(1 == ~T7_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 122: Hoare triple {70584#false} assume !(1 == ~T8_E~0); {70584#false} is VALID [2022-02-21 04:23:18,126 INFO L290 TraceCheckUtils]: 123: Hoare triple {70584#false} assume !(1 == ~T9_E~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 124: Hoare triple {70584#false} assume !(1 == ~T10_E~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 125: Hoare triple {70584#false} assume !(1 == ~T11_E~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 126: Hoare triple {70584#false} assume !(1 == ~E_M~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 127: Hoare triple {70584#false} assume !(1 == ~E_1~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 128: Hoare triple {70584#false} assume 1 == ~E_2~0;~E_2~0 := 2; {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 129: Hoare triple {70584#false} assume !(1 == ~E_3~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 130: Hoare triple {70584#false} assume !(1 == ~E_4~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 131: Hoare triple {70584#false} assume !(1 == ~E_5~0); {70584#false} is VALID [2022-02-21 04:23:18,127 INFO L290 TraceCheckUtils]: 132: Hoare triple {70584#false} assume !(1 == ~E_6~0); {70584#false} is VALID [2022-02-21 04:23:18,128 INFO L290 TraceCheckUtils]: 133: Hoare triple {70584#false} assume !(1 == ~E_7~0); {70584#false} is VALID [2022-02-21 04:23:18,128 INFO L290 TraceCheckUtils]: 134: Hoare triple {70584#false} assume !(1 == ~E_8~0); {70584#false} is VALID [2022-02-21 04:23:18,128 INFO L290 TraceCheckUtils]: 135: Hoare triple {70584#false} assume !(1 == ~E_9~0); {70584#false} is VALID [2022-02-21 04:23:18,128 INFO L290 TraceCheckUtils]: 136: Hoare triple {70584#false} assume 1 == ~E_10~0;~E_10~0 := 2; {70584#false} is VALID [2022-02-21 04:23:18,128 INFO L290 TraceCheckUtils]: 137: Hoare triple {70584#false} assume !(1 == ~E_11~0); {70584#false} is VALID [2022-02-21 04:23:18,128 INFO L290 TraceCheckUtils]: 138: Hoare triple {70584#false} assume { :end_inline_reset_delta_events } true; {70584#false} is VALID [2022-02-21 04:23:18,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:18,129 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:18,129 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782773449] [2022-02-21 04:23:18,129 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782773449] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:18,129 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:18,129 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:18,129 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65616398] [2022-02-21 04:23:18,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:18,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:18,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:18,130 INFO L85 PathProgramCache]: Analyzing trace with hash 1121573323, now seen corresponding path program 1 times [2022-02-21 04:23:18,130 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:18,130 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982259416] [2022-02-21 04:23:18,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:18,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:18,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:18,151 INFO L290 TraceCheckUtils]: 0: Hoare triple {70587#true} assume !false; {70587#true} is VALID [2022-02-21 04:23:18,151 INFO L290 TraceCheckUtils]: 1: Hoare triple {70587#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {70587#true} is VALID [2022-02-21 04:23:18,151 INFO L290 TraceCheckUtils]: 2: Hoare triple {70587#true} assume !false; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 3: Hoare triple {70587#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 4: Hoare triple {70587#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 5: Hoare triple {70587#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 6: Hoare triple {70587#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 7: Hoare triple {70587#true} assume !(0 != eval_~tmp~0#1); {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 8: Hoare triple {70587#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 9: Hoare triple {70587#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 10: Hoare triple {70587#true} assume 0 == ~M_E~0;~M_E~0 := 1; {70587#true} is VALID [2022-02-21 04:23:18,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {70587#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {70587#true} is VALID [2022-02-21 04:23:18,153 INFO L290 TraceCheckUtils]: 12: Hoare triple {70587#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,153 INFO L290 TraceCheckUtils]: 13: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T3_E~0); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,153 INFO L290 TraceCheckUtils]: 14: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,154 INFO L290 TraceCheckUtils]: 15: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,154 INFO L290 TraceCheckUtils]: 16: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,154 INFO L290 TraceCheckUtils]: 17: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,154 INFO L290 TraceCheckUtils]: 18: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,155 INFO L290 TraceCheckUtils]: 19: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,155 INFO L290 TraceCheckUtils]: 20: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,155 INFO L290 TraceCheckUtils]: 21: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T11_E~0); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,155 INFO L290 TraceCheckUtils]: 22: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,156 INFO L290 TraceCheckUtils]: 23: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,156 INFO L290 TraceCheckUtils]: 24: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,156 INFO L290 TraceCheckUtils]: 25: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,156 INFO L290 TraceCheckUtils]: 26: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,157 INFO L290 TraceCheckUtils]: 27: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,157 INFO L290 TraceCheckUtils]: 28: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,157 INFO L290 TraceCheckUtils]: 29: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_7~0); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,160 INFO L290 TraceCheckUtils]: 30: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,161 INFO L290 TraceCheckUtils]: 31: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,161 INFO L290 TraceCheckUtils]: 32: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,161 INFO L290 TraceCheckUtils]: 33: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,161 INFO L290 TraceCheckUtils]: 34: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,162 INFO L290 TraceCheckUtils]: 35: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,162 INFO L290 TraceCheckUtils]: 36: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,162 INFO L290 TraceCheckUtils]: 37: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,162 INFO L290 TraceCheckUtils]: 38: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,162 INFO L290 TraceCheckUtils]: 39: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,163 INFO L290 TraceCheckUtils]: 40: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,163 INFO L290 TraceCheckUtils]: 41: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,163 INFO L290 TraceCheckUtils]: 42: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,163 INFO L290 TraceCheckUtils]: 43: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,164 INFO L290 TraceCheckUtils]: 44: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,164 INFO L290 TraceCheckUtils]: 45: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,164 INFO L290 TraceCheckUtils]: 46: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,164 INFO L290 TraceCheckUtils]: 47: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,164 INFO L290 TraceCheckUtils]: 48: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,165 INFO L290 TraceCheckUtils]: 49: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,165 INFO L290 TraceCheckUtils]: 50: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,165 INFO L290 TraceCheckUtils]: 51: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,165 INFO L290 TraceCheckUtils]: 52: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,166 INFO L290 TraceCheckUtils]: 53: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,166 INFO L290 TraceCheckUtils]: 54: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,166 INFO L290 TraceCheckUtils]: 55: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,166 INFO L290 TraceCheckUtils]: 56: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,166 INFO L290 TraceCheckUtils]: 57: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,167 INFO L290 TraceCheckUtils]: 58: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,167 INFO L290 TraceCheckUtils]: 59: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,167 INFO L290 TraceCheckUtils]: 60: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,167 INFO L290 TraceCheckUtils]: 61: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,168 INFO L290 TraceCheckUtils]: 62: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,168 INFO L290 TraceCheckUtils]: 63: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,168 INFO L290 TraceCheckUtils]: 64: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,168 INFO L290 TraceCheckUtils]: 65: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,168 INFO L290 TraceCheckUtils]: 66: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,169 INFO L290 TraceCheckUtils]: 67: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,169 INFO L290 TraceCheckUtils]: 68: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,169 INFO L290 TraceCheckUtils]: 69: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,169 INFO L290 TraceCheckUtils]: 70: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,170 INFO L290 TraceCheckUtils]: 71: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,170 INFO L290 TraceCheckUtils]: 72: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,170 INFO L290 TraceCheckUtils]: 73: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,170 INFO L290 TraceCheckUtils]: 74: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,170 INFO L290 TraceCheckUtils]: 75: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,171 INFO L290 TraceCheckUtils]: 76: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,171 INFO L290 TraceCheckUtils]: 77: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,171 INFO L290 TraceCheckUtils]: 78: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,171 INFO L290 TraceCheckUtils]: 79: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,172 INFO L290 TraceCheckUtils]: 80: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,172 INFO L290 TraceCheckUtils]: 81: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,172 INFO L290 TraceCheckUtils]: 82: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,172 INFO L290 TraceCheckUtils]: 83: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,172 INFO L290 TraceCheckUtils]: 84: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,173 INFO L290 TraceCheckUtils]: 85: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,173 INFO L290 TraceCheckUtils]: 86: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,173 INFO L290 TraceCheckUtils]: 87: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,173 INFO L290 TraceCheckUtils]: 88: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,174 INFO L290 TraceCheckUtils]: 89: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,174 INFO L290 TraceCheckUtils]: 90: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,174 INFO L290 TraceCheckUtils]: 91: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,174 INFO L290 TraceCheckUtils]: 92: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,174 INFO L290 TraceCheckUtils]: 93: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,175 INFO L290 TraceCheckUtils]: 94: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,175 INFO L290 TraceCheckUtils]: 95: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,175 INFO L290 TraceCheckUtils]: 96: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,175 INFO L290 TraceCheckUtils]: 97: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,176 INFO L290 TraceCheckUtils]: 98: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,176 INFO L290 TraceCheckUtils]: 99: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,176 INFO L290 TraceCheckUtils]: 100: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,176 INFO L290 TraceCheckUtils]: 101: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,176 INFO L290 TraceCheckUtils]: 102: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,177 INFO L290 TraceCheckUtils]: 103: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,177 INFO L290 TraceCheckUtils]: 104: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,177 INFO L290 TraceCheckUtils]: 105: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,177 INFO L290 TraceCheckUtils]: 106: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 107: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 108: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {70589#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 109: Hoare triple {70589#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 110: Hoare triple {70588#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 111: Hoare triple {70588#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 112: Hoare triple {70588#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 113: Hoare triple {70588#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 114: Hoare triple {70588#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 115: Hoare triple {70588#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 116: Hoare triple {70588#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,178 INFO L290 TraceCheckUtils]: 117: Hoare triple {70588#false} assume !(1 == ~T10_E~0); {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 118: Hoare triple {70588#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 119: Hoare triple {70588#false} assume 1 == ~E_M~0;~E_M~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 120: Hoare triple {70588#false} assume 1 == ~E_1~0;~E_1~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 121: Hoare triple {70588#false} assume 1 == ~E_2~0;~E_2~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 122: Hoare triple {70588#false} assume 1 == ~E_3~0;~E_3~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 123: Hoare triple {70588#false} assume 1 == ~E_4~0;~E_4~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 124: Hoare triple {70588#false} assume 1 == ~E_5~0;~E_5~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 125: Hoare triple {70588#false} assume !(1 == ~E_6~0); {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 126: Hoare triple {70588#false} assume 1 == ~E_7~0;~E_7~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 127: Hoare triple {70588#false} assume 1 == ~E_8~0;~E_8~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 128: Hoare triple {70588#false} assume 1 == ~E_9~0;~E_9~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 129: Hoare triple {70588#false} assume 1 == ~E_10~0;~E_10~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 130: Hoare triple {70588#false} assume 1 == ~E_11~0;~E_11~0 := 2; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 131: Hoare triple {70588#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 132: Hoare triple {70588#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 133: Hoare triple {70588#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {70588#false} is VALID [2022-02-21 04:23:18,179 INFO L290 TraceCheckUtils]: 134: Hoare triple {70588#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 135: Hoare triple {70588#false} assume !(0 == start_simulation_~tmp~3#1); {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 136: Hoare triple {70588#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 137: Hoare triple {70588#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 138: Hoare triple {70588#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 139: Hoare triple {70588#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 140: Hoare triple {70588#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 141: Hoare triple {70588#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 142: Hoare triple {70588#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L290 TraceCheckUtils]: 143: Hoare triple {70588#false} assume !(0 != start_simulation_~tmp___0~1#1); {70588#false} is VALID [2022-02-21 04:23:18,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:18,180 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:18,180 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982259416] [2022-02-21 04:23:18,181 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982259416] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:18,181 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:18,181 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:18,181 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139283350] [2022-02-21 04:23:18,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:18,181 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:18,181 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:18,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:18,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:18,182 INFO L87 Difference]: Start difference. First operand 1566 states and 2315 transitions. cyclomatic complexity: 750 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:20,844 INFO L93 Difference]: Finished difference Result 2895 states and 4265 transitions. [2022-02-21 04:23:20,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:20,844 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:20,917 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:20,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,092 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2022-02-21 04:23:21,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2895 states to 2895 states and 4265 transitions. [2022-02-21 04:23:21,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2895 [2022-02-21 04:23:21,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2895 [2022-02-21 04:23:21,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:21,267 INFO L681 BuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-02-21 04:23:21,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2895 to 2895. [2022-02-21 04:23:21,293 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:21,296 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2895 states and 4265 transitions. Second operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,298 INFO L74 IsIncluded]: Start isIncluded. First operand 2895 states and 4265 transitions. Second operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,300 INFO L87 Difference]: Start difference. First operand 2895 states and 4265 transitions. Second operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,472 INFO L93 Difference]: Finished difference Result 2895 states and 4265 transitions. [2022-02-21 04:23:21,472 INFO L276 IsEmpty]: Start isEmpty. Operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,474 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,474 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,477 INFO L74 IsIncluded]: Start isIncluded. First operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,478 INFO L87 Difference]: Start difference. First operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,646 INFO L93 Difference]: Finished difference Result 2895 states and 4265 transitions. [2022-02-21 04:23:21,646 INFO L276 IsEmpty]: Start isEmpty. Operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,649 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,649 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,649 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:21,649 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:21,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2895 states to 2895 states and 4265 transitions. [2022-02-21 04:23:21,823 INFO L704 BuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-02-21 04:23:21,823 INFO L587 BuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-02-21 04:23:21,823 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:21,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2895 states and 4265 transitions. [2022-02-21 04:23:21,828 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2022-02-21 04:23:21,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:21,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:21,829 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,829 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,829 INFO L791 eck$LassoCheckResult]: Stem: 74226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 74227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 74995#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74996#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73725#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 73726#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75006#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74969#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74970#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74074#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74075#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74489#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74935#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 73986#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 73987#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 73872#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 73873#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74855#L1109 assume !(0 == ~M_E~0); 74877#L1109-2 assume !(0 == ~T1_E~0); 73879#L1114-1 assume !(0 == ~T2_E~0); 73880#L1119-1 assume !(0 == ~T3_E~0); 74939#L1124-1 assume !(0 == ~T4_E~0); 73540#L1129-1 assume !(0 == ~T5_E~0); 73541#L1134-1 assume !(0 == ~T6_E~0); 74156#L1139-1 assume !(0 == ~T7_E~0); 74861#L1144-1 assume !(0 == ~T8_E~0); 74724#L1149-1 assume !(0 == ~T9_E~0); 73647#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 73648#L1159-1 assume !(0 == ~T11_E~0); 74708#L1164-1 assume !(0 == ~E_M~0); 74040#L1169-1 assume !(0 == ~E_1~0); 73929#L1174-1 assume !(0 == ~E_2~0); 73802#L1179-1 assume !(0 == ~E_3~0); 73729#L1184-1 assume !(0 == ~E_4~0); 73730#L1189-1 assume !(0 == ~E_5~0); 73761#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 73848#L1199-1 assume !(0 == ~E_7~0); 74732#L1204-1 assume !(0 == ~E_8~0); 74665#L1209-1 assume !(0 == ~E_9~0); 74666#L1214-1 assume !(0 == ~E_10~0); 75019#L1219-1 assume !(0 == ~E_11~0); 75111#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74057#L544 assume 1 == ~m_pc~0; 74058#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 74926#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74739#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73691#L1379 assume !(0 != activate_threads_~tmp~1#1); 73692#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74472#L563 assume !(1 == ~t1_pc~0); 74268#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73550#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73551#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 74600#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 73546#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73547#L582 assume 1 == ~t2_pc~0; 74246#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 74613#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74614#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74723#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 73579#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73580#L601 assume !(1 == ~t3_pc~0); 74262#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74261#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74927#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74650#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 74651#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74590#L620 assume 1 == ~t4_pc~0; 73560#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73561#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74122#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74123#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 74486#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74683#L639 assume 1 == ~t5_pc~0; 74559#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73852#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73853#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74507#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 74508#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74435#L658 assume !(1 == ~t6_pc~0); 74054#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 74055#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74640#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74997#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 74655#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73892#L677 assume 1 == ~t7_pc~0; 73893#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 73795#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74824#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74960#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 74961#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75040#L696 assume !(1 == ~t8_pc~0); 74112#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 74113#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75005#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75027#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 75083#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74541#L715 assume 1 == ~t9_pc~0; 74542#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74206#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74110#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74111#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 74528#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74819#L734 assume !(1 == ~t10_pc~0); 74820#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 74012#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74013#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74031#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 74758#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74088#L753 assume 1 == ~t11_pc~0; 74089#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 74660#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74201#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74202#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 74352#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74409#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 74410#L1237-2 assume !(1 == ~T1_E~0); 75194#L1242-1 assume !(1 == ~T2_E~0); 75104#L1247-1 assume !(1 == ~T3_E~0); 75193#L1252-1 assume !(1 == ~T4_E~0); 75188#L1257-1 assume !(1 == ~T5_E~0); 75183#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74950#L1267-1 assume !(1 == ~T7_E~0); 74951#L1272-1 assume !(1 == ~T8_E~0); 74255#L1277-1 assume !(1 == ~T9_E~0); 74256#L1282-1 assume !(1 == ~T10_E~0); 74693#L1287-1 assume !(1 == ~T11_E~0); 74694#L1292-1 assume !(1 == ~E_M~0); 74653#L1297-1 assume !(1 == ~E_1~0); 74654#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 75169#L1307-1 assume !(1 == ~E_3~0); 75168#L1312-1 assume !(1 == ~E_4~0); 75167#L1317-1 assume !(1 == ~E_5~0); 75166#L1322-1 assume !(1 == ~E_6~0); 75165#L1327-1 assume !(1 == ~E_7~0); 75164#L1332-1 assume !(1 == ~E_8~0); 75163#L1337-1 assume !(1 == ~E_9~0); 75162#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 75161#L1347-1 assume !(1 == ~E_11~0); 75156#L1352-1 assume { :end_inline_reset_delta_events } true; 75155#L1678-2 [2022-02-21 04:23:21,830 INFO L793 eck$LassoCheckResult]: Loop: 75155#L1678-2 assume !false; 75149#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75146#L1084 assume !false; 75145#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 75036#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 73666#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 75100#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 75132#L925 assume !(0 != eval_~tmp~0#1); 75131#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75130#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75128#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 75129#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76347#L1114-3 assume !(0 == ~T2_E~0); 76346#L1119-3 assume !(0 == ~T3_E~0); 76345#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76344#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76343#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76342#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76341#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 76340#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 76339#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 76338#L1159-3 assume !(0 == ~T11_E~0); 76337#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 76336#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76335#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76334#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76333#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76332#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76331#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76330#L1199-3 assume !(0 == ~E_7~0); 76329#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76328#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76327#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76326#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 76325#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76324#L544-39 assume !(1 == ~m_pc~0); 76323#L544-41 is_master_triggered_~__retres1~0#1 := 0; 76321#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76320#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76319#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 76318#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76317#L563-39 assume 1 == ~t1_pc~0; 76315#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76314#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76313#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76312#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76311#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76310#L582-39 assume 1 == ~t2_pc~0; 76309#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76307#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76306#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76305#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76304#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76303#L601-39 assume 1 == ~t3_pc~0; 76301#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76300#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76299#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76298#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76297#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76296#L620-39 assume 1 == ~t4_pc~0; 76295#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76293#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76292#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76291#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76290#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76289#L639-39 assume !(1 == ~t5_pc~0); 76288#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 76286#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76285#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76284#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76283#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76282#L658-39 assume 1 == ~t6_pc~0; 76281#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76279#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76278#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76277#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76276#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76275#L677-39 assume 1 == ~t7_pc~0; 76273#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76272#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74908#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73783#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 73784#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74354#L696-39 assume !(1 == ~t8_pc~0); 74319#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 74198#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74199#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 74498#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 74461#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74333#L715-39 assume 1 == ~t9_pc~0; 73528#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73529#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74760#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75127#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 74686#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74687#L734-39 assume 1 == ~t10_pc~0; 74609#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 74039#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74355#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 73681#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 73682#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74973#L753-39 assume !(1 == ~t11_pc~0); 73601#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 73602#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74930#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74323#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 74324#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74427#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 74428#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74711#L1242-3 assume !(1 == ~T2_E~0); 74712#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74949#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74629#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 74630#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74931#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 74979#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75080#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 73753#L1282-3 assume !(1 == ~T10_E~0); 73754#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73663#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 73664#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 74830#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 74831#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75038#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75119#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75120#L1322-3 assume !(1 == ~E_6~0); 75831#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75830#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75829#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 75828#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 75827#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 75826#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 74826#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 73645#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 73910#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 74641#L1697 assume !(0 == start_simulation_~tmp~3#1); 74910#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 75076#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 73769#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 74544#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 74545#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74492#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74081#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 74082#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 75155#L1678-2 [2022-02-21 04:23:21,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,830 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2022-02-21 04:23:21,830 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,831 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140877571] [2022-02-21 04:23:21,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,854 INFO L290 TraceCheckUtils]: 0: Hoare triple {82175#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,854 INFO L290 TraceCheckUtils]: 1: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,854 INFO L290 TraceCheckUtils]: 2: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,855 INFO L290 TraceCheckUtils]: 3: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,855 INFO L290 TraceCheckUtils]: 4: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,855 INFO L290 TraceCheckUtils]: 5: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,855 INFO L290 TraceCheckUtils]: 6: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,856 INFO L290 TraceCheckUtils]: 7: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,856 INFO L290 TraceCheckUtils]: 8: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,856 INFO L290 TraceCheckUtils]: 9: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,856 INFO L290 TraceCheckUtils]: 10: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,857 INFO L290 TraceCheckUtils]: 11: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,857 INFO L290 TraceCheckUtils]: 12: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,857 INFO L290 TraceCheckUtils]: 13: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,857 INFO L290 TraceCheckUtils]: 14: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,858 INFO L290 TraceCheckUtils]: 15: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,858 INFO L290 TraceCheckUtils]: 16: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {82177#(= ~T10_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:21,858 INFO L290 TraceCheckUtils]: 17: Hoare triple {82177#(= ~T10_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,859 INFO L290 TraceCheckUtils]: 18: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T1_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,859 INFO L290 TraceCheckUtils]: 19: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T2_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,859 INFO L290 TraceCheckUtils]: 20: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T3_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,859 INFO L290 TraceCheckUtils]: 21: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T4_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,860 INFO L290 TraceCheckUtils]: 22: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T5_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,860 INFO L290 TraceCheckUtils]: 23: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T6_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,860 INFO L290 TraceCheckUtils]: 24: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T7_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,860 INFO L290 TraceCheckUtils]: 25: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T8_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 26: Hoare triple {82178#(not (= ~T10_E~0 0))} assume !(0 == ~T9_E~0); {82178#(not (= ~T10_E~0 0))} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 27: Hoare triple {82178#(not (= ~T10_E~0 0))} assume 0 == ~T10_E~0;~T10_E~0 := 1; {82176#false} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 28: Hoare triple {82176#false} assume !(0 == ~T11_E~0); {82176#false} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 29: Hoare triple {82176#false} assume !(0 == ~E_M~0); {82176#false} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 30: Hoare triple {82176#false} assume !(0 == ~E_1~0); {82176#false} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 31: Hoare triple {82176#false} assume !(0 == ~E_2~0); {82176#false} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 32: Hoare triple {82176#false} assume !(0 == ~E_3~0); {82176#false} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 33: Hoare triple {82176#false} assume !(0 == ~E_4~0); {82176#false} is VALID [2022-02-21 04:23:21,861 INFO L290 TraceCheckUtils]: 34: Hoare triple {82176#false} assume !(0 == ~E_5~0); {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 35: Hoare triple {82176#false} assume 0 == ~E_6~0;~E_6~0 := 1; {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 36: Hoare triple {82176#false} assume !(0 == ~E_7~0); {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 37: Hoare triple {82176#false} assume !(0 == ~E_8~0); {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 38: Hoare triple {82176#false} assume !(0 == ~E_9~0); {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 39: Hoare triple {82176#false} assume !(0 == ~E_10~0); {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 40: Hoare triple {82176#false} assume !(0 == ~E_11~0); {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 41: Hoare triple {82176#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82176#false} is VALID [2022-02-21 04:23:21,862 INFO L290 TraceCheckUtils]: 42: Hoare triple {82176#false} assume 1 == ~m_pc~0; {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 43: Hoare triple {82176#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 44: Hoare triple {82176#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 45: Hoare triple {82176#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 46: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp~1#1); {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 47: Hoare triple {82176#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 48: Hoare triple {82176#false} assume !(1 == ~t1_pc~0); {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 49: Hoare triple {82176#false} is_transmit1_triggered_~__retres1~1#1 := 0; {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 50: Hoare triple {82176#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82176#false} is VALID [2022-02-21 04:23:21,863 INFO L290 TraceCheckUtils]: 51: Hoare triple {82176#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 52: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___0~0#1); {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 53: Hoare triple {82176#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 54: Hoare triple {82176#false} assume 1 == ~t2_pc~0; {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 55: Hoare triple {82176#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 56: Hoare triple {82176#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 57: Hoare triple {82176#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 58: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___1~0#1); {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 59: Hoare triple {82176#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82176#false} is VALID [2022-02-21 04:23:21,864 INFO L290 TraceCheckUtils]: 60: Hoare triple {82176#false} assume !(1 == ~t3_pc~0); {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 61: Hoare triple {82176#false} is_transmit3_triggered_~__retres1~3#1 := 0; {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 62: Hoare triple {82176#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 63: Hoare triple {82176#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 64: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___2~0#1); {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 65: Hoare triple {82176#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 66: Hoare triple {82176#false} assume 1 == ~t4_pc~0; {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 67: Hoare triple {82176#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 68: Hoare triple {82176#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82176#false} is VALID [2022-02-21 04:23:21,865 INFO L290 TraceCheckUtils]: 69: Hoare triple {82176#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 70: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___3~0#1); {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 71: Hoare triple {82176#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 72: Hoare triple {82176#false} assume 1 == ~t5_pc~0; {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 73: Hoare triple {82176#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 74: Hoare triple {82176#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 75: Hoare triple {82176#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 76: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___4~0#1); {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 77: Hoare triple {82176#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82176#false} is VALID [2022-02-21 04:23:21,866 INFO L290 TraceCheckUtils]: 78: Hoare triple {82176#false} assume !(1 == ~t6_pc~0); {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 79: Hoare triple {82176#false} is_transmit6_triggered_~__retres1~6#1 := 0; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 80: Hoare triple {82176#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 81: Hoare triple {82176#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 82: Hoare triple {82176#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 83: Hoare triple {82176#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 84: Hoare triple {82176#false} assume 1 == ~t7_pc~0; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 85: Hoare triple {82176#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 86: Hoare triple {82176#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 87: Hoare triple {82176#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82176#false} is VALID [2022-02-21 04:23:21,867 INFO L290 TraceCheckUtils]: 88: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___6~0#1); {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 89: Hoare triple {82176#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 90: Hoare triple {82176#false} assume !(1 == ~t8_pc~0); {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 91: Hoare triple {82176#false} is_transmit8_triggered_~__retres1~8#1 := 0; {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 92: Hoare triple {82176#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 93: Hoare triple {82176#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 94: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___7~0#1); {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 95: Hoare triple {82176#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82176#false} is VALID [2022-02-21 04:23:21,868 INFO L290 TraceCheckUtils]: 96: Hoare triple {82176#false} assume 1 == ~t9_pc~0; {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 97: Hoare triple {82176#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 98: Hoare triple {82176#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 99: Hoare triple {82176#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 100: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___8~0#1); {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 101: Hoare triple {82176#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 102: Hoare triple {82176#false} assume !(1 == ~t10_pc~0); {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 103: Hoare triple {82176#false} is_transmit10_triggered_~__retres1~10#1 := 0; {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 104: Hoare triple {82176#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82176#false} is VALID [2022-02-21 04:23:21,869 INFO L290 TraceCheckUtils]: 105: Hoare triple {82176#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 106: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___9~0#1); {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 107: Hoare triple {82176#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 108: Hoare triple {82176#false} assume 1 == ~t11_pc~0; {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 109: Hoare triple {82176#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 110: Hoare triple {82176#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 111: Hoare triple {82176#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 112: Hoare triple {82176#false} assume !(0 != activate_threads_~tmp___10~0#1); {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 113: Hoare triple {82176#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82176#false} is VALID [2022-02-21 04:23:21,870 INFO L290 TraceCheckUtils]: 114: Hoare triple {82176#false} assume 1 == ~M_E~0;~M_E~0 := 2; {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 115: Hoare triple {82176#false} assume !(1 == ~T1_E~0); {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 116: Hoare triple {82176#false} assume !(1 == ~T2_E~0); {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 117: Hoare triple {82176#false} assume !(1 == ~T3_E~0); {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 118: Hoare triple {82176#false} assume !(1 == ~T4_E~0); {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 119: Hoare triple {82176#false} assume !(1 == ~T5_E~0); {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 120: Hoare triple {82176#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 121: Hoare triple {82176#false} assume !(1 == ~T7_E~0); {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 122: Hoare triple {82176#false} assume !(1 == ~T8_E~0); {82176#false} is VALID [2022-02-21 04:23:21,871 INFO L290 TraceCheckUtils]: 123: Hoare triple {82176#false} assume !(1 == ~T9_E~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 124: Hoare triple {82176#false} assume !(1 == ~T10_E~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 125: Hoare triple {82176#false} assume !(1 == ~T11_E~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 126: Hoare triple {82176#false} assume !(1 == ~E_M~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 127: Hoare triple {82176#false} assume !(1 == ~E_1~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 128: Hoare triple {82176#false} assume 1 == ~E_2~0;~E_2~0 := 2; {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 129: Hoare triple {82176#false} assume !(1 == ~E_3~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 130: Hoare triple {82176#false} assume !(1 == ~E_4~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 131: Hoare triple {82176#false} assume !(1 == ~E_5~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 132: Hoare triple {82176#false} assume !(1 == ~E_6~0); {82176#false} is VALID [2022-02-21 04:23:21,872 INFO L290 TraceCheckUtils]: 133: Hoare triple {82176#false} assume !(1 == ~E_7~0); {82176#false} is VALID [2022-02-21 04:23:21,873 INFO L290 TraceCheckUtils]: 134: Hoare triple {82176#false} assume !(1 == ~E_8~0); {82176#false} is VALID [2022-02-21 04:23:21,873 INFO L290 TraceCheckUtils]: 135: Hoare triple {82176#false} assume !(1 == ~E_9~0); {82176#false} is VALID [2022-02-21 04:23:21,873 INFO L290 TraceCheckUtils]: 136: Hoare triple {82176#false} assume 1 == ~E_10~0;~E_10~0 := 2; {82176#false} is VALID [2022-02-21 04:23:21,873 INFO L290 TraceCheckUtils]: 137: Hoare triple {82176#false} assume !(1 == ~E_11~0); {82176#false} is VALID [2022-02-21 04:23:21,873 INFO L290 TraceCheckUtils]: 138: Hoare triple {82176#false} assume { :end_inline_reset_delta_events } true; {82176#false} is VALID [2022-02-21 04:23:21,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,874 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,874 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140877571] [2022-02-21 04:23:21,874 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140877571] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,874 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,874 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,874 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984950421] [2022-02-21 04:23:21,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,875 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:21,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,875 INFO L85 PathProgramCache]: Analyzing trace with hash 229934154, now seen corresponding path program 1 times [2022-02-21 04:23:21,875 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,875 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090283118] [2022-02-21 04:23:21,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,899 INFO L290 TraceCheckUtils]: 0: Hoare triple {82179#true} assume !false; {82179#true} is VALID [2022-02-21 04:23:21,899 INFO L290 TraceCheckUtils]: 1: Hoare triple {82179#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {82179#true} is VALID [2022-02-21 04:23:21,899 INFO L290 TraceCheckUtils]: 2: Hoare triple {82179#true} assume !false; {82179#true} is VALID [2022-02-21 04:23:21,899 INFO L290 TraceCheckUtils]: 3: Hoare triple {82179#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {82179#true} is VALID [2022-02-21 04:23:21,899 INFO L290 TraceCheckUtils]: 4: Hoare triple {82179#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {82179#true} is VALID [2022-02-21 04:23:21,899 INFO L290 TraceCheckUtils]: 5: Hoare triple {82179#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {82179#true} is VALID [2022-02-21 04:23:21,899 INFO L290 TraceCheckUtils]: 6: Hoare triple {82179#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 7: Hoare triple {82179#true} assume !(0 != eval_~tmp~0#1); {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 8: Hoare triple {82179#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 9: Hoare triple {82179#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 10: Hoare triple {82179#true} assume 0 == ~M_E~0;~M_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 11: Hoare triple {82179#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 12: Hoare triple {82179#true} assume !(0 == ~T2_E~0); {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 13: Hoare triple {82179#true} assume !(0 == ~T3_E~0); {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 14: Hoare triple {82179#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,900 INFO L290 TraceCheckUtils]: 15: Hoare triple {82179#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,901 INFO L290 TraceCheckUtils]: 16: Hoare triple {82179#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,901 INFO L290 TraceCheckUtils]: 17: Hoare triple {82179#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,901 INFO L290 TraceCheckUtils]: 18: Hoare triple {82179#true} assume 0 == ~T8_E~0;~T8_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,901 INFO L290 TraceCheckUtils]: 19: Hoare triple {82179#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {82179#true} is VALID [2022-02-21 04:23:21,901 INFO L290 TraceCheckUtils]: 20: Hoare triple {82179#true} assume 0 == ~T10_E~0;~T10_E~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,902 INFO L290 TraceCheckUtils]: 21: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(0 == ~T11_E~0); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,902 INFO L290 TraceCheckUtils]: 22: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,902 INFO L290 TraceCheckUtils]: 23: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,902 INFO L290 TraceCheckUtils]: 24: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,903 INFO L290 TraceCheckUtils]: 25: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,903 INFO L290 TraceCheckUtils]: 26: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,903 INFO L290 TraceCheckUtils]: 27: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,904 INFO L290 TraceCheckUtils]: 28: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,904 INFO L290 TraceCheckUtils]: 29: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(0 == ~E_7~0); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,904 INFO L290 TraceCheckUtils]: 30: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,904 INFO L290 TraceCheckUtils]: 31: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,905 INFO L290 TraceCheckUtils]: 32: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,905 INFO L290 TraceCheckUtils]: 33: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,905 INFO L290 TraceCheckUtils]: 34: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,906 INFO L290 TraceCheckUtils]: 35: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(1 == ~m_pc~0); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,906 INFO L290 TraceCheckUtils]: 36: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,906 INFO L290 TraceCheckUtils]: 37: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,906 INFO L290 TraceCheckUtils]: 38: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,907 INFO L290 TraceCheckUtils]: 39: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,907 INFO L290 TraceCheckUtils]: 40: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,907 INFO L290 TraceCheckUtils]: 41: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t1_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,908 INFO L290 TraceCheckUtils]: 42: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,908 INFO L290 TraceCheckUtils]: 43: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,908 INFO L290 TraceCheckUtils]: 44: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,908 INFO L290 TraceCheckUtils]: 45: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,909 INFO L290 TraceCheckUtils]: 46: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,909 INFO L290 TraceCheckUtils]: 47: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t2_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,909 INFO L290 TraceCheckUtils]: 48: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,910 INFO L290 TraceCheckUtils]: 49: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,910 INFO L290 TraceCheckUtils]: 50: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,910 INFO L290 TraceCheckUtils]: 51: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,910 INFO L290 TraceCheckUtils]: 52: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,911 INFO L290 TraceCheckUtils]: 53: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t3_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,911 INFO L290 TraceCheckUtils]: 54: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,911 INFO L290 TraceCheckUtils]: 55: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,912 INFO L290 TraceCheckUtils]: 56: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,912 INFO L290 TraceCheckUtils]: 57: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,912 INFO L290 TraceCheckUtils]: 58: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,912 INFO L290 TraceCheckUtils]: 59: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t4_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,913 INFO L290 TraceCheckUtils]: 60: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,913 INFO L290 TraceCheckUtils]: 61: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,913 INFO L290 TraceCheckUtils]: 62: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,914 INFO L290 TraceCheckUtils]: 63: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,914 INFO L290 TraceCheckUtils]: 64: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,914 INFO L290 TraceCheckUtils]: 65: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(1 == ~t5_pc~0); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,914 INFO L290 TraceCheckUtils]: 66: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,915 INFO L290 TraceCheckUtils]: 67: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,915 INFO L290 TraceCheckUtils]: 68: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,915 INFO L290 TraceCheckUtils]: 69: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,916 INFO L290 TraceCheckUtils]: 70: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,916 INFO L290 TraceCheckUtils]: 71: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t6_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,916 INFO L290 TraceCheckUtils]: 72: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,916 INFO L290 TraceCheckUtils]: 73: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,917 INFO L290 TraceCheckUtils]: 74: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,917 INFO L290 TraceCheckUtils]: 75: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,917 INFO L290 TraceCheckUtils]: 76: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,918 INFO L290 TraceCheckUtils]: 77: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t7_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,918 INFO L290 TraceCheckUtils]: 78: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,918 INFO L290 TraceCheckUtils]: 79: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,918 INFO L290 TraceCheckUtils]: 80: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,919 INFO L290 TraceCheckUtils]: 81: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,919 INFO L290 TraceCheckUtils]: 82: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,919 INFO L290 TraceCheckUtils]: 83: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(1 == ~t8_pc~0); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,920 INFO L290 TraceCheckUtils]: 84: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,920 INFO L290 TraceCheckUtils]: 85: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,920 INFO L290 TraceCheckUtils]: 86: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,920 INFO L290 TraceCheckUtils]: 87: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,921 INFO L290 TraceCheckUtils]: 88: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,921 INFO L290 TraceCheckUtils]: 89: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t9_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,921 INFO L290 TraceCheckUtils]: 90: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,922 INFO L290 TraceCheckUtils]: 91: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,922 INFO L290 TraceCheckUtils]: 92: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,922 INFO L290 TraceCheckUtils]: 93: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,922 INFO L290 TraceCheckUtils]: 94: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,923 INFO L290 TraceCheckUtils]: 95: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~t10_pc~0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,923 INFO L290 TraceCheckUtils]: 96: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,923 INFO L290 TraceCheckUtils]: 97: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,923 INFO L290 TraceCheckUtils]: 98: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,924 INFO L290 TraceCheckUtils]: 99: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,924 INFO L290 TraceCheckUtils]: 100: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,924 INFO L290 TraceCheckUtils]: 101: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(1 == ~t11_pc~0); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,925 INFO L290 TraceCheckUtils]: 102: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,925 INFO L290 TraceCheckUtils]: 103: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,925 INFO L290 TraceCheckUtils]: 104: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,925 INFO L290 TraceCheckUtils]: 105: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,926 INFO L290 TraceCheckUtils]: 106: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,926 INFO L290 TraceCheckUtils]: 107: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,926 INFO L290 TraceCheckUtils]: 108: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,927 INFO L290 TraceCheckUtils]: 109: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(1 == ~T2_E~0); {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,927 INFO L290 TraceCheckUtils]: 110: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,927 INFO L290 TraceCheckUtils]: 111: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,927 INFO L290 TraceCheckUtils]: 112: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,928 INFO L290 TraceCheckUtils]: 113: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,928 INFO L290 TraceCheckUtils]: 114: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,928 INFO L290 TraceCheckUtils]: 115: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T8_E~0;~T8_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,929 INFO L290 TraceCheckUtils]: 116: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {82181#(= (+ (- 1) ~T10_E~0) 0)} is VALID [2022-02-21 04:23:21,929 INFO L290 TraceCheckUtils]: 117: Hoare triple {82181#(= (+ (- 1) ~T10_E~0) 0)} assume !(1 == ~T10_E~0); {82180#false} is VALID [2022-02-21 04:23:21,929 INFO L290 TraceCheckUtils]: 118: Hoare triple {82180#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,929 INFO L290 TraceCheckUtils]: 119: Hoare triple {82180#false} assume 1 == ~E_M~0;~E_M~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,929 INFO L290 TraceCheckUtils]: 120: Hoare triple {82180#false} assume 1 == ~E_1~0;~E_1~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,929 INFO L290 TraceCheckUtils]: 121: Hoare triple {82180#false} assume 1 == ~E_2~0;~E_2~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,929 INFO L290 TraceCheckUtils]: 122: Hoare triple {82180#false} assume 1 == ~E_3~0;~E_3~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 123: Hoare triple {82180#false} assume 1 == ~E_4~0;~E_4~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 124: Hoare triple {82180#false} assume 1 == ~E_5~0;~E_5~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 125: Hoare triple {82180#false} assume !(1 == ~E_6~0); {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 126: Hoare triple {82180#false} assume 1 == ~E_7~0;~E_7~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 127: Hoare triple {82180#false} assume 1 == ~E_8~0;~E_8~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 128: Hoare triple {82180#false} assume 1 == ~E_9~0;~E_9~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 129: Hoare triple {82180#false} assume 1 == ~E_10~0;~E_10~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 130: Hoare triple {82180#false} assume 1 == ~E_11~0;~E_11~0 := 2; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 131: Hoare triple {82180#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {82180#false} is VALID [2022-02-21 04:23:21,930 INFO L290 TraceCheckUtils]: 132: Hoare triple {82180#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 133: Hoare triple {82180#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 134: Hoare triple {82180#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 135: Hoare triple {82180#false} assume !(0 == start_simulation_~tmp~3#1); {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 136: Hoare triple {82180#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 137: Hoare triple {82180#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 138: Hoare triple {82180#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 139: Hoare triple {82180#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 140: Hoare triple {82180#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {82180#false} is VALID [2022-02-21 04:23:21,931 INFO L290 TraceCheckUtils]: 141: Hoare triple {82180#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {82180#false} is VALID [2022-02-21 04:23:21,932 INFO L290 TraceCheckUtils]: 142: Hoare triple {82180#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {82180#false} is VALID [2022-02-21 04:23:21,932 INFO L290 TraceCheckUtils]: 143: Hoare triple {82180#false} assume !(0 != start_simulation_~tmp___0~1#1); {82180#false} is VALID [2022-02-21 04:23:21,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,932 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,932 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090283118] [2022-02-21 04:23:21,932 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090283118] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,933 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,933 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,933 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934657879] [2022-02-21 04:23:21,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,933 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:21,933 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:21,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:21,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:21,934 INFO L87 Difference]: Start difference. First operand 2895 states and 4265 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,915 INFO L93 Difference]: Finished difference Result 5541 states and 8142 transitions. [2022-02-21 04:23:24,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:24,916 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,003 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:25,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5541 states and 8142 transitions. [2022-02-21 04:23:25,614 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2022-02-21 04:23:26,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5541 states to 5541 states and 8142 transitions. [2022-02-21 04:23:26,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5541 [2022-02-21 04:23:26,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5541 [2022-02-21 04:23:26,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5541 states and 8142 transitions. [2022-02-21 04:23:26,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:26,264 INFO L681 BuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-02-21 04:23:26,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5541 states and 8142 transitions. [2022-02-21 04:23:26,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5541 to 5541. [2022-02-21 04:23:26,317 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:26,323 INFO L82 GeneralOperation]: Start isEquivalent. First operand 5541 states and 8142 transitions. Second operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,328 INFO L74 IsIncluded]: Start isIncluded. First operand 5541 states and 8142 transitions. Second operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,333 INFO L87 Difference]: Start difference. First operand 5541 states and 8142 transitions. Second operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,971 INFO L93 Difference]: Finished difference Result 5541 states and 8142 transitions. [2022-02-21 04:23:26,971 INFO L276 IsEmpty]: Start isEmpty. Operand 5541 states and 8142 transitions. [2022-02-21 04:23:26,976 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,976 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,981 INFO L74 IsIncluded]: Start isIncluded. First operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5541 states and 8142 transitions. [2022-02-21 04:23:26,984 INFO L87 Difference]: Start difference. First operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5541 states and 8142 transitions. [2022-02-21 04:23:27,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:27,627 INFO L93 Difference]: Finished difference Result 5541 states and 8142 transitions. [2022-02-21 04:23:27,627 INFO L276 IsEmpty]: Start isEmpty. Operand 5541 states and 8142 transitions. [2022-02-21 04:23:27,632 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:27,633 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:27,633 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:27,633 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:27,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5541 states to 5541 states and 8142 transitions. [2022-02-21 04:23:28,335 INFO L704 BuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-02-21 04:23:28,335 INFO L587 BuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-02-21 04:23:28,335 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:23:28,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5541 states and 8142 transitions. [2022-02-21 04:23:28,344 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2022-02-21 04:23:28,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:28,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:28,345 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:28,345 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:28,346 INFO L791 eck$LassoCheckResult]: Stem: 88467#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 88468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 89267#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89268#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87963#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 87964#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89280#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89236#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89237#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88316#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88317#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88732#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 89202#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 88226#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 88227#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 88111#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 88112#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89111#L1109 assume !(0 == ~M_E~0); 89138#L1109-2 assume !(0 == ~T1_E~0); 88118#L1114-1 assume !(0 == ~T2_E~0); 88119#L1119-1 assume !(0 == ~T3_E~0); 89206#L1124-1 assume !(0 == ~T4_E~0); 87778#L1129-1 assume !(0 == ~T5_E~0); 87779#L1134-1 assume !(0 == ~T6_E~0); 88398#L1139-1 assume !(0 == ~T7_E~0); 89120#L1144-1 assume !(0 == ~T8_E~0); 88973#L1149-1 assume !(0 == ~T9_E~0); 87885#L1154-1 assume !(0 == ~T10_E~0); 87886#L1159-1 assume !(0 == ~T11_E~0); 88958#L1164-1 assume !(0 == ~E_M~0); 88280#L1169-1 assume !(0 == ~E_1~0); 88169#L1174-1 assume !(0 == ~E_2~0); 88041#L1179-1 assume !(0 == ~E_3~0); 87967#L1184-1 assume !(0 == ~E_4~0); 87968#L1189-1 assume !(0 == ~E_5~0); 88000#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 88087#L1199-1 assume !(0 == ~E_7~0); 88981#L1204-1 assume !(0 == ~E_8~0); 88911#L1209-1 assume !(0 == ~E_9~0); 88912#L1214-1 assume !(0 == ~E_10~0); 89295#L1219-1 assume !(0 == ~E_11~0); 89401#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88297#L544 assume 1 == ~m_pc~0; 88298#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 89192#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88989#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87929#L1379 assume !(0 != activate_threads_~tmp~1#1); 87930#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88715#L563 assume !(1 == ~t1_pc~0); 88509#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87788#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87789#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88848#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 87784#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87785#L582 assume 1 == ~t2_pc~0; 88487#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88859#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88860#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88972#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 87817#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87818#L601 assume !(1 == ~t3_pc~0); 88503#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88502#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89193#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88896#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 88897#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88837#L620 assume 1 == ~t4_pc~0; 87798#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 87799#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88364#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88365#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 88729#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88929#L639 assume 1 == ~t5_pc~0; 88804#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 88091#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88092#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88750#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 88751#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88679#L658 assume !(1 == ~t6_pc~0); 88294#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 88295#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88886#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89269#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88900#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88131#L677 assume 1 == ~t7_pc~0; 88132#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88034#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89077#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 89228#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 89229#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89317#L696 assume !(1 == ~t8_pc~0); 88354#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 88355#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89279#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89304#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 89372#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88785#L715 assume 1 == ~t9_pc~0; 88786#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88447#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88352#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88353#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 88771#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89072#L734 assume !(1 == ~t10_pc~0); 89073#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 88252#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88253#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88271#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 89007#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88330#L753 assume 1 == ~t11_pc~0; 88331#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 88905#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88441#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88442#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 88593#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88652#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 88653#L1237-2 assume !(1 == ~T1_E~0); 89352#L1242-1 assume !(1 == ~T2_E~0); 89391#L1247-1 assume !(1 == ~T3_E~0); 89225#L1252-1 assume !(1 == ~T4_E~0); 89226#L1257-1 assume !(1 == ~T5_E~0); 89741#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 89739#L1267-1 assume !(1 == ~T7_E~0); 89737#L1272-1 assume !(1 == ~T8_E~0); 89701#L1277-1 assume !(1 == ~T9_E~0); 89699#L1282-1 assume !(1 == ~T10_E~0); 89696#L1287-1 assume !(1 == ~T11_E~0); 89694#L1292-1 assume !(1 == ~E_M~0); 89660#L1297-1 assume !(1 == ~E_1~0); 89617#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 89578#L1307-1 assume !(1 == ~E_3~0); 89573#L1312-1 assume !(1 == ~E_4~0); 89555#L1317-1 assume !(1 == ~E_5~0); 89538#L1322-1 assume !(1 == ~E_6~0); 89525#L1327-1 assume !(1 == ~E_7~0); 89505#L1332-1 assume !(1 == ~E_8~0); 89484#L1337-1 assume !(1 == ~E_9~0); 89482#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 89468#L1347-1 assume !(1 == ~E_11~0); 89459#L1352-1 assume { :end_inline_reset_delta_events } true; 89451#L1678-2 [2022-02-21 04:23:28,346 INFO L793 eck$LassoCheckResult]: Loop: 89451#L1678-2 assume !false; 89444#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89441#L1084 assume !false; 89440#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 89430#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 89427#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 89426#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 89424#L925 assume !(0 != eval_~tmp~0#1); 89423#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89422#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89420#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 89421#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 92590#L1114-3 assume !(0 == ~T2_E~0); 92589#L1119-3 assume !(0 == ~T3_E~0); 92588#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92587#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 92586#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 92585#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 92584#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 92583#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 92582#L1154-3 assume !(0 == ~T10_E~0); 92581#L1159-3 assume !(0 == ~T11_E~0); 92580#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 92579#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 92578#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 92577#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92576#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 92575#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 92574#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92573#L1199-3 assume !(0 == ~E_7~0); 92572#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 92571#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 90717#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 90716#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 90715#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88823#L544-39 assume !(1 == ~m_pc~0); 87730#L544-41 is_master_triggered_~__retres1~0#1 := 0; 87731#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87981#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87982#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 88139#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89042#L563-39 assume !(1 == ~t1_pc~0); 89363#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 92011#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88797#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88798#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89393#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89396#L582-39 assume !(1 == ~t2_pc~0); 88207#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 88208#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88952#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89146#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 89147#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90506#L601-39 assume 1 == ~t3_pc~0; 90503#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 90501#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90499#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 90497#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 90495#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88674#L620-39 assume !(1 == ~t4_pc~0); 88675#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 88885#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90299#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90296#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 90294#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90252#L639-39 assume !(1 == ~t5_pc~0); 90249#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 90246#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90244#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 90200#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 90198#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90196#L658-39 assume !(1 == ~t6_pc~0); 90193#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 90151#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90148#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90146#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 90144#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90105#L677-39 assume !(1 == ~t7_pc~0); 90061#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 90058#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90024#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 90022#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 90021#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89961#L696-39 assume !(1 == ~t8_pc~0); 89959#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 89956#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89953#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89951#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 89949#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89948#L715-39 assume !(1 == ~t9_pc~0); 89947#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 89945#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89944#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89943#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 89942#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89941#L734-39 assume 1 == ~t10_pc~0; 89939#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 89938#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89935#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 89933#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 89931#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 89929#L753-39 assume 1 == ~t11_pc~0; 88535#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 87840#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 89196#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89835#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 89833#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89831#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88671#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89829#L1242-3 assume !(1 == ~T2_E~0); 88963#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89826#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89788#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89786#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 89784#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 89753#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 89750#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89711#L1282-3 assume !(1 == ~T10_E~0); 89675#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89643#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 89640#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89638#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 89637#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 89636#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89635#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89634#L1322-3 assume !(1 == ~E_6~0); 89633#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89632#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89631#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89630#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89629#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 89627#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 89590#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 89587#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 89585#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 89583#L1697 assume !(0 == start_simulation_~tmp~3#1); 89174#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 89534#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 89524#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 89504#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 89483#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89481#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89467#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 89458#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 89451#L1678-2 [2022-02-21 04:23:28,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:28,346 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2022-02-21 04:23:28,347 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:28,347 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127259701] [2022-02-21 04:23:28,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:28,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:28,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:28,369 INFO L290 TraceCheckUtils]: 0: Hoare triple {104351#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,369 INFO L290 TraceCheckUtils]: 1: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,369 INFO L290 TraceCheckUtils]: 2: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,370 INFO L290 TraceCheckUtils]: 3: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,370 INFO L290 TraceCheckUtils]: 4: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,370 INFO L290 TraceCheckUtils]: 5: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,371 INFO L290 TraceCheckUtils]: 6: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,371 INFO L290 TraceCheckUtils]: 7: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,371 INFO L290 TraceCheckUtils]: 8: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,371 INFO L290 TraceCheckUtils]: 9: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,372 INFO L290 TraceCheckUtils]: 10: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,372 INFO L290 TraceCheckUtils]: 11: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,372 INFO L290 TraceCheckUtils]: 12: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,373 INFO L290 TraceCheckUtils]: 13: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,373 INFO L290 TraceCheckUtils]: 14: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,373 INFO L290 TraceCheckUtils]: 15: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,373 INFO L290 TraceCheckUtils]: 16: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {104353#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:23:28,374 INFO L290 TraceCheckUtils]: 17: Hoare triple {104353#(= ~E_6~0 ~M_E~0)} assume !(0 == ~M_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,374 INFO L290 TraceCheckUtils]: 18: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T1_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,374 INFO L290 TraceCheckUtils]: 19: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T2_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,374 INFO L290 TraceCheckUtils]: 20: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T3_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,375 INFO L290 TraceCheckUtils]: 21: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T4_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,375 INFO L290 TraceCheckUtils]: 22: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T5_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,375 INFO L290 TraceCheckUtils]: 23: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T6_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,375 INFO L290 TraceCheckUtils]: 24: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T7_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,376 INFO L290 TraceCheckUtils]: 25: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T8_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,376 INFO L290 TraceCheckUtils]: 26: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T9_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,376 INFO L290 TraceCheckUtils]: 27: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T10_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,376 INFO L290 TraceCheckUtils]: 28: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~T11_E~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,377 INFO L290 TraceCheckUtils]: 29: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~E_M~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,377 INFO L290 TraceCheckUtils]: 30: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~E_1~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,377 INFO L290 TraceCheckUtils]: 31: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~E_2~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,377 INFO L290 TraceCheckUtils]: 32: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~E_3~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,378 INFO L290 TraceCheckUtils]: 33: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~E_4~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,378 INFO L290 TraceCheckUtils]: 34: Hoare triple {104354#(not (= ~E_6~0 0))} assume !(0 == ~E_5~0); {104354#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:23:28,378 INFO L290 TraceCheckUtils]: 35: Hoare triple {104354#(not (= ~E_6~0 0))} assume 0 == ~E_6~0;~E_6~0 := 1; {104352#false} is VALID [2022-02-21 04:23:28,378 INFO L290 TraceCheckUtils]: 36: Hoare triple {104352#false} assume !(0 == ~E_7~0); {104352#false} is VALID [2022-02-21 04:23:28,378 INFO L290 TraceCheckUtils]: 37: Hoare triple {104352#false} assume !(0 == ~E_8~0); {104352#false} is VALID [2022-02-21 04:23:28,378 INFO L290 TraceCheckUtils]: 38: Hoare triple {104352#false} assume !(0 == ~E_9~0); {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 39: Hoare triple {104352#false} assume !(0 == ~E_10~0); {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 40: Hoare triple {104352#false} assume !(0 == ~E_11~0); {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 41: Hoare triple {104352#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 42: Hoare triple {104352#false} assume 1 == ~m_pc~0; {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 43: Hoare triple {104352#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 44: Hoare triple {104352#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 45: Hoare triple {104352#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 46: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp~1#1); {104352#false} is VALID [2022-02-21 04:23:28,379 INFO L290 TraceCheckUtils]: 47: Hoare triple {104352#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 48: Hoare triple {104352#false} assume !(1 == ~t1_pc~0); {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 49: Hoare triple {104352#false} is_transmit1_triggered_~__retres1~1#1 := 0; {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 50: Hoare triple {104352#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 51: Hoare triple {104352#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 52: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___0~0#1); {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 53: Hoare triple {104352#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 54: Hoare triple {104352#false} assume 1 == ~t2_pc~0; {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 55: Hoare triple {104352#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {104352#false} is VALID [2022-02-21 04:23:28,380 INFO L290 TraceCheckUtils]: 56: Hoare triple {104352#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 57: Hoare triple {104352#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 58: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___1~0#1); {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 59: Hoare triple {104352#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 60: Hoare triple {104352#false} assume !(1 == ~t3_pc~0); {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 61: Hoare triple {104352#false} is_transmit3_triggered_~__retres1~3#1 := 0; {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 62: Hoare triple {104352#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 63: Hoare triple {104352#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 64: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___2~0#1); {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 65: Hoare triple {104352#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {104352#false} is VALID [2022-02-21 04:23:28,381 INFO L290 TraceCheckUtils]: 66: Hoare triple {104352#false} assume 1 == ~t4_pc~0; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 67: Hoare triple {104352#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 68: Hoare triple {104352#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 69: Hoare triple {104352#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 70: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___3~0#1); {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 71: Hoare triple {104352#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 72: Hoare triple {104352#false} assume 1 == ~t5_pc~0; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 73: Hoare triple {104352#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 74: Hoare triple {104352#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {104352#false} is VALID [2022-02-21 04:23:28,382 INFO L290 TraceCheckUtils]: 75: Hoare triple {104352#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 76: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___4~0#1); {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 77: Hoare triple {104352#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 78: Hoare triple {104352#false} assume !(1 == ~t6_pc~0); {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 79: Hoare triple {104352#false} is_transmit6_triggered_~__retres1~6#1 := 0; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 80: Hoare triple {104352#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 81: Hoare triple {104352#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 82: Hoare triple {104352#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 83: Hoare triple {104352#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 84: Hoare triple {104352#false} assume 1 == ~t7_pc~0; {104352#false} is VALID [2022-02-21 04:23:28,383 INFO L290 TraceCheckUtils]: 85: Hoare triple {104352#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 86: Hoare triple {104352#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 87: Hoare triple {104352#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 88: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___6~0#1); {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 89: Hoare triple {104352#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 90: Hoare triple {104352#false} assume !(1 == ~t8_pc~0); {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 91: Hoare triple {104352#false} is_transmit8_triggered_~__retres1~8#1 := 0; {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 92: Hoare triple {104352#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 93: Hoare triple {104352#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {104352#false} is VALID [2022-02-21 04:23:28,384 INFO L290 TraceCheckUtils]: 94: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___7~0#1); {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 95: Hoare triple {104352#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 96: Hoare triple {104352#false} assume 1 == ~t9_pc~0; {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 97: Hoare triple {104352#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 98: Hoare triple {104352#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 99: Hoare triple {104352#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 100: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___8~0#1); {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 101: Hoare triple {104352#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 102: Hoare triple {104352#false} assume !(1 == ~t10_pc~0); {104352#false} is VALID [2022-02-21 04:23:28,385 INFO L290 TraceCheckUtils]: 103: Hoare triple {104352#false} is_transmit10_triggered_~__retres1~10#1 := 0; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 104: Hoare triple {104352#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 105: Hoare triple {104352#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 106: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___9~0#1); {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 107: Hoare triple {104352#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 108: Hoare triple {104352#false} assume 1 == ~t11_pc~0; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 109: Hoare triple {104352#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 110: Hoare triple {104352#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 111: Hoare triple {104352#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 112: Hoare triple {104352#false} assume !(0 != activate_threads_~tmp___10~0#1); {104352#false} is VALID [2022-02-21 04:23:28,386 INFO L290 TraceCheckUtils]: 113: Hoare triple {104352#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 114: Hoare triple {104352#false} assume 1 == ~M_E~0;~M_E~0 := 2; {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 115: Hoare triple {104352#false} assume !(1 == ~T1_E~0); {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 116: Hoare triple {104352#false} assume !(1 == ~T2_E~0); {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 117: Hoare triple {104352#false} assume !(1 == ~T3_E~0); {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 118: Hoare triple {104352#false} assume !(1 == ~T4_E~0); {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 119: Hoare triple {104352#false} assume !(1 == ~T5_E~0); {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 120: Hoare triple {104352#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 121: Hoare triple {104352#false} assume !(1 == ~T7_E~0); {104352#false} is VALID [2022-02-21 04:23:28,387 INFO L290 TraceCheckUtils]: 122: Hoare triple {104352#false} assume !(1 == ~T8_E~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 123: Hoare triple {104352#false} assume !(1 == ~T9_E~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 124: Hoare triple {104352#false} assume !(1 == ~T10_E~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 125: Hoare triple {104352#false} assume !(1 == ~T11_E~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 126: Hoare triple {104352#false} assume !(1 == ~E_M~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 127: Hoare triple {104352#false} assume !(1 == ~E_1~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 128: Hoare triple {104352#false} assume 1 == ~E_2~0;~E_2~0 := 2; {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 129: Hoare triple {104352#false} assume !(1 == ~E_3~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 130: Hoare triple {104352#false} assume !(1 == ~E_4~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 131: Hoare triple {104352#false} assume !(1 == ~E_5~0); {104352#false} is VALID [2022-02-21 04:23:28,388 INFO L290 TraceCheckUtils]: 132: Hoare triple {104352#false} assume !(1 == ~E_6~0); {104352#false} is VALID [2022-02-21 04:23:28,389 INFO L290 TraceCheckUtils]: 133: Hoare triple {104352#false} assume !(1 == ~E_7~0); {104352#false} is VALID [2022-02-21 04:23:28,389 INFO L290 TraceCheckUtils]: 134: Hoare triple {104352#false} assume !(1 == ~E_8~0); {104352#false} is VALID [2022-02-21 04:23:28,389 INFO L290 TraceCheckUtils]: 135: Hoare triple {104352#false} assume !(1 == ~E_9~0); {104352#false} is VALID [2022-02-21 04:23:28,389 INFO L290 TraceCheckUtils]: 136: Hoare triple {104352#false} assume 1 == ~E_10~0;~E_10~0 := 2; {104352#false} is VALID [2022-02-21 04:23:28,389 INFO L290 TraceCheckUtils]: 137: Hoare triple {104352#false} assume !(1 == ~E_11~0); {104352#false} is VALID [2022-02-21 04:23:28,389 INFO L290 TraceCheckUtils]: 138: Hoare triple {104352#false} assume { :end_inline_reset_delta_events } true; {104352#false} is VALID [2022-02-21 04:23:28,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:28,390 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:28,390 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [127259701] [2022-02-21 04:23:28,390 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [127259701] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:28,390 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:28,390 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:28,390 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492001401] [2022-02-21 04:23:28,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:28,392 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:28,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:28,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1676577101, now seen corresponding path program 1 times [2022-02-21 04:23:28,392 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:28,392 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364273106] [2022-02-21 04:23:28,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:28,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:28,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:28,414 INFO L290 TraceCheckUtils]: 0: Hoare triple {104355#true} assume !false; {104355#true} is VALID [2022-02-21 04:23:28,415 INFO L290 TraceCheckUtils]: 1: Hoare triple {104355#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {104355#true} is VALID [2022-02-21 04:23:28,415 INFO L290 TraceCheckUtils]: 2: Hoare triple {104355#true} assume !false; {104355#true} is VALID [2022-02-21 04:23:28,415 INFO L290 TraceCheckUtils]: 3: Hoare triple {104355#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {104355#true} is VALID [2022-02-21 04:23:28,415 INFO L290 TraceCheckUtils]: 4: Hoare triple {104355#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {104355#true} is VALID [2022-02-21 04:23:28,423 INFO L290 TraceCheckUtils]: 5: Hoare triple {104355#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {104355#true} is VALID [2022-02-21 04:23:28,423 INFO L290 TraceCheckUtils]: 6: Hoare triple {104355#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {104355#true} is VALID [2022-02-21 04:23:28,423 INFO L290 TraceCheckUtils]: 7: Hoare triple {104355#true} assume !(0 != eval_~tmp~0#1); {104355#true} is VALID [2022-02-21 04:23:28,423 INFO L290 TraceCheckUtils]: 8: Hoare triple {104355#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {104355#true} is VALID [2022-02-21 04:23:28,423 INFO L290 TraceCheckUtils]: 9: Hoare triple {104355#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 10: Hoare triple {104355#true} assume 0 == ~M_E~0;~M_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 11: Hoare triple {104355#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 12: Hoare triple {104355#true} assume !(0 == ~T2_E~0); {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 13: Hoare triple {104355#true} assume !(0 == ~T3_E~0); {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 14: Hoare triple {104355#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 15: Hoare triple {104355#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 16: Hoare triple {104355#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 17: Hoare triple {104355#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,424 INFO L290 TraceCheckUtils]: 18: Hoare triple {104355#true} assume 0 == ~T8_E~0;~T8_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 19: Hoare triple {104355#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 20: Hoare triple {104355#true} assume !(0 == ~T10_E~0); {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 21: Hoare triple {104355#true} assume !(0 == ~T11_E~0); {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 22: Hoare triple {104355#true} assume 0 == ~E_M~0;~E_M~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 23: Hoare triple {104355#true} assume 0 == ~E_1~0;~E_1~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 24: Hoare triple {104355#true} assume 0 == ~E_2~0;~E_2~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 25: Hoare triple {104355#true} assume 0 == ~E_3~0;~E_3~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 26: Hoare triple {104355#true} assume 0 == ~E_4~0;~E_4~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,425 INFO L290 TraceCheckUtils]: 27: Hoare triple {104355#true} assume 0 == ~E_5~0;~E_5~0 := 1; {104355#true} is VALID [2022-02-21 04:23:28,426 INFO L290 TraceCheckUtils]: 28: Hoare triple {104355#true} assume 0 == ~E_6~0;~E_6~0 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,426 INFO L290 TraceCheckUtils]: 29: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(0 == ~E_7~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,426 INFO L290 TraceCheckUtils]: 30: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,427 INFO L290 TraceCheckUtils]: 31: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,427 INFO L290 TraceCheckUtils]: 32: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,427 INFO L290 TraceCheckUtils]: 33: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,427 INFO L290 TraceCheckUtils]: 34: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,428 INFO L290 TraceCheckUtils]: 35: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~m_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,428 INFO L290 TraceCheckUtils]: 36: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,428 INFO L290 TraceCheckUtils]: 37: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,428 INFO L290 TraceCheckUtils]: 38: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,429 INFO L290 TraceCheckUtils]: 39: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,429 INFO L290 TraceCheckUtils]: 40: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,429 INFO L290 TraceCheckUtils]: 41: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t1_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,429 INFO L290 TraceCheckUtils]: 42: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,430 INFO L290 TraceCheckUtils]: 43: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,430 INFO L290 TraceCheckUtils]: 44: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,430 INFO L290 TraceCheckUtils]: 45: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,430 INFO L290 TraceCheckUtils]: 46: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,431 INFO L290 TraceCheckUtils]: 47: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t2_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,431 INFO L290 TraceCheckUtils]: 48: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,431 INFO L290 TraceCheckUtils]: 49: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,431 INFO L290 TraceCheckUtils]: 50: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,432 INFO L290 TraceCheckUtils]: 51: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,432 INFO L290 TraceCheckUtils]: 52: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,432 INFO L290 TraceCheckUtils]: 53: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t3_pc~0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,432 INFO L290 TraceCheckUtils]: 54: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,433 INFO L290 TraceCheckUtils]: 55: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,433 INFO L290 TraceCheckUtils]: 56: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,433 INFO L290 TraceCheckUtils]: 57: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,433 INFO L290 TraceCheckUtils]: 58: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,434 INFO L290 TraceCheckUtils]: 59: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t4_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,434 INFO L290 TraceCheckUtils]: 60: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,434 INFO L290 TraceCheckUtils]: 61: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,434 INFO L290 TraceCheckUtils]: 62: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,435 INFO L290 TraceCheckUtils]: 63: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,435 INFO L290 TraceCheckUtils]: 64: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,435 INFO L290 TraceCheckUtils]: 65: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t5_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,435 INFO L290 TraceCheckUtils]: 66: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,436 INFO L290 TraceCheckUtils]: 67: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,436 INFO L290 TraceCheckUtils]: 68: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,436 INFO L290 TraceCheckUtils]: 69: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,436 INFO L290 TraceCheckUtils]: 70: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,437 INFO L290 TraceCheckUtils]: 71: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t6_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,437 INFO L290 TraceCheckUtils]: 72: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,437 INFO L290 TraceCheckUtils]: 73: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,437 INFO L290 TraceCheckUtils]: 74: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,438 INFO L290 TraceCheckUtils]: 75: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,438 INFO L290 TraceCheckUtils]: 76: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,438 INFO L290 TraceCheckUtils]: 77: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,438 INFO L290 TraceCheckUtils]: 78: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,439 INFO L290 TraceCheckUtils]: 79: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,439 INFO L290 TraceCheckUtils]: 80: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,439 INFO L290 TraceCheckUtils]: 81: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,439 INFO L290 TraceCheckUtils]: 82: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,440 INFO L290 TraceCheckUtils]: 83: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t8_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,440 INFO L290 TraceCheckUtils]: 84: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,440 INFO L290 TraceCheckUtils]: 85: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,440 INFO L290 TraceCheckUtils]: 86: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,441 INFO L290 TraceCheckUtils]: 87: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,441 INFO L290 TraceCheckUtils]: 88: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,441 INFO L290 TraceCheckUtils]: 89: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t9_pc~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,441 INFO L290 TraceCheckUtils]: 90: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,442 INFO L290 TraceCheckUtils]: 91: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,442 INFO L290 TraceCheckUtils]: 92: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,442 INFO L290 TraceCheckUtils]: 93: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,442 INFO L290 TraceCheckUtils]: 94: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,443 INFO L290 TraceCheckUtils]: 95: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t10_pc~0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,443 INFO L290 TraceCheckUtils]: 96: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,443 INFO L290 TraceCheckUtils]: 97: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,443 INFO L290 TraceCheckUtils]: 98: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,444 INFO L290 TraceCheckUtils]: 99: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,444 INFO L290 TraceCheckUtils]: 100: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,444 INFO L290 TraceCheckUtils]: 101: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t11_pc~0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,444 INFO L290 TraceCheckUtils]: 102: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,444 INFO L290 TraceCheckUtils]: 103: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,445 INFO L290 TraceCheckUtils]: 104: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,445 INFO L290 TraceCheckUtils]: 105: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,445 INFO L290 TraceCheckUtils]: 106: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,445 INFO L290 TraceCheckUtils]: 107: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,446 INFO L290 TraceCheckUtils]: 108: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,446 INFO L290 TraceCheckUtils]: 109: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T2_E~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,446 INFO L290 TraceCheckUtils]: 110: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,446 INFO L290 TraceCheckUtils]: 111: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,447 INFO L290 TraceCheckUtils]: 112: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,447 INFO L290 TraceCheckUtils]: 113: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,447 INFO L290 TraceCheckUtils]: 114: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,447 INFO L290 TraceCheckUtils]: 115: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T8_E~0;~T8_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,448 INFO L290 TraceCheckUtils]: 116: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,448 INFO L290 TraceCheckUtils]: 117: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T10_E~0); {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,448 INFO L290 TraceCheckUtils]: 118: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T11_E~0;~T11_E~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,448 INFO L290 TraceCheckUtils]: 119: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,449 INFO L290 TraceCheckUtils]: 120: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,449 INFO L290 TraceCheckUtils]: 121: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,449 INFO L290 TraceCheckUtils]: 122: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,449 INFO L290 TraceCheckUtils]: 123: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,450 INFO L290 TraceCheckUtils]: 124: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {104357#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:28,450 INFO L290 TraceCheckUtils]: 125: Hoare triple {104357#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {104356#false} is VALID [2022-02-21 04:23:28,450 INFO L290 TraceCheckUtils]: 126: Hoare triple {104356#false} assume 1 == ~E_7~0;~E_7~0 := 2; {104356#false} is VALID [2022-02-21 04:23:28,450 INFO L290 TraceCheckUtils]: 127: Hoare triple {104356#false} assume 1 == ~E_8~0;~E_8~0 := 2; {104356#false} is VALID [2022-02-21 04:23:28,450 INFO L290 TraceCheckUtils]: 128: Hoare triple {104356#false} assume 1 == ~E_9~0;~E_9~0 := 2; {104356#false} is VALID [2022-02-21 04:23:28,450 INFO L290 TraceCheckUtils]: 129: Hoare triple {104356#false} assume 1 == ~E_10~0;~E_10~0 := 2; {104356#false} is VALID [2022-02-21 04:23:28,450 INFO L290 TraceCheckUtils]: 130: Hoare triple {104356#false} assume 1 == ~E_11~0;~E_11~0 := 2; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 131: Hoare triple {104356#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 132: Hoare triple {104356#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 133: Hoare triple {104356#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 134: Hoare triple {104356#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 135: Hoare triple {104356#false} assume !(0 == start_simulation_~tmp~3#1); {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 136: Hoare triple {104356#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 137: Hoare triple {104356#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 138: Hoare triple {104356#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {104356#false} is VALID [2022-02-21 04:23:28,451 INFO L290 TraceCheckUtils]: 139: Hoare triple {104356#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {104356#false} is VALID [2022-02-21 04:23:28,452 INFO L290 TraceCheckUtils]: 140: Hoare triple {104356#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {104356#false} is VALID [2022-02-21 04:23:28,452 INFO L290 TraceCheckUtils]: 141: Hoare triple {104356#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {104356#false} is VALID [2022-02-21 04:23:28,452 INFO L290 TraceCheckUtils]: 142: Hoare triple {104356#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {104356#false} is VALID [2022-02-21 04:23:28,452 INFO L290 TraceCheckUtils]: 143: Hoare triple {104356#false} assume !(0 != start_simulation_~tmp___0~1#1); {104356#false} is VALID [2022-02-21 04:23:28,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:28,452 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:28,453 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364273106] [2022-02-21 04:23:28,453 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364273106] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:28,453 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:28,453 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:28,453 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625348907] [2022-02-21 04:23:28,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:28,453 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:28,454 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:28,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:28,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:28,454 INFO L87 Difference]: Start difference. First operand 5541 states and 8142 transitions. cyclomatic complexity: 2605 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,055 INFO L93 Difference]: Finished difference Result 10453 states and 15329 transitions. [2022-02-21 04:23:33,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:33,055 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,134 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:33,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10453 states and 15329 transitions. [2022-02-21 04:23:35,226 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2022-02-21 04:23:37,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10453 states to 10453 states and 15329 transitions. [2022-02-21 04:23:37,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10453 [2022-02-21 04:23:37,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10453 [2022-02-21 04:23:37,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10453 states and 15329 transitions. [2022-02-21 04:23:37,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:37,422 INFO L681 BuchiCegarLoop]: Abstraction has 10453 states and 15329 transitions. [2022-02-21 04:23:37,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10453 states and 15329 transitions. [2022-02-21 04:23:37,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10453 to 10449. [2022-02-21 04:23:37,510 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:37,522 INFO L82 GeneralOperation]: Start isEquivalent. First operand 10453 states and 15329 transitions. Second operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,533 INFO L74 IsIncluded]: Start isIncluded. First operand 10453 states and 15329 transitions. Second operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:37,545 INFO L87 Difference]: Start difference. First operand 10453 states and 15329 transitions. Second operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:39,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:39,834 INFO L93 Difference]: Finished difference Result 10453 states and 15329 transitions. [2022-02-21 04:23:39,835 INFO L276 IsEmpty]: Start isEmpty. Operand 10453 states and 15329 transitions. [2022-02-21 04:23:39,844 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:39,845 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:39,856 INFO L74 IsIncluded]: Start isIncluded. First operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 10453 states and 15329 transitions. [2022-02-21 04:23:39,867 INFO L87 Difference]: Start difference. First operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 10453 states and 15329 transitions. [2022-02-21 04:23:42,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:42,137 INFO L93 Difference]: Finished difference Result 10453 states and 15329 transitions. [2022-02-21 04:23:42,137 INFO L276 IsEmpty]: Start isEmpty. Operand 10453 states and 15329 transitions. [2022-02-21 04:23:42,143 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:42,143 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:42,143 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:42,143 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:42,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:44,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10449 states to 10449 states and 15325 transitions. [2022-02-21 04:23:44,524 INFO L704 BuchiCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2022-02-21 04:23:44,524 INFO L587 BuchiCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2022-02-21 04:23:44,524 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:23:44,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10449 states and 15325 transitions. [2022-02-21 04:23:44,545 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2022-02-21 04:23:44,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:44,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:44,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:44,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:44,547 INFO L791 eck$LassoCheckResult]: Stem: 115550#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 115551#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 116337#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116338#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 115051#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 115052#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116348#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 116308#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 116309#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115402#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115403#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115818#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 116273#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 115313#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115314#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 115199#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 115200#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116193#L1109 assume !(0 == ~M_E~0); 116217#L1109-2 assume !(0 == ~T1_E~0); 115206#L1114-1 assume !(0 == ~T2_E~0); 115207#L1119-1 assume !(0 == ~T3_E~0); 116277#L1124-1 assume !(0 == ~T4_E~0); 114868#L1129-1 assume !(0 == ~T5_E~0); 114869#L1134-1 assume !(0 == ~T6_E~0); 115482#L1139-1 assume !(0 == ~T7_E~0); 116199#L1144-1 assume !(0 == ~T8_E~0); 116061#L1149-1 assume !(0 == ~T9_E~0); 114973#L1154-1 assume !(0 == ~T10_E~0); 114974#L1159-1 assume !(0 == ~T11_E~0); 116044#L1164-1 assume !(0 == ~E_M~0); 115367#L1169-1 assume !(0 == ~E_1~0); 115256#L1174-1 assume !(0 == ~E_2~0); 115129#L1179-1 assume !(0 == ~E_3~0); 115055#L1184-1 assume !(0 == ~E_4~0); 115056#L1189-1 assume !(0 == ~E_5~0); 115088#L1194-1 assume !(0 == ~E_6~0); 115175#L1199-1 assume !(0 == ~E_7~0); 116071#L1204-1 assume !(0 == ~E_8~0); 115998#L1209-1 assume !(0 == ~E_9~0); 115999#L1214-1 assume !(0 == ~E_10~0); 116360#L1219-1 assume !(0 == ~E_11~0); 116458#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115385#L544 assume 1 == ~m_pc~0; 115386#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 116264#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116079#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 115017#L1379 assume !(0 != activate_threads_~tmp~1#1); 115018#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115801#L563 assume !(1 == ~t1_pc~0); 115592#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114876#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114877#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 115931#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 114872#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114873#L582 assume 1 == ~t2_pc~0; 115570#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 115942#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115943#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116060#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 114905#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114906#L601 assume !(1 == ~t3_pc~0); 115586#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115585#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116265#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 115984#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 115985#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 115921#L620 assume 1 == ~t4_pc~0; 114886#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114887#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115450#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 115451#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 115815#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116016#L639 assume 1 == ~t5_pc~0; 115892#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 115179#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115180#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 115836#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 115837#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 115765#L658 assume !(1 == ~t6_pc~0); 115382#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 115383#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115973#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116339#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 115988#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115219#L677 assume 1 == ~t7_pc~0; 115220#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115122#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116162#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116301#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 116302#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 116381#L696 assume !(1 == ~t8_pc~0); 115440#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 115441#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 116347#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116370#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 116427#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 115873#L715 assume 1 == ~t9_pc~0; 115874#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 115530#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 115438#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115439#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 115858#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116158#L734 assume !(1 == ~t10_pc~0); 116159#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 115339#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 115340#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 115358#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 116098#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 115416#L753 assume 1 == ~t11_pc~0; 115417#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 115993#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115525#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 115526#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 115679#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115738#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 115739#L1237-2 assume !(1 == ~T1_E~0); 116411#L1242-1 assume !(1 == ~T2_E~0); 116914#L1247-1 assume !(1 == ~T3_E~0); 116912#L1252-1 assume !(1 == ~T4_E~0); 116910#L1257-1 assume !(1 == ~T5_E~0); 116908#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116292#L1267-1 assume !(1 == ~T7_E~0); 116293#L1272-1 assume !(1 == ~T8_E~0); 116294#L1277-1 assume !(1 == ~T9_E~0); 116818#L1282-1 assume !(1 == ~T10_E~0); 116763#L1287-1 assume !(1 == ~T11_E~0); 116761#L1292-1 assume !(1 == ~E_M~0); 116681#L1297-1 assume !(1 == ~E_1~0); 116679#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 116620#L1307-1 assume !(1 == ~E_3~0); 116618#L1312-1 assume !(1 == ~E_4~0); 116583#L1317-1 assume !(1 == ~E_5~0); 116580#L1322-1 assume !(1 == ~E_6~0); 116576#L1327-1 assume !(1 == ~E_7~0); 116574#L1332-1 assume !(1 == ~E_8~0); 116554#L1337-1 assume !(1 == ~E_9~0); 116540#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 116525#L1347-1 assume !(1 == ~E_11~0); 116516#L1352-1 assume { :end_inline_reset_delta_events } true; 116508#L1678-2 [2022-02-21 04:23:44,547 INFO L793 eck$LassoCheckResult]: Loop: 116508#L1678-2 assume !false; 116501#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116498#L1084 assume !false; 116497#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116487#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116484#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116483#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 116481#L925 assume !(0 != eval_~tmp~0#1); 116480#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116479#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116477#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 116478#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117802#L1114-3 assume !(0 == ~T2_E~0); 117678#L1119-3 assume !(0 == ~T3_E~0); 117676#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117674#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117671#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117669#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117667#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117665#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117663#L1154-3 assume !(0 == ~T10_E~0); 117661#L1159-3 assume !(0 == ~T11_E~0); 117659#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117657#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117655#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 117653#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117651#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117649#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117647#L1194-3 assume !(0 == ~E_6~0); 117645#L1199-3 assume !(0 == ~E_7~0); 117643#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117641#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117639#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 117532#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117530#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117528#L544-39 assume 1 == ~m_pc~0; 117525#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 117523#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117521#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117519#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 117517#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117514#L563-39 assume 1 == ~t1_pc~0; 117511#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 117509#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117507#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 117505#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117504#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117387#L582-39 assume !(1 == ~t2_pc~0); 117383#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 117381#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117379#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117377#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117375#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117374#L601-39 assume !(1 == ~t3_pc~0); 117373#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 117370#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117258#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117255#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117253#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117251#L620-39 assume 1 == ~t4_pc~0; 117248#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 117245#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117242#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117240#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117238#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117236#L639-39 assume 1 == ~t5_pc~0; 117233#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 117231#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117228#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117226#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 117224#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117222#L658-39 assume 1 == ~t6_pc~0; 117213#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 117210#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117208#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117206#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 117204#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117201#L677-39 assume !(1 == ~t7_pc~0); 117199#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 117196#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117194#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117192#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 117190#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117189#L696-39 assume 1 == ~t8_pc~0; 117187#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117184#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117082#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116953#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 116951#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116950#L715-39 assume 1 == ~t9_pc~0; 116947#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 116945#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 116943#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 116941#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 116938#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116936#L734-39 assume 1 == ~t10_pc~0; 116933#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 116931#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 116929#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 116927#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 116925#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116862#L753-39 assume !(1 == ~t11_pc~0); 116859#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 116857#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116855#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 116852#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116850#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116848#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 115757#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116780#L1242-3 assume !(1 == ~T2_E~0); 116778#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116776#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116774#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116772#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116769#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116767#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 116765#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 116706#L1282-3 assume !(1 == ~T10_E~0); 116703#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 116701#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116699#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116697#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116695#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116693#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116691#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116687#L1322-3 assume !(1 == ~E_6~0); 116686#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 116685#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 116684#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 116683#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 116682#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 116680#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116643#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116630#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116622#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 116621#L1697 assume !(0 == start_simulation_~tmp~3#1); 116249#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116592#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116555#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116541#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 116539#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116538#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116524#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 116515#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 116508#L1678-2 [2022-02-21 04:23:44,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:44,548 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2022-02-21 04:23:44,548 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:44,548 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154519328] [2022-02-21 04:23:44,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:44,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:44,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:44,579 INFO L290 TraceCheckUtils]: 0: Hoare triple {146171#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,579 INFO L290 TraceCheckUtils]: 1: Hoare triple {146173#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,580 INFO L290 TraceCheckUtils]: 2: Hoare triple {146173#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,580 INFO L290 TraceCheckUtils]: 3: Hoare triple {146173#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,580 INFO L290 TraceCheckUtils]: 4: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,580 INFO L290 TraceCheckUtils]: 5: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,581 INFO L290 TraceCheckUtils]: 6: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,581 INFO L290 TraceCheckUtils]: 7: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,581 INFO L290 TraceCheckUtils]: 8: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,581 INFO L290 TraceCheckUtils]: 9: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,582 INFO L290 TraceCheckUtils]: 10: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,582 INFO L290 TraceCheckUtils]: 11: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,582 INFO L290 TraceCheckUtils]: 12: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,582 INFO L290 TraceCheckUtils]: 13: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,582 INFO L290 TraceCheckUtils]: 14: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,583 INFO L290 TraceCheckUtils]: 15: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,583 INFO L290 TraceCheckUtils]: 16: Hoare triple {146173#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,583 INFO L290 TraceCheckUtils]: 17: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,583 INFO L290 TraceCheckUtils]: 18: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,584 INFO L290 TraceCheckUtils]: 19: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,584 INFO L290 TraceCheckUtils]: 20: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,584 INFO L290 TraceCheckUtils]: 21: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,584 INFO L290 TraceCheckUtils]: 22: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,585 INFO L290 TraceCheckUtils]: 23: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,585 INFO L290 TraceCheckUtils]: 24: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T7_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,585 INFO L290 TraceCheckUtils]: 25: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T8_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,585 INFO L290 TraceCheckUtils]: 26: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T9_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,586 INFO L290 TraceCheckUtils]: 27: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T10_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,586 INFO L290 TraceCheckUtils]: 28: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~T11_E~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,586 INFO L290 TraceCheckUtils]: 29: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,587 INFO L290 TraceCheckUtils]: 30: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,587 INFO L290 TraceCheckUtils]: 31: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,587 INFO L290 TraceCheckUtils]: 32: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,587 INFO L290 TraceCheckUtils]: 33: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,587 INFO L290 TraceCheckUtils]: 34: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,588 INFO L290 TraceCheckUtils]: 35: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,588 INFO L290 TraceCheckUtils]: 36: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_7~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,588 INFO L290 TraceCheckUtils]: 37: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_8~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,588 INFO L290 TraceCheckUtils]: 38: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_9~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,589 INFO L290 TraceCheckUtils]: 39: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_10~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,589 INFO L290 TraceCheckUtils]: 40: Hoare triple {146173#(= ~m_pc~0 0)} assume !(0 == ~E_11~0); {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,589 INFO L290 TraceCheckUtils]: 41: Hoare triple {146173#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {146173#(= ~m_pc~0 0)} is VALID [2022-02-21 04:23:44,589 INFO L290 TraceCheckUtils]: 42: Hoare triple {146173#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {146172#false} is VALID [2022-02-21 04:23:44,589 INFO L290 TraceCheckUtils]: 43: Hoare triple {146172#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 44: Hoare triple {146172#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 45: Hoare triple {146172#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 46: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp~1#1); {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 47: Hoare triple {146172#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 48: Hoare triple {146172#false} assume !(1 == ~t1_pc~0); {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 49: Hoare triple {146172#false} is_transmit1_triggered_~__retres1~1#1 := 0; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 50: Hoare triple {146172#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 51: Hoare triple {146172#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 52: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___0~0#1); {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 53: Hoare triple {146172#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 54: Hoare triple {146172#false} assume 1 == ~t2_pc~0; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 55: Hoare triple {146172#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 56: Hoare triple {146172#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 57: Hoare triple {146172#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {146172#false} is VALID [2022-02-21 04:23:44,590 INFO L290 TraceCheckUtils]: 58: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___1~0#1); {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 59: Hoare triple {146172#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 60: Hoare triple {146172#false} assume !(1 == ~t3_pc~0); {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 61: Hoare triple {146172#false} is_transmit3_triggered_~__retres1~3#1 := 0; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 62: Hoare triple {146172#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 63: Hoare triple {146172#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 64: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___2~0#1); {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 65: Hoare triple {146172#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 66: Hoare triple {146172#false} assume 1 == ~t4_pc~0; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 67: Hoare triple {146172#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 68: Hoare triple {146172#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 69: Hoare triple {146172#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 70: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___3~0#1); {146172#false} is VALID [2022-02-21 04:23:44,591 INFO L290 TraceCheckUtils]: 71: Hoare triple {146172#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 72: Hoare triple {146172#false} assume 1 == ~t5_pc~0; {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 73: Hoare triple {146172#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 74: Hoare triple {146172#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 75: Hoare triple {146172#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 76: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___4~0#1); {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 77: Hoare triple {146172#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 78: Hoare triple {146172#false} assume !(1 == ~t6_pc~0); {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 79: Hoare triple {146172#false} is_transmit6_triggered_~__retres1~6#1 := 0; {146172#false} is VALID [2022-02-21 04:23:44,592 INFO L290 TraceCheckUtils]: 80: Hoare triple {146172#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 81: Hoare triple {146172#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 82: Hoare triple {146172#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 83: Hoare triple {146172#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 84: Hoare triple {146172#false} assume 1 == ~t7_pc~0; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 85: Hoare triple {146172#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 86: Hoare triple {146172#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 87: Hoare triple {146172#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 88: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___6~0#1); {146172#false} is VALID [2022-02-21 04:23:44,593 INFO L290 TraceCheckUtils]: 89: Hoare triple {146172#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 90: Hoare triple {146172#false} assume !(1 == ~t8_pc~0); {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 91: Hoare triple {146172#false} is_transmit8_triggered_~__retres1~8#1 := 0; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 92: Hoare triple {146172#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 93: Hoare triple {146172#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 94: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___7~0#1); {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 95: Hoare triple {146172#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 96: Hoare triple {146172#false} assume 1 == ~t9_pc~0; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 97: Hoare triple {146172#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 98: Hoare triple {146172#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 99: Hoare triple {146172#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 100: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___8~0#1); {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 101: Hoare triple {146172#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 102: Hoare triple {146172#false} assume !(1 == ~t10_pc~0); {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 103: Hoare triple {146172#false} is_transmit10_triggered_~__retres1~10#1 := 0; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 104: Hoare triple {146172#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {146172#false} is VALID [2022-02-21 04:23:44,594 INFO L290 TraceCheckUtils]: 105: Hoare triple {146172#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 106: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___9~0#1); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 107: Hoare triple {146172#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 108: Hoare triple {146172#false} assume 1 == ~t11_pc~0; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 109: Hoare triple {146172#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 110: Hoare triple {146172#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 111: Hoare triple {146172#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 112: Hoare triple {146172#false} assume !(0 != activate_threads_~tmp___10~0#1); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 113: Hoare triple {146172#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 114: Hoare triple {146172#false} assume 1 == ~M_E~0;~M_E~0 := 2; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 115: Hoare triple {146172#false} assume !(1 == ~T1_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 116: Hoare triple {146172#false} assume !(1 == ~T2_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 117: Hoare triple {146172#false} assume !(1 == ~T3_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 118: Hoare triple {146172#false} assume !(1 == ~T4_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 119: Hoare triple {146172#false} assume !(1 == ~T5_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 120: Hoare triple {146172#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 121: Hoare triple {146172#false} assume !(1 == ~T7_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 122: Hoare triple {146172#false} assume !(1 == ~T8_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 123: Hoare triple {146172#false} assume !(1 == ~T9_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 124: Hoare triple {146172#false} assume !(1 == ~T10_E~0); {146172#false} is VALID [2022-02-21 04:23:44,595 INFO L290 TraceCheckUtils]: 125: Hoare triple {146172#false} assume !(1 == ~T11_E~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 126: Hoare triple {146172#false} assume !(1 == ~E_M~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 127: Hoare triple {146172#false} assume !(1 == ~E_1~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 128: Hoare triple {146172#false} assume 1 == ~E_2~0;~E_2~0 := 2; {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 129: Hoare triple {146172#false} assume !(1 == ~E_3~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 130: Hoare triple {146172#false} assume !(1 == ~E_4~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 131: Hoare triple {146172#false} assume !(1 == ~E_5~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 132: Hoare triple {146172#false} assume !(1 == ~E_6~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 133: Hoare triple {146172#false} assume !(1 == ~E_7~0); {146172#false} is VALID [2022-02-21 04:23:44,596 INFO L290 TraceCheckUtils]: 134: Hoare triple {146172#false} assume !(1 == ~E_8~0); {146172#false} is VALID [2022-02-21 04:23:44,597 INFO L290 TraceCheckUtils]: 135: Hoare triple {146172#false} assume !(1 == ~E_9~0); {146172#false} is VALID [2022-02-21 04:23:44,597 INFO L290 TraceCheckUtils]: 136: Hoare triple {146172#false} assume 1 == ~E_10~0;~E_10~0 := 2; {146172#false} is VALID [2022-02-21 04:23:44,597 INFO L290 TraceCheckUtils]: 137: Hoare triple {146172#false} assume !(1 == ~E_11~0); {146172#false} is VALID [2022-02-21 04:23:44,597 INFO L290 TraceCheckUtils]: 138: Hoare triple {146172#false} assume { :end_inline_reset_delta_events } true; {146172#false} is VALID [2022-02-21 04:23:44,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:44,597 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:44,597 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154519328] [2022-02-21 04:23:44,598 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154519328] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:44,598 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:44,598 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:44,598 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850473205] [2022-02-21 04:23:44,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:44,598 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:44,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:44,599 INFO L85 PathProgramCache]: Analyzing trace with hash 832666374, now seen corresponding path program 1 times [2022-02-21 04:23:44,599 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:44,599 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981253825] [2022-02-21 04:23:44,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:44,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:44,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:44,618 INFO L290 TraceCheckUtils]: 0: Hoare triple {146174#true} assume !false; {146174#true} is VALID [2022-02-21 04:23:44,618 INFO L290 TraceCheckUtils]: 1: Hoare triple {146174#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 2: Hoare triple {146174#true} assume !false; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 3: Hoare triple {146174#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 4: Hoare triple {146174#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 5: Hoare triple {146174#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 6: Hoare triple {146174#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 7: Hoare triple {146174#true} assume !(0 != eval_~tmp~0#1); {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 8: Hoare triple {146174#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 9: Hoare triple {146174#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {146174#true} is VALID [2022-02-21 04:23:44,619 INFO L290 TraceCheckUtils]: 10: Hoare triple {146174#true} assume 0 == ~M_E~0;~M_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 11: Hoare triple {146174#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 12: Hoare triple {146174#true} assume !(0 == ~T2_E~0); {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 13: Hoare triple {146174#true} assume !(0 == ~T3_E~0); {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 14: Hoare triple {146174#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 15: Hoare triple {146174#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 16: Hoare triple {146174#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 17: Hoare triple {146174#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 18: Hoare triple {146174#true} assume 0 == ~T8_E~0;~T8_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 19: Hoare triple {146174#true} assume 0 == ~T9_E~0;~T9_E~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,620 INFO L290 TraceCheckUtils]: 20: Hoare triple {146174#true} assume !(0 == ~T10_E~0); {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 21: Hoare triple {146174#true} assume !(0 == ~T11_E~0); {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 22: Hoare triple {146174#true} assume 0 == ~E_M~0;~E_M~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 23: Hoare triple {146174#true} assume 0 == ~E_1~0;~E_1~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 24: Hoare triple {146174#true} assume 0 == ~E_2~0;~E_2~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 25: Hoare triple {146174#true} assume 0 == ~E_3~0;~E_3~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 26: Hoare triple {146174#true} assume 0 == ~E_4~0;~E_4~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 27: Hoare triple {146174#true} assume 0 == ~E_5~0;~E_5~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 28: Hoare triple {146174#true} assume !(0 == ~E_6~0); {146174#true} is VALID [2022-02-21 04:23:44,621 INFO L290 TraceCheckUtils]: 29: Hoare triple {146174#true} assume !(0 == ~E_7~0); {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 30: Hoare triple {146174#true} assume 0 == ~E_8~0;~E_8~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 31: Hoare triple {146174#true} assume 0 == ~E_9~0;~E_9~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 32: Hoare triple {146174#true} assume 0 == ~E_10~0;~E_10~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 33: Hoare triple {146174#true} assume 0 == ~E_11~0;~E_11~0 := 1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 34: Hoare triple {146174#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 35: Hoare triple {146174#true} assume 1 == ~m_pc~0; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 36: Hoare triple {146174#true} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 37: Hoare triple {146174#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 38: Hoare triple {146174#true} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {146174#true} is VALID [2022-02-21 04:23:44,622 INFO L290 TraceCheckUtils]: 39: Hoare triple {146174#true} assume !(0 != activate_threads_~tmp~1#1); {146174#true} is VALID [2022-02-21 04:23:44,623 INFO L290 TraceCheckUtils]: 40: Hoare triple {146174#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {146174#true} is VALID [2022-02-21 04:23:44,623 INFO L290 TraceCheckUtils]: 41: Hoare triple {146174#true} assume 1 == ~t1_pc~0; {146174#true} is VALID [2022-02-21 04:23:44,623 INFO L290 TraceCheckUtils]: 42: Hoare triple {146174#true} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {146174#true} is VALID [2022-02-21 04:23:44,623 INFO L290 TraceCheckUtils]: 43: Hoare triple {146174#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {146174#true} is VALID [2022-02-21 04:23:44,628 INFO L290 TraceCheckUtils]: 44: Hoare triple {146174#true} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {146174#true} is VALID [2022-02-21 04:23:44,628 INFO L290 TraceCheckUtils]: 45: Hoare triple {146174#true} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {146174#true} is VALID [2022-02-21 04:23:44,628 INFO L290 TraceCheckUtils]: 46: Hoare triple {146174#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {146174#true} is VALID [2022-02-21 04:23:44,628 INFO L290 TraceCheckUtils]: 47: Hoare triple {146174#true} assume !(1 == ~t2_pc~0); {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 48: Hoare triple {146174#true} is_transmit2_triggered_~__retres1~2#1 := 0; {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 49: Hoare triple {146174#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 50: Hoare triple {146174#true} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 51: Hoare triple {146174#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 52: Hoare triple {146174#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 53: Hoare triple {146174#true} assume !(1 == ~t3_pc~0); {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 54: Hoare triple {146174#true} is_transmit3_triggered_~__retres1~3#1 := 0; {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 55: Hoare triple {146174#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {146174#true} is VALID [2022-02-21 04:23:44,629 INFO L290 TraceCheckUtils]: 56: Hoare triple {146174#true} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 57: Hoare triple {146174#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 58: Hoare triple {146174#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 59: Hoare triple {146174#true} assume 1 == ~t4_pc~0; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 60: Hoare triple {146174#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 61: Hoare triple {146174#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 62: Hoare triple {146174#true} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 63: Hoare triple {146174#true} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 64: Hoare triple {146174#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 65: Hoare triple {146174#true} assume 1 == ~t5_pc~0; {146174#true} is VALID [2022-02-21 04:23:44,630 INFO L290 TraceCheckUtils]: 66: Hoare triple {146174#true} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {146174#true} is VALID [2022-02-21 04:23:44,631 INFO L290 TraceCheckUtils]: 67: Hoare triple {146174#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {146174#true} is VALID [2022-02-21 04:23:44,631 INFO L290 TraceCheckUtils]: 68: Hoare triple {146174#true} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {146174#true} is VALID [2022-02-21 04:23:44,631 INFO L290 TraceCheckUtils]: 69: Hoare triple {146174#true} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {146174#true} is VALID [2022-02-21 04:23:44,631 INFO L290 TraceCheckUtils]: 70: Hoare triple {146174#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {146174#true} is VALID [2022-02-21 04:23:44,631 INFO L290 TraceCheckUtils]: 71: Hoare triple {146174#true} assume 1 == ~t6_pc~0; {146174#true} is VALID [2022-02-21 04:23:44,631 INFO L290 TraceCheckUtils]: 72: Hoare triple {146174#true} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,632 INFO L290 TraceCheckUtils]: 73: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,632 INFO L290 TraceCheckUtils]: 74: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,632 INFO L290 TraceCheckUtils]: 75: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,632 INFO L290 TraceCheckUtils]: 76: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,633 INFO L290 TraceCheckUtils]: 77: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t7_pc~0); {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,633 INFO L290 TraceCheckUtils]: 78: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,633 INFO L290 TraceCheckUtils]: 79: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,633 INFO L290 TraceCheckUtils]: 80: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,634 INFO L290 TraceCheckUtils]: 81: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,634 INFO L290 TraceCheckUtils]: 82: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,634 INFO L290 TraceCheckUtils]: 83: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t8_pc~0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,634 INFO L290 TraceCheckUtils]: 84: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,634 INFO L290 TraceCheckUtils]: 85: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,635 INFO L290 TraceCheckUtils]: 86: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,635 INFO L290 TraceCheckUtils]: 87: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,635 INFO L290 TraceCheckUtils]: 88: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,635 INFO L290 TraceCheckUtils]: 89: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t9_pc~0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,636 INFO L290 TraceCheckUtils]: 90: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,636 INFO L290 TraceCheckUtils]: 91: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,636 INFO L290 TraceCheckUtils]: 92: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,636 INFO L290 TraceCheckUtils]: 93: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,637 INFO L290 TraceCheckUtils]: 94: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,637 INFO L290 TraceCheckUtils]: 95: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~t10_pc~0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,637 INFO L290 TraceCheckUtils]: 96: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,637 INFO L290 TraceCheckUtils]: 97: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,638 INFO L290 TraceCheckUtils]: 98: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,638 INFO L290 TraceCheckUtils]: 99: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,638 INFO L290 TraceCheckUtils]: 100: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,638 INFO L290 TraceCheckUtils]: 101: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~t11_pc~0); {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,638 INFO L290 TraceCheckUtils]: 102: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,639 INFO L290 TraceCheckUtils]: 103: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,639 INFO L290 TraceCheckUtils]: 104: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,639 INFO L290 TraceCheckUtils]: 105: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,639 INFO L290 TraceCheckUtils]: 106: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,640 INFO L290 TraceCheckUtils]: 107: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,640 INFO L290 TraceCheckUtils]: 108: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,640 INFO L290 TraceCheckUtils]: 109: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T2_E~0); {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,640 INFO L290 TraceCheckUtils]: 110: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,641 INFO L290 TraceCheckUtils]: 111: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,641 INFO L290 TraceCheckUtils]: 112: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,641 INFO L290 TraceCheckUtils]: 113: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,641 INFO L290 TraceCheckUtils]: 114: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,642 INFO L290 TraceCheckUtils]: 115: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T8_E~0;~T8_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,642 INFO L290 TraceCheckUtils]: 116: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,642 INFO L290 TraceCheckUtils]: 117: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~T10_E~0); {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,642 INFO L290 TraceCheckUtils]: 118: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~T11_E~0;~T11_E~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,643 INFO L290 TraceCheckUtils]: 119: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,643 INFO L290 TraceCheckUtils]: 120: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,643 INFO L290 TraceCheckUtils]: 121: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,643 INFO L290 TraceCheckUtils]: 122: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,643 INFO L290 TraceCheckUtils]: 123: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_4~0;~E_4~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,644 INFO L290 TraceCheckUtils]: 124: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume 1 == ~E_5~0;~E_5~0 := 2; {146176#(= (+ (- 1) ~E_6~0) 0)} is VALID [2022-02-21 04:23:44,644 INFO L290 TraceCheckUtils]: 125: Hoare triple {146176#(= (+ (- 1) ~E_6~0) 0)} assume !(1 == ~E_6~0); {146175#false} is VALID [2022-02-21 04:23:44,644 INFO L290 TraceCheckUtils]: 126: Hoare triple {146175#false} assume 1 == ~E_7~0;~E_7~0 := 2; {146175#false} is VALID [2022-02-21 04:23:44,644 INFO L290 TraceCheckUtils]: 127: Hoare triple {146175#false} assume 1 == ~E_8~0;~E_8~0 := 2; {146175#false} is VALID [2022-02-21 04:23:44,644 INFO L290 TraceCheckUtils]: 128: Hoare triple {146175#false} assume 1 == ~E_9~0;~E_9~0 := 2; {146175#false} is VALID [2022-02-21 04:23:44,644 INFO L290 TraceCheckUtils]: 129: Hoare triple {146175#false} assume 1 == ~E_10~0;~E_10~0 := 2; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 130: Hoare triple {146175#false} assume 1 == ~E_11~0;~E_11~0 := 2; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 131: Hoare triple {146175#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 132: Hoare triple {146175#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 133: Hoare triple {146175#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 134: Hoare triple {146175#false} start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 135: Hoare triple {146175#false} assume !(0 == start_simulation_~tmp~3#1); {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 136: Hoare triple {146175#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 137: Hoare triple {146175#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 138: Hoare triple {146175#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; {146175#false} is VALID [2022-02-21 04:23:44,645 INFO L290 TraceCheckUtils]: 139: Hoare triple {146175#false} stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; {146175#false} is VALID [2022-02-21 04:23:44,646 INFO L290 TraceCheckUtils]: 140: Hoare triple {146175#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {146175#false} is VALID [2022-02-21 04:23:44,646 INFO L290 TraceCheckUtils]: 141: Hoare triple {146175#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {146175#false} is VALID [2022-02-21 04:23:44,646 INFO L290 TraceCheckUtils]: 142: Hoare triple {146175#false} start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {146175#false} is VALID [2022-02-21 04:23:44,646 INFO L290 TraceCheckUtils]: 143: Hoare triple {146175#false} assume !(0 != start_simulation_~tmp___0~1#1); {146175#false} is VALID [2022-02-21 04:23:44,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:44,646 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:44,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981253825] [2022-02-21 04:23:44,647 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981253825] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:44,647 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:44,647 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:44,648 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039730987] [2022-02-21 04:23:44,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:44,648 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:44,648 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:44,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:44,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:44,649 INFO L87 Difference]: Start difference. First operand 10449 states and 15325 transitions. cyclomatic complexity: 4884 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:54,433 INFO L93 Difference]: Finished difference Result 20529 states and 29894 transitions. [2022-02-21 04:23:54,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:54,434 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,514 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:54,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20529 states and 29894 transitions. [2022-02-21 04:24:03,193 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20279