./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.12.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.12.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:23:02,321 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:23:02,323 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:23:02,354 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:23:02,355 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:23:02,357 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:23:02,358 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:23:02,360 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:23:02,361 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:23:02,364 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:23:02,365 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:23:02,366 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:23:02,366 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:23:02,368 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:23:02,369 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:23:02,371 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:23:02,372 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:23:02,372 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:23:02,374 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:23:02,378 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:23:02,378 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:23:02,379 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:23:02,380 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:23:02,381 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:23:02,385 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:23:02,386 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:23:02,386 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:23:02,387 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:23:02,387 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:23:02,388 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:23:02,388 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:23:02,389 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:23:02,390 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:23:02,391 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:23:02,392 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:23:02,392 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:23:02,393 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:23:02,393 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:23:02,393 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:23:02,394 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:23:02,394 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:23:02,395 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:23:02,418 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:23:02,419 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:23:02,419 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:23:02,419 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:23:02,420 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:23:02,420 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:23:02,420 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:23:02,420 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:23:02,421 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:23:02,421 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:23:02,421 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:23:02,421 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:23:02,422 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:23:02,422 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:23:02,422 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:23:02,422 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:23:02,422 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:23:02,422 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:23:02,422 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:23:02,423 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:23:02,424 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:23:02,424 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:23:02,424 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:23:02,424 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:23:02,425 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:23:02,425 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 962623ba1d780e7ad35b9b6d7f5839750bc2f361556d46080824a3701cf71595 [2022-02-21 04:23:02,641 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:23:02,661 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:23:02,663 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:23:02,664 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:23:02,679 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:23:02,681 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2022-02-21 04:23:02,747 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/16e58b8b1/a3f1b318e0c34841a302389e7faa4604/FLAGb55076e8e [2022-02-21 04:23:03,109 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:23:03,110 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-1.c [2022-02-21 04:23:03,134 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/16e58b8b1/a3f1b318e0c34841a302389e7faa4604/FLAGb55076e8e [2022-02-21 04:23:03,145 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/16e58b8b1/a3f1b318e0c34841a302389e7faa4604 [2022-02-21 04:23:03,147 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:23:03,149 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:23:03,151 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:03,151 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:23:03,153 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:23:03,154 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,154 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@63fe8aee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03, skipping insertion in model container [2022-02-21 04:23:03,155 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,159 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:23:03,197 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:23:03,343 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2022-02-21 04:23:03,449 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:03,456 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:23:03,463 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.12.cil-1.c[671,684] [2022-02-21 04:23:03,503 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:23:03,516 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:23:03,516 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03 WrapperNode [2022-02-21 04:23:03,516 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:23:03,517 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:03,517 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:23:03,517 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:23:03,522 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,539 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,647 INFO L137 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4146 [2022-02-21 04:23:03,648 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:23:03,648 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:23:03,648 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:23:03,649 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:23:03,654 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,654 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,661 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,661 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,686 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,712 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,717 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,726 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:23:03,727 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:23:03,727 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:23:03,727 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:23:03,728 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (1/1) ... [2022-02-21 04:23:03,744 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:23:03,751 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:23:03,761 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:23:03,828 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:23:03,854 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:23:03,855 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:23:03,855 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:23:03,855 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:23:03,981 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:23:03,982 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:23:05,514 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:23:05,526 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:23:05,526 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2022-02-21 04:23:05,528 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:05 BoogieIcfgContainer [2022-02-21 04:23:05,528 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:23:05,529 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:23:05,529 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:23:05,532 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:23:05,532 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:05,532 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:23:03" (1/3) ... [2022-02-21 04:23:05,533 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7368e7b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:05, skipping insertion in model container [2022-02-21 04:23:05,533 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:05,533 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:23:03" (2/3) ... [2022-02-21 04:23:05,533 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7368e7b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:23:05, skipping insertion in model container [2022-02-21 04:23:05,533 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:23:05,533 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:23:05" (3/3) ... [2022-02-21 04:23:05,534 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-1.c [2022-02-21 04:23:05,559 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:23:05,559 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:23:05,559 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:23:05,559 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:23:05,560 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:23:05,560 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:23:05,560 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:23:05,560 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:23:05,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:05,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2022-02-21 04:23:05,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:05,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:05,879 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,879 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:05,879 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:23:05,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:06,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1631 [2022-02-21 04:23:06,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:06,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:06,057 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:06,057 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:06,063 INFO L791 eck$LassoCheckResult]: Stem: 437#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1725#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 125#L1778true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113#L846true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1178#L853true assume !(1 == ~m_i~0);~m_st~0 := 2; 979#L853-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 271#L858-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3#L863-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 758#L868-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 885#L873-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1654#L878-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1613#L883-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1685#L888-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 384#L893-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 786#L898-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1787#L903-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 715#L908-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1404#L913-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 846#L1206true assume !(0 == ~M_E~0); 373#L1206-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1172#L1211-1true assume !(0 == ~T2_E~0); 1334#L1216-1true assume !(0 == ~T3_E~0); 261#L1221-1true assume !(0 == ~T4_E~0); 1255#L1226-1true assume !(0 == ~T5_E~0); 92#L1231-1true assume !(0 == ~T6_E~0); 1409#L1236-1true assume !(0 == ~T7_E~0); 1238#L1241-1true assume !(0 == ~T8_E~0); 296#L1246-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 417#L1251-1true assume !(0 == ~T10_E~0); 930#L1256-1true assume !(0 == ~T11_E~0); 8#L1261-1true assume !(0 == ~T12_E~0); 1624#L1266-1true assume !(0 == ~E_M~0); 1566#L1271-1true assume !(0 == ~E_1~0); 874#L1276-1true assume !(0 == ~E_2~0); 1556#L1281-1true assume !(0 == ~E_3~0); 807#L1286-1true assume 0 == ~E_4~0;~E_4~0 := 1; 212#L1291-1true assume !(0 == ~E_5~0); 1651#L1296-1true assume !(0 == ~E_6~0); 650#L1301-1true assume !(0 == ~E_7~0); 1116#L1306-1true assume !(0 == ~E_8~0); 1075#L1311-1true assume !(0 == ~E_9~0); 195#L1316-1true assume !(0 == ~E_10~0); 1490#L1321-1true assume !(0 == ~E_11~0); 662#L1326-1true assume 0 == ~E_12~0;~E_12~0 := 1; 121#L1331-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1782#L598true assume 1 == ~m_pc~0; 151#L599true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1207#L609true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1741#L610true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1432#L1497true assume !(0 != activate_threads_~tmp~1#1); 1686#L1497-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1295#L617true assume !(1 == ~t1_pc~0); 307#L617-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1731#L628true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 234#L629true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1479#L1505true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 726#L1505-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1325#L636true assume 1 == ~t2_pc~0; 292#L637true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 560#L647true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204#L648true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1469#L1513true assume !(0 != activate_threads_~tmp___1~0#1); 757#L1513-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 492#L655true assume !(1 == ~t3_pc~0); 1439#L655-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1705#L666true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136#L667true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1789#L1521true assume !(0 != activate_threads_~tmp___2~0#1); 1568#L1521-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1594#L674true assume 1 == ~t4_pc~0; 51#L675true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1663#L685true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 878#L686true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 205#L1529true assume !(0 != activate_threads_~tmp___3~0#1); 490#L1529-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1346#L693true assume !(1 == ~t5_pc~0); 616#L693-2true is_transmit5_triggered_~__retres1~5#1 := 0; 374#L704true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1115#L705true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1080#L1537true assume !(0 != activate_threads_~tmp___4~0#1); 425#L1537-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 387#L712true assume 1 == ~t6_pc~0; 907#L713true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 685#L723true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 952#L724true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1673#L1545true assume !(0 != activate_threads_~tmp___5~0#1); 774#L1545-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 769#L731true assume 1 == ~t7_pc~0; 123#L732true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226#L742true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 868#L743true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1089#L1553true assume !(0 != activate_threads_~tmp___6~0#1); 995#L1553-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 182#L750true assume !(1 == ~t8_pc~0); 860#L750-2true is_transmit8_triggered_~__retres1~8#1 := 0; 277#L761true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1763#L762true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1102#L1561true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 348#L1561-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 724#L769true assume 1 == ~t9_pc~0; 1732#L770true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103#L780true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 539#L781true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 926#L1569true assume !(0 != activate_threads_~tmp___8~0#1); 1365#L1569-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1019#L788true assume !(1 == ~t10_pc~0); 626#L788-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1241#L799true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 822#L800true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1141#L1577true assume !(0 != activate_threads_~tmp___9~0#1); 180#L1577-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1026#L807true assume 1 == ~t11_pc~0; 1218#L808true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 759#L818true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1278#L819true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1799#L1585true assume !(0 != activate_threads_~tmp___10~0#1); 1783#L1585-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1182#L826true assume !(1 == ~t12_pc~0); 388#L826-2true is_transmit12_triggered_~__retres1~12#1 := 0; 782#L837true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1610#L838true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1369#L1593true assume !(0 != activate_threads_~tmp___11~0#1); 486#L1593-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 430#L1344true assume !(1 == ~M_E~0); 521#L1344-2true assume !(1 == ~T1_E~0); 1747#L1349-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 655#L1354-1true assume !(1 == ~T3_E~0); 1007#L1359-1true assume !(1 == ~T4_E~0); 1587#L1364-1true assume !(1 == ~T5_E~0); 235#L1369-1true assume !(1 == ~T6_E~0); 983#L1374-1true assume !(1 == ~T7_E~0); 660#L1379-1true assume !(1 == ~T8_E~0); 713#L1384-1true assume !(1 == ~T9_E~0); 1769#L1389-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1246#L1394-1true assume !(1 == ~T11_E~0); 1674#L1399-1true assume !(1 == ~T12_E~0); 1470#L1404-1true assume !(1 == ~E_M~0); 298#L1409-1true assume !(1 == ~E_1~0); 1428#L1414-1true assume !(1 == ~E_2~0); 908#L1419-1true assume !(1 == ~E_3~0); 109#L1424-1true assume !(1 == ~E_4~0); 666#L1429-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1273#L1434-1true assume !(1 == ~E_6~0); 1658#L1439-1true assume !(1 == ~E_7~0); 134#L1444-1true assume !(1 == ~E_8~0); 854#L1449-1true assume !(1 == ~E_9~0); 351#L1454-1true assume !(1 == ~E_10~0); 1327#L1459-1true assume !(1 == ~E_11~0); 740#L1464-1true assume !(1 == ~E_12~0); 787#L1469-1true assume { :end_inline_reset_delta_events } true; 1521#L1815-2true [2022-02-21 04:23:06,066 INFO L793 eck$LassoCheckResult]: Loop: 1521#L1815-2true assume !false; 928#L1816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 689#L1181true assume false; 1759#L1196true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106#L846-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1653#L1206-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1670#L1206-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 739#L1211-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 173#L1216-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 500#L1221-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1032#L1226-3true assume !(0 == ~T5_E~0); 207#L1231-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 371#L1236-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1784#L1241-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1362#L1246-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1156#L1251-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 835#L1256-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 185#L1261-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 545#L1266-3true assume !(0 == ~E_M~0); 206#L1271-3true assume 0 == ~E_1~0;~E_1~0 := 1; 520#L1276-3true assume 0 == ~E_2~0;~E_2~0 := 1; 467#L1281-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1216#L1286-3true assume 0 == ~E_4~0;~E_4~0 := 1; 902#L1291-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1666#L1296-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1584#L1301-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1448#L1306-3true assume !(0 == ~E_8~0); 555#L1311-3true assume 0 == ~E_9~0;~E_9~0 := 1; 143#L1316-3true assume 0 == ~E_10~0;~E_10~0 := 1; 186#L1321-3true assume 0 == ~E_11~0;~E_11~0 := 1; 632#L1326-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1418#L1331-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 914#L598-42true assume !(1 == ~m_pc~0); 1054#L598-44true is_master_triggered_~__retres1~0#1 := 0; 1191#L609-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227#L610-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1449#L1497-42true assume !(0 != activate_threads_~tmp~1#1); 1704#L1497-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 672#L617-42true assume 1 == ~t1_pc~0; 497#L618-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 415#L628-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 718#L629-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1440#L1505-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 258#L1505-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1424#L636-42true assume !(1 == ~t2_pc~0); 529#L636-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1745#L647-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 820#L648-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1101#L1513-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1003#L1513-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 856#L655-42true assume 1 == ~t3_pc~0; 1603#L656-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1064#L666-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297#L667-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1758#L1521-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1214#L1521-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1112#L674-42true assume !(1 == ~t4_pc~0); 841#L674-44true is_transmit4_triggered_~__retres1~4#1 := 0; 775#L685-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84#L686-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 970#L1529-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 615#L1529-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1197#L693-42true assume !(1 == ~t5_pc~0); 1514#L693-44true is_transmit5_triggered_~__retres1~5#1 := 0; 881#L704-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1466#L705-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 877#L1537-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1159#L1537-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 355#L712-42true assume !(1 == ~t6_pc~0); 1591#L712-44true is_transmit6_triggered_~__retres1~6#1 := 0; 997#L723-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 735#L724-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1788#L1545-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 420#L1545-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1379#L731-42true assume !(1 == ~t7_pc~0); 255#L731-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1383#L742-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1095#L743-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 366#L1553-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1061#L1553-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 210#L750-42true assume 1 == ~t8_pc~0; 542#L751-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1562#L761-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 896#L762-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 152#L1561-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1696#L1561-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 614#L769-42true assume 1 == ~t9_pc~0; 480#L770-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1119#L780-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1239#L781-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1596#L1569-42true assume !(0 != activate_threads_~tmp___8~0#1); 259#L1569-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 620#L788-42true assume !(1 == ~t10_pc~0); 906#L788-44true is_transmit10_triggered_~__retres1~10#1 := 0; 1699#L799-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 578#L800-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1677#L1577-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1626#L1577-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1542#L807-42true assume !(1 == ~t11_pc~0); 60#L807-44true is_transmit11_triggered_~__retres1~11#1 := 0; 544#L818-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126#L819-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 127#L1585-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1155#L1585-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 257#L826-42true assume 1 == ~t12_pc~0; 1743#L827-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 986#L837-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1340#L838-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 253#L1593-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1487#L1593-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 838#L1344-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1225#L1344-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 776#L1349-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 334#L1354-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 790#L1359-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1662#L1364-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1553#L1369-3true assume !(1 == ~T6_E~0); 1272#L1374-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 213#L1379-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1162#L1384-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 333#L1389-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 514#L1394-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1727#L1399-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1293#L1404-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1232#L1409-3true assume !(1 == ~E_1~0); 1361#L1414-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1386#L1419-3true assume 1 == ~E_3~0;~E_3~0 := 2; 976#L1424-3true assume 1 == ~E_4~0;~E_4~0 := 2; 161#L1429-3true assume 1 == ~E_5~0;~E_5~0 := 2; 789#L1434-3true assume 1 == ~E_6~0;~E_6~0 := 2; 962#L1439-3true assume 1 == ~E_7~0;~E_7~0 := 2; 130#L1444-3true assume 1 == ~E_8~0;~E_8~0 := 2; 191#L1449-3true assume !(1 == ~E_9~0); 1447#L1454-3true assume 1 == ~E_10~0;~E_10~0 := 2; 785#L1459-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1775#L1464-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1268#L1469-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 676#L926-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83#L993-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 403#L994-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1592#L1834true assume !(0 == start_simulation_~tmp~3#1); 1108#L1834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 910#L926-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 584#L993-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 745#L994-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1252#L1789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1597#L1796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76#L1797true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 977#L1847true assume !(0 != start_simulation_~tmp___0~1#1); 1521#L1815-2true [2022-02-21 04:23:06,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:06,070 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-02-21 04:23:06,077 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:06,077 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200410761] [2022-02-21 04:23:06,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:06,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:06,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:06,297 INFO L290 TraceCheckUtils]: 0: Hoare triple {1802#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {1802#true} is VALID [2022-02-21 04:23:06,298 INFO L290 TraceCheckUtils]: 1: Hoare triple {1802#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {1804#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:06,298 INFO L290 TraceCheckUtils]: 2: Hoare triple {1804#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1804#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:06,299 INFO L290 TraceCheckUtils]: 3: Hoare triple {1804#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1804#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:06,300 INFO L290 TraceCheckUtils]: 4: Hoare triple {1804#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,300 INFO L290 TraceCheckUtils]: 5: Hoare triple {1803#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1803#false} is VALID [2022-02-21 04:23:06,300 INFO L290 TraceCheckUtils]: 6: Hoare triple {1803#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,300 INFO L290 TraceCheckUtils]: 7: Hoare triple {1803#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,301 INFO L290 TraceCheckUtils]: 8: Hoare triple {1803#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,301 INFO L290 TraceCheckUtils]: 9: Hoare triple {1803#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,301 INFO L290 TraceCheckUtils]: 10: Hoare triple {1803#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,301 INFO L290 TraceCheckUtils]: 11: Hoare triple {1803#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,301 INFO L290 TraceCheckUtils]: 12: Hoare triple {1803#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,302 INFO L290 TraceCheckUtils]: 13: Hoare triple {1803#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1803#false} is VALID [2022-02-21 04:23:06,302 INFO L290 TraceCheckUtils]: 14: Hoare triple {1803#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,302 INFO L290 TraceCheckUtils]: 15: Hoare triple {1803#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,302 INFO L290 TraceCheckUtils]: 16: Hoare triple {1803#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,302 INFO L290 TraceCheckUtils]: 17: Hoare triple {1803#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1803#false} is VALID [2022-02-21 04:23:06,303 INFO L290 TraceCheckUtils]: 18: Hoare triple {1803#false} assume !(0 == ~M_E~0); {1803#false} is VALID [2022-02-21 04:23:06,303 INFO L290 TraceCheckUtils]: 19: Hoare triple {1803#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1803#false} is VALID [2022-02-21 04:23:06,303 INFO L290 TraceCheckUtils]: 20: Hoare triple {1803#false} assume !(0 == ~T2_E~0); {1803#false} is VALID [2022-02-21 04:23:06,303 INFO L290 TraceCheckUtils]: 21: Hoare triple {1803#false} assume !(0 == ~T3_E~0); {1803#false} is VALID [2022-02-21 04:23:06,303 INFO L290 TraceCheckUtils]: 22: Hoare triple {1803#false} assume !(0 == ~T4_E~0); {1803#false} is VALID [2022-02-21 04:23:06,304 INFO L290 TraceCheckUtils]: 23: Hoare triple {1803#false} assume !(0 == ~T5_E~0); {1803#false} is VALID [2022-02-21 04:23:06,304 INFO L290 TraceCheckUtils]: 24: Hoare triple {1803#false} assume !(0 == ~T6_E~0); {1803#false} is VALID [2022-02-21 04:23:06,304 INFO L290 TraceCheckUtils]: 25: Hoare triple {1803#false} assume !(0 == ~T7_E~0); {1803#false} is VALID [2022-02-21 04:23:06,304 INFO L290 TraceCheckUtils]: 26: Hoare triple {1803#false} assume !(0 == ~T8_E~0); {1803#false} is VALID [2022-02-21 04:23:06,304 INFO L290 TraceCheckUtils]: 27: Hoare triple {1803#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1803#false} is VALID [2022-02-21 04:23:06,304 INFO L290 TraceCheckUtils]: 28: Hoare triple {1803#false} assume !(0 == ~T10_E~0); {1803#false} is VALID [2022-02-21 04:23:06,305 INFO L290 TraceCheckUtils]: 29: Hoare triple {1803#false} assume !(0 == ~T11_E~0); {1803#false} is VALID [2022-02-21 04:23:06,305 INFO L290 TraceCheckUtils]: 30: Hoare triple {1803#false} assume !(0 == ~T12_E~0); {1803#false} is VALID [2022-02-21 04:23:06,305 INFO L290 TraceCheckUtils]: 31: Hoare triple {1803#false} assume !(0 == ~E_M~0); {1803#false} is VALID [2022-02-21 04:23:06,305 INFO L290 TraceCheckUtils]: 32: Hoare triple {1803#false} assume !(0 == ~E_1~0); {1803#false} is VALID [2022-02-21 04:23:06,305 INFO L290 TraceCheckUtils]: 33: Hoare triple {1803#false} assume !(0 == ~E_2~0); {1803#false} is VALID [2022-02-21 04:23:06,306 INFO L290 TraceCheckUtils]: 34: Hoare triple {1803#false} assume !(0 == ~E_3~0); {1803#false} is VALID [2022-02-21 04:23:06,306 INFO L290 TraceCheckUtils]: 35: Hoare triple {1803#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1803#false} is VALID [2022-02-21 04:23:06,306 INFO L290 TraceCheckUtils]: 36: Hoare triple {1803#false} assume !(0 == ~E_5~0); {1803#false} is VALID [2022-02-21 04:23:06,306 INFO L290 TraceCheckUtils]: 37: Hoare triple {1803#false} assume !(0 == ~E_6~0); {1803#false} is VALID [2022-02-21 04:23:06,306 INFO L290 TraceCheckUtils]: 38: Hoare triple {1803#false} assume !(0 == ~E_7~0); {1803#false} is VALID [2022-02-21 04:23:06,307 INFO L290 TraceCheckUtils]: 39: Hoare triple {1803#false} assume !(0 == ~E_8~0); {1803#false} is VALID [2022-02-21 04:23:06,307 INFO L290 TraceCheckUtils]: 40: Hoare triple {1803#false} assume !(0 == ~E_9~0); {1803#false} is VALID [2022-02-21 04:23:06,307 INFO L290 TraceCheckUtils]: 41: Hoare triple {1803#false} assume !(0 == ~E_10~0); {1803#false} is VALID [2022-02-21 04:23:06,307 INFO L290 TraceCheckUtils]: 42: Hoare triple {1803#false} assume !(0 == ~E_11~0); {1803#false} is VALID [2022-02-21 04:23:06,307 INFO L290 TraceCheckUtils]: 43: Hoare triple {1803#false} assume 0 == ~E_12~0;~E_12~0 := 1; {1803#false} is VALID [2022-02-21 04:23:06,308 INFO L290 TraceCheckUtils]: 44: Hoare triple {1803#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1803#false} is VALID [2022-02-21 04:23:06,308 INFO L290 TraceCheckUtils]: 45: Hoare triple {1803#false} assume 1 == ~m_pc~0; {1803#false} is VALID [2022-02-21 04:23:06,308 INFO L290 TraceCheckUtils]: 46: Hoare triple {1803#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1803#false} is VALID [2022-02-21 04:23:06,308 INFO L290 TraceCheckUtils]: 47: Hoare triple {1803#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1803#false} is VALID [2022-02-21 04:23:06,308 INFO L290 TraceCheckUtils]: 48: Hoare triple {1803#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1803#false} is VALID [2022-02-21 04:23:06,309 INFO L290 TraceCheckUtils]: 49: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp~1#1); {1803#false} is VALID [2022-02-21 04:23:06,309 INFO L290 TraceCheckUtils]: 50: Hoare triple {1803#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1803#false} is VALID [2022-02-21 04:23:06,309 INFO L290 TraceCheckUtils]: 51: Hoare triple {1803#false} assume !(1 == ~t1_pc~0); {1803#false} is VALID [2022-02-21 04:23:06,309 INFO L290 TraceCheckUtils]: 52: Hoare triple {1803#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1803#false} is VALID [2022-02-21 04:23:06,309 INFO L290 TraceCheckUtils]: 53: Hoare triple {1803#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1803#false} is VALID [2022-02-21 04:23:06,310 INFO L290 TraceCheckUtils]: 54: Hoare triple {1803#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1803#false} is VALID [2022-02-21 04:23:06,310 INFO L290 TraceCheckUtils]: 55: Hoare triple {1803#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1803#false} is VALID [2022-02-21 04:23:06,310 INFO L290 TraceCheckUtils]: 56: Hoare triple {1803#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1803#false} is VALID [2022-02-21 04:23:06,310 INFO L290 TraceCheckUtils]: 57: Hoare triple {1803#false} assume 1 == ~t2_pc~0; {1803#false} is VALID [2022-02-21 04:23:06,310 INFO L290 TraceCheckUtils]: 58: Hoare triple {1803#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1803#false} is VALID [2022-02-21 04:23:06,311 INFO L290 TraceCheckUtils]: 59: Hoare triple {1803#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1803#false} is VALID [2022-02-21 04:23:06,311 INFO L290 TraceCheckUtils]: 60: Hoare triple {1803#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1803#false} is VALID [2022-02-21 04:23:06,311 INFO L290 TraceCheckUtils]: 61: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___1~0#1); {1803#false} is VALID [2022-02-21 04:23:06,311 INFO L290 TraceCheckUtils]: 62: Hoare triple {1803#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1803#false} is VALID [2022-02-21 04:23:06,311 INFO L290 TraceCheckUtils]: 63: Hoare triple {1803#false} assume !(1 == ~t3_pc~0); {1803#false} is VALID [2022-02-21 04:23:06,312 INFO L290 TraceCheckUtils]: 64: Hoare triple {1803#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1803#false} is VALID [2022-02-21 04:23:06,312 INFO L290 TraceCheckUtils]: 65: Hoare triple {1803#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1803#false} is VALID [2022-02-21 04:23:06,312 INFO L290 TraceCheckUtils]: 66: Hoare triple {1803#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1803#false} is VALID [2022-02-21 04:23:06,312 INFO L290 TraceCheckUtils]: 67: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___2~0#1); {1803#false} is VALID [2022-02-21 04:23:06,312 INFO L290 TraceCheckUtils]: 68: Hoare triple {1803#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1803#false} is VALID [2022-02-21 04:23:06,313 INFO L290 TraceCheckUtils]: 69: Hoare triple {1803#false} assume 1 == ~t4_pc~0; {1803#false} is VALID [2022-02-21 04:23:06,313 INFO L290 TraceCheckUtils]: 70: Hoare triple {1803#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1803#false} is VALID [2022-02-21 04:23:06,313 INFO L290 TraceCheckUtils]: 71: Hoare triple {1803#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1803#false} is VALID [2022-02-21 04:23:06,313 INFO L290 TraceCheckUtils]: 72: Hoare triple {1803#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1803#false} is VALID [2022-02-21 04:23:06,313 INFO L290 TraceCheckUtils]: 73: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___3~0#1); {1803#false} is VALID [2022-02-21 04:23:06,314 INFO L290 TraceCheckUtils]: 74: Hoare triple {1803#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1803#false} is VALID [2022-02-21 04:23:06,314 INFO L290 TraceCheckUtils]: 75: Hoare triple {1803#false} assume !(1 == ~t5_pc~0); {1803#false} is VALID [2022-02-21 04:23:06,314 INFO L290 TraceCheckUtils]: 76: Hoare triple {1803#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1803#false} is VALID [2022-02-21 04:23:06,314 INFO L290 TraceCheckUtils]: 77: Hoare triple {1803#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1803#false} is VALID [2022-02-21 04:23:06,314 INFO L290 TraceCheckUtils]: 78: Hoare triple {1803#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1803#false} is VALID [2022-02-21 04:23:06,315 INFO L290 TraceCheckUtils]: 79: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___4~0#1); {1803#false} is VALID [2022-02-21 04:23:06,315 INFO L290 TraceCheckUtils]: 80: Hoare triple {1803#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1803#false} is VALID [2022-02-21 04:23:06,315 INFO L290 TraceCheckUtils]: 81: Hoare triple {1803#false} assume 1 == ~t6_pc~0; {1803#false} is VALID [2022-02-21 04:23:06,315 INFO L290 TraceCheckUtils]: 82: Hoare triple {1803#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1803#false} is VALID [2022-02-21 04:23:06,315 INFO L290 TraceCheckUtils]: 83: Hoare triple {1803#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1803#false} is VALID [2022-02-21 04:23:06,315 INFO L290 TraceCheckUtils]: 84: Hoare triple {1803#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1803#false} is VALID [2022-02-21 04:23:06,316 INFO L290 TraceCheckUtils]: 85: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___5~0#1); {1803#false} is VALID [2022-02-21 04:23:06,316 INFO L290 TraceCheckUtils]: 86: Hoare triple {1803#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1803#false} is VALID [2022-02-21 04:23:06,316 INFO L290 TraceCheckUtils]: 87: Hoare triple {1803#false} assume 1 == ~t7_pc~0; {1803#false} is VALID [2022-02-21 04:23:06,316 INFO L290 TraceCheckUtils]: 88: Hoare triple {1803#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1803#false} is VALID [2022-02-21 04:23:06,316 INFO L290 TraceCheckUtils]: 89: Hoare triple {1803#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1803#false} is VALID [2022-02-21 04:23:06,317 INFO L290 TraceCheckUtils]: 90: Hoare triple {1803#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1803#false} is VALID [2022-02-21 04:23:06,317 INFO L290 TraceCheckUtils]: 91: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___6~0#1); {1803#false} is VALID [2022-02-21 04:23:06,317 INFO L290 TraceCheckUtils]: 92: Hoare triple {1803#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1803#false} is VALID [2022-02-21 04:23:06,317 INFO L290 TraceCheckUtils]: 93: Hoare triple {1803#false} assume !(1 == ~t8_pc~0); {1803#false} is VALID [2022-02-21 04:23:06,317 INFO L290 TraceCheckUtils]: 94: Hoare triple {1803#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1803#false} is VALID [2022-02-21 04:23:06,318 INFO L290 TraceCheckUtils]: 95: Hoare triple {1803#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1803#false} is VALID [2022-02-21 04:23:06,318 INFO L290 TraceCheckUtils]: 96: Hoare triple {1803#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1803#false} is VALID [2022-02-21 04:23:06,318 INFO L290 TraceCheckUtils]: 97: Hoare triple {1803#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1803#false} is VALID [2022-02-21 04:23:06,318 INFO L290 TraceCheckUtils]: 98: Hoare triple {1803#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1803#false} is VALID [2022-02-21 04:23:06,318 INFO L290 TraceCheckUtils]: 99: Hoare triple {1803#false} assume 1 == ~t9_pc~0; {1803#false} is VALID [2022-02-21 04:23:06,319 INFO L290 TraceCheckUtils]: 100: Hoare triple {1803#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1803#false} is VALID [2022-02-21 04:23:06,319 INFO L290 TraceCheckUtils]: 101: Hoare triple {1803#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1803#false} is VALID [2022-02-21 04:23:06,319 INFO L290 TraceCheckUtils]: 102: Hoare triple {1803#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1803#false} is VALID [2022-02-21 04:23:06,319 INFO L290 TraceCheckUtils]: 103: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___8~0#1); {1803#false} is VALID [2022-02-21 04:23:06,319 INFO L290 TraceCheckUtils]: 104: Hoare triple {1803#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1803#false} is VALID [2022-02-21 04:23:06,320 INFO L290 TraceCheckUtils]: 105: Hoare triple {1803#false} assume !(1 == ~t10_pc~0); {1803#false} is VALID [2022-02-21 04:23:06,320 INFO L290 TraceCheckUtils]: 106: Hoare triple {1803#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1803#false} is VALID [2022-02-21 04:23:06,320 INFO L290 TraceCheckUtils]: 107: Hoare triple {1803#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1803#false} is VALID [2022-02-21 04:23:06,320 INFO L290 TraceCheckUtils]: 108: Hoare triple {1803#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1803#false} is VALID [2022-02-21 04:23:06,320 INFO L290 TraceCheckUtils]: 109: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___9~0#1); {1803#false} is VALID [2022-02-21 04:23:06,321 INFO L290 TraceCheckUtils]: 110: Hoare triple {1803#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1803#false} is VALID [2022-02-21 04:23:06,321 INFO L290 TraceCheckUtils]: 111: Hoare triple {1803#false} assume 1 == ~t11_pc~0; {1803#false} is VALID [2022-02-21 04:23:06,321 INFO L290 TraceCheckUtils]: 112: Hoare triple {1803#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {1803#false} is VALID [2022-02-21 04:23:06,321 INFO L290 TraceCheckUtils]: 113: Hoare triple {1803#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1803#false} is VALID [2022-02-21 04:23:06,321 INFO L290 TraceCheckUtils]: 114: Hoare triple {1803#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1803#false} is VALID [2022-02-21 04:23:06,321 INFO L290 TraceCheckUtils]: 115: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___10~0#1); {1803#false} is VALID [2022-02-21 04:23:06,322 INFO L290 TraceCheckUtils]: 116: Hoare triple {1803#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1803#false} is VALID [2022-02-21 04:23:06,322 INFO L290 TraceCheckUtils]: 117: Hoare triple {1803#false} assume !(1 == ~t12_pc~0); {1803#false} is VALID [2022-02-21 04:23:06,322 INFO L290 TraceCheckUtils]: 118: Hoare triple {1803#false} is_transmit12_triggered_~__retres1~12#1 := 0; {1803#false} is VALID [2022-02-21 04:23:06,322 INFO L290 TraceCheckUtils]: 119: Hoare triple {1803#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1803#false} is VALID [2022-02-21 04:23:06,322 INFO L290 TraceCheckUtils]: 120: Hoare triple {1803#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1803#false} is VALID [2022-02-21 04:23:06,323 INFO L290 TraceCheckUtils]: 121: Hoare triple {1803#false} assume !(0 != activate_threads_~tmp___11~0#1); {1803#false} is VALID [2022-02-21 04:23:06,323 INFO L290 TraceCheckUtils]: 122: Hoare triple {1803#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1803#false} is VALID [2022-02-21 04:23:06,323 INFO L290 TraceCheckUtils]: 123: Hoare triple {1803#false} assume !(1 == ~M_E~0); {1803#false} is VALID [2022-02-21 04:23:06,323 INFO L290 TraceCheckUtils]: 124: Hoare triple {1803#false} assume !(1 == ~T1_E~0); {1803#false} is VALID [2022-02-21 04:23:06,323 INFO L290 TraceCheckUtils]: 125: Hoare triple {1803#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,324 INFO L290 TraceCheckUtils]: 126: Hoare triple {1803#false} assume !(1 == ~T3_E~0); {1803#false} is VALID [2022-02-21 04:23:06,324 INFO L290 TraceCheckUtils]: 127: Hoare triple {1803#false} assume !(1 == ~T4_E~0); {1803#false} is VALID [2022-02-21 04:23:06,324 INFO L290 TraceCheckUtils]: 128: Hoare triple {1803#false} assume !(1 == ~T5_E~0); {1803#false} is VALID [2022-02-21 04:23:06,324 INFO L290 TraceCheckUtils]: 129: Hoare triple {1803#false} assume !(1 == ~T6_E~0); {1803#false} is VALID [2022-02-21 04:23:06,324 INFO L290 TraceCheckUtils]: 130: Hoare triple {1803#false} assume !(1 == ~T7_E~0); {1803#false} is VALID [2022-02-21 04:23:06,325 INFO L290 TraceCheckUtils]: 131: Hoare triple {1803#false} assume !(1 == ~T8_E~0); {1803#false} is VALID [2022-02-21 04:23:06,325 INFO L290 TraceCheckUtils]: 132: Hoare triple {1803#false} assume !(1 == ~T9_E~0); {1803#false} is VALID [2022-02-21 04:23:06,325 INFO L290 TraceCheckUtils]: 133: Hoare triple {1803#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,325 INFO L290 TraceCheckUtils]: 134: Hoare triple {1803#false} assume !(1 == ~T11_E~0); {1803#false} is VALID [2022-02-21 04:23:06,325 INFO L290 TraceCheckUtils]: 135: Hoare triple {1803#false} assume !(1 == ~T12_E~0); {1803#false} is VALID [2022-02-21 04:23:06,325 INFO L290 TraceCheckUtils]: 136: Hoare triple {1803#false} assume !(1 == ~E_M~0); {1803#false} is VALID [2022-02-21 04:23:06,326 INFO L290 TraceCheckUtils]: 137: Hoare triple {1803#false} assume !(1 == ~E_1~0); {1803#false} is VALID [2022-02-21 04:23:06,326 INFO L290 TraceCheckUtils]: 138: Hoare triple {1803#false} assume !(1 == ~E_2~0); {1803#false} is VALID [2022-02-21 04:23:06,326 INFO L290 TraceCheckUtils]: 139: Hoare triple {1803#false} assume !(1 == ~E_3~0); {1803#false} is VALID [2022-02-21 04:23:06,326 INFO L290 TraceCheckUtils]: 140: Hoare triple {1803#false} assume !(1 == ~E_4~0); {1803#false} is VALID [2022-02-21 04:23:06,326 INFO L290 TraceCheckUtils]: 141: Hoare triple {1803#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1803#false} is VALID [2022-02-21 04:23:06,326 INFO L290 TraceCheckUtils]: 142: Hoare triple {1803#false} assume !(1 == ~E_6~0); {1803#false} is VALID [2022-02-21 04:23:06,327 INFO L290 TraceCheckUtils]: 143: Hoare triple {1803#false} assume !(1 == ~E_7~0); {1803#false} is VALID [2022-02-21 04:23:06,327 INFO L290 TraceCheckUtils]: 144: Hoare triple {1803#false} assume !(1 == ~E_8~0); {1803#false} is VALID [2022-02-21 04:23:06,327 INFO L290 TraceCheckUtils]: 145: Hoare triple {1803#false} assume !(1 == ~E_9~0); {1803#false} is VALID [2022-02-21 04:23:06,327 INFO L290 TraceCheckUtils]: 146: Hoare triple {1803#false} assume !(1 == ~E_10~0); {1803#false} is VALID [2022-02-21 04:23:06,327 INFO L290 TraceCheckUtils]: 147: Hoare triple {1803#false} assume !(1 == ~E_11~0); {1803#false} is VALID [2022-02-21 04:23:06,328 INFO L290 TraceCheckUtils]: 148: Hoare triple {1803#false} assume !(1 == ~E_12~0); {1803#false} is VALID [2022-02-21 04:23:06,328 INFO L290 TraceCheckUtils]: 149: Hoare triple {1803#false} assume { :end_inline_reset_delta_events } true; {1803#false} is VALID [2022-02-21 04:23:06,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:06,330 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:06,330 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200410761] [2022-02-21 04:23:06,330 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200410761] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:06,330 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:06,331 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:06,332 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254937992] [2022-02-21 04:23:06,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:06,335 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:06,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:06,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1437628410, now seen corresponding path program 1 times [2022-02-21 04:23:06,336 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:06,336 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139125080] [2022-02-21 04:23:06,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:06,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:06,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:06,370 INFO L290 TraceCheckUtils]: 0: Hoare triple {1805#true} assume !false; {1805#true} is VALID [2022-02-21 04:23:06,371 INFO L290 TraceCheckUtils]: 1: Hoare triple {1805#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1805#true} is VALID [2022-02-21 04:23:06,371 INFO L290 TraceCheckUtils]: 2: Hoare triple {1805#true} assume false; {1806#false} is VALID [2022-02-21 04:23:06,372 INFO L290 TraceCheckUtils]: 3: Hoare triple {1806#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1806#false} is VALID [2022-02-21 04:23:06,372 INFO L290 TraceCheckUtils]: 4: Hoare triple {1806#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1806#false} is VALID [2022-02-21 04:23:06,372 INFO L290 TraceCheckUtils]: 5: Hoare triple {1806#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,372 INFO L290 TraceCheckUtils]: 6: Hoare triple {1806#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,372 INFO L290 TraceCheckUtils]: 7: Hoare triple {1806#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,372 INFO L290 TraceCheckUtils]: 8: Hoare triple {1806#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,373 INFO L290 TraceCheckUtils]: 9: Hoare triple {1806#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,373 INFO L290 TraceCheckUtils]: 10: Hoare triple {1806#false} assume !(0 == ~T5_E~0); {1806#false} is VALID [2022-02-21 04:23:06,373 INFO L290 TraceCheckUtils]: 11: Hoare triple {1806#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,373 INFO L290 TraceCheckUtils]: 12: Hoare triple {1806#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,373 INFO L290 TraceCheckUtils]: 13: Hoare triple {1806#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,374 INFO L290 TraceCheckUtils]: 14: Hoare triple {1806#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,374 INFO L290 TraceCheckUtils]: 15: Hoare triple {1806#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,374 INFO L290 TraceCheckUtils]: 16: Hoare triple {1806#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,374 INFO L290 TraceCheckUtils]: 17: Hoare triple {1806#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,374 INFO L290 TraceCheckUtils]: 18: Hoare triple {1806#false} assume !(0 == ~E_M~0); {1806#false} is VALID [2022-02-21 04:23:06,375 INFO L290 TraceCheckUtils]: 19: Hoare triple {1806#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,375 INFO L290 TraceCheckUtils]: 20: Hoare triple {1806#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,375 INFO L290 TraceCheckUtils]: 21: Hoare triple {1806#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,375 INFO L290 TraceCheckUtils]: 22: Hoare triple {1806#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,375 INFO L290 TraceCheckUtils]: 23: Hoare triple {1806#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,375 INFO L290 TraceCheckUtils]: 24: Hoare triple {1806#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,376 INFO L290 TraceCheckUtils]: 25: Hoare triple {1806#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,376 INFO L290 TraceCheckUtils]: 26: Hoare triple {1806#false} assume !(0 == ~E_8~0); {1806#false} is VALID [2022-02-21 04:23:06,376 INFO L290 TraceCheckUtils]: 27: Hoare triple {1806#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,376 INFO L290 TraceCheckUtils]: 28: Hoare triple {1806#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,376 INFO L290 TraceCheckUtils]: 29: Hoare triple {1806#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,377 INFO L290 TraceCheckUtils]: 30: Hoare triple {1806#false} assume 0 == ~E_12~0;~E_12~0 := 1; {1806#false} is VALID [2022-02-21 04:23:06,377 INFO L290 TraceCheckUtils]: 31: Hoare triple {1806#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1806#false} is VALID [2022-02-21 04:23:06,377 INFO L290 TraceCheckUtils]: 32: Hoare triple {1806#false} assume !(1 == ~m_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,377 INFO L290 TraceCheckUtils]: 33: Hoare triple {1806#false} is_master_triggered_~__retres1~0#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,377 INFO L290 TraceCheckUtils]: 34: Hoare triple {1806#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1806#false} is VALID [2022-02-21 04:23:06,378 INFO L290 TraceCheckUtils]: 35: Hoare triple {1806#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1806#false} is VALID [2022-02-21 04:23:06,378 INFO L290 TraceCheckUtils]: 36: Hoare triple {1806#false} assume !(0 != activate_threads_~tmp~1#1); {1806#false} is VALID [2022-02-21 04:23:06,378 INFO L290 TraceCheckUtils]: 37: Hoare triple {1806#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1806#false} is VALID [2022-02-21 04:23:06,378 INFO L290 TraceCheckUtils]: 38: Hoare triple {1806#false} assume 1 == ~t1_pc~0; {1806#false} is VALID [2022-02-21 04:23:06,378 INFO L290 TraceCheckUtils]: 39: Hoare triple {1806#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1806#false} is VALID [2022-02-21 04:23:06,379 INFO L290 TraceCheckUtils]: 40: Hoare triple {1806#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1806#false} is VALID [2022-02-21 04:23:06,379 INFO L290 TraceCheckUtils]: 41: Hoare triple {1806#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1806#false} is VALID [2022-02-21 04:23:06,379 INFO L290 TraceCheckUtils]: 42: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,379 INFO L290 TraceCheckUtils]: 43: Hoare triple {1806#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1806#false} is VALID [2022-02-21 04:23:06,379 INFO L290 TraceCheckUtils]: 44: Hoare triple {1806#false} assume !(1 == ~t2_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,379 INFO L290 TraceCheckUtils]: 45: Hoare triple {1806#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,380 INFO L290 TraceCheckUtils]: 46: Hoare triple {1806#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1806#false} is VALID [2022-02-21 04:23:06,380 INFO L290 TraceCheckUtils]: 47: Hoare triple {1806#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1806#false} is VALID [2022-02-21 04:23:06,380 INFO L290 TraceCheckUtils]: 48: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,380 INFO L290 TraceCheckUtils]: 49: Hoare triple {1806#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1806#false} is VALID [2022-02-21 04:23:06,380 INFO L290 TraceCheckUtils]: 50: Hoare triple {1806#false} assume 1 == ~t3_pc~0; {1806#false} is VALID [2022-02-21 04:23:06,381 INFO L290 TraceCheckUtils]: 51: Hoare triple {1806#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1806#false} is VALID [2022-02-21 04:23:06,381 INFO L290 TraceCheckUtils]: 52: Hoare triple {1806#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1806#false} is VALID [2022-02-21 04:23:06,381 INFO L290 TraceCheckUtils]: 53: Hoare triple {1806#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1806#false} is VALID [2022-02-21 04:23:06,381 INFO L290 TraceCheckUtils]: 54: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,381 INFO L290 TraceCheckUtils]: 55: Hoare triple {1806#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1806#false} is VALID [2022-02-21 04:23:06,382 INFO L290 TraceCheckUtils]: 56: Hoare triple {1806#false} assume !(1 == ~t4_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,382 INFO L290 TraceCheckUtils]: 57: Hoare triple {1806#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,382 INFO L290 TraceCheckUtils]: 58: Hoare triple {1806#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1806#false} is VALID [2022-02-21 04:23:06,382 INFO L290 TraceCheckUtils]: 59: Hoare triple {1806#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1806#false} is VALID [2022-02-21 04:23:06,382 INFO L290 TraceCheckUtils]: 60: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,383 INFO L290 TraceCheckUtils]: 61: Hoare triple {1806#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1806#false} is VALID [2022-02-21 04:23:06,383 INFO L290 TraceCheckUtils]: 62: Hoare triple {1806#false} assume !(1 == ~t5_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,383 INFO L290 TraceCheckUtils]: 63: Hoare triple {1806#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,383 INFO L290 TraceCheckUtils]: 64: Hoare triple {1806#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1806#false} is VALID [2022-02-21 04:23:06,383 INFO L290 TraceCheckUtils]: 65: Hoare triple {1806#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1806#false} is VALID [2022-02-21 04:23:06,383 INFO L290 TraceCheckUtils]: 66: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,384 INFO L290 TraceCheckUtils]: 67: Hoare triple {1806#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1806#false} is VALID [2022-02-21 04:23:06,384 INFO L290 TraceCheckUtils]: 68: Hoare triple {1806#false} assume !(1 == ~t6_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,384 INFO L290 TraceCheckUtils]: 69: Hoare triple {1806#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,384 INFO L290 TraceCheckUtils]: 70: Hoare triple {1806#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1806#false} is VALID [2022-02-21 04:23:06,384 INFO L290 TraceCheckUtils]: 71: Hoare triple {1806#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1806#false} is VALID [2022-02-21 04:23:06,385 INFO L290 TraceCheckUtils]: 72: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,385 INFO L290 TraceCheckUtils]: 73: Hoare triple {1806#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1806#false} is VALID [2022-02-21 04:23:06,385 INFO L290 TraceCheckUtils]: 74: Hoare triple {1806#false} assume !(1 == ~t7_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,385 INFO L290 TraceCheckUtils]: 75: Hoare triple {1806#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,385 INFO L290 TraceCheckUtils]: 76: Hoare triple {1806#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1806#false} is VALID [2022-02-21 04:23:06,386 INFO L290 TraceCheckUtils]: 77: Hoare triple {1806#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1806#false} is VALID [2022-02-21 04:23:06,386 INFO L290 TraceCheckUtils]: 78: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,386 INFO L290 TraceCheckUtils]: 79: Hoare triple {1806#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1806#false} is VALID [2022-02-21 04:23:06,386 INFO L290 TraceCheckUtils]: 80: Hoare triple {1806#false} assume 1 == ~t8_pc~0; {1806#false} is VALID [2022-02-21 04:23:06,386 INFO L290 TraceCheckUtils]: 81: Hoare triple {1806#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1806#false} is VALID [2022-02-21 04:23:06,387 INFO L290 TraceCheckUtils]: 82: Hoare triple {1806#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1806#false} is VALID [2022-02-21 04:23:06,387 INFO L290 TraceCheckUtils]: 83: Hoare triple {1806#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1806#false} is VALID [2022-02-21 04:23:06,387 INFO L290 TraceCheckUtils]: 84: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,387 INFO L290 TraceCheckUtils]: 85: Hoare triple {1806#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1806#false} is VALID [2022-02-21 04:23:06,387 INFO L290 TraceCheckUtils]: 86: Hoare triple {1806#false} assume 1 == ~t9_pc~0; {1806#false} is VALID [2022-02-21 04:23:06,388 INFO L290 TraceCheckUtils]: 87: Hoare triple {1806#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1806#false} is VALID [2022-02-21 04:23:06,388 INFO L290 TraceCheckUtils]: 88: Hoare triple {1806#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1806#false} is VALID [2022-02-21 04:23:06,388 INFO L290 TraceCheckUtils]: 89: Hoare triple {1806#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1806#false} is VALID [2022-02-21 04:23:06,388 INFO L290 TraceCheckUtils]: 90: Hoare triple {1806#false} assume !(0 != activate_threads_~tmp___8~0#1); {1806#false} is VALID [2022-02-21 04:23:06,388 INFO L290 TraceCheckUtils]: 91: Hoare triple {1806#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1806#false} is VALID [2022-02-21 04:23:06,388 INFO L290 TraceCheckUtils]: 92: Hoare triple {1806#false} assume !(1 == ~t10_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,389 INFO L290 TraceCheckUtils]: 93: Hoare triple {1806#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,389 INFO L290 TraceCheckUtils]: 94: Hoare triple {1806#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1806#false} is VALID [2022-02-21 04:23:06,389 INFO L290 TraceCheckUtils]: 95: Hoare triple {1806#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1806#false} is VALID [2022-02-21 04:23:06,389 INFO L290 TraceCheckUtils]: 96: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,389 INFO L290 TraceCheckUtils]: 97: Hoare triple {1806#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1806#false} is VALID [2022-02-21 04:23:06,390 INFO L290 TraceCheckUtils]: 98: Hoare triple {1806#false} assume !(1 == ~t11_pc~0); {1806#false} is VALID [2022-02-21 04:23:06,390 INFO L290 TraceCheckUtils]: 99: Hoare triple {1806#false} is_transmit11_triggered_~__retres1~11#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,390 INFO L290 TraceCheckUtils]: 100: Hoare triple {1806#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1806#false} is VALID [2022-02-21 04:23:06,390 INFO L290 TraceCheckUtils]: 101: Hoare triple {1806#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1806#false} is VALID [2022-02-21 04:23:06,390 INFO L290 TraceCheckUtils]: 102: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,391 INFO L290 TraceCheckUtils]: 103: Hoare triple {1806#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1806#false} is VALID [2022-02-21 04:23:06,391 INFO L290 TraceCheckUtils]: 104: Hoare triple {1806#false} assume 1 == ~t12_pc~0; {1806#false} is VALID [2022-02-21 04:23:06,391 INFO L290 TraceCheckUtils]: 105: Hoare triple {1806#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {1806#false} is VALID [2022-02-21 04:23:06,391 INFO L290 TraceCheckUtils]: 106: Hoare triple {1806#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1806#false} is VALID [2022-02-21 04:23:06,391 INFO L290 TraceCheckUtils]: 107: Hoare triple {1806#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1806#false} is VALID [2022-02-21 04:23:06,391 INFO L290 TraceCheckUtils]: 108: Hoare triple {1806#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {1806#false} is VALID [2022-02-21 04:23:06,392 INFO L290 TraceCheckUtils]: 109: Hoare triple {1806#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1806#false} is VALID [2022-02-21 04:23:06,392 INFO L290 TraceCheckUtils]: 110: Hoare triple {1806#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,392 INFO L290 TraceCheckUtils]: 111: Hoare triple {1806#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,392 INFO L290 TraceCheckUtils]: 112: Hoare triple {1806#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,392 INFO L290 TraceCheckUtils]: 113: Hoare triple {1806#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,392 INFO L290 TraceCheckUtils]: 114: Hoare triple {1806#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,393 INFO L290 TraceCheckUtils]: 115: Hoare triple {1806#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,393 INFO L290 TraceCheckUtils]: 116: Hoare triple {1806#false} assume !(1 == ~T6_E~0); {1806#false} is VALID [2022-02-21 04:23:06,393 INFO L290 TraceCheckUtils]: 117: Hoare triple {1806#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,393 INFO L290 TraceCheckUtils]: 118: Hoare triple {1806#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,393 INFO L290 TraceCheckUtils]: 119: Hoare triple {1806#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,393 INFO L290 TraceCheckUtils]: 120: Hoare triple {1806#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,394 INFO L290 TraceCheckUtils]: 121: Hoare triple {1806#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,394 INFO L290 TraceCheckUtils]: 122: Hoare triple {1806#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,394 INFO L290 TraceCheckUtils]: 123: Hoare triple {1806#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,394 INFO L290 TraceCheckUtils]: 124: Hoare triple {1806#false} assume !(1 == ~E_1~0); {1806#false} is VALID [2022-02-21 04:23:06,394 INFO L290 TraceCheckUtils]: 125: Hoare triple {1806#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,394 INFO L290 TraceCheckUtils]: 126: Hoare triple {1806#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,395 INFO L290 TraceCheckUtils]: 127: Hoare triple {1806#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,395 INFO L290 TraceCheckUtils]: 128: Hoare triple {1806#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,395 INFO L290 TraceCheckUtils]: 129: Hoare triple {1806#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,395 INFO L290 TraceCheckUtils]: 130: Hoare triple {1806#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,395 INFO L290 TraceCheckUtils]: 131: Hoare triple {1806#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,395 INFO L290 TraceCheckUtils]: 132: Hoare triple {1806#false} assume !(1 == ~E_9~0); {1806#false} is VALID [2022-02-21 04:23:06,396 INFO L290 TraceCheckUtils]: 133: Hoare triple {1806#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,396 INFO L290 TraceCheckUtils]: 134: Hoare triple {1806#false} assume 1 == ~E_11~0;~E_11~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,396 INFO L290 TraceCheckUtils]: 135: Hoare triple {1806#false} assume 1 == ~E_12~0;~E_12~0 := 2; {1806#false} is VALID [2022-02-21 04:23:06,396 INFO L290 TraceCheckUtils]: 136: Hoare triple {1806#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {1806#false} is VALID [2022-02-21 04:23:06,396 INFO L290 TraceCheckUtils]: 137: Hoare triple {1806#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {1806#false} is VALID [2022-02-21 04:23:06,396 INFO L290 TraceCheckUtils]: 138: Hoare triple {1806#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {1806#false} is VALID [2022-02-21 04:23:06,397 INFO L290 TraceCheckUtils]: 139: Hoare triple {1806#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {1806#false} is VALID [2022-02-21 04:23:06,397 INFO L290 TraceCheckUtils]: 140: Hoare triple {1806#false} assume !(0 == start_simulation_~tmp~3#1); {1806#false} is VALID [2022-02-21 04:23:06,397 INFO L290 TraceCheckUtils]: 141: Hoare triple {1806#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {1806#false} is VALID [2022-02-21 04:23:06,397 INFO L290 TraceCheckUtils]: 142: Hoare triple {1806#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {1806#false} is VALID [2022-02-21 04:23:06,397 INFO L290 TraceCheckUtils]: 143: Hoare triple {1806#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {1806#false} is VALID [2022-02-21 04:23:06,397 INFO L290 TraceCheckUtils]: 144: Hoare triple {1806#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {1806#false} is VALID [2022-02-21 04:23:06,398 INFO L290 TraceCheckUtils]: 145: Hoare triple {1806#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1806#false} is VALID [2022-02-21 04:23:06,398 INFO L290 TraceCheckUtils]: 146: Hoare triple {1806#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1806#false} is VALID [2022-02-21 04:23:06,398 INFO L290 TraceCheckUtils]: 147: Hoare triple {1806#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {1806#false} is VALID [2022-02-21 04:23:06,398 INFO L290 TraceCheckUtils]: 148: Hoare triple {1806#false} assume !(0 != start_simulation_~tmp___0~1#1); {1806#false} is VALID [2022-02-21 04:23:06,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:06,399 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:06,399 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139125080] [2022-02-21 04:23:06,399 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139125080] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:06,400 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:06,400 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:06,400 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [504216059] [2022-02-21 04:23:06,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:06,401 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:06,402 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:06,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:23:06,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:23:06,424 INFO L87 Difference]: Start difference. First operand has 1798 states, 1797 states have (on average 1.4997217584863662) internal successors, (2695), 1797 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,324 INFO L93 Difference]: Finished difference Result 1796 states and 2661 transitions. [2022-02-21 04:23:07,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:23:07,330 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,428 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 149 edges. 149 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:07,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1796 states and 2661 transitions. [2022-02-21 04:23:07,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:07,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1796 states to 1790 states and 2655 transitions. [2022-02-21 04:23:07,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:07,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:07,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2655 transitions. [2022-02-21 04:23:07,612 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:07,612 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-02-21 04:23:07,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2655 transitions. [2022-02-21 04:23:07,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:07,676 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:07,683 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2655 transitions. Second operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,689 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2655 transitions. Second operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,693 INFO L87 Difference]: Start difference. First operand 1790 states and 2655 transitions. Second operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,771 INFO L93 Difference]: Finished difference Result 1790 states and 2655 transitions. [2022-02-21 04:23:07,772 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2655 transitions. [2022-02-21 04:23:07,776 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,776 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,779 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2655 transitions. [2022-02-21 04:23:07,782 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2655 transitions. [2022-02-21 04:23:07,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:07,859 INFO L93 Difference]: Finished difference Result 1790 states and 2655 transitions. [2022-02-21 04:23:07,859 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2655 transitions. [2022-02-21 04:23:07,861 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:07,862 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:07,862 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:07,862 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:07,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4832402234636872) internal successors, (2655), 1789 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:07,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2655 transitions. [2022-02-21 04:23:07,942 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-02-21 04:23:07,942 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2655 transitions. [2022-02-21 04:23:07,942 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:23:07,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2655 transitions. [2022-02-21 04:23:07,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:07,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:07,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:07,950 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,951 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:07,951 INFO L791 eck$LassoCheckResult]: Stem: 4447#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3871#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3841#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3842#L853 assume !(1 == ~m_i~0);~m_st~0 := 2; 5103#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4150#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3603#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3604#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4875#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5014#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5380#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5381#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4360#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4361#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4901#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4821#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4822#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4974#L1206 assume !(0 == ~M_E~0); 4339#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4340#L1211-1 assume !(0 == ~T2_E~0); 5233#L1216-1 assume !(0 == ~T3_E~0); 4132#L1221-1 assume !(0 == ~T4_E~0); 4133#L1226-1 assume !(0 == ~T5_E~0); 3795#L1231-1 assume !(0 == ~T6_E~0); 3796#L1236-1 assume !(0 == ~T7_E~0); 5264#L1241-1 assume !(0 == ~T8_E~0); 4194#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4195#L1251-1 assume !(0 == ~T10_E~0); 4415#L1256-1 assume !(0 == ~T11_E~0); 3615#L1261-1 assume !(0 == ~T12_E~0); 3616#L1266-1 assume !(0 == ~E_M~0); 5367#L1271-1 assume !(0 == ~E_1~0); 5002#L1276-1 assume !(0 == ~E_2~0); 5003#L1281-1 assume !(0 == ~E_3~0); 4928#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4036#L1291-1 assume !(0 == ~E_5~0); 4037#L1296-1 assume !(0 == ~E_6~0); 4743#L1301-1 assume !(0 == ~E_7~0); 4744#L1306-1 assume !(0 == ~E_8~0); 5176#L1311-1 assume !(0 == ~E_9~0); 3997#L1316-1 assume !(0 == ~E_10~0); 3998#L1321-1 assume !(0 == ~E_11~0); 4760#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3861#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3862#L598 assume 1 == ~m_pc~0; 3921#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3922#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5246#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5338#L1497 assume !(0 != activate_threads_~tmp~1#1); 5339#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5295#L617 assume !(1 == ~t1_pc~0); 4217#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4218#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4078#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4838#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4839#L636 assume 1 == ~t2_pc~0; 4186#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4187#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4017#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4018#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 4874#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4537#L655 assume !(1 == ~t3_pc~0); 4538#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5251#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3891#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3892#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 5368#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5369#L674 assume 1 == ~t4_pc~0; 3711#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3712#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5009#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4019#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 4020#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4534#L693 assume !(1 == ~t5_pc~0); 4697#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4341#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4342#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5178#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 4427#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4364#L712 assume 1 == ~t6_pc~0; 4365#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4792#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4793#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5079#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 4890#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4888#L731 assume 1 == ~t7_pc~0; 3865#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3866#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4060#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4997#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 5116#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3975#L750 assume !(1 == ~t8_pc~0); 3646#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3645#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4161#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5191#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4298#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4299#L769 assume 1 == ~t9_pc~0; 4834#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3819#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3820#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4603#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 5055#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5136#L788 assume !(1 == ~t10_pc~0); 4711#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4712#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4943#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4944#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 3971#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3972#L807 assume 1 == ~t11_pc~0; 5145#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4723#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4876#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5287#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 5392#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5235#L826 assume !(1 == ~t12_pc~0); 4367#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4368#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4896#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5327#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 4527#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4436#L1344 assume !(1 == ~M_E~0); 4437#L1344-2 assume !(1 == ~T1_E~0); 4578#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4750#L1354-1 assume !(1 == ~T3_E~0); 4751#L1359-1 assume !(1 == ~T4_E~0); 5125#L1364-1 assume !(1 == ~T5_E~0); 4079#L1369-1 assume !(1 == ~T6_E~0); 4080#L1374-1 assume !(1 == ~T7_E~0); 4756#L1379-1 assume !(1 == ~T8_E~0); 4757#L1384-1 assume !(1 == ~T9_E~0); 4820#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5266#L1394-1 assume !(1 == ~T11_E~0); 5267#L1399-1 assume !(1 == ~T12_E~0); 5346#L1404-1 assume !(1 == ~E_M~0); 4198#L1409-1 assume !(1 == ~E_1~0); 4199#L1414-1 assume !(1 == ~E_2~0); 5036#L1419-1 assume !(1 == ~E_3~0); 3832#L1424-1 assume !(1 == ~E_4~0); 3833#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4767#L1434-1 assume !(1 == ~E_6~0); 5285#L1439-1 assume !(1 == ~E_7~0); 3887#L1444-1 assume !(1 == ~E_8~0); 3888#L1449-1 assume !(1 == ~E_9~0); 4303#L1454-1 assume !(1 == ~E_10~0); 4304#L1459-1 assume !(1 == ~E_11~0); 4854#L1464-1 assume !(1 == ~E_12~0); 4855#L1469-1 assume { :end_inline_reset_delta_events } true; 4902#L1815-2 [2022-02-21 04:23:07,952 INFO L793 eck$LassoCheckResult]: Loop: 4902#L1815-2 assume !false; 5056#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4725#L1181 assume !false; 4796#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4748#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3606#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4335#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4886#L1008 assume !(0 != eval_~tmp~0#1); 4887#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3825#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3826#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5386#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4853#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3959#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3960#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4550#L1226-3 assume !(0 == ~T5_E~0); 4023#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4024#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4336#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5323#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5226#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4962#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3981#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3982#L1266-3 assume !(0 == ~E_M~0); 4021#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4022#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4494#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4495#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5032#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5033#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5375#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5343#L1306-3 assume !(0 == ~E_8~0); 4619#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3905#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3906#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3983#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4718#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5043#L598-42 assume !(1 == ~m_pc~0); 5044#L598-44 is_master_triggered_~__retres1~0#1 := 0; 5158#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4061#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4062#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 5344#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4774#L617-42 assume 1 == ~t1_pc~0; 4546#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4411#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4412#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4826#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4126#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4127#L636-42 assume 1 == ~t2_pc~0; 5328#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4591#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4941#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4942#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5121#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L655-42 assume !(1 == ~t3_pc~0); 4563#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4564#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4196#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4197#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5250#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5195#L674-42 assume !(1 == ~t4_pc~0); 4969#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4891#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3780#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3781#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4695#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4696#L693-42 assume 1 == ~t5_pc~0; 4951#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4952#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5012#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5007#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5008#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4310#L712-42 assume !(1 == ~t6_pc~0); 4311#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4637#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4845#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4846#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4419#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4420#L731-42 assume !(1 == ~t7_pc~0); 4118#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4119#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5186#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4327#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4328#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4031#L750-42 assume 1 == ~t8_pc~0; 4032#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4606#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5029#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3924#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3925#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4694#L769-42 assume 1 == ~t9_pc~0; 4516#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4517#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5200#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5265#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 4128#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4129#L788-42 assume 1 == ~t10_pc~0; 4702#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4916#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4646#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4647#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5384#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5362#L807-42 assume !(1 == ~t11_pc~0); 3732#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3733#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3872#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3873#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3874#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4123#L826-42 assume 1 == ~t12_pc~0; 4124#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4316#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5108#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4113#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4114#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4965#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4966#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4892#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4273#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4274#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4906#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5364#L1369-3 assume !(1 == ~T6_E~0); 5284#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4038#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4039#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4271#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4272#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4570#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5293#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5256#L1409-3 assume !(1 == ~E_1~0); 5257#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5322#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5102#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3939#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3940#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4905#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3879#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3880#L1449-3 assume !(1 == ~E_9~0); 3989#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4899#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4900#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5281#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4779#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3778#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3779#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4395#L1834 assume !(0 == start_simulation_~tmp~3#1); 5015#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5038#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4472#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4651#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4863#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5271#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3764#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3765#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 4902#L1815-2 [2022-02-21 04:23:07,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:07,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-02-21 04:23:07,953 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:07,953 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338153980] [2022-02-21 04:23:07,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:07,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:07,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:07,992 INFO L290 TraceCheckUtils]: 0: Hoare triple {8976#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {8976#true} is VALID [2022-02-21 04:23:07,993 INFO L290 TraceCheckUtils]: 1: Hoare triple {8976#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {8978#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:07,993 INFO L290 TraceCheckUtils]: 2: Hoare triple {8978#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8978#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:07,994 INFO L290 TraceCheckUtils]: 3: Hoare triple {8978#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8978#(= ~m_i~0 1)} is VALID [2022-02-21 04:23:07,994 INFO L290 TraceCheckUtils]: 4: Hoare triple {8978#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,994 INFO L290 TraceCheckUtils]: 5: Hoare triple {8977#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8977#false} is VALID [2022-02-21 04:23:07,994 INFO L290 TraceCheckUtils]: 6: Hoare triple {8977#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,995 INFO L290 TraceCheckUtils]: 7: Hoare triple {8977#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,995 INFO L290 TraceCheckUtils]: 8: Hoare triple {8977#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,995 INFO L290 TraceCheckUtils]: 9: Hoare triple {8977#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,995 INFO L290 TraceCheckUtils]: 10: Hoare triple {8977#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,995 INFO L290 TraceCheckUtils]: 11: Hoare triple {8977#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,995 INFO L290 TraceCheckUtils]: 12: Hoare triple {8977#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,995 INFO L290 TraceCheckUtils]: 13: Hoare triple {8977#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {8977#false} is VALID [2022-02-21 04:23:07,996 INFO L290 TraceCheckUtils]: 14: Hoare triple {8977#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,996 INFO L290 TraceCheckUtils]: 15: Hoare triple {8977#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,996 INFO L290 TraceCheckUtils]: 16: Hoare triple {8977#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {8977#false} is VALID [2022-02-21 04:23:07,996 INFO L290 TraceCheckUtils]: 17: Hoare triple {8977#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8977#false} is VALID [2022-02-21 04:23:07,996 INFO L290 TraceCheckUtils]: 18: Hoare triple {8977#false} assume !(0 == ~M_E~0); {8977#false} is VALID [2022-02-21 04:23:07,996 INFO L290 TraceCheckUtils]: 19: Hoare triple {8977#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8977#false} is VALID [2022-02-21 04:23:07,996 INFO L290 TraceCheckUtils]: 20: Hoare triple {8977#false} assume !(0 == ~T2_E~0); {8977#false} is VALID [2022-02-21 04:23:07,997 INFO L290 TraceCheckUtils]: 21: Hoare triple {8977#false} assume !(0 == ~T3_E~0); {8977#false} is VALID [2022-02-21 04:23:07,997 INFO L290 TraceCheckUtils]: 22: Hoare triple {8977#false} assume !(0 == ~T4_E~0); {8977#false} is VALID [2022-02-21 04:23:07,997 INFO L290 TraceCheckUtils]: 23: Hoare triple {8977#false} assume !(0 == ~T5_E~0); {8977#false} is VALID [2022-02-21 04:23:07,997 INFO L290 TraceCheckUtils]: 24: Hoare triple {8977#false} assume !(0 == ~T6_E~0); {8977#false} is VALID [2022-02-21 04:23:07,997 INFO L290 TraceCheckUtils]: 25: Hoare triple {8977#false} assume !(0 == ~T7_E~0); {8977#false} is VALID [2022-02-21 04:23:07,997 INFO L290 TraceCheckUtils]: 26: Hoare triple {8977#false} assume !(0 == ~T8_E~0); {8977#false} is VALID [2022-02-21 04:23:07,997 INFO L290 TraceCheckUtils]: 27: Hoare triple {8977#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {8977#false} is VALID [2022-02-21 04:23:07,998 INFO L290 TraceCheckUtils]: 28: Hoare triple {8977#false} assume !(0 == ~T10_E~0); {8977#false} is VALID [2022-02-21 04:23:07,998 INFO L290 TraceCheckUtils]: 29: Hoare triple {8977#false} assume !(0 == ~T11_E~0); {8977#false} is VALID [2022-02-21 04:23:07,998 INFO L290 TraceCheckUtils]: 30: Hoare triple {8977#false} assume !(0 == ~T12_E~0); {8977#false} is VALID [2022-02-21 04:23:07,998 INFO L290 TraceCheckUtils]: 31: Hoare triple {8977#false} assume !(0 == ~E_M~0); {8977#false} is VALID [2022-02-21 04:23:07,998 INFO L290 TraceCheckUtils]: 32: Hoare triple {8977#false} assume !(0 == ~E_1~0); {8977#false} is VALID [2022-02-21 04:23:07,998 INFO L290 TraceCheckUtils]: 33: Hoare triple {8977#false} assume !(0 == ~E_2~0); {8977#false} is VALID [2022-02-21 04:23:07,999 INFO L290 TraceCheckUtils]: 34: Hoare triple {8977#false} assume !(0 == ~E_3~0); {8977#false} is VALID [2022-02-21 04:23:07,999 INFO L290 TraceCheckUtils]: 35: Hoare triple {8977#false} assume 0 == ~E_4~0;~E_4~0 := 1; {8977#false} is VALID [2022-02-21 04:23:07,999 INFO L290 TraceCheckUtils]: 36: Hoare triple {8977#false} assume !(0 == ~E_5~0); {8977#false} is VALID [2022-02-21 04:23:07,999 INFO L290 TraceCheckUtils]: 37: Hoare triple {8977#false} assume !(0 == ~E_6~0); {8977#false} is VALID [2022-02-21 04:23:07,999 INFO L290 TraceCheckUtils]: 38: Hoare triple {8977#false} assume !(0 == ~E_7~0); {8977#false} is VALID [2022-02-21 04:23:07,999 INFO L290 TraceCheckUtils]: 39: Hoare triple {8977#false} assume !(0 == ~E_8~0); {8977#false} is VALID [2022-02-21 04:23:07,999 INFO L290 TraceCheckUtils]: 40: Hoare triple {8977#false} assume !(0 == ~E_9~0); {8977#false} is VALID [2022-02-21 04:23:08,000 INFO L290 TraceCheckUtils]: 41: Hoare triple {8977#false} assume !(0 == ~E_10~0); {8977#false} is VALID [2022-02-21 04:23:08,000 INFO L290 TraceCheckUtils]: 42: Hoare triple {8977#false} assume !(0 == ~E_11~0); {8977#false} is VALID [2022-02-21 04:23:08,000 INFO L290 TraceCheckUtils]: 43: Hoare triple {8977#false} assume 0 == ~E_12~0;~E_12~0 := 1; {8977#false} is VALID [2022-02-21 04:23:08,000 INFO L290 TraceCheckUtils]: 44: Hoare triple {8977#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8977#false} is VALID [2022-02-21 04:23:08,000 INFO L290 TraceCheckUtils]: 45: Hoare triple {8977#false} assume 1 == ~m_pc~0; {8977#false} is VALID [2022-02-21 04:23:08,000 INFO L290 TraceCheckUtils]: 46: Hoare triple {8977#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {8977#false} is VALID [2022-02-21 04:23:08,000 INFO L290 TraceCheckUtils]: 47: Hoare triple {8977#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8977#false} is VALID [2022-02-21 04:23:08,001 INFO L290 TraceCheckUtils]: 48: Hoare triple {8977#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8977#false} is VALID [2022-02-21 04:23:08,001 INFO L290 TraceCheckUtils]: 49: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp~1#1); {8977#false} is VALID [2022-02-21 04:23:08,001 INFO L290 TraceCheckUtils]: 50: Hoare triple {8977#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8977#false} is VALID [2022-02-21 04:23:08,001 INFO L290 TraceCheckUtils]: 51: Hoare triple {8977#false} assume !(1 == ~t1_pc~0); {8977#false} is VALID [2022-02-21 04:23:08,001 INFO L290 TraceCheckUtils]: 52: Hoare triple {8977#false} is_transmit1_triggered_~__retres1~1#1 := 0; {8977#false} is VALID [2022-02-21 04:23:08,001 INFO L290 TraceCheckUtils]: 53: Hoare triple {8977#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8977#false} is VALID [2022-02-21 04:23:08,002 INFO L290 TraceCheckUtils]: 54: Hoare triple {8977#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8977#false} is VALID [2022-02-21 04:23:08,002 INFO L290 TraceCheckUtils]: 55: Hoare triple {8977#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8977#false} is VALID [2022-02-21 04:23:08,002 INFO L290 TraceCheckUtils]: 56: Hoare triple {8977#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8977#false} is VALID [2022-02-21 04:23:08,002 INFO L290 TraceCheckUtils]: 57: Hoare triple {8977#false} assume 1 == ~t2_pc~0; {8977#false} is VALID [2022-02-21 04:23:08,002 INFO L290 TraceCheckUtils]: 58: Hoare triple {8977#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8977#false} is VALID [2022-02-21 04:23:08,002 INFO L290 TraceCheckUtils]: 59: Hoare triple {8977#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8977#false} is VALID [2022-02-21 04:23:08,002 INFO L290 TraceCheckUtils]: 60: Hoare triple {8977#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8977#false} is VALID [2022-02-21 04:23:08,003 INFO L290 TraceCheckUtils]: 61: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___1~0#1); {8977#false} is VALID [2022-02-21 04:23:08,003 INFO L290 TraceCheckUtils]: 62: Hoare triple {8977#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8977#false} is VALID [2022-02-21 04:23:08,003 INFO L290 TraceCheckUtils]: 63: Hoare triple {8977#false} assume !(1 == ~t3_pc~0); {8977#false} is VALID [2022-02-21 04:23:08,003 INFO L290 TraceCheckUtils]: 64: Hoare triple {8977#false} is_transmit3_triggered_~__retres1~3#1 := 0; {8977#false} is VALID [2022-02-21 04:23:08,003 INFO L290 TraceCheckUtils]: 65: Hoare triple {8977#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8977#false} is VALID [2022-02-21 04:23:08,003 INFO L290 TraceCheckUtils]: 66: Hoare triple {8977#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8977#false} is VALID [2022-02-21 04:23:08,003 INFO L290 TraceCheckUtils]: 67: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___2~0#1); {8977#false} is VALID [2022-02-21 04:23:08,004 INFO L290 TraceCheckUtils]: 68: Hoare triple {8977#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8977#false} is VALID [2022-02-21 04:23:08,004 INFO L290 TraceCheckUtils]: 69: Hoare triple {8977#false} assume 1 == ~t4_pc~0; {8977#false} is VALID [2022-02-21 04:23:08,004 INFO L290 TraceCheckUtils]: 70: Hoare triple {8977#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8977#false} is VALID [2022-02-21 04:23:08,004 INFO L290 TraceCheckUtils]: 71: Hoare triple {8977#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8977#false} is VALID [2022-02-21 04:23:08,004 INFO L290 TraceCheckUtils]: 72: Hoare triple {8977#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {8977#false} is VALID [2022-02-21 04:23:08,004 INFO L290 TraceCheckUtils]: 73: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___3~0#1); {8977#false} is VALID [2022-02-21 04:23:08,004 INFO L290 TraceCheckUtils]: 74: Hoare triple {8977#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8977#false} is VALID [2022-02-21 04:23:08,005 INFO L290 TraceCheckUtils]: 75: Hoare triple {8977#false} assume !(1 == ~t5_pc~0); {8977#false} is VALID [2022-02-21 04:23:08,005 INFO L290 TraceCheckUtils]: 76: Hoare triple {8977#false} is_transmit5_triggered_~__retres1~5#1 := 0; {8977#false} is VALID [2022-02-21 04:23:08,005 INFO L290 TraceCheckUtils]: 77: Hoare triple {8977#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8977#false} is VALID [2022-02-21 04:23:08,005 INFO L290 TraceCheckUtils]: 78: Hoare triple {8977#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {8977#false} is VALID [2022-02-21 04:23:08,005 INFO L290 TraceCheckUtils]: 79: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___4~0#1); {8977#false} is VALID [2022-02-21 04:23:08,005 INFO L290 TraceCheckUtils]: 80: Hoare triple {8977#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8977#false} is VALID [2022-02-21 04:23:08,005 INFO L290 TraceCheckUtils]: 81: Hoare triple {8977#false} assume 1 == ~t6_pc~0; {8977#false} is VALID [2022-02-21 04:23:08,006 INFO L290 TraceCheckUtils]: 82: Hoare triple {8977#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {8977#false} is VALID [2022-02-21 04:23:08,006 INFO L290 TraceCheckUtils]: 83: Hoare triple {8977#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8977#false} is VALID [2022-02-21 04:23:08,006 INFO L290 TraceCheckUtils]: 84: Hoare triple {8977#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {8977#false} is VALID [2022-02-21 04:23:08,006 INFO L290 TraceCheckUtils]: 85: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___5~0#1); {8977#false} is VALID [2022-02-21 04:23:08,006 INFO L290 TraceCheckUtils]: 86: Hoare triple {8977#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8977#false} is VALID [2022-02-21 04:23:08,006 INFO L290 TraceCheckUtils]: 87: Hoare triple {8977#false} assume 1 == ~t7_pc~0; {8977#false} is VALID [2022-02-21 04:23:08,006 INFO L290 TraceCheckUtils]: 88: Hoare triple {8977#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {8977#false} is VALID [2022-02-21 04:23:08,007 INFO L290 TraceCheckUtils]: 89: Hoare triple {8977#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8977#false} is VALID [2022-02-21 04:23:08,007 INFO L290 TraceCheckUtils]: 90: Hoare triple {8977#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {8977#false} is VALID [2022-02-21 04:23:08,007 INFO L290 TraceCheckUtils]: 91: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___6~0#1); {8977#false} is VALID [2022-02-21 04:23:08,007 INFO L290 TraceCheckUtils]: 92: Hoare triple {8977#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8977#false} is VALID [2022-02-21 04:23:08,007 INFO L290 TraceCheckUtils]: 93: Hoare triple {8977#false} assume !(1 == ~t8_pc~0); {8977#false} is VALID [2022-02-21 04:23:08,007 INFO L290 TraceCheckUtils]: 94: Hoare triple {8977#false} is_transmit8_triggered_~__retres1~8#1 := 0; {8977#false} is VALID [2022-02-21 04:23:08,007 INFO L290 TraceCheckUtils]: 95: Hoare triple {8977#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8977#false} is VALID [2022-02-21 04:23:08,008 INFO L290 TraceCheckUtils]: 96: Hoare triple {8977#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {8977#false} is VALID [2022-02-21 04:23:08,008 INFO L290 TraceCheckUtils]: 97: Hoare triple {8977#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {8977#false} is VALID [2022-02-21 04:23:08,008 INFO L290 TraceCheckUtils]: 98: Hoare triple {8977#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {8977#false} is VALID [2022-02-21 04:23:08,008 INFO L290 TraceCheckUtils]: 99: Hoare triple {8977#false} assume 1 == ~t9_pc~0; {8977#false} is VALID [2022-02-21 04:23:08,008 INFO L290 TraceCheckUtils]: 100: Hoare triple {8977#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {8977#false} is VALID [2022-02-21 04:23:08,008 INFO L290 TraceCheckUtils]: 101: Hoare triple {8977#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {8977#false} is VALID [2022-02-21 04:23:08,008 INFO L290 TraceCheckUtils]: 102: Hoare triple {8977#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {8977#false} is VALID [2022-02-21 04:23:08,009 INFO L290 TraceCheckUtils]: 103: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___8~0#1); {8977#false} is VALID [2022-02-21 04:23:08,009 INFO L290 TraceCheckUtils]: 104: Hoare triple {8977#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {8977#false} is VALID [2022-02-21 04:23:08,009 INFO L290 TraceCheckUtils]: 105: Hoare triple {8977#false} assume !(1 == ~t10_pc~0); {8977#false} is VALID [2022-02-21 04:23:08,009 INFO L290 TraceCheckUtils]: 106: Hoare triple {8977#false} is_transmit10_triggered_~__retres1~10#1 := 0; {8977#false} is VALID [2022-02-21 04:23:08,009 INFO L290 TraceCheckUtils]: 107: Hoare triple {8977#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {8977#false} is VALID [2022-02-21 04:23:08,009 INFO L290 TraceCheckUtils]: 108: Hoare triple {8977#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {8977#false} is VALID [2022-02-21 04:23:08,009 INFO L290 TraceCheckUtils]: 109: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___9~0#1); {8977#false} is VALID [2022-02-21 04:23:08,010 INFO L290 TraceCheckUtils]: 110: Hoare triple {8977#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {8977#false} is VALID [2022-02-21 04:23:08,010 INFO L290 TraceCheckUtils]: 111: Hoare triple {8977#false} assume 1 == ~t11_pc~0; {8977#false} is VALID [2022-02-21 04:23:08,010 INFO L290 TraceCheckUtils]: 112: Hoare triple {8977#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {8977#false} is VALID [2022-02-21 04:23:08,010 INFO L290 TraceCheckUtils]: 113: Hoare triple {8977#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {8977#false} is VALID [2022-02-21 04:23:08,010 INFO L290 TraceCheckUtils]: 114: Hoare triple {8977#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {8977#false} is VALID [2022-02-21 04:23:08,010 INFO L290 TraceCheckUtils]: 115: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___10~0#1); {8977#false} is VALID [2022-02-21 04:23:08,011 INFO L290 TraceCheckUtils]: 116: Hoare triple {8977#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {8977#false} is VALID [2022-02-21 04:23:08,011 INFO L290 TraceCheckUtils]: 117: Hoare triple {8977#false} assume !(1 == ~t12_pc~0); {8977#false} is VALID [2022-02-21 04:23:08,011 INFO L290 TraceCheckUtils]: 118: Hoare triple {8977#false} is_transmit12_triggered_~__retres1~12#1 := 0; {8977#false} is VALID [2022-02-21 04:23:08,011 INFO L290 TraceCheckUtils]: 119: Hoare triple {8977#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {8977#false} is VALID [2022-02-21 04:23:08,011 INFO L290 TraceCheckUtils]: 120: Hoare triple {8977#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {8977#false} is VALID [2022-02-21 04:23:08,011 INFO L290 TraceCheckUtils]: 121: Hoare triple {8977#false} assume !(0 != activate_threads_~tmp___11~0#1); {8977#false} is VALID [2022-02-21 04:23:08,011 INFO L290 TraceCheckUtils]: 122: Hoare triple {8977#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8977#false} is VALID [2022-02-21 04:23:08,012 INFO L290 TraceCheckUtils]: 123: Hoare triple {8977#false} assume !(1 == ~M_E~0); {8977#false} is VALID [2022-02-21 04:23:08,012 INFO L290 TraceCheckUtils]: 124: Hoare triple {8977#false} assume !(1 == ~T1_E~0); {8977#false} is VALID [2022-02-21 04:23:08,012 INFO L290 TraceCheckUtils]: 125: Hoare triple {8977#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8977#false} is VALID [2022-02-21 04:23:08,012 INFO L290 TraceCheckUtils]: 126: Hoare triple {8977#false} assume !(1 == ~T3_E~0); {8977#false} is VALID [2022-02-21 04:23:08,012 INFO L290 TraceCheckUtils]: 127: Hoare triple {8977#false} assume !(1 == ~T4_E~0); {8977#false} is VALID [2022-02-21 04:23:08,012 INFO L290 TraceCheckUtils]: 128: Hoare triple {8977#false} assume !(1 == ~T5_E~0); {8977#false} is VALID [2022-02-21 04:23:08,012 INFO L290 TraceCheckUtils]: 129: Hoare triple {8977#false} assume !(1 == ~T6_E~0); {8977#false} is VALID [2022-02-21 04:23:08,013 INFO L290 TraceCheckUtils]: 130: Hoare triple {8977#false} assume !(1 == ~T7_E~0); {8977#false} is VALID [2022-02-21 04:23:08,013 INFO L290 TraceCheckUtils]: 131: Hoare triple {8977#false} assume !(1 == ~T8_E~0); {8977#false} is VALID [2022-02-21 04:23:08,013 INFO L290 TraceCheckUtils]: 132: Hoare triple {8977#false} assume !(1 == ~T9_E~0); {8977#false} is VALID [2022-02-21 04:23:08,013 INFO L290 TraceCheckUtils]: 133: Hoare triple {8977#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {8977#false} is VALID [2022-02-21 04:23:08,013 INFO L290 TraceCheckUtils]: 134: Hoare triple {8977#false} assume !(1 == ~T11_E~0); {8977#false} is VALID [2022-02-21 04:23:08,013 INFO L290 TraceCheckUtils]: 135: Hoare triple {8977#false} assume !(1 == ~T12_E~0); {8977#false} is VALID [2022-02-21 04:23:08,013 INFO L290 TraceCheckUtils]: 136: Hoare triple {8977#false} assume !(1 == ~E_M~0); {8977#false} is VALID [2022-02-21 04:23:08,014 INFO L290 TraceCheckUtils]: 137: Hoare triple {8977#false} assume !(1 == ~E_1~0); {8977#false} is VALID [2022-02-21 04:23:08,014 INFO L290 TraceCheckUtils]: 138: Hoare triple {8977#false} assume !(1 == ~E_2~0); {8977#false} is VALID [2022-02-21 04:23:08,014 INFO L290 TraceCheckUtils]: 139: Hoare triple {8977#false} assume !(1 == ~E_3~0); {8977#false} is VALID [2022-02-21 04:23:08,014 INFO L290 TraceCheckUtils]: 140: Hoare triple {8977#false} assume !(1 == ~E_4~0); {8977#false} is VALID [2022-02-21 04:23:08,014 INFO L290 TraceCheckUtils]: 141: Hoare triple {8977#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8977#false} is VALID [2022-02-21 04:23:08,014 INFO L290 TraceCheckUtils]: 142: Hoare triple {8977#false} assume !(1 == ~E_6~0); {8977#false} is VALID [2022-02-21 04:23:08,015 INFO L290 TraceCheckUtils]: 143: Hoare triple {8977#false} assume !(1 == ~E_7~0); {8977#false} is VALID [2022-02-21 04:23:08,015 INFO L290 TraceCheckUtils]: 144: Hoare triple {8977#false} assume !(1 == ~E_8~0); {8977#false} is VALID [2022-02-21 04:23:08,015 INFO L290 TraceCheckUtils]: 145: Hoare triple {8977#false} assume !(1 == ~E_9~0); {8977#false} is VALID [2022-02-21 04:23:08,015 INFO L290 TraceCheckUtils]: 146: Hoare triple {8977#false} assume !(1 == ~E_10~0); {8977#false} is VALID [2022-02-21 04:23:08,015 INFO L290 TraceCheckUtils]: 147: Hoare triple {8977#false} assume !(1 == ~E_11~0); {8977#false} is VALID [2022-02-21 04:23:08,015 INFO L290 TraceCheckUtils]: 148: Hoare triple {8977#false} assume !(1 == ~E_12~0); {8977#false} is VALID [2022-02-21 04:23:08,015 INFO L290 TraceCheckUtils]: 149: Hoare triple {8977#false} assume { :end_inline_reset_delta_events } true; {8977#false} is VALID [2022-02-21 04:23:08,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:08,016 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:08,016 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338153980] [2022-02-21 04:23:08,017 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338153980] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:08,017 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:08,017 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:08,017 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581537959] [2022-02-21 04:23:08,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:08,018 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:08,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:08,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1784148501, now seen corresponding path program 1 times [2022-02-21 04:23:08,018 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:08,018 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617160618] [2022-02-21 04:23:08,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:08,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:08,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:08,128 INFO L290 TraceCheckUtils]: 0: Hoare triple {8979#true} assume !false; {8979#true} is VALID [2022-02-21 04:23:08,128 INFO L290 TraceCheckUtils]: 1: Hoare triple {8979#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8979#true} is VALID [2022-02-21 04:23:08,128 INFO L290 TraceCheckUtils]: 2: Hoare triple {8979#true} assume !false; {8979#true} is VALID [2022-02-21 04:23:08,128 INFO L290 TraceCheckUtils]: 3: Hoare triple {8979#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8979#true} is VALID [2022-02-21 04:23:08,129 INFO L290 TraceCheckUtils]: 4: Hoare triple {8979#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8979#true} is VALID [2022-02-21 04:23:08,129 INFO L290 TraceCheckUtils]: 5: Hoare triple {8979#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8979#true} is VALID [2022-02-21 04:23:08,129 INFO L290 TraceCheckUtils]: 6: Hoare triple {8979#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {8979#true} is VALID [2022-02-21 04:23:08,129 INFO L290 TraceCheckUtils]: 7: Hoare triple {8979#true} assume !(0 != eval_~tmp~0#1); {8979#true} is VALID [2022-02-21 04:23:08,129 INFO L290 TraceCheckUtils]: 8: Hoare triple {8979#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8979#true} is VALID [2022-02-21 04:23:08,129 INFO L290 TraceCheckUtils]: 9: Hoare triple {8979#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8979#true} is VALID [2022-02-21 04:23:08,129 INFO L290 TraceCheckUtils]: 10: Hoare triple {8979#true} assume 0 == ~M_E~0;~M_E~0 := 1; {8979#true} is VALID [2022-02-21 04:23:08,130 INFO L290 TraceCheckUtils]: 11: Hoare triple {8979#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8979#true} is VALID [2022-02-21 04:23:08,130 INFO L290 TraceCheckUtils]: 12: Hoare triple {8979#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8979#true} is VALID [2022-02-21 04:23:08,130 INFO L290 TraceCheckUtils]: 13: Hoare triple {8979#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8979#true} is VALID [2022-02-21 04:23:08,130 INFO L290 TraceCheckUtils]: 14: Hoare triple {8979#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8979#true} is VALID [2022-02-21 04:23:08,130 INFO L290 TraceCheckUtils]: 15: Hoare triple {8979#true} assume !(0 == ~T5_E~0); {8979#true} is VALID [2022-02-21 04:23:08,131 INFO L290 TraceCheckUtils]: 16: Hoare triple {8979#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,131 INFO L290 TraceCheckUtils]: 17: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,131 INFO L290 TraceCheckUtils]: 18: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,132 INFO L290 TraceCheckUtils]: 19: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,132 INFO L290 TraceCheckUtils]: 20: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,132 INFO L290 TraceCheckUtils]: 21: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,133 INFO L290 TraceCheckUtils]: 22: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,133 INFO L290 TraceCheckUtils]: 23: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,133 INFO L290 TraceCheckUtils]: 24: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,134 INFO L290 TraceCheckUtils]: 25: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,134 INFO L290 TraceCheckUtils]: 26: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,134 INFO L290 TraceCheckUtils]: 27: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,135 INFO L290 TraceCheckUtils]: 28: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,135 INFO L290 TraceCheckUtils]: 29: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,137 INFO L290 TraceCheckUtils]: 30: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,138 INFO L290 TraceCheckUtils]: 31: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,138 INFO L290 TraceCheckUtils]: 32: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,139 INFO L290 TraceCheckUtils]: 33: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,140 INFO L290 TraceCheckUtils]: 34: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,140 INFO L290 TraceCheckUtils]: 35: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,140 INFO L290 TraceCheckUtils]: 36: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,141 INFO L290 TraceCheckUtils]: 37: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,142 INFO L290 TraceCheckUtils]: 38: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,142 INFO L290 TraceCheckUtils]: 39: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,143 INFO L290 TraceCheckUtils]: 40: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,143 INFO L290 TraceCheckUtils]: 41: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,143 INFO L290 TraceCheckUtils]: 42: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,144 INFO L290 TraceCheckUtils]: 43: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,144 INFO L290 TraceCheckUtils]: 44: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,144 INFO L290 TraceCheckUtils]: 45: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,145 INFO L290 TraceCheckUtils]: 46: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,145 INFO L290 TraceCheckUtils]: 47: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,145 INFO L290 TraceCheckUtils]: 48: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,146 INFO L290 TraceCheckUtils]: 49: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,146 INFO L290 TraceCheckUtils]: 50: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,146 INFO L290 TraceCheckUtils]: 51: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,146 INFO L290 TraceCheckUtils]: 52: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,147 INFO L290 TraceCheckUtils]: 53: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,147 INFO L290 TraceCheckUtils]: 54: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,148 INFO L290 TraceCheckUtils]: 55: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,151 INFO L290 TraceCheckUtils]: 56: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,163 INFO L290 TraceCheckUtils]: 57: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,164 INFO L290 TraceCheckUtils]: 58: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,164 INFO L290 TraceCheckUtils]: 59: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,165 INFO L290 TraceCheckUtils]: 60: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,165 INFO L290 TraceCheckUtils]: 61: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,165 INFO L290 TraceCheckUtils]: 62: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,166 INFO L290 TraceCheckUtils]: 63: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,166 INFO L290 TraceCheckUtils]: 64: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,166 INFO L290 TraceCheckUtils]: 65: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,167 INFO L290 TraceCheckUtils]: 66: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,167 INFO L290 TraceCheckUtils]: 67: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,167 INFO L290 TraceCheckUtils]: 68: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,168 INFO L290 TraceCheckUtils]: 69: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,168 INFO L290 TraceCheckUtils]: 70: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,168 INFO L290 TraceCheckUtils]: 71: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,169 INFO L290 TraceCheckUtils]: 72: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,169 INFO L290 TraceCheckUtils]: 73: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,169 INFO L290 TraceCheckUtils]: 74: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,170 INFO L290 TraceCheckUtils]: 75: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,170 INFO L290 TraceCheckUtils]: 76: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,170 INFO L290 TraceCheckUtils]: 77: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,171 INFO L290 TraceCheckUtils]: 78: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,171 INFO L290 TraceCheckUtils]: 79: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,171 INFO L290 TraceCheckUtils]: 80: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,172 INFO L290 TraceCheckUtils]: 81: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,172 INFO L290 TraceCheckUtils]: 82: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,172 INFO L290 TraceCheckUtils]: 83: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,173 INFO L290 TraceCheckUtils]: 84: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,173 INFO L290 TraceCheckUtils]: 85: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,173 INFO L290 TraceCheckUtils]: 86: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,174 INFO L290 TraceCheckUtils]: 87: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,174 INFO L290 TraceCheckUtils]: 88: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,174 INFO L290 TraceCheckUtils]: 89: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,174 INFO L290 TraceCheckUtils]: 90: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,175 INFO L290 TraceCheckUtils]: 91: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,175 INFO L290 TraceCheckUtils]: 92: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,175 INFO L290 TraceCheckUtils]: 93: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,176 INFO L290 TraceCheckUtils]: 94: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,176 INFO L290 TraceCheckUtils]: 95: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,176 INFO L290 TraceCheckUtils]: 96: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,177 INFO L290 TraceCheckUtils]: 97: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,177 INFO L290 TraceCheckUtils]: 98: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,178 INFO L290 TraceCheckUtils]: 99: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,178 INFO L290 TraceCheckUtils]: 100: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,178 INFO L290 TraceCheckUtils]: 101: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,179 INFO L290 TraceCheckUtils]: 102: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,180 INFO L290 TraceCheckUtils]: 103: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t11_pc~0); {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,180 INFO L290 TraceCheckUtils]: 104: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,181 INFO L290 TraceCheckUtils]: 105: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,181 INFO L290 TraceCheckUtils]: 106: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,181 INFO L290 TraceCheckUtils]: 107: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,182 INFO L290 TraceCheckUtils]: 108: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,182 INFO L290 TraceCheckUtils]: 109: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,182 INFO L290 TraceCheckUtils]: 110: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,183 INFO L290 TraceCheckUtils]: 111: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,183 INFO L290 TraceCheckUtils]: 112: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,183 INFO L290 TraceCheckUtils]: 113: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,184 INFO L290 TraceCheckUtils]: 114: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,184 INFO L290 TraceCheckUtils]: 115: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,184 INFO L290 TraceCheckUtils]: 116: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,185 INFO L290 TraceCheckUtils]: 117: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,185 INFO L290 TraceCheckUtils]: 118: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,185 INFO L290 TraceCheckUtils]: 119: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,186 INFO L290 TraceCheckUtils]: 120: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8981#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:08,186 INFO L290 TraceCheckUtils]: 121: Hoare triple {8981#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {8980#false} is VALID [2022-02-21 04:23:08,186 INFO L290 TraceCheckUtils]: 122: Hoare triple {8980#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,186 INFO L290 TraceCheckUtils]: 123: Hoare triple {8980#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,186 INFO L290 TraceCheckUtils]: 124: Hoare triple {8980#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,187 INFO L290 TraceCheckUtils]: 125: Hoare triple {8980#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,187 INFO L290 TraceCheckUtils]: 126: Hoare triple {8980#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,187 INFO L290 TraceCheckUtils]: 127: Hoare triple {8980#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,187 INFO L290 TraceCheckUtils]: 128: Hoare triple {8980#false} assume 1 == ~E_M~0;~E_M~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,187 INFO L290 TraceCheckUtils]: 129: Hoare triple {8980#false} assume !(1 == ~E_1~0); {8980#false} is VALID [2022-02-21 04:23:08,187 INFO L290 TraceCheckUtils]: 130: Hoare triple {8980#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,187 INFO L290 TraceCheckUtils]: 131: Hoare triple {8980#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 132: Hoare triple {8980#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 133: Hoare triple {8980#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 134: Hoare triple {8980#false} assume 1 == ~E_6~0;~E_6~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 135: Hoare triple {8980#false} assume 1 == ~E_7~0;~E_7~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 136: Hoare triple {8980#false} assume 1 == ~E_8~0;~E_8~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 137: Hoare triple {8980#false} assume !(1 == ~E_9~0); {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 138: Hoare triple {8980#false} assume 1 == ~E_10~0;~E_10~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,188 INFO L290 TraceCheckUtils]: 139: Hoare triple {8980#false} assume 1 == ~E_11~0;~E_11~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,189 INFO L290 TraceCheckUtils]: 140: Hoare triple {8980#false} assume 1 == ~E_12~0;~E_12~0 := 2; {8980#false} is VALID [2022-02-21 04:23:08,189 INFO L290 TraceCheckUtils]: 141: Hoare triple {8980#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8980#false} is VALID [2022-02-21 04:23:08,189 INFO L290 TraceCheckUtils]: 142: Hoare triple {8980#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8980#false} is VALID [2022-02-21 04:23:08,189 INFO L290 TraceCheckUtils]: 143: Hoare triple {8980#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8980#false} is VALID [2022-02-21 04:23:08,189 INFO L290 TraceCheckUtils]: 144: Hoare triple {8980#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {8980#false} is VALID [2022-02-21 04:23:08,189 INFO L290 TraceCheckUtils]: 145: Hoare triple {8980#false} assume !(0 == start_simulation_~tmp~3#1); {8980#false} is VALID [2022-02-21 04:23:08,189 INFO L290 TraceCheckUtils]: 146: Hoare triple {8980#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8980#false} is VALID [2022-02-21 04:23:08,190 INFO L290 TraceCheckUtils]: 147: Hoare triple {8980#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8980#false} is VALID [2022-02-21 04:23:08,190 INFO L290 TraceCheckUtils]: 148: Hoare triple {8980#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8980#false} is VALID [2022-02-21 04:23:08,190 INFO L290 TraceCheckUtils]: 149: Hoare triple {8980#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {8980#false} is VALID [2022-02-21 04:23:08,190 INFO L290 TraceCheckUtils]: 150: Hoare triple {8980#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8980#false} is VALID [2022-02-21 04:23:08,190 INFO L290 TraceCheckUtils]: 151: Hoare triple {8980#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8980#false} is VALID [2022-02-21 04:23:08,190 INFO L290 TraceCheckUtils]: 152: Hoare triple {8980#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {8980#false} is VALID [2022-02-21 04:23:08,190 INFO L290 TraceCheckUtils]: 153: Hoare triple {8980#false} assume !(0 != start_simulation_~tmp___0~1#1); {8980#false} is VALID [2022-02-21 04:23:08,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:08,191 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:08,191 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617160618] [2022-02-21 04:23:08,192 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617160618] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:08,192 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:08,192 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:08,192 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130510256] [2022-02-21 04:23:08,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:08,193 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:08,193 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:08,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:08,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:08,194 INFO L87 Difference]: Start difference. First operand 1790 states and 2655 transitions. cyclomatic complexity: 866 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:09,535 INFO L93 Difference]: Finished difference Result 1790 states and 2654 transitions. [2022-02-21 04:23:09,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:09,536 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,634 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:09,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2654 transitions. [2022-02-21 04:23:09,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:09,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2654 transitions. [2022-02-21 04:23:09,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:09,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:09,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2654 transitions. [2022-02-21 04:23:09,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:09,824 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-02-21 04:23:09,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2654 transitions. [2022-02-21 04:23:09,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:09,841 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:09,844 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2654 transitions. Second operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,846 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2654 transitions. Second operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,848 INFO L87 Difference]: Start difference. First operand 1790 states and 2654 transitions. Second operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:09,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:09,927 INFO L93 Difference]: Finished difference Result 1790 states and 2654 transitions. [2022-02-21 04:23:09,927 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2654 transitions. [2022-02-21 04:23:09,929 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:09,929 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:09,932 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2654 transitions. [2022-02-21 04:23:09,934 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2654 transitions. [2022-02-21 04:23:10,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:10,012 INFO L93 Difference]: Finished difference Result 1790 states and 2654 transitions. [2022-02-21 04:23:10,012 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2654 transitions. [2022-02-21 04:23:10,027 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:10,028 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:10,028 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:10,028 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:10,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.48268156424581) internal successors, (2654), 1789 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:10,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2654 transitions. [2022-02-21 04:23:10,132 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-02-21 04:23:10,132 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2654 transitions. [2022-02-21 04:23:10,132 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:23:10,132 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2654 transitions. [2022-02-21 04:23:10,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:10,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:10,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:10,139 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,139 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:10,140 INFO L791 eck$LassoCheckResult]: Stem: 11616#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11040#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11010#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11011#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 12272#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11319#L858-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 10772#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10773#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12044#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12183#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12549#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12550#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11529#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11530#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12070#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11990#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11991#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12143#L1206 assume !(0 == ~M_E~0); 11508#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11509#L1211-1 assume !(0 == ~T2_E~0); 12402#L1216-1 assume !(0 == ~T3_E~0); 11301#L1221-1 assume !(0 == ~T4_E~0); 11302#L1226-1 assume !(0 == ~T5_E~0); 10964#L1231-1 assume !(0 == ~T6_E~0); 10965#L1236-1 assume !(0 == ~T7_E~0); 12433#L1241-1 assume !(0 == ~T8_E~0); 11363#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11364#L1251-1 assume !(0 == ~T10_E~0); 11584#L1256-1 assume !(0 == ~T11_E~0); 10784#L1261-1 assume !(0 == ~T12_E~0); 10785#L1266-1 assume !(0 == ~E_M~0); 12536#L1271-1 assume !(0 == ~E_1~0); 12171#L1276-1 assume !(0 == ~E_2~0); 12172#L1281-1 assume !(0 == ~E_3~0); 12097#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 11205#L1291-1 assume !(0 == ~E_5~0); 11206#L1296-1 assume !(0 == ~E_6~0); 11912#L1301-1 assume !(0 == ~E_7~0); 11913#L1306-1 assume !(0 == ~E_8~0); 12345#L1311-1 assume !(0 == ~E_9~0); 11166#L1316-1 assume !(0 == ~E_10~0); 11167#L1321-1 assume !(0 == ~E_11~0); 11929#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11030#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11031#L598 assume 1 == ~m_pc~0; 11090#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11091#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12415#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12507#L1497 assume !(0 != activate_threads_~tmp~1#1); 12508#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12464#L617 assume !(1 == ~t1_pc~0); 11386#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11387#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11246#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11247#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12007#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12008#L636 assume 1 == ~t2_pc~0; 11355#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11356#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11186#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11187#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 12043#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11706#L655 assume !(1 == ~t3_pc~0); 11707#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12420#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11060#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11061#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 12537#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12538#L674 assume 1 == ~t4_pc~0; 10880#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10881#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12178#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11188#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 11189#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11703#L693 assume !(1 == ~t5_pc~0); 11866#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11510#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11511#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12347#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 11596#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11533#L712 assume 1 == ~t6_pc~0; 11534#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11961#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11962#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12248#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 12059#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12057#L731 assume 1 == ~t7_pc~0; 11034#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11035#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11229#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12166#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 12285#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11144#L750 assume !(1 == ~t8_pc~0); 10815#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10814#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11330#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12360#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11467#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11468#L769 assume 1 == ~t9_pc~0; 12003#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10988#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10989#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11772#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 12224#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12305#L788 assume !(1 == ~t10_pc~0); 11880#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11881#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12112#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12113#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 11140#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11141#L807 assume 1 == ~t11_pc~0; 12314#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11892#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12045#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12456#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 12561#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12404#L826 assume !(1 == ~t12_pc~0); 11536#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11537#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12065#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12496#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 11696#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11605#L1344 assume !(1 == ~M_E~0); 11606#L1344-2 assume !(1 == ~T1_E~0); 11747#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11919#L1354-1 assume !(1 == ~T3_E~0); 11920#L1359-1 assume !(1 == ~T4_E~0); 12294#L1364-1 assume !(1 == ~T5_E~0); 11248#L1369-1 assume !(1 == ~T6_E~0); 11249#L1374-1 assume !(1 == ~T7_E~0); 11925#L1379-1 assume !(1 == ~T8_E~0); 11926#L1384-1 assume !(1 == ~T9_E~0); 11989#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12435#L1394-1 assume !(1 == ~T11_E~0); 12436#L1399-1 assume !(1 == ~T12_E~0); 12515#L1404-1 assume !(1 == ~E_M~0); 11367#L1409-1 assume !(1 == ~E_1~0); 11368#L1414-1 assume !(1 == ~E_2~0); 12205#L1419-1 assume !(1 == ~E_3~0); 11001#L1424-1 assume !(1 == ~E_4~0); 11002#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11936#L1434-1 assume !(1 == ~E_6~0); 12454#L1439-1 assume !(1 == ~E_7~0); 11056#L1444-1 assume !(1 == ~E_8~0); 11057#L1449-1 assume !(1 == ~E_9~0); 11472#L1454-1 assume !(1 == ~E_10~0); 11473#L1459-1 assume !(1 == ~E_11~0); 12023#L1464-1 assume !(1 == ~E_12~0); 12024#L1469-1 assume { :end_inline_reset_delta_events } true; 12071#L1815-2 [2022-02-21 04:23:10,141 INFO L793 eck$LassoCheckResult]: Loop: 12071#L1815-2 assume !false; 12225#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11894#L1181 assume !false; 11965#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11917#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10775#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11504#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12055#L1008 assume !(0 != eval_~tmp~0#1); 12056#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10994#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10995#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12555#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12022#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11128#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11129#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11719#L1226-3 assume !(0 == ~T5_E~0); 11192#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11193#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11505#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12492#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12395#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12131#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11150#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11151#L1266-3 assume !(0 == ~E_M~0); 11190#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11191#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11663#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11664#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12201#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12202#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12544#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12512#L1306-3 assume !(0 == ~E_8~0); 11788#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11074#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11075#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11152#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11887#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12212#L598-42 assume !(1 == ~m_pc~0); 12213#L598-44 is_master_triggered_~__retres1~0#1 := 0; 12327#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11230#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11231#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 12513#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11943#L617-42 assume 1 == ~t1_pc~0; 11715#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11580#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11581#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11995#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11295#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11296#L636-42 assume 1 == ~t2_pc~0; 12497#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11760#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12110#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12111#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12290#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12152#L655-42 assume !(1 == ~t3_pc~0); 11732#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 11733#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11365#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11366#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12419#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12364#L674-42 assume !(1 == ~t4_pc~0); 12138#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12060#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10949#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10950#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11864#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11865#L693-42 assume 1 == ~t5_pc~0; 12120#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12121#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12181#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12176#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12177#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11479#L712-42 assume !(1 == ~t6_pc~0); 11480#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 11806#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12014#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12015#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11588#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11589#L731-42 assume !(1 == ~t7_pc~0); 11287#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11288#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12355#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11496#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11497#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11200#L750-42 assume 1 == ~t8_pc~0; 11201#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11775#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12198#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11093#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11094#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11863#L769-42 assume 1 == ~t9_pc~0; 11685#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11686#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12369#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12434#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 11297#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11298#L788-42 assume !(1 == ~t10_pc~0); 11872#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 12085#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11815#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11816#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12553#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12531#L807-42 assume !(1 == ~t11_pc~0); 10901#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 10902#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11041#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11042#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11043#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11292#L826-42 assume 1 == ~t12_pc~0; 11293#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11485#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12277#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11282#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11283#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12134#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12135#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12061#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11442#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11443#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12075#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12533#L1369-3 assume !(1 == ~T6_E~0); 12453#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11207#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11208#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11440#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11441#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11739#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12462#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12425#L1409-3 assume !(1 == ~E_1~0); 12426#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12491#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12271#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11108#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11109#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12074#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11048#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11049#L1449-3 assume !(1 == ~E_9~0); 11158#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12068#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12069#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12450#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11948#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10947#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10948#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11564#L1834 assume !(0 == start_simulation_~tmp~3#1); 12184#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12207#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11641#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11820#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12032#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12440#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10933#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 10934#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 12071#L1815-2 [2022-02-21 04:23:10,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,143 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-02-21 04:23:10,143 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,143 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139976841] [2022-02-21 04:23:10,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,204 INFO L290 TraceCheckUtils]: 0: Hoare triple {16145#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {16145#true} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 1: Hoare triple {16145#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {16147#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 2: Hoare triple {16147#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {16147#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:10,205 INFO L290 TraceCheckUtils]: 3: Hoare triple {16147#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {16147#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 4: Hoare triple {16147#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {16147#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 5: Hoare triple {16147#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {16147#(= ~t2_i~0 1)} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 6: Hoare triple {16147#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,206 INFO L290 TraceCheckUtils]: 7: Hoare triple {16146#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 8: Hoare triple {16146#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 9: Hoare triple {16146#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 10: Hoare triple {16146#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 11: Hoare triple {16146#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 12: Hoare triple {16146#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 13: Hoare triple {16146#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {16146#false} is VALID [2022-02-21 04:23:10,207 INFO L290 TraceCheckUtils]: 14: Hoare triple {16146#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 15: Hoare triple {16146#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 16: Hoare triple {16146#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 17: Hoare triple {16146#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 18: Hoare triple {16146#false} assume !(0 == ~M_E~0); {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 19: Hoare triple {16146#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 20: Hoare triple {16146#false} assume !(0 == ~T2_E~0); {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 21: Hoare triple {16146#false} assume !(0 == ~T3_E~0); {16146#false} is VALID [2022-02-21 04:23:10,208 INFO L290 TraceCheckUtils]: 22: Hoare triple {16146#false} assume !(0 == ~T4_E~0); {16146#false} is VALID [2022-02-21 04:23:10,209 INFO L290 TraceCheckUtils]: 23: Hoare triple {16146#false} assume !(0 == ~T5_E~0); {16146#false} is VALID [2022-02-21 04:23:10,209 INFO L290 TraceCheckUtils]: 24: Hoare triple {16146#false} assume !(0 == ~T6_E~0); {16146#false} is VALID [2022-02-21 04:23:10,209 INFO L290 TraceCheckUtils]: 25: Hoare triple {16146#false} assume !(0 == ~T7_E~0); {16146#false} is VALID [2022-02-21 04:23:10,209 INFO L290 TraceCheckUtils]: 26: Hoare triple {16146#false} assume !(0 == ~T8_E~0); {16146#false} is VALID [2022-02-21 04:23:10,209 INFO L290 TraceCheckUtils]: 27: Hoare triple {16146#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {16146#false} is VALID [2022-02-21 04:23:10,210 INFO L290 TraceCheckUtils]: 28: Hoare triple {16146#false} assume !(0 == ~T10_E~0); {16146#false} is VALID [2022-02-21 04:23:10,211 INFO L290 TraceCheckUtils]: 29: Hoare triple {16146#false} assume !(0 == ~T11_E~0); {16146#false} is VALID [2022-02-21 04:23:10,211 INFO L290 TraceCheckUtils]: 30: Hoare triple {16146#false} assume !(0 == ~T12_E~0); {16146#false} is VALID [2022-02-21 04:23:10,212 INFO L290 TraceCheckUtils]: 31: Hoare triple {16146#false} assume !(0 == ~E_M~0); {16146#false} is VALID [2022-02-21 04:23:10,212 INFO L290 TraceCheckUtils]: 32: Hoare triple {16146#false} assume !(0 == ~E_1~0); {16146#false} is VALID [2022-02-21 04:23:10,212 INFO L290 TraceCheckUtils]: 33: Hoare triple {16146#false} assume !(0 == ~E_2~0); {16146#false} is VALID [2022-02-21 04:23:10,212 INFO L290 TraceCheckUtils]: 34: Hoare triple {16146#false} assume !(0 == ~E_3~0); {16146#false} is VALID [2022-02-21 04:23:10,212 INFO L290 TraceCheckUtils]: 35: Hoare triple {16146#false} assume 0 == ~E_4~0;~E_4~0 := 1; {16146#false} is VALID [2022-02-21 04:23:10,213 INFO L290 TraceCheckUtils]: 36: Hoare triple {16146#false} assume !(0 == ~E_5~0); {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 37: Hoare triple {16146#false} assume !(0 == ~E_6~0); {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 38: Hoare triple {16146#false} assume !(0 == ~E_7~0); {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 39: Hoare triple {16146#false} assume !(0 == ~E_8~0); {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 40: Hoare triple {16146#false} assume !(0 == ~E_9~0); {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 41: Hoare triple {16146#false} assume !(0 == ~E_10~0); {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 42: Hoare triple {16146#false} assume !(0 == ~E_11~0); {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 43: Hoare triple {16146#false} assume 0 == ~E_12~0;~E_12~0 := 1; {16146#false} is VALID [2022-02-21 04:23:10,214 INFO L290 TraceCheckUtils]: 44: Hoare triple {16146#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16146#false} is VALID [2022-02-21 04:23:10,215 INFO L290 TraceCheckUtils]: 45: Hoare triple {16146#false} assume 1 == ~m_pc~0; {16146#false} is VALID [2022-02-21 04:23:10,215 INFO L290 TraceCheckUtils]: 46: Hoare triple {16146#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {16146#false} is VALID [2022-02-21 04:23:10,215 INFO L290 TraceCheckUtils]: 47: Hoare triple {16146#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16146#false} is VALID [2022-02-21 04:23:10,217 INFO L290 TraceCheckUtils]: 48: Hoare triple {16146#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16146#false} is VALID [2022-02-21 04:23:10,217 INFO L290 TraceCheckUtils]: 49: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp~1#1); {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 50: Hoare triple {16146#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 51: Hoare triple {16146#false} assume !(1 == ~t1_pc~0); {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 52: Hoare triple {16146#false} is_transmit1_triggered_~__retres1~1#1 := 0; {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 53: Hoare triple {16146#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 54: Hoare triple {16146#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 55: Hoare triple {16146#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 56: Hoare triple {16146#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16146#false} is VALID [2022-02-21 04:23:10,218 INFO L290 TraceCheckUtils]: 57: Hoare triple {16146#false} assume 1 == ~t2_pc~0; {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 58: Hoare triple {16146#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 59: Hoare triple {16146#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 60: Hoare triple {16146#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 61: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___1~0#1); {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 62: Hoare triple {16146#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 63: Hoare triple {16146#false} assume !(1 == ~t3_pc~0); {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 64: Hoare triple {16146#false} is_transmit3_triggered_~__retres1~3#1 := 0; {16146#false} is VALID [2022-02-21 04:23:10,219 INFO L290 TraceCheckUtils]: 65: Hoare triple {16146#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 66: Hoare triple {16146#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 67: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___2~0#1); {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 68: Hoare triple {16146#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 69: Hoare triple {16146#false} assume 1 == ~t4_pc~0; {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 70: Hoare triple {16146#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 71: Hoare triple {16146#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 72: Hoare triple {16146#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 73: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___3~0#1); {16146#false} is VALID [2022-02-21 04:23:10,220 INFO L290 TraceCheckUtils]: 74: Hoare triple {16146#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 75: Hoare triple {16146#false} assume !(1 == ~t5_pc~0); {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 76: Hoare triple {16146#false} is_transmit5_triggered_~__retres1~5#1 := 0; {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 77: Hoare triple {16146#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 78: Hoare triple {16146#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 79: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___4~0#1); {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 80: Hoare triple {16146#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 81: Hoare triple {16146#false} assume 1 == ~t6_pc~0; {16146#false} is VALID [2022-02-21 04:23:10,221 INFO L290 TraceCheckUtils]: 82: Hoare triple {16146#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {16146#false} is VALID [2022-02-21 04:23:10,222 INFO L290 TraceCheckUtils]: 83: Hoare triple {16146#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16146#false} is VALID [2022-02-21 04:23:10,222 INFO L290 TraceCheckUtils]: 84: Hoare triple {16146#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {16146#false} is VALID [2022-02-21 04:23:10,222 INFO L290 TraceCheckUtils]: 85: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___5~0#1); {16146#false} is VALID [2022-02-21 04:23:10,222 INFO L290 TraceCheckUtils]: 86: Hoare triple {16146#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16146#false} is VALID [2022-02-21 04:23:10,222 INFO L290 TraceCheckUtils]: 87: Hoare triple {16146#false} assume 1 == ~t7_pc~0; {16146#false} is VALID [2022-02-21 04:23:10,222 INFO L290 TraceCheckUtils]: 88: Hoare triple {16146#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16146#false} is VALID [2022-02-21 04:23:10,222 INFO L290 TraceCheckUtils]: 89: Hoare triple {16146#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 90: Hoare triple {16146#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 91: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___6~0#1); {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 92: Hoare triple {16146#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 93: Hoare triple {16146#false} assume !(1 == ~t8_pc~0); {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 94: Hoare triple {16146#false} is_transmit8_triggered_~__retres1~8#1 := 0; {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 95: Hoare triple {16146#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 96: Hoare triple {16146#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 97: Hoare triple {16146#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {16146#false} is VALID [2022-02-21 04:23:10,223 INFO L290 TraceCheckUtils]: 98: Hoare triple {16146#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 99: Hoare triple {16146#false} assume 1 == ~t9_pc~0; {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 100: Hoare triple {16146#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 101: Hoare triple {16146#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 102: Hoare triple {16146#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 103: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___8~0#1); {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 104: Hoare triple {16146#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 105: Hoare triple {16146#false} assume !(1 == ~t10_pc~0); {16146#false} is VALID [2022-02-21 04:23:10,224 INFO L290 TraceCheckUtils]: 106: Hoare triple {16146#false} is_transmit10_triggered_~__retres1~10#1 := 0; {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 107: Hoare triple {16146#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 108: Hoare triple {16146#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 109: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___9~0#1); {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 110: Hoare triple {16146#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 111: Hoare triple {16146#false} assume 1 == ~t11_pc~0; {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 112: Hoare triple {16146#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 113: Hoare triple {16146#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {16146#false} is VALID [2022-02-21 04:23:10,225 INFO L290 TraceCheckUtils]: 114: Hoare triple {16146#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {16146#false} is VALID [2022-02-21 04:23:10,226 INFO L290 TraceCheckUtils]: 115: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___10~0#1); {16146#false} is VALID [2022-02-21 04:23:10,226 INFO L290 TraceCheckUtils]: 116: Hoare triple {16146#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {16146#false} is VALID [2022-02-21 04:23:10,226 INFO L290 TraceCheckUtils]: 117: Hoare triple {16146#false} assume !(1 == ~t12_pc~0); {16146#false} is VALID [2022-02-21 04:23:10,226 INFO L290 TraceCheckUtils]: 118: Hoare triple {16146#false} is_transmit12_triggered_~__retres1~12#1 := 0; {16146#false} is VALID [2022-02-21 04:23:10,226 INFO L290 TraceCheckUtils]: 119: Hoare triple {16146#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {16146#false} is VALID [2022-02-21 04:23:10,226 INFO L290 TraceCheckUtils]: 120: Hoare triple {16146#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {16146#false} is VALID [2022-02-21 04:23:10,238 INFO L290 TraceCheckUtils]: 121: Hoare triple {16146#false} assume !(0 != activate_threads_~tmp___11~0#1); {16146#false} is VALID [2022-02-21 04:23:10,249 INFO L290 TraceCheckUtils]: 122: Hoare triple {16146#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16146#false} is VALID [2022-02-21 04:23:10,250 INFO L290 TraceCheckUtils]: 123: Hoare triple {16146#false} assume !(1 == ~M_E~0); {16146#false} is VALID [2022-02-21 04:23:10,250 INFO L290 TraceCheckUtils]: 124: Hoare triple {16146#false} assume !(1 == ~T1_E~0); {16146#false} is VALID [2022-02-21 04:23:10,250 INFO L290 TraceCheckUtils]: 125: Hoare triple {16146#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,250 INFO L290 TraceCheckUtils]: 126: Hoare triple {16146#false} assume !(1 == ~T3_E~0); {16146#false} is VALID [2022-02-21 04:23:10,250 INFO L290 TraceCheckUtils]: 127: Hoare triple {16146#false} assume !(1 == ~T4_E~0); {16146#false} is VALID [2022-02-21 04:23:10,250 INFO L290 TraceCheckUtils]: 128: Hoare triple {16146#false} assume !(1 == ~T5_E~0); {16146#false} is VALID [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 129: Hoare triple {16146#false} assume !(1 == ~T6_E~0); {16146#false} is VALID [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 130: Hoare triple {16146#false} assume !(1 == ~T7_E~0); {16146#false} is VALID [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 131: Hoare triple {16146#false} assume !(1 == ~T8_E~0); {16146#false} is VALID [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 132: Hoare triple {16146#false} assume !(1 == ~T9_E~0); {16146#false} is VALID [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 133: Hoare triple {16146#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 134: Hoare triple {16146#false} assume !(1 == ~T11_E~0); {16146#false} is VALID [2022-02-21 04:23:10,251 INFO L290 TraceCheckUtils]: 135: Hoare triple {16146#false} assume !(1 == ~T12_E~0); {16146#false} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 136: Hoare triple {16146#false} assume !(1 == ~E_M~0); {16146#false} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 137: Hoare triple {16146#false} assume !(1 == ~E_1~0); {16146#false} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 138: Hoare triple {16146#false} assume !(1 == ~E_2~0); {16146#false} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 139: Hoare triple {16146#false} assume !(1 == ~E_3~0); {16146#false} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 140: Hoare triple {16146#false} assume !(1 == ~E_4~0); {16146#false} is VALID [2022-02-21 04:23:10,252 INFO L290 TraceCheckUtils]: 141: Hoare triple {16146#false} assume 1 == ~E_5~0;~E_5~0 := 2; {16146#false} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 142: Hoare triple {16146#false} assume !(1 == ~E_6~0); {16146#false} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 143: Hoare triple {16146#false} assume !(1 == ~E_7~0); {16146#false} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 144: Hoare triple {16146#false} assume !(1 == ~E_8~0); {16146#false} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 145: Hoare triple {16146#false} assume !(1 == ~E_9~0); {16146#false} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 146: Hoare triple {16146#false} assume !(1 == ~E_10~0); {16146#false} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 147: Hoare triple {16146#false} assume !(1 == ~E_11~0); {16146#false} is VALID [2022-02-21 04:23:10,253 INFO L290 TraceCheckUtils]: 148: Hoare triple {16146#false} assume !(1 == ~E_12~0); {16146#false} is VALID [2022-02-21 04:23:10,254 INFO L290 TraceCheckUtils]: 149: Hoare triple {16146#false} assume { :end_inline_reset_delta_events } true; {16146#false} is VALID [2022-02-21 04:23:10,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,254 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,255 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139976841] [2022-02-21 04:23:10,255 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139976841] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,255 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,255 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,255 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983494502] [2022-02-21 04:23:10,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,256 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:10,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:10,257 INFO L85 PathProgramCache]: Analyzing trace with hash 2024415830, now seen corresponding path program 1 times [2022-02-21 04:23:10,257 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:10,257 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593137289] [2022-02-21 04:23:10,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:10,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:10,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:10,346 INFO L290 TraceCheckUtils]: 0: Hoare triple {16148#true} assume !false; {16148#true} is VALID [2022-02-21 04:23:10,346 INFO L290 TraceCheckUtils]: 1: Hoare triple {16148#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {16148#true} is VALID [2022-02-21 04:23:10,346 INFO L290 TraceCheckUtils]: 2: Hoare triple {16148#true} assume !false; {16148#true} is VALID [2022-02-21 04:23:10,346 INFO L290 TraceCheckUtils]: 3: Hoare triple {16148#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {16148#true} is VALID [2022-02-21 04:23:10,346 INFO L290 TraceCheckUtils]: 4: Hoare triple {16148#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {16148#true} is VALID [2022-02-21 04:23:10,347 INFO L290 TraceCheckUtils]: 5: Hoare triple {16148#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {16148#true} is VALID [2022-02-21 04:23:10,347 INFO L290 TraceCheckUtils]: 6: Hoare triple {16148#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {16148#true} is VALID [2022-02-21 04:23:10,347 INFO L290 TraceCheckUtils]: 7: Hoare triple {16148#true} assume !(0 != eval_~tmp~0#1); {16148#true} is VALID [2022-02-21 04:23:10,347 INFO L290 TraceCheckUtils]: 8: Hoare triple {16148#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {16148#true} is VALID [2022-02-21 04:23:10,347 INFO L290 TraceCheckUtils]: 9: Hoare triple {16148#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {16148#true} is VALID [2022-02-21 04:23:10,347 INFO L290 TraceCheckUtils]: 10: Hoare triple {16148#true} assume 0 == ~M_E~0;~M_E~0 := 1; {16148#true} is VALID [2022-02-21 04:23:10,347 INFO L290 TraceCheckUtils]: 11: Hoare triple {16148#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {16148#true} is VALID [2022-02-21 04:23:10,348 INFO L290 TraceCheckUtils]: 12: Hoare triple {16148#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {16148#true} is VALID [2022-02-21 04:23:10,348 INFO L290 TraceCheckUtils]: 13: Hoare triple {16148#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {16148#true} is VALID [2022-02-21 04:23:10,348 INFO L290 TraceCheckUtils]: 14: Hoare triple {16148#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {16148#true} is VALID [2022-02-21 04:23:10,348 INFO L290 TraceCheckUtils]: 15: Hoare triple {16148#true} assume !(0 == ~T5_E~0); {16148#true} is VALID [2022-02-21 04:23:10,349 INFO L290 TraceCheckUtils]: 16: Hoare triple {16148#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,349 INFO L290 TraceCheckUtils]: 17: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,349 INFO L290 TraceCheckUtils]: 18: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,350 INFO L290 TraceCheckUtils]: 19: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,350 INFO L290 TraceCheckUtils]: 20: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,350 INFO L290 TraceCheckUtils]: 21: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,351 INFO L290 TraceCheckUtils]: 22: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,351 INFO L290 TraceCheckUtils]: 23: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,351 INFO L290 TraceCheckUtils]: 24: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,352 INFO L290 TraceCheckUtils]: 25: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,352 INFO L290 TraceCheckUtils]: 26: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,352 INFO L290 TraceCheckUtils]: 27: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,353 INFO L290 TraceCheckUtils]: 28: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,353 INFO L290 TraceCheckUtils]: 29: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,353 INFO L290 TraceCheckUtils]: 30: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,354 INFO L290 TraceCheckUtils]: 31: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,354 INFO L290 TraceCheckUtils]: 32: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,354 INFO L290 TraceCheckUtils]: 33: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,355 INFO L290 TraceCheckUtils]: 34: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,355 INFO L290 TraceCheckUtils]: 35: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,355 INFO L290 TraceCheckUtils]: 36: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,356 INFO L290 TraceCheckUtils]: 37: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,356 INFO L290 TraceCheckUtils]: 38: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,356 INFO L290 TraceCheckUtils]: 39: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,357 INFO L290 TraceCheckUtils]: 40: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,357 INFO L290 TraceCheckUtils]: 41: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,357 INFO L290 TraceCheckUtils]: 42: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,358 INFO L290 TraceCheckUtils]: 43: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,358 INFO L290 TraceCheckUtils]: 44: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,358 INFO L290 TraceCheckUtils]: 45: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,359 INFO L290 TraceCheckUtils]: 46: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,359 INFO L290 TraceCheckUtils]: 47: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,359 INFO L290 TraceCheckUtils]: 48: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,360 INFO L290 TraceCheckUtils]: 49: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,360 INFO L290 TraceCheckUtils]: 50: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,361 INFO L290 TraceCheckUtils]: 51: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,361 INFO L290 TraceCheckUtils]: 52: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,361 INFO L290 TraceCheckUtils]: 53: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,362 INFO L290 TraceCheckUtils]: 54: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,362 INFO L290 TraceCheckUtils]: 55: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,363 INFO L290 TraceCheckUtils]: 56: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,363 INFO L290 TraceCheckUtils]: 57: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,363 INFO L290 TraceCheckUtils]: 58: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,364 INFO L290 TraceCheckUtils]: 59: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,364 INFO L290 TraceCheckUtils]: 60: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,364 INFO L290 TraceCheckUtils]: 61: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,365 INFO L290 TraceCheckUtils]: 62: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,365 INFO L290 TraceCheckUtils]: 63: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,365 INFO L290 TraceCheckUtils]: 64: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,366 INFO L290 TraceCheckUtils]: 65: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,366 INFO L290 TraceCheckUtils]: 66: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,366 INFO L290 TraceCheckUtils]: 67: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,367 INFO L290 TraceCheckUtils]: 68: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,367 INFO L290 TraceCheckUtils]: 69: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,367 INFO L290 TraceCheckUtils]: 70: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,368 INFO L290 TraceCheckUtils]: 71: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,368 INFO L290 TraceCheckUtils]: 72: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,368 INFO L290 TraceCheckUtils]: 73: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,369 INFO L290 TraceCheckUtils]: 74: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,369 INFO L290 TraceCheckUtils]: 75: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,369 INFO L290 TraceCheckUtils]: 76: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,370 INFO L290 TraceCheckUtils]: 77: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,370 INFO L290 TraceCheckUtils]: 78: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,371 INFO L290 TraceCheckUtils]: 79: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,371 INFO L290 TraceCheckUtils]: 80: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,371 INFO L290 TraceCheckUtils]: 81: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,372 INFO L290 TraceCheckUtils]: 82: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,372 INFO L290 TraceCheckUtils]: 83: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,372 INFO L290 TraceCheckUtils]: 84: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,373 INFO L290 TraceCheckUtils]: 85: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,373 INFO L290 TraceCheckUtils]: 86: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,373 INFO L290 TraceCheckUtils]: 87: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,374 INFO L290 TraceCheckUtils]: 88: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,374 INFO L290 TraceCheckUtils]: 89: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,374 INFO L290 TraceCheckUtils]: 90: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,375 INFO L290 TraceCheckUtils]: 91: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,375 INFO L290 TraceCheckUtils]: 92: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,375 INFO L290 TraceCheckUtils]: 93: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,376 INFO L290 TraceCheckUtils]: 94: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,376 INFO L290 TraceCheckUtils]: 95: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,376 INFO L290 TraceCheckUtils]: 96: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,377 INFO L290 TraceCheckUtils]: 97: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t10_pc~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,377 INFO L290 TraceCheckUtils]: 98: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,377 INFO L290 TraceCheckUtils]: 99: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,378 INFO L290 TraceCheckUtils]: 100: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,378 INFO L290 TraceCheckUtils]: 101: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,378 INFO L290 TraceCheckUtils]: 102: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,379 INFO L290 TraceCheckUtils]: 103: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t11_pc~0); {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,379 INFO L290 TraceCheckUtils]: 104: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,379 INFO L290 TraceCheckUtils]: 105: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,380 INFO L290 TraceCheckUtils]: 106: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,380 INFO L290 TraceCheckUtils]: 107: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,380 INFO L290 TraceCheckUtils]: 108: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,381 INFO L290 TraceCheckUtils]: 109: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,381 INFO L290 TraceCheckUtils]: 110: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,381 INFO L290 TraceCheckUtils]: 111: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,382 INFO L290 TraceCheckUtils]: 112: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,382 INFO L290 TraceCheckUtils]: 113: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,382 INFO L290 TraceCheckUtils]: 114: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,383 INFO L290 TraceCheckUtils]: 115: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,383 INFO L290 TraceCheckUtils]: 116: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,383 INFO L290 TraceCheckUtils]: 117: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,384 INFO L290 TraceCheckUtils]: 118: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,384 INFO L290 TraceCheckUtils]: 119: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,385 INFO L290 TraceCheckUtils]: 120: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {16150#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:10,385 INFO L290 TraceCheckUtils]: 121: Hoare triple {16150#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {16149#false} is VALID [2022-02-21 04:23:10,385 INFO L290 TraceCheckUtils]: 122: Hoare triple {16149#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,385 INFO L290 TraceCheckUtils]: 123: Hoare triple {16149#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,385 INFO L290 TraceCheckUtils]: 124: Hoare triple {16149#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 125: Hoare triple {16149#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 126: Hoare triple {16149#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 127: Hoare triple {16149#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 128: Hoare triple {16149#false} assume 1 == ~E_M~0;~E_M~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 129: Hoare triple {16149#false} assume !(1 == ~E_1~0); {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 130: Hoare triple {16149#false} assume 1 == ~E_2~0;~E_2~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 131: Hoare triple {16149#false} assume 1 == ~E_3~0;~E_3~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,386 INFO L290 TraceCheckUtils]: 132: Hoare triple {16149#false} assume 1 == ~E_4~0;~E_4~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 133: Hoare triple {16149#false} assume 1 == ~E_5~0;~E_5~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 134: Hoare triple {16149#false} assume 1 == ~E_6~0;~E_6~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 135: Hoare triple {16149#false} assume 1 == ~E_7~0;~E_7~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 136: Hoare triple {16149#false} assume 1 == ~E_8~0;~E_8~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 137: Hoare triple {16149#false} assume !(1 == ~E_9~0); {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 138: Hoare triple {16149#false} assume 1 == ~E_10~0;~E_10~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 139: Hoare triple {16149#false} assume 1 == ~E_11~0;~E_11~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,387 INFO L290 TraceCheckUtils]: 140: Hoare triple {16149#false} assume 1 == ~E_12~0;~E_12~0 := 2; {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 141: Hoare triple {16149#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 142: Hoare triple {16149#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 143: Hoare triple {16149#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 144: Hoare triple {16149#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 145: Hoare triple {16149#false} assume !(0 == start_simulation_~tmp~3#1); {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 146: Hoare triple {16149#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 147: Hoare triple {16149#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {16149#false} is VALID [2022-02-21 04:23:10,388 INFO L290 TraceCheckUtils]: 148: Hoare triple {16149#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {16149#false} is VALID [2022-02-21 04:23:10,389 INFO L290 TraceCheckUtils]: 149: Hoare triple {16149#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {16149#false} is VALID [2022-02-21 04:23:10,389 INFO L290 TraceCheckUtils]: 150: Hoare triple {16149#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {16149#false} is VALID [2022-02-21 04:23:10,389 INFO L290 TraceCheckUtils]: 151: Hoare triple {16149#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {16149#false} is VALID [2022-02-21 04:23:10,389 INFO L290 TraceCheckUtils]: 152: Hoare triple {16149#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {16149#false} is VALID [2022-02-21 04:23:10,389 INFO L290 TraceCheckUtils]: 153: Hoare triple {16149#false} assume !(0 != start_simulation_~tmp___0~1#1); {16149#false} is VALID [2022-02-21 04:23:10,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:10,390 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:10,390 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593137289] [2022-02-21 04:23:10,390 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593137289] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:10,390 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:10,390 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:10,390 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721780449] [2022-02-21 04:23:10,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:10,391 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:10,391 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:10,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:10,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:10,392 INFO L87 Difference]: Start difference. First operand 1790 states and 2654 transitions. cyclomatic complexity: 865 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:11,725 INFO L93 Difference]: Finished difference Result 1790 states and 2653 transitions. [2022-02-21 04:23:11,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:11,725 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:11,831 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:11,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2653 transitions. [2022-02-21 04:23:11,907 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:11,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2653 transitions. [2022-02-21 04:23:11,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:11,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:11,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2653 transitions. [2022-02-21 04:23:11,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:11,982 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-02-21 04:23:11,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2653 transitions. [2022-02-21 04:23:11,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:11,999 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:12,001 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2653 transitions. Second operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:12,003 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2653 transitions. Second operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:12,013 INFO L87 Difference]: Start difference. First operand 1790 states and 2653 transitions. Second operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:12,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:12,147 INFO L93 Difference]: Finished difference Result 1790 states and 2653 transitions. [2022-02-21 04:23:12,147 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2653 transitions. [2022-02-21 04:23:12,150 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:12,163 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:12,166 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2653 transitions. [2022-02-21 04:23:12,168 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2653 transitions. [2022-02-21 04:23:12,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:12,296 INFO L93 Difference]: Finished difference Result 1790 states and 2653 transitions. [2022-02-21 04:23:12,296 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2653 transitions. [2022-02-21 04:23:12,299 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:12,299 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:12,299 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:12,299 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:12,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.482122905027933) internal successors, (2653), 1789 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:12,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2653 transitions. [2022-02-21 04:23:12,369 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-02-21 04:23:12,369 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2653 transitions. [2022-02-21 04:23:12,369 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:23:12,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2653 transitions. [2022-02-21 04:23:12,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:12,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:12,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:12,376 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:12,376 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:12,376 INFO L791 eck$LassoCheckResult]: Stem: 18787#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18211#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18184#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18185#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 19441#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18488#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17941#L863-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 17942#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 19213#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19352#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19718#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19719#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18700#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18701#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19239#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19159#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19160#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19312#L1206 assume !(0 == ~M_E~0); 18677#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18678#L1211-1 assume !(0 == ~T2_E~0); 19571#L1216-1 assume !(0 == ~T3_E~0); 18470#L1221-1 assume !(0 == ~T4_E~0); 18471#L1226-1 assume !(0 == ~T5_E~0); 18135#L1231-1 assume !(0 == ~T6_E~0); 18136#L1236-1 assume !(0 == ~T7_E~0); 19602#L1241-1 assume !(0 == ~T8_E~0); 18532#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18533#L1251-1 assume !(0 == ~T10_E~0); 18753#L1256-1 assume !(0 == ~T11_E~0); 17953#L1261-1 assume !(0 == ~T12_E~0); 17954#L1266-1 assume !(0 == ~E_M~0); 19705#L1271-1 assume !(0 == ~E_1~0); 19340#L1276-1 assume !(0 == ~E_2~0); 19341#L1281-1 assume !(0 == ~E_3~0); 19268#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 18374#L1291-1 assume !(0 == ~E_5~0); 18375#L1296-1 assume !(0 == ~E_6~0); 19081#L1301-1 assume !(0 == ~E_7~0); 19082#L1306-1 assume !(0 == ~E_8~0); 19514#L1311-1 assume !(0 == ~E_9~0); 18335#L1316-1 assume !(0 == ~E_10~0); 18336#L1321-1 assume !(0 == ~E_11~0); 19098#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18201#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18202#L598 assume 1 == ~m_pc~0; 18259#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18260#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19584#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19676#L1497 assume !(0 != activate_threads_~tmp~1#1); 19677#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19633#L617 assume !(1 == ~t1_pc~0); 18555#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18556#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18415#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18416#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19176#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19177#L636 assume 1 == ~t2_pc~0; 18524#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18525#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18355#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18356#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 19212#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18876#L655 assume !(1 == ~t3_pc~0); 18877#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19589#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18229#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18230#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 19706#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19707#L674 assume 1 == ~t4_pc~0; 18049#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18050#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19347#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18359#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 18360#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18872#L693 assume !(1 == ~t5_pc~0); 19035#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18682#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18683#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19516#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 18765#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18702#L712 assume 1 == ~t6_pc~0; 18703#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19130#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19131#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19417#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 19228#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19226#L731 assume 1 == ~t7_pc~0; 18203#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18204#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18400#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19336#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 19454#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18313#L750 assume !(1 == ~t8_pc~0); 17984#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17983#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18499#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19529#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18636#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18637#L769 assume 1 == ~t9_pc~0; 19174#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18157#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18158#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18941#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 19393#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19474#L788 assume !(1 == ~t10_pc~0); 19049#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19050#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19283#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19284#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 18311#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18312#L807 assume 1 == ~t11_pc~0; 19483#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19061#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19214#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19625#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 19730#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19573#L826 assume !(1 == ~t12_pc~0); 18707#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18708#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19234#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19665#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 18865#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18774#L1344 assume !(1 == ~M_E~0); 18775#L1344-2 assume !(1 == ~T1_E~0); 18916#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19089#L1354-1 assume !(1 == ~T3_E~0); 19090#L1359-1 assume !(1 == ~T4_E~0); 19463#L1364-1 assume !(1 == ~T5_E~0); 18417#L1369-1 assume !(1 == ~T6_E~0); 18418#L1374-1 assume !(1 == ~T7_E~0); 19096#L1379-1 assume !(1 == ~T8_E~0); 19097#L1384-1 assume !(1 == ~T9_E~0); 19158#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19604#L1394-1 assume !(1 == ~T11_E~0); 19605#L1399-1 assume !(1 == ~T12_E~0); 19684#L1404-1 assume !(1 == ~E_M~0); 18536#L1409-1 assume !(1 == ~E_1~0); 18537#L1414-1 assume !(1 == ~E_2~0); 19374#L1419-1 assume !(1 == ~E_3~0); 18170#L1424-1 assume !(1 == ~E_4~0); 18171#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19108#L1434-1 assume !(1 == ~E_6~0); 19623#L1439-1 assume !(1 == ~E_7~0); 18225#L1444-1 assume !(1 == ~E_8~0); 18226#L1449-1 assume !(1 == ~E_9~0); 18641#L1454-1 assume !(1 == ~E_10~0); 18642#L1459-1 assume !(1 == ~E_11~0); 19192#L1464-1 assume !(1 == ~E_12~0); 19193#L1469-1 assume { :end_inline_reset_delta_events } true; 19240#L1815-2 [2022-02-21 04:23:12,376 INFO L793 eck$LassoCheckResult]: Loop: 19240#L1815-2 assume !false; 19394#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19063#L1181 assume !false; 19134#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19086#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17944#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18674#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19224#L1008 assume !(0 != eval_~tmp~0#1); 19225#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18165#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18166#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19724#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19191#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18297#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18298#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18888#L1226-3 assume !(0 == ~T5_E~0); 18361#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18362#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18673#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19661#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19564#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19300#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18319#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18320#L1266-3 assume !(0 == ~E_M~0); 18357#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18358#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18832#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18833#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19370#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19371#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19713#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19681#L1306-3 assume !(0 == ~E_8~0); 18957#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18243#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18244#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18321#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 19055#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19381#L598-42 assume !(1 == ~m_pc~0); 19382#L598-44 is_master_triggered_~__retres1~0#1 := 0; 19496#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18398#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18399#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 19682#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19112#L617-42 assume 1 == ~t1_pc~0; 18884#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18749#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18750#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19164#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18464#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18465#L636-42 assume !(1 == ~t2_pc~0); 18928#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18929#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19279#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19280#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19459#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19321#L655-42 assume !(1 == ~t3_pc~0); 18901#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 18902#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18534#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18535#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19588#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19533#L674-42 assume !(1 == ~t4_pc~0); 19307#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 19229#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18118#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18119#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19033#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19034#L693-42 assume 1 == ~t5_pc~0; 19289#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19290#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19350#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19345#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19346#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18648#L712-42 assume !(1 == ~t6_pc~0); 18649#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 18975#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19183#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19184#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18757#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18758#L731-42 assume !(1 == ~t7_pc~0); 18456#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18457#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19524#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18665#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18666#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18369#L750-42 assume 1 == ~t8_pc~0; 18370#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18944#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19367#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18262#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18263#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19032#L769-42 assume 1 == ~t9_pc~0; 18854#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18855#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19538#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19603#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 18466#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18467#L788-42 assume 1 == ~t10_pc~0; 19040#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19254#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18984#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18985#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19722#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19700#L807-42 assume !(1 == ~t11_pc~0); 18070#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 18071#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18209#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18210#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18212#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18461#L826-42 assume 1 == ~t12_pc~0; 18462#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18654#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19446#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18451#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18452#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19303#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19304#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19230#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18611#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18612#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19244#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19702#L1369-3 assume !(1 == ~T6_E~0); 19622#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18376#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18377#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18609#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18610#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18908#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19631#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19594#L1409-3 assume !(1 == ~E_1~0); 19595#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19660#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19440#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18277#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18278#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19243#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18217#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18218#L1449-3 assume !(1 == ~E_9~0); 18327#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19237#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19238#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19619#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19117#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18116#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18117#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18733#L1834 assume !(0 == start_simulation_~tmp~3#1); 19353#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19376#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18810#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18989#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19201#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19609#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18102#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18103#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 19240#L1815-2 [2022-02-21 04:23:12,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:12,377 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-02-21 04:23:12,378 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:12,378 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230012919] [2022-02-21 04:23:12,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:12,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:12,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:12,413 INFO L290 TraceCheckUtils]: 0: Hoare triple {23314#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {23314#true} is VALID [2022-02-21 04:23:12,413 INFO L290 TraceCheckUtils]: 1: Hoare triple {23314#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {23316#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:12,413 INFO L290 TraceCheckUtils]: 2: Hoare triple {23316#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {23316#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:12,414 INFO L290 TraceCheckUtils]: 3: Hoare triple {23316#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {23316#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:12,414 INFO L290 TraceCheckUtils]: 4: Hoare triple {23316#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {23316#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:12,414 INFO L290 TraceCheckUtils]: 5: Hoare triple {23316#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {23316#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:12,415 INFO L290 TraceCheckUtils]: 6: Hoare triple {23316#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {23316#(= ~t3_i~0 1)} is VALID [2022-02-21 04:23:12,415 INFO L290 TraceCheckUtils]: 7: Hoare triple {23316#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,415 INFO L290 TraceCheckUtils]: 8: Hoare triple {23315#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,415 INFO L290 TraceCheckUtils]: 9: Hoare triple {23315#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,415 INFO L290 TraceCheckUtils]: 10: Hoare triple {23315#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,415 INFO L290 TraceCheckUtils]: 11: Hoare triple {23315#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,415 INFO L290 TraceCheckUtils]: 12: Hoare triple {23315#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 13: Hoare triple {23315#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 14: Hoare triple {23315#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 15: Hoare triple {23315#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 16: Hoare triple {23315#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 17: Hoare triple {23315#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 18: Hoare triple {23315#false} assume !(0 == ~M_E~0); {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 19: Hoare triple {23315#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 20: Hoare triple {23315#false} assume !(0 == ~T2_E~0); {23315#false} is VALID [2022-02-21 04:23:12,416 INFO L290 TraceCheckUtils]: 21: Hoare triple {23315#false} assume !(0 == ~T3_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 22: Hoare triple {23315#false} assume !(0 == ~T4_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 23: Hoare triple {23315#false} assume !(0 == ~T5_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 24: Hoare triple {23315#false} assume !(0 == ~T6_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 25: Hoare triple {23315#false} assume !(0 == ~T7_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 26: Hoare triple {23315#false} assume !(0 == ~T8_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 27: Hoare triple {23315#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 28: Hoare triple {23315#false} assume !(0 == ~T10_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 29: Hoare triple {23315#false} assume !(0 == ~T11_E~0); {23315#false} is VALID [2022-02-21 04:23:12,417 INFO L290 TraceCheckUtils]: 30: Hoare triple {23315#false} assume !(0 == ~T12_E~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 31: Hoare triple {23315#false} assume !(0 == ~E_M~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 32: Hoare triple {23315#false} assume !(0 == ~E_1~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 33: Hoare triple {23315#false} assume !(0 == ~E_2~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 34: Hoare triple {23315#false} assume !(0 == ~E_3~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 35: Hoare triple {23315#false} assume 0 == ~E_4~0;~E_4~0 := 1; {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 36: Hoare triple {23315#false} assume !(0 == ~E_5~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 37: Hoare triple {23315#false} assume !(0 == ~E_6~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 38: Hoare triple {23315#false} assume !(0 == ~E_7~0); {23315#false} is VALID [2022-02-21 04:23:12,418 INFO L290 TraceCheckUtils]: 39: Hoare triple {23315#false} assume !(0 == ~E_8~0); {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 40: Hoare triple {23315#false} assume !(0 == ~E_9~0); {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 41: Hoare triple {23315#false} assume !(0 == ~E_10~0); {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 42: Hoare triple {23315#false} assume !(0 == ~E_11~0); {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 43: Hoare triple {23315#false} assume 0 == ~E_12~0;~E_12~0 := 1; {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 44: Hoare triple {23315#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 45: Hoare triple {23315#false} assume 1 == ~m_pc~0; {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 46: Hoare triple {23315#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {23315#false} is VALID [2022-02-21 04:23:12,419 INFO L290 TraceCheckUtils]: 47: Hoare triple {23315#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 48: Hoare triple {23315#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 49: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp~1#1); {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 50: Hoare triple {23315#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 51: Hoare triple {23315#false} assume !(1 == ~t1_pc~0); {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 52: Hoare triple {23315#false} is_transmit1_triggered_~__retres1~1#1 := 0; {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 53: Hoare triple {23315#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 54: Hoare triple {23315#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 55: Hoare triple {23315#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23315#false} is VALID [2022-02-21 04:23:12,420 INFO L290 TraceCheckUtils]: 56: Hoare triple {23315#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 57: Hoare triple {23315#false} assume 1 == ~t2_pc~0; {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 58: Hoare triple {23315#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 59: Hoare triple {23315#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 60: Hoare triple {23315#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 61: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___1~0#1); {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 62: Hoare triple {23315#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 63: Hoare triple {23315#false} assume !(1 == ~t3_pc~0); {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 64: Hoare triple {23315#false} is_transmit3_triggered_~__retres1~3#1 := 0; {23315#false} is VALID [2022-02-21 04:23:12,421 INFO L290 TraceCheckUtils]: 65: Hoare triple {23315#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 66: Hoare triple {23315#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 67: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___2~0#1); {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 68: Hoare triple {23315#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 69: Hoare triple {23315#false} assume 1 == ~t4_pc~0; {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 70: Hoare triple {23315#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 71: Hoare triple {23315#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 72: Hoare triple {23315#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 73: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___3~0#1); {23315#false} is VALID [2022-02-21 04:23:12,422 INFO L290 TraceCheckUtils]: 74: Hoare triple {23315#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 75: Hoare triple {23315#false} assume !(1 == ~t5_pc~0); {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 76: Hoare triple {23315#false} is_transmit5_triggered_~__retres1~5#1 := 0; {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 77: Hoare triple {23315#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 78: Hoare triple {23315#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 79: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___4~0#1); {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 80: Hoare triple {23315#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 81: Hoare triple {23315#false} assume 1 == ~t6_pc~0; {23315#false} is VALID [2022-02-21 04:23:12,423 INFO L290 TraceCheckUtils]: 82: Hoare triple {23315#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 83: Hoare triple {23315#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 84: Hoare triple {23315#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 85: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___5~0#1); {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 86: Hoare triple {23315#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 87: Hoare triple {23315#false} assume 1 == ~t7_pc~0; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 88: Hoare triple {23315#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 89: Hoare triple {23315#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 90: Hoare triple {23315#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23315#false} is VALID [2022-02-21 04:23:12,424 INFO L290 TraceCheckUtils]: 91: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___6~0#1); {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 92: Hoare triple {23315#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 93: Hoare triple {23315#false} assume !(1 == ~t8_pc~0); {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 94: Hoare triple {23315#false} is_transmit8_triggered_~__retres1~8#1 := 0; {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 95: Hoare triple {23315#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 96: Hoare triple {23315#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 97: Hoare triple {23315#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 98: Hoare triple {23315#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 99: Hoare triple {23315#false} assume 1 == ~t9_pc~0; {23315#false} is VALID [2022-02-21 04:23:12,425 INFO L290 TraceCheckUtils]: 100: Hoare triple {23315#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 101: Hoare triple {23315#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 102: Hoare triple {23315#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 103: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___8~0#1); {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 104: Hoare triple {23315#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 105: Hoare triple {23315#false} assume !(1 == ~t10_pc~0); {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 106: Hoare triple {23315#false} is_transmit10_triggered_~__retres1~10#1 := 0; {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 107: Hoare triple {23315#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23315#false} is VALID [2022-02-21 04:23:12,426 INFO L290 TraceCheckUtils]: 108: Hoare triple {23315#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {23315#false} is VALID [2022-02-21 04:23:12,427 INFO L290 TraceCheckUtils]: 109: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___9~0#1); {23315#false} is VALID [2022-02-21 04:23:12,427 INFO L290 TraceCheckUtils]: 110: Hoare triple {23315#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {23315#false} is VALID [2022-02-21 04:23:12,427 INFO L290 TraceCheckUtils]: 111: Hoare triple {23315#false} assume 1 == ~t11_pc~0; {23315#false} is VALID [2022-02-21 04:23:12,427 INFO L290 TraceCheckUtils]: 112: Hoare triple {23315#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {23315#false} is VALID [2022-02-21 04:23:12,427 INFO L290 TraceCheckUtils]: 113: Hoare triple {23315#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 114: Hoare triple {23315#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 115: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___10~0#1); {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 116: Hoare triple {23315#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 117: Hoare triple {23315#false} assume !(1 == ~t12_pc~0); {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 118: Hoare triple {23315#false} is_transmit12_triggered_~__retres1~12#1 := 0; {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 119: Hoare triple {23315#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 120: Hoare triple {23315#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 121: Hoare triple {23315#false} assume !(0 != activate_threads_~tmp___11~0#1); {23315#false} is VALID [2022-02-21 04:23:12,428 INFO L290 TraceCheckUtils]: 122: Hoare triple {23315#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 123: Hoare triple {23315#false} assume !(1 == ~M_E~0); {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 124: Hoare triple {23315#false} assume !(1 == ~T1_E~0); {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 125: Hoare triple {23315#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 126: Hoare triple {23315#false} assume !(1 == ~T3_E~0); {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 127: Hoare triple {23315#false} assume !(1 == ~T4_E~0); {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 128: Hoare triple {23315#false} assume !(1 == ~T5_E~0); {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 129: Hoare triple {23315#false} assume !(1 == ~T6_E~0); {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 130: Hoare triple {23315#false} assume !(1 == ~T7_E~0); {23315#false} is VALID [2022-02-21 04:23:12,429 INFO L290 TraceCheckUtils]: 131: Hoare triple {23315#false} assume !(1 == ~T8_E~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 132: Hoare triple {23315#false} assume !(1 == ~T9_E~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 133: Hoare triple {23315#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 134: Hoare triple {23315#false} assume !(1 == ~T11_E~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 135: Hoare triple {23315#false} assume !(1 == ~T12_E~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 136: Hoare triple {23315#false} assume !(1 == ~E_M~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 137: Hoare triple {23315#false} assume !(1 == ~E_1~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 138: Hoare triple {23315#false} assume !(1 == ~E_2~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 139: Hoare triple {23315#false} assume !(1 == ~E_3~0); {23315#false} is VALID [2022-02-21 04:23:12,430 INFO L290 TraceCheckUtils]: 140: Hoare triple {23315#false} assume !(1 == ~E_4~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 141: Hoare triple {23315#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 142: Hoare triple {23315#false} assume !(1 == ~E_6~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 143: Hoare triple {23315#false} assume !(1 == ~E_7~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 144: Hoare triple {23315#false} assume !(1 == ~E_8~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 145: Hoare triple {23315#false} assume !(1 == ~E_9~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 146: Hoare triple {23315#false} assume !(1 == ~E_10~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 147: Hoare triple {23315#false} assume !(1 == ~E_11~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 148: Hoare triple {23315#false} assume !(1 == ~E_12~0); {23315#false} is VALID [2022-02-21 04:23:12,431 INFO L290 TraceCheckUtils]: 149: Hoare triple {23315#false} assume { :end_inline_reset_delta_events } true; {23315#false} is VALID [2022-02-21 04:23:12,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:12,432 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:12,432 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230012919] [2022-02-21 04:23:12,433 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230012919] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:12,433 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:12,433 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:12,433 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386904526] [2022-02-21 04:23:12,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:12,434 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:12,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:12,434 INFO L85 PathProgramCache]: Analyzing trace with hash 2071608406, now seen corresponding path program 1 times [2022-02-21 04:23:12,434 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:12,437 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008492619] [2022-02-21 04:23:12,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:12,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:12,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 0: Hoare triple {23317#true} assume !false; {23317#true} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 1: Hoare triple {23317#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {23317#true} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 2: Hoare triple {23317#true} assume !false; {23317#true} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 3: Hoare triple {23317#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {23317#true} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 4: Hoare triple {23317#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {23317#true} is VALID [2022-02-21 04:23:12,492 INFO L290 TraceCheckUtils]: 5: Hoare triple {23317#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 6: Hoare triple {23317#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 7: Hoare triple {23317#true} assume !(0 != eval_~tmp~0#1); {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 8: Hoare triple {23317#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 9: Hoare triple {23317#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 10: Hoare triple {23317#true} assume 0 == ~M_E~0;~M_E~0 := 1; {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 11: Hoare triple {23317#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 12: Hoare triple {23317#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {23317#true} is VALID [2022-02-21 04:23:12,493 INFO L290 TraceCheckUtils]: 13: Hoare triple {23317#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23317#true} is VALID [2022-02-21 04:23:12,494 INFO L290 TraceCheckUtils]: 14: Hoare triple {23317#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {23317#true} is VALID [2022-02-21 04:23:12,494 INFO L290 TraceCheckUtils]: 15: Hoare triple {23317#true} assume !(0 == ~T5_E~0); {23317#true} is VALID [2022-02-21 04:23:12,494 INFO L290 TraceCheckUtils]: 16: Hoare triple {23317#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,494 INFO L290 TraceCheckUtils]: 17: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,495 INFO L290 TraceCheckUtils]: 18: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,495 INFO L290 TraceCheckUtils]: 19: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,495 INFO L290 TraceCheckUtils]: 20: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,495 INFO L290 TraceCheckUtils]: 21: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,496 INFO L290 TraceCheckUtils]: 22: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,496 INFO L290 TraceCheckUtils]: 23: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,496 INFO L290 TraceCheckUtils]: 24: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,497 INFO L290 TraceCheckUtils]: 25: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,497 INFO L290 TraceCheckUtils]: 26: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,497 INFO L290 TraceCheckUtils]: 27: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,497 INFO L290 TraceCheckUtils]: 28: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,498 INFO L290 TraceCheckUtils]: 29: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,498 INFO L290 TraceCheckUtils]: 30: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,498 INFO L290 TraceCheckUtils]: 31: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,499 INFO L290 TraceCheckUtils]: 32: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,499 INFO L290 TraceCheckUtils]: 33: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,499 INFO L290 TraceCheckUtils]: 34: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,499 INFO L290 TraceCheckUtils]: 35: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,500 INFO L290 TraceCheckUtils]: 36: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,500 INFO L290 TraceCheckUtils]: 37: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,500 INFO L290 TraceCheckUtils]: 38: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,501 INFO L290 TraceCheckUtils]: 39: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,501 INFO L290 TraceCheckUtils]: 40: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,501 INFO L290 TraceCheckUtils]: 41: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,501 INFO L290 TraceCheckUtils]: 42: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,502 INFO L290 TraceCheckUtils]: 43: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,502 INFO L290 TraceCheckUtils]: 44: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,502 INFO L290 TraceCheckUtils]: 45: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 46: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 47: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 48: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,503 INFO L290 TraceCheckUtils]: 49: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 50: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 51: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,504 INFO L290 TraceCheckUtils]: 52: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,505 INFO L290 TraceCheckUtils]: 53: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,505 INFO L290 TraceCheckUtils]: 54: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,505 INFO L290 TraceCheckUtils]: 55: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,505 INFO L290 TraceCheckUtils]: 56: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,506 INFO L290 TraceCheckUtils]: 57: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,506 INFO L290 TraceCheckUtils]: 58: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,506 INFO L290 TraceCheckUtils]: 59: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,507 INFO L290 TraceCheckUtils]: 60: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,507 INFO L290 TraceCheckUtils]: 61: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,507 INFO L290 TraceCheckUtils]: 62: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,507 INFO L290 TraceCheckUtils]: 63: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,508 INFO L290 TraceCheckUtils]: 64: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,508 INFO L290 TraceCheckUtils]: 65: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,508 INFO L290 TraceCheckUtils]: 66: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,509 INFO L290 TraceCheckUtils]: 67: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,509 INFO L290 TraceCheckUtils]: 68: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,509 INFO L290 TraceCheckUtils]: 69: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,509 INFO L290 TraceCheckUtils]: 70: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 71: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 72: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,510 INFO L290 TraceCheckUtils]: 73: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,511 INFO L290 TraceCheckUtils]: 74: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,511 INFO L290 TraceCheckUtils]: 75: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,511 INFO L290 TraceCheckUtils]: 76: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,511 INFO L290 TraceCheckUtils]: 77: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 78: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 79: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,512 INFO L290 TraceCheckUtils]: 80: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,513 INFO L290 TraceCheckUtils]: 81: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,513 INFO L290 TraceCheckUtils]: 82: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,513 INFO L290 TraceCheckUtils]: 83: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,513 INFO L290 TraceCheckUtils]: 84: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,514 INFO L290 TraceCheckUtils]: 85: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,514 INFO L290 TraceCheckUtils]: 86: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,514 INFO L290 TraceCheckUtils]: 87: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,515 INFO L290 TraceCheckUtils]: 88: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,515 INFO L290 TraceCheckUtils]: 89: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,515 INFO L290 TraceCheckUtils]: 90: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,515 INFO L290 TraceCheckUtils]: 91: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,516 INFO L290 TraceCheckUtils]: 92: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,516 INFO L290 TraceCheckUtils]: 93: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,516 INFO L290 TraceCheckUtils]: 94: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,517 INFO L290 TraceCheckUtils]: 95: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,517 INFO L290 TraceCheckUtils]: 96: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,517 INFO L290 TraceCheckUtils]: 97: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,517 INFO L290 TraceCheckUtils]: 98: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,518 INFO L290 TraceCheckUtils]: 99: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,518 INFO L290 TraceCheckUtils]: 100: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,518 INFO L290 TraceCheckUtils]: 101: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,519 INFO L290 TraceCheckUtils]: 102: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,519 INFO L290 TraceCheckUtils]: 103: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t11_pc~0); {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,519 INFO L290 TraceCheckUtils]: 104: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,519 INFO L290 TraceCheckUtils]: 105: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,520 INFO L290 TraceCheckUtils]: 106: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,520 INFO L290 TraceCheckUtils]: 107: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,520 INFO L290 TraceCheckUtils]: 108: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,521 INFO L290 TraceCheckUtils]: 109: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,521 INFO L290 TraceCheckUtils]: 110: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,521 INFO L290 TraceCheckUtils]: 111: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,521 INFO L290 TraceCheckUtils]: 112: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,522 INFO L290 TraceCheckUtils]: 113: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,522 INFO L290 TraceCheckUtils]: 114: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,522 INFO L290 TraceCheckUtils]: 115: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,523 INFO L290 TraceCheckUtils]: 116: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,523 INFO L290 TraceCheckUtils]: 117: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,523 INFO L290 TraceCheckUtils]: 118: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,523 INFO L290 TraceCheckUtils]: 119: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,524 INFO L290 TraceCheckUtils]: 120: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23319#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:12,524 INFO L290 TraceCheckUtils]: 121: Hoare triple {23319#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {23318#false} is VALID [2022-02-21 04:23:12,524 INFO L290 TraceCheckUtils]: 122: Hoare triple {23318#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,524 INFO L290 TraceCheckUtils]: 123: Hoare triple {23318#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,524 INFO L290 TraceCheckUtils]: 124: Hoare triple {23318#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,524 INFO L290 TraceCheckUtils]: 125: Hoare triple {23318#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 126: Hoare triple {23318#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 127: Hoare triple {23318#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 128: Hoare triple {23318#false} assume 1 == ~E_M~0;~E_M~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 129: Hoare triple {23318#false} assume !(1 == ~E_1~0); {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 130: Hoare triple {23318#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 131: Hoare triple {23318#false} assume 1 == ~E_3~0;~E_3~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 132: Hoare triple {23318#false} assume 1 == ~E_4~0;~E_4~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,525 INFO L290 TraceCheckUtils]: 133: Hoare triple {23318#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 134: Hoare triple {23318#false} assume 1 == ~E_6~0;~E_6~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 135: Hoare triple {23318#false} assume 1 == ~E_7~0;~E_7~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 136: Hoare triple {23318#false} assume 1 == ~E_8~0;~E_8~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 137: Hoare triple {23318#false} assume !(1 == ~E_9~0); {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 138: Hoare triple {23318#false} assume 1 == ~E_10~0;~E_10~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 139: Hoare triple {23318#false} assume 1 == ~E_11~0;~E_11~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 140: Hoare triple {23318#false} assume 1 == ~E_12~0;~E_12~0 := 2; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 141: Hoare triple {23318#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {23318#false} is VALID [2022-02-21 04:23:12,526 INFO L290 TraceCheckUtils]: 142: Hoare triple {23318#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 143: Hoare triple {23318#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 144: Hoare triple {23318#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 145: Hoare triple {23318#false} assume !(0 == start_simulation_~tmp~3#1); {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 146: Hoare triple {23318#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 147: Hoare triple {23318#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 148: Hoare triple {23318#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 149: Hoare triple {23318#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {23318#false} is VALID [2022-02-21 04:23:12,527 INFO L290 TraceCheckUtils]: 150: Hoare triple {23318#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {23318#false} is VALID [2022-02-21 04:23:12,528 INFO L290 TraceCheckUtils]: 151: Hoare triple {23318#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {23318#false} is VALID [2022-02-21 04:23:12,528 INFO L290 TraceCheckUtils]: 152: Hoare triple {23318#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {23318#false} is VALID [2022-02-21 04:23:12,528 INFO L290 TraceCheckUtils]: 153: Hoare triple {23318#false} assume !(0 != start_simulation_~tmp___0~1#1); {23318#false} is VALID [2022-02-21 04:23:12,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:12,529 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:12,529 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008492619] [2022-02-21 04:23:12,529 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008492619] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:12,529 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:12,529 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:12,530 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462666456] [2022-02-21 04:23:12,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:12,530 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:12,530 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:12,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:12,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:12,531 INFO L87 Difference]: Start difference. First operand 1790 states and 2653 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:13,791 INFO L93 Difference]: Finished difference Result 1790 states and 2652 transitions. [2022-02-21 04:23:13,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:13,792 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:13,910 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:13,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2652 transitions. [2022-02-21 04:23:13,980 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:14,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2652 transitions. [2022-02-21 04:23:14,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:14,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:14,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2652 transitions. [2022-02-21 04:23:14,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:14,050 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-02-21 04:23:14,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2652 transitions. [2022-02-21 04:23:14,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:14,067 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:14,069 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2652 transitions. Second operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,070 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2652 transitions. Second operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,072 INFO L87 Difference]: Start difference. First operand 1790 states and 2652 transitions. Second operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,138 INFO L93 Difference]: Finished difference Result 1790 states and 2652 transitions. [2022-02-21 04:23:14,138 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2652 transitions. [2022-02-21 04:23:14,140 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,140 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,143 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2652 transitions. [2022-02-21 04:23:14,144 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2652 transitions. [2022-02-21 04:23:14,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:14,211 INFO L93 Difference]: Finished difference Result 1790 states and 2652 transitions. [2022-02-21 04:23:14,212 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2652 transitions. [2022-02-21 04:23:14,214 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:14,214 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:14,214 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:14,214 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:14,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.481564245810056) internal successors, (2652), 1789 states have internal predecessors, (2652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:14,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2652 transitions. [2022-02-21 04:23:14,283 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-02-21 04:23:14,284 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2652 transitions. [2022-02-21 04:23:14,284 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:23:14,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2652 transitions. [2022-02-21 04:23:14,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:14,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:14,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:14,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,290 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:14,290 INFO L791 eck$LassoCheckResult]: Stem: 25954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25955#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25380#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25348#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25349#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 26610#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25657#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25110#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25111#L868-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 26382#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 26521#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26887#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26888#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25869#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25870#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26408#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26328#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26329#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26481#L1206 assume !(0 == ~M_E~0); 25846#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25847#L1211-1 assume !(0 == ~T2_E~0); 26740#L1216-1 assume !(0 == ~T3_E~0); 25639#L1221-1 assume !(0 == ~T4_E~0); 25640#L1226-1 assume !(0 == ~T5_E~0); 25302#L1231-1 assume !(0 == ~T6_E~0); 25303#L1236-1 assume !(0 == ~T7_E~0); 26771#L1241-1 assume !(0 == ~T8_E~0); 25701#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25702#L1251-1 assume !(0 == ~T10_E~0); 25922#L1256-1 assume !(0 == ~T11_E~0); 25122#L1261-1 assume !(0 == ~T12_E~0); 25123#L1266-1 assume !(0 == ~E_M~0); 26874#L1271-1 assume !(0 == ~E_1~0); 26509#L1276-1 assume !(0 == ~E_2~0); 26510#L1281-1 assume !(0 == ~E_3~0); 26435#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 25543#L1291-1 assume !(0 == ~E_5~0); 25544#L1296-1 assume !(0 == ~E_6~0); 26250#L1301-1 assume !(0 == ~E_7~0); 26251#L1306-1 assume !(0 == ~E_8~0); 26683#L1311-1 assume !(0 == ~E_9~0); 25504#L1316-1 assume !(0 == ~E_10~0); 25505#L1321-1 assume !(0 == ~E_11~0); 26267#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25368#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25369#L598 assume 1 == ~m_pc~0; 25428#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25429#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26753#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26845#L1497 assume !(0 != activate_threads_~tmp~1#1); 26846#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26802#L617 assume !(1 == ~t1_pc~0); 25724#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25725#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25584#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25585#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26345#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26346#L636 assume 1 == ~t2_pc~0; 25693#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25694#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25524#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25525#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 26381#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26044#L655 assume !(1 == ~t3_pc~0); 26045#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26758#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25398#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25399#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 26875#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26876#L674 assume 1 == ~t4_pc~0; 25218#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25219#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26516#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25526#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 25527#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26041#L693 assume !(1 == ~t5_pc~0); 26204#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25849#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25850#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26685#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 25934#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25871#L712 assume 1 == ~t6_pc~0; 25872#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26299#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26300#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26586#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 26397#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26395#L731 assume 1 == ~t7_pc~0; 25372#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25373#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25567#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26504#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 26623#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25482#L750 assume !(1 == ~t8_pc~0); 25153#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25152#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25668#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26698#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25805#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25806#L769 assume 1 == ~t9_pc~0; 26343#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25326#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25327#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26110#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 26562#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26643#L788 assume !(1 == ~t10_pc~0); 26218#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26219#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26451#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26452#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 25478#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25479#L807 assume 1 == ~t11_pc~0; 26652#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26230#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26383#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26794#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 26899#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26742#L826 assume !(1 == ~t12_pc~0); 25874#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25875#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26403#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26834#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 26034#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25943#L1344 assume !(1 == ~M_E~0); 25944#L1344-2 assume !(1 == ~T1_E~0); 26085#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26258#L1354-1 assume !(1 == ~T3_E~0); 26259#L1359-1 assume !(1 == ~T4_E~0); 26632#L1364-1 assume !(1 == ~T5_E~0); 25586#L1369-1 assume !(1 == ~T6_E~0); 25587#L1374-1 assume !(1 == ~T7_E~0); 26265#L1379-1 assume !(1 == ~T8_E~0); 26266#L1384-1 assume !(1 == ~T9_E~0); 26327#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26773#L1394-1 assume !(1 == ~T11_E~0); 26774#L1399-1 assume !(1 == ~T12_E~0); 26853#L1404-1 assume !(1 == ~E_M~0); 25705#L1409-1 assume !(1 == ~E_1~0); 25706#L1414-1 assume !(1 == ~E_2~0); 26543#L1419-1 assume !(1 == ~E_3~0); 25339#L1424-1 assume !(1 == ~E_4~0); 25340#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26274#L1434-1 assume !(1 == ~E_6~0); 26792#L1439-1 assume !(1 == ~E_7~0); 25394#L1444-1 assume !(1 == ~E_8~0); 25395#L1449-1 assume !(1 == ~E_9~0); 25810#L1454-1 assume !(1 == ~E_10~0); 25811#L1459-1 assume !(1 == ~E_11~0); 26361#L1464-1 assume !(1 == ~E_12~0); 26362#L1469-1 assume { :end_inline_reset_delta_events } true; 26409#L1815-2 [2022-02-21 04:23:14,291 INFO L793 eck$LassoCheckResult]: Loop: 26409#L1815-2 assume !false; 26563#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26232#L1181 assume !false; 26303#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26255#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25113#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25842#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26393#L1008 assume !(0 != eval_~tmp~0#1); 26394#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25334#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25335#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26893#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26360#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25466#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25467#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26057#L1226-3 assume !(0 == ~T5_E~0); 25530#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25531#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25843#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26831#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26733#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26469#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25488#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25489#L1266-3 assume !(0 == ~E_M~0); 25528#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25529#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26001#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26002#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26539#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26540#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26882#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26850#L1306-3 assume !(0 == ~E_8~0); 26126#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25412#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25413#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25490#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26225#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26550#L598-42 assume !(1 == ~m_pc~0); 26551#L598-44 is_master_triggered_~__retres1~0#1 := 0; 26665#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25568#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25569#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 26851#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26281#L617-42 assume 1 == ~t1_pc~0; 26054#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25918#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25919#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26333#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25633#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25634#L636-42 assume !(1 == ~t2_pc~0); 26097#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26098#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26448#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26449#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26628#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26490#L655-42 assume !(1 == ~t3_pc~0); 26074#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 26075#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25703#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25704#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26757#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26702#L674-42 assume !(1 == ~t4_pc~0); 26476#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 26398#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25287#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25288#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26202#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26203#L693-42 assume 1 == ~t5_pc~0; 26461#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26462#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26519#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26514#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26515#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25817#L712-42 assume !(1 == ~t6_pc~0); 25818#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26145#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26352#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26353#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25926#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25927#L731-42 assume !(1 == ~t7_pc~0); 25622#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25623#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26693#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25834#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25835#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25535#L750-42 assume 1 == ~t8_pc~0; 25536#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26113#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26536#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25431#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25432#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26201#L769-42 assume 1 == ~t9_pc~0; 26021#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26022#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26707#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26772#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 25635#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25636#L788-42 assume 1 == ~t10_pc~0; 26209#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26420#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26153#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26154#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26891#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26867#L807-42 assume !(1 == ~t11_pc~0); 25239#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25240#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25378#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25379#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25381#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25630#L826-42 assume !(1 == ~t12_pc~0); 25632#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25823#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26615#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25620#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25621#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26472#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26473#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26399#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25780#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25781#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26413#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26871#L1369-3 assume !(1 == ~T6_E~0); 26791#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25545#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25546#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25778#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25779#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26077#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26800#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26763#L1409-3 assume !(1 == ~E_1~0); 26764#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26829#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26609#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25446#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25447#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26412#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25384#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25385#L1449-3 assume !(1 == ~E_9~0); 25496#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26405#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26406#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26788#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26286#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25285#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25286#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25902#L1834 assume !(0 == start_simulation_~tmp~3#1); 26522#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26545#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25979#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26158#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26370#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26778#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25271#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25272#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 26409#L1815-2 [2022-02-21 04:23:14,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-02-21 04:23:14,291 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,292 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746195989] [2022-02-21 04:23:14,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,316 INFO L290 TraceCheckUtils]: 0: Hoare triple {30483#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {30483#true} is VALID [2022-02-21 04:23:14,316 INFO L290 TraceCheckUtils]: 1: Hoare triple {30483#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {30485#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:14,316 INFO L290 TraceCheckUtils]: 2: Hoare triple {30485#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {30485#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:14,317 INFO L290 TraceCheckUtils]: 3: Hoare triple {30485#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {30485#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:14,317 INFO L290 TraceCheckUtils]: 4: Hoare triple {30485#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {30485#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:14,317 INFO L290 TraceCheckUtils]: 5: Hoare triple {30485#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {30485#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:14,317 INFO L290 TraceCheckUtils]: 6: Hoare triple {30485#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {30485#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:14,318 INFO L290 TraceCheckUtils]: 7: Hoare triple {30485#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {30485#(= ~t4_i~0 1)} is VALID [2022-02-21 04:23:14,318 INFO L290 TraceCheckUtils]: 8: Hoare triple {30485#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,318 INFO L290 TraceCheckUtils]: 9: Hoare triple {30484#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,318 INFO L290 TraceCheckUtils]: 10: Hoare triple {30484#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,318 INFO L290 TraceCheckUtils]: 11: Hoare triple {30484#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,318 INFO L290 TraceCheckUtils]: 12: Hoare triple {30484#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 13: Hoare triple {30484#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 14: Hoare triple {30484#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 15: Hoare triple {30484#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 16: Hoare triple {30484#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 17: Hoare triple {30484#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 18: Hoare triple {30484#false} assume !(0 == ~M_E~0); {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 19: Hoare triple {30484#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 20: Hoare triple {30484#false} assume !(0 == ~T2_E~0); {30484#false} is VALID [2022-02-21 04:23:14,319 INFO L290 TraceCheckUtils]: 21: Hoare triple {30484#false} assume !(0 == ~T3_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 22: Hoare triple {30484#false} assume !(0 == ~T4_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 23: Hoare triple {30484#false} assume !(0 == ~T5_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 24: Hoare triple {30484#false} assume !(0 == ~T6_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 25: Hoare triple {30484#false} assume !(0 == ~T7_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 26: Hoare triple {30484#false} assume !(0 == ~T8_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 27: Hoare triple {30484#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 28: Hoare triple {30484#false} assume !(0 == ~T10_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 29: Hoare triple {30484#false} assume !(0 == ~T11_E~0); {30484#false} is VALID [2022-02-21 04:23:14,320 INFO L290 TraceCheckUtils]: 30: Hoare triple {30484#false} assume !(0 == ~T12_E~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 31: Hoare triple {30484#false} assume !(0 == ~E_M~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 32: Hoare triple {30484#false} assume !(0 == ~E_1~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 33: Hoare triple {30484#false} assume !(0 == ~E_2~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 34: Hoare triple {30484#false} assume !(0 == ~E_3~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 35: Hoare triple {30484#false} assume 0 == ~E_4~0;~E_4~0 := 1; {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 36: Hoare triple {30484#false} assume !(0 == ~E_5~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 37: Hoare triple {30484#false} assume !(0 == ~E_6~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 38: Hoare triple {30484#false} assume !(0 == ~E_7~0); {30484#false} is VALID [2022-02-21 04:23:14,321 INFO L290 TraceCheckUtils]: 39: Hoare triple {30484#false} assume !(0 == ~E_8~0); {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 40: Hoare triple {30484#false} assume !(0 == ~E_9~0); {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 41: Hoare triple {30484#false} assume !(0 == ~E_10~0); {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 42: Hoare triple {30484#false} assume !(0 == ~E_11~0); {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 43: Hoare triple {30484#false} assume 0 == ~E_12~0;~E_12~0 := 1; {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 44: Hoare triple {30484#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 45: Hoare triple {30484#false} assume 1 == ~m_pc~0; {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 46: Hoare triple {30484#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 47: Hoare triple {30484#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30484#false} is VALID [2022-02-21 04:23:14,322 INFO L290 TraceCheckUtils]: 48: Hoare triple {30484#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 49: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp~1#1); {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 50: Hoare triple {30484#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 51: Hoare triple {30484#false} assume !(1 == ~t1_pc~0); {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 52: Hoare triple {30484#false} is_transmit1_triggered_~__retres1~1#1 := 0; {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 53: Hoare triple {30484#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 54: Hoare triple {30484#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 55: Hoare triple {30484#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {30484#false} is VALID [2022-02-21 04:23:14,323 INFO L290 TraceCheckUtils]: 56: Hoare triple {30484#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 57: Hoare triple {30484#false} assume 1 == ~t2_pc~0; {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 58: Hoare triple {30484#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 59: Hoare triple {30484#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 60: Hoare triple {30484#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 61: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___1~0#1); {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 62: Hoare triple {30484#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 63: Hoare triple {30484#false} assume !(1 == ~t3_pc~0); {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 64: Hoare triple {30484#false} is_transmit3_triggered_~__retres1~3#1 := 0; {30484#false} is VALID [2022-02-21 04:23:14,324 INFO L290 TraceCheckUtils]: 65: Hoare triple {30484#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 66: Hoare triple {30484#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 67: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___2~0#1); {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 68: Hoare triple {30484#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 69: Hoare triple {30484#false} assume 1 == ~t4_pc~0; {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 70: Hoare triple {30484#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 71: Hoare triple {30484#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 72: Hoare triple {30484#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 73: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___3~0#1); {30484#false} is VALID [2022-02-21 04:23:14,325 INFO L290 TraceCheckUtils]: 74: Hoare triple {30484#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 75: Hoare triple {30484#false} assume !(1 == ~t5_pc~0); {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 76: Hoare triple {30484#false} is_transmit5_triggered_~__retres1~5#1 := 0; {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 77: Hoare triple {30484#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 78: Hoare triple {30484#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 79: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___4~0#1); {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 80: Hoare triple {30484#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 81: Hoare triple {30484#false} assume 1 == ~t6_pc~0; {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 82: Hoare triple {30484#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30484#false} is VALID [2022-02-21 04:23:14,326 INFO L290 TraceCheckUtils]: 83: Hoare triple {30484#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 84: Hoare triple {30484#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 85: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___5~0#1); {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 86: Hoare triple {30484#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 87: Hoare triple {30484#false} assume 1 == ~t7_pc~0; {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 88: Hoare triple {30484#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 89: Hoare triple {30484#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 90: Hoare triple {30484#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 91: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___6~0#1); {30484#false} is VALID [2022-02-21 04:23:14,327 INFO L290 TraceCheckUtils]: 92: Hoare triple {30484#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 93: Hoare triple {30484#false} assume !(1 == ~t8_pc~0); {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 94: Hoare triple {30484#false} is_transmit8_triggered_~__retres1~8#1 := 0; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 95: Hoare triple {30484#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 96: Hoare triple {30484#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 97: Hoare triple {30484#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 98: Hoare triple {30484#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 99: Hoare triple {30484#false} assume 1 == ~t9_pc~0; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 100: Hoare triple {30484#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {30484#false} is VALID [2022-02-21 04:23:14,328 INFO L290 TraceCheckUtils]: 101: Hoare triple {30484#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 102: Hoare triple {30484#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 103: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___8~0#1); {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 104: Hoare triple {30484#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 105: Hoare triple {30484#false} assume !(1 == ~t10_pc~0); {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 106: Hoare triple {30484#false} is_transmit10_triggered_~__retres1~10#1 := 0; {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 107: Hoare triple {30484#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 108: Hoare triple {30484#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 109: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___9~0#1); {30484#false} is VALID [2022-02-21 04:23:14,329 INFO L290 TraceCheckUtils]: 110: Hoare triple {30484#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 111: Hoare triple {30484#false} assume 1 == ~t11_pc~0; {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 112: Hoare triple {30484#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 113: Hoare triple {30484#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 114: Hoare triple {30484#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 115: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___10~0#1); {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 116: Hoare triple {30484#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 117: Hoare triple {30484#false} assume !(1 == ~t12_pc~0); {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 118: Hoare triple {30484#false} is_transmit12_triggered_~__retres1~12#1 := 0; {30484#false} is VALID [2022-02-21 04:23:14,330 INFO L290 TraceCheckUtils]: 119: Hoare triple {30484#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 120: Hoare triple {30484#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 121: Hoare triple {30484#false} assume !(0 != activate_threads_~tmp___11~0#1); {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 122: Hoare triple {30484#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 123: Hoare triple {30484#false} assume !(1 == ~M_E~0); {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 124: Hoare triple {30484#false} assume !(1 == ~T1_E~0); {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 125: Hoare triple {30484#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 126: Hoare triple {30484#false} assume !(1 == ~T3_E~0); {30484#false} is VALID [2022-02-21 04:23:14,331 INFO L290 TraceCheckUtils]: 127: Hoare triple {30484#false} assume !(1 == ~T4_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 128: Hoare triple {30484#false} assume !(1 == ~T5_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 129: Hoare triple {30484#false} assume !(1 == ~T6_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 130: Hoare triple {30484#false} assume !(1 == ~T7_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 131: Hoare triple {30484#false} assume !(1 == ~T8_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 132: Hoare triple {30484#false} assume !(1 == ~T9_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 133: Hoare triple {30484#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 134: Hoare triple {30484#false} assume !(1 == ~T11_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 135: Hoare triple {30484#false} assume !(1 == ~T12_E~0); {30484#false} is VALID [2022-02-21 04:23:14,332 INFO L290 TraceCheckUtils]: 136: Hoare triple {30484#false} assume !(1 == ~E_M~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 137: Hoare triple {30484#false} assume !(1 == ~E_1~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 138: Hoare triple {30484#false} assume !(1 == ~E_2~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 139: Hoare triple {30484#false} assume !(1 == ~E_3~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 140: Hoare triple {30484#false} assume !(1 == ~E_4~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 141: Hoare triple {30484#false} assume 1 == ~E_5~0;~E_5~0 := 2; {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 142: Hoare triple {30484#false} assume !(1 == ~E_6~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 143: Hoare triple {30484#false} assume !(1 == ~E_7~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 144: Hoare triple {30484#false} assume !(1 == ~E_8~0); {30484#false} is VALID [2022-02-21 04:23:14,333 INFO L290 TraceCheckUtils]: 145: Hoare triple {30484#false} assume !(1 == ~E_9~0); {30484#false} is VALID [2022-02-21 04:23:14,334 INFO L290 TraceCheckUtils]: 146: Hoare triple {30484#false} assume !(1 == ~E_10~0); {30484#false} is VALID [2022-02-21 04:23:14,334 INFO L290 TraceCheckUtils]: 147: Hoare triple {30484#false} assume !(1 == ~E_11~0); {30484#false} is VALID [2022-02-21 04:23:14,334 INFO L290 TraceCheckUtils]: 148: Hoare triple {30484#false} assume !(1 == ~E_12~0); {30484#false} is VALID [2022-02-21 04:23:14,334 INFO L290 TraceCheckUtils]: 149: Hoare triple {30484#false} assume { :end_inline_reset_delta_events } true; {30484#false} is VALID [2022-02-21 04:23:14,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,334 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,335 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [746195989] [2022-02-21 04:23:14,335 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [746195989] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,335 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,335 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,335 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446773995] [2022-02-21 04:23:14,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,335 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:14,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:14,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1198130711, now seen corresponding path program 1 times [2022-02-21 04:23:14,336 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:14,336 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943031065] [2022-02-21 04:23:14,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:14,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:14,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:14,366 INFO L290 TraceCheckUtils]: 0: Hoare triple {30486#true} assume !false; {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 1: Hoare triple {30486#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 2: Hoare triple {30486#true} assume !false; {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 3: Hoare triple {30486#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 4: Hoare triple {30486#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 5: Hoare triple {30486#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 6: Hoare triple {30486#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 7: Hoare triple {30486#true} assume !(0 != eval_~tmp~0#1); {30486#true} is VALID [2022-02-21 04:23:14,367 INFO L290 TraceCheckUtils]: 8: Hoare triple {30486#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {30486#true} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 9: Hoare triple {30486#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {30486#true} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 10: Hoare triple {30486#true} assume 0 == ~M_E~0;~M_E~0 := 1; {30486#true} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 11: Hoare triple {30486#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {30486#true} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 12: Hoare triple {30486#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {30486#true} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 13: Hoare triple {30486#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {30486#true} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 14: Hoare triple {30486#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {30486#true} is VALID [2022-02-21 04:23:14,368 INFO L290 TraceCheckUtils]: 15: Hoare triple {30486#true} assume !(0 == ~T5_E~0); {30486#true} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 16: Hoare triple {30486#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 17: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 18: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,369 INFO L290 TraceCheckUtils]: 19: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,370 INFO L290 TraceCheckUtils]: 20: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,370 INFO L290 TraceCheckUtils]: 21: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,370 INFO L290 TraceCheckUtils]: 22: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,371 INFO L290 TraceCheckUtils]: 23: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,371 INFO L290 TraceCheckUtils]: 24: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,371 INFO L290 TraceCheckUtils]: 25: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,371 INFO L290 TraceCheckUtils]: 26: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,372 INFO L290 TraceCheckUtils]: 27: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,372 INFO L290 TraceCheckUtils]: 28: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,372 INFO L290 TraceCheckUtils]: 29: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,372 INFO L290 TraceCheckUtils]: 30: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,373 INFO L290 TraceCheckUtils]: 31: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,373 INFO L290 TraceCheckUtils]: 32: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,373 INFO L290 TraceCheckUtils]: 33: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,374 INFO L290 TraceCheckUtils]: 34: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,374 INFO L290 TraceCheckUtils]: 35: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,374 INFO L290 TraceCheckUtils]: 36: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,374 INFO L290 TraceCheckUtils]: 37: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 38: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 39: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,375 INFO L290 TraceCheckUtils]: 40: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 41: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 42: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 43: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,376 INFO L290 TraceCheckUtils]: 44: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 45: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 46: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 47: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,377 INFO L290 TraceCheckUtils]: 48: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 49: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 50: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,378 INFO L290 TraceCheckUtils]: 51: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 52: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 53: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 54: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,379 INFO L290 TraceCheckUtils]: 55: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,380 INFO L290 TraceCheckUtils]: 56: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,380 INFO L290 TraceCheckUtils]: 57: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,380 INFO L290 TraceCheckUtils]: 58: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,381 INFO L290 TraceCheckUtils]: 59: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,381 INFO L290 TraceCheckUtils]: 60: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,381 INFO L290 TraceCheckUtils]: 61: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,381 INFO L290 TraceCheckUtils]: 62: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,382 INFO L290 TraceCheckUtils]: 63: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,382 INFO L290 TraceCheckUtils]: 64: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,382 INFO L290 TraceCheckUtils]: 65: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,382 INFO L290 TraceCheckUtils]: 66: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,383 INFO L290 TraceCheckUtils]: 67: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,383 INFO L290 TraceCheckUtils]: 68: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,383 INFO L290 TraceCheckUtils]: 69: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,384 INFO L290 TraceCheckUtils]: 70: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,384 INFO L290 TraceCheckUtils]: 71: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,384 INFO L290 TraceCheckUtils]: 72: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,384 INFO L290 TraceCheckUtils]: 73: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 74: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 75: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,385 INFO L290 TraceCheckUtils]: 76: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 77: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 78: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 79: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,386 INFO L290 TraceCheckUtils]: 80: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 81: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 82: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 83: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,387 INFO L290 TraceCheckUtils]: 84: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 85: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 86: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,388 INFO L290 TraceCheckUtils]: 87: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 88: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 89: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 90: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,389 INFO L290 TraceCheckUtils]: 91: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,390 INFO L290 TraceCheckUtils]: 92: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,390 INFO L290 TraceCheckUtils]: 93: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,390 INFO L290 TraceCheckUtils]: 94: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 95: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 96: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 97: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,391 INFO L290 TraceCheckUtils]: 98: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 99: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 100: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 101: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,392 INFO L290 TraceCheckUtils]: 102: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 103: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t11_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 104: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,393 INFO L290 TraceCheckUtils]: 105: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 106: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 107: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 108: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,394 INFO L290 TraceCheckUtils]: 109: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t12_pc~0); {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,395 INFO L290 TraceCheckUtils]: 110: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,395 INFO L290 TraceCheckUtils]: 111: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,395 INFO L290 TraceCheckUtils]: 112: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 113: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 114: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 115: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,396 INFO L290 TraceCheckUtils]: 116: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 117: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 118: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 119: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,397 INFO L290 TraceCheckUtils]: 120: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {30488#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 121: Hoare triple {30488#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {30487#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 122: Hoare triple {30487#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 123: Hoare triple {30487#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 124: Hoare triple {30487#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 125: Hoare triple {30487#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 126: Hoare triple {30487#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,398 INFO L290 TraceCheckUtils]: 127: Hoare triple {30487#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 128: Hoare triple {30487#false} assume 1 == ~E_M~0;~E_M~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 129: Hoare triple {30487#false} assume !(1 == ~E_1~0); {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 130: Hoare triple {30487#false} assume 1 == ~E_2~0;~E_2~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 131: Hoare triple {30487#false} assume 1 == ~E_3~0;~E_3~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 132: Hoare triple {30487#false} assume 1 == ~E_4~0;~E_4~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 133: Hoare triple {30487#false} assume 1 == ~E_5~0;~E_5~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 134: Hoare triple {30487#false} assume 1 == ~E_6~0;~E_6~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 135: Hoare triple {30487#false} assume 1 == ~E_7~0;~E_7~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,399 INFO L290 TraceCheckUtils]: 136: Hoare triple {30487#false} assume 1 == ~E_8~0;~E_8~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 137: Hoare triple {30487#false} assume !(1 == ~E_9~0); {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 138: Hoare triple {30487#false} assume 1 == ~E_10~0;~E_10~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 139: Hoare triple {30487#false} assume 1 == ~E_11~0;~E_11~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 140: Hoare triple {30487#false} assume 1 == ~E_12~0;~E_12~0 := 2; {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 141: Hoare triple {30487#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 142: Hoare triple {30487#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 143: Hoare triple {30487#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {30487#false} is VALID [2022-02-21 04:23:14,400 INFO L290 TraceCheckUtils]: 144: Hoare triple {30487#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 145: Hoare triple {30487#false} assume !(0 == start_simulation_~tmp~3#1); {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 146: Hoare triple {30487#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 147: Hoare triple {30487#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 148: Hoare triple {30487#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 149: Hoare triple {30487#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 150: Hoare triple {30487#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 151: Hoare triple {30487#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 152: Hoare triple {30487#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {30487#false} is VALID [2022-02-21 04:23:14,401 INFO L290 TraceCheckUtils]: 153: Hoare triple {30487#false} assume !(0 != start_simulation_~tmp___0~1#1); {30487#false} is VALID [2022-02-21 04:23:14,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:14,402 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:14,402 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943031065] [2022-02-21 04:23:14,402 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1943031065] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:14,402 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:14,402 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:14,403 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012891792] [2022-02-21 04:23:14,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:14,403 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:14,403 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:14,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:14,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:14,404 INFO L87 Difference]: Start difference. First operand 1790 states and 2652 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,611 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2022-02-21 04:23:15,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:15,612 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,701 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:15,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2022-02-21 04:23:15,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:15,839 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2651 transitions. [2022-02-21 04:23:15,839 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:15,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:15,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2651 transitions. [2022-02-21 04:23:15,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:15,842 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-02-21 04:23:15,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2651 transitions. [2022-02-21 04:23:15,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:15,859 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:15,861 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2651 transitions. Second operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,863 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2651 transitions. Second operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,865 INFO L87 Difference]: Start difference. First operand 1790 states and 2651 transitions. Second operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:15,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:15,931 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2022-02-21 04:23:15,931 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2651 transitions. [2022-02-21 04:23:15,933 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:15,933 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:15,936 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2651 transitions. [2022-02-21 04:23:15,937 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2651 transitions. [2022-02-21 04:23:16,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:16,004 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2022-02-21 04:23:16,004 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2651 transitions. [2022-02-21 04:23:16,006 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:16,006 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:16,006 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:16,006 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:16,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4810055865921787) internal successors, (2651), 1789 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:16,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2651 transitions. [2022-02-21 04:23:16,075 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-02-21 04:23:16,075 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2651 transitions. [2022-02-21 04:23:16,075 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:23:16,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2651 transitions. [2022-02-21 04:23:16,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:16,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:16,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:16,080 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,080 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:16,080 INFO L791 eck$LassoCheckResult]: Stem: 33123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32547#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32517#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32518#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 33779#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32826#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32279#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32280#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33551#L873-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 33690#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 34056#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 34057#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33036#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33037#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33577#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33497#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33498#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33650#L1206 assume !(0 == ~M_E~0); 33015#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33016#L1211-1 assume !(0 == ~T2_E~0); 33909#L1216-1 assume !(0 == ~T3_E~0); 32808#L1221-1 assume !(0 == ~T4_E~0); 32809#L1226-1 assume !(0 == ~T5_E~0); 32471#L1231-1 assume !(0 == ~T6_E~0); 32472#L1236-1 assume !(0 == ~T7_E~0); 33940#L1241-1 assume !(0 == ~T8_E~0); 32870#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32871#L1251-1 assume !(0 == ~T10_E~0); 33091#L1256-1 assume !(0 == ~T11_E~0); 32291#L1261-1 assume !(0 == ~T12_E~0); 32292#L1266-1 assume !(0 == ~E_M~0); 34043#L1271-1 assume !(0 == ~E_1~0); 33678#L1276-1 assume !(0 == ~E_2~0); 33679#L1281-1 assume !(0 == ~E_3~0); 33604#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 32712#L1291-1 assume !(0 == ~E_5~0); 32713#L1296-1 assume !(0 == ~E_6~0); 33419#L1301-1 assume !(0 == ~E_7~0); 33420#L1306-1 assume !(0 == ~E_8~0); 33852#L1311-1 assume !(0 == ~E_9~0); 32673#L1316-1 assume !(0 == ~E_10~0); 32674#L1321-1 assume !(0 == ~E_11~0); 33436#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32537#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32538#L598 assume 1 == ~m_pc~0; 32597#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32598#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33922#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34014#L1497 assume !(0 != activate_threads_~tmp~1#1); 34015#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33971#L617 assume !(1 == ~t1_pc~0); 32893#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32894#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32753#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32754#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33514#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33515#L636 assume 1 == ~t2_pc~0; 32862#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32863#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32693#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32694#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 33550#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33213#L655 assume !(1 == ~t3_pc~0); 33214#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33927#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32567#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32568#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 34044#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34045#L674 assume 1 == ~t4_pc~0; 32387#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32388#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33685#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32695#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 32696#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33210#L693 assume !(1 == ~t5_pc~0); 33373#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33017#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33018#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33854#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 33103#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33040#L712 assume 1 == ~t6_pc~0; 33041#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33468#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33469#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33755#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 33566#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33564#L731 assume 1 == ~t7_pc~0; 32541#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32542#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32736#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33673#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 33792#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32651#L750 assume !(1 == ~t8_pc~0); 32322#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32321#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32837#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33867#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32974#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32975#L769 assume 1 == ~t9_pc~0; 33510#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32495#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32496#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33279#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 33731#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33812#L788 assume !(1 == ~t10_pc~0); 33387#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33388#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33619#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33620#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 32647#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32648#L807 assume 1 == ~t11_pc~0; 33821#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33399#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33552#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33963#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 34068#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33911#L826 assume !(1 == ~t12_pc~0); 33043#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33044#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33572#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34003#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 33203#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33112#L1344 assume !(1 == ~M_E~0); 33113#L1344-2 assume !(1 == ~T1_E~0); 33254#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33426#L1354-1 assume !(1 == ~T3_E~0); 33427#L1359-1 assume !(1 == ~T4_E~0); 33801#L1364-1 assume !(1 == ~T5_E~0); 32755#L1369-1 assume !(1 == ~T6_E~0); 32756#L1374-1 assume !(1 == ~T7_E~0); 33432#L1379-1 assume !(1 == ~T8_E~0); 33433#L1384-1 assume !(1 == ~T9_E~0); 33496#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33942#L1394-1 assume !(1 == ~T11_E~0); 33943#L1399-1 assume !(1 == ~T12_E~0); 34022#L1404-1 assume !(1 == ~E_M~0); 32874#L1409-1 assume !(1 == ~E_1~0); 32875#L1414-1 assume !(1 == ~E_2~0); 33712#L1419-1 assume !(1 == ~E_3~0); 32508#L1424-1 assume !(1 == ~E_4~0); 32509#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33443#L1434-1 assume !(1 == ~E_6~0); 33961#L1439-1 assume !(1 == ~E_7~0); 32563#L1444-1 assume !(1 == ~E_8~0); 32564#L1449-1 assume !(1 == ~E_9~0); 32979#L1454-1 assume !(1 == ~E_10~0); 32980#L1459-1 assume !(1 == ~E_11~0); 33530#L1464-1 assume !(1 == ~E_12~0); 33531#L1469-1 assume { :end_inline_reset_delta_events } true; 33578#L1815-2 [2022-02-21 04:23:16,080 INFO L793 eck$LassoCheckResult]: Loop: 33578#L1815-2 assume !false; 33732#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33401#L1181 assume !false; 33472#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33424#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32282#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33011#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33562#L1008 assume !(0 != eval_~tmp~0#1); 33563#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32501#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32502#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34062#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33529#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32635#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32636#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33226#L1226-3 assume !(0 == ~T5_E~0); 32699#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32700#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33012#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33999#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33902#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33638#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32657#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32658#L1266-3 assume !(0 == ~E_M~0); 32697#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32698#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33170#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33171#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33708#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33709#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34051#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34019#L1306-3 assume !(0 == ~E_8~0); 33295#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32581#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32582#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32659#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33394#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33719#L598-42 assume !(1 == ~m_pc~0); 33720#L598-44 is_master_triggered_~__retres1~0#1 := 0; 33834#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32737#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32738#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 34020#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33450#L617-42 assume 1 == ~t1_pc~0; 33222#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33087#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33088#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33502#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32802#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32803#L636-42 assume !(1 == ~t2_pc~0); 33266#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33267#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33617#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33618#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33797#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33659#L655-42 assume !(1 == ~t3_pc~0); 33239#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 33240#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32872#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32873#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33926#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33871#L674-42 assume 1 == ~t4_pc~0; 33872#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33567#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32456#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32457#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33371#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33372#L693-42 assume 1 == ~t5_pc~0; 33627#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33628#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33688#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33683#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33684#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32986#L712-42 assume !(1 == ~t6_pc~0); 32987#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33313#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33521#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33522#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33095#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33096#L731-42 assume !(1 == ~t7_pc~0); 32794#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 32795#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33862#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33003#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33004#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32707#L750-42 assume 1 == ~t8_pc~0; 32708#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33282#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33705#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32600#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32601#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33370#L769-42 assume 1 == ~t9_pc~0; 33192#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33193#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33876#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33941#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 32804#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32805#L788-42 assume 1 == ~t10_pc~0; 33378#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33592#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33322#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33323#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34060#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34038#L807-42 assume !(1 == ~t11_pc~0); 32408#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 32409#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32548#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32549#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32550#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32799#L826-42 assume 1 == ~t12_pc~0; 32800#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32992#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33784#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32789#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32790#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33641#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33642#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33568#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32949#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32950#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33582#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34040#L1369-3 assume !(1 == ~T6_E~0); 33960#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32714#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32715#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32947#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32948#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33246#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33969#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33932#L1409-3 assume !(1 == ~E_1~0); 33933#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33998#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33778#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32615#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32616#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33581#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32555#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32556#L1449-3 assume !(1 == ~E_9~0); 32665#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33575#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33576#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33957#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33455#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32454#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32455#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33071#L1834 assume !(0 == start_simulation_~tmp~3#1); 33691#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33714#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33148#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33327#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 33539#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33947#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32440#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32441#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 33578#L1815-2 [2022-02-21 04:23:16,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,081 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-02-21 04:23:16,081 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,081 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497272830] [2022-02-21 04:23:16,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,102 INFO L290 TraceCheckUtils]: 0: Hoare triple {37652#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {37652#true} is VALID [2022-02-21 04:23:16,103 INFO L290 TraceCheckUtils]: 1: Hoare triple {37652#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,103 INFO L290 TraceCheckUtils]: 2: Hoare triple {37654#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,103 INFO L290 TraceCheckUtils]: 3: Hoare triple {37654#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,104 INFO L290 TraceCheckUtils]: 4: Hoare triple {37654#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,104 INFO L290 TraceCheckUtils]: 5: Hoare triple {37654#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,104 INFO L290 TraceCheckUtils]: 6: Hoare triple {37654#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,105 INFO L290 TraceCheckUtils]: 7: Hoare triple {37654#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,105 INFO L290 TraceCheckUtils]: 8: Hoare triple {37654#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {37654#(= ~t5_i~0 1)} is VALID [2022-02-21 04:23:16,105 INFO L290 TraceCheckUtils]: 9: Hoare triple {37654#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,105 INFO L290 TraceCheckUtils]: 10: Hoare triple {37653#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,105 INFO L290 TraceCheckUtils]: 11: Hoare triple {37653#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,105 INFO L290 TraceCheckUtils]: 12: Hoare triple {37653#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 13: Hoare triple {37653#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 14: Hoare triple {37653#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 15: Hoare triple {37653#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 16: Hoare triple {37653#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 17: Hoare triple {37653#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 18: Hoare triple {37653#false} assume !(0 == ~M_E~0); {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 19: Hoare triple {37653#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 20: Hoare triple {37653#false} assume !(0 == ~T2_E~0); {37653#false} is VALID [2022-02-21 04:23:16,106 INFO L290 TraceCheckUtils]: 21: Hoare triple {37653#false} assume !(0 == ~T3_E~0); {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 22: Hoare triple {37653#false} assume !(0 == ~T4_E~0); {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 23: Hoare triple {37653#false} assume !(0 == ~T5_E~0); {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 24: Hoare triple {37653#false} assume !(0 == ~T6_E~0); {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 25: Hoare triple {37653#false} assume !(0 == ~T7_E~0); {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 26: Hoare triple {37653#false} assume !(0 == ~T8_E~0); {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 27: Hoare triple {37653#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 28: Hoare triple {37653#false} assume !(0 == ~T10_E~0); {37653#false} is VALID [2022-02-21 04:23:16,107 INFO L290 TraceCheckUtils]: 29: Hoare triple {37653#false} assume !(0 == ~T11_E~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 30: Hoare triple {37653#false} assume !(0 == ~T12_E~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 31: Hoare triple {37653#false} assume !(0 == ~E_M~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 32: Hoare triple {37653#false} assume !(0 == ~E_1~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 33: Hoare triple {37653#false} assume !(0 == ~E_2~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 34: Hoare triple {37653#false} assume !(0 == ~E_3~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 35: Hoare triple {37653#false} assume 0 == ~E_4~0;~E_4~0 := 1; {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 36: Hoare triple {37653#false} assume !(0 == ~E_5~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 37: Hoare triple {37653#false} assume !(0 == ~E_6~0); {37653#false} is VALID [2022-02-21 04:23:16,108 INFO L290 TraceCheckUtils]: 38: Hoare triple {37653#false} assume !(0 == ~E_7~0); {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 39: Hoare triple {37653#false} assume !(0 == ~E_8~0); {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 40: Hoare triple {37653#false} assume !(0 == ~E_9~0); {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 41: Hoare triple {37653#false} assume !(0 == ~E_10~0); {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 42: Hoare triple {37653#false} assume !(0 == ~E_11~0); {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 43: Hoare triple {37653#false} assume 0 == ~E_12~0;~E_12~0 := 1; {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 44: Hoare triple {37653#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 45: Hoare triple {37653#false} assume 1 == ~m_pc~0; {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 46: Hoare triple {37653#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {37653#false} is VALID [2022-02-21 04:23:16,109 INFO L290 TraceCheckUtils]: 47: Hoare triple {37653#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 48: Hoare triple {37653#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 49: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp~1#1); {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 50: Hoare triple {37653#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 51: Hoare triple {37653#false} assume !(1 == ~t1_pc~0); {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 52: Hoare triple {37653#false} is_transmit1_triggered_~__retres1~1#1 := 0; {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 53: Hoare triple {37653#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 54: Hoare triple {37653#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 55: Hoare triple {37653#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37653#false} is VALID [2022-02-21 04:23:16,110 INFO L290 TraceCheckUtils]: 56: Hoare triple {37653#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 57: Hoare triple {37653#false} assume 1 == ~t2_pc~0; {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 58: Hoare triple {37653#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 59: Hoare triple {37653#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 60: Hoare triple {37653#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 61: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___1~0#1); {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 62: Hoare triple {37653#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 63: Hoare triple {37653#false} assume !(1 == ~t3_pc~0); {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 64: Hoare triple {37653#false} is_transmit3_triggered_~__retres1~3#1 := 0; {37653#false} is VALID [2022-02-21 04:23:16,111 INFO L290 TraceCheckUtils]: 65: Hoare triple {37653#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 66: Hoare triple {37653#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 67: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___2~0#1); {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 68: Hoare triple {37653#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 69: Hoare triple {37653#false} assume 1 == ~t4_pc~0; {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 70: Hoare triple {37653#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 71: Hoare triple {37653#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 72: Hoare triple {37653#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {37653#false} is VALID [2022-02-21 04:23:16,112 INFO L290 TraceCheckUtils]: 73: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___3~0#1); {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 74: Hoare triple {37653#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 75: Hoare triple {37653#false} assume !(1 == ~t5_pc~0); {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 76: Hoare triple {37653#false} is_transmit5_triggered_~__retres1~5#1 := 0; {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 77: Hoare triple {37653#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 78: Hoare triple {37653#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 79: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___4~0#1); {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 80: Hoare triple {37653#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 81: Hoare triple {37653#false} assume 1 == ~t6_pc~0; {37653#false} is VALID [2022-02-21 04:23:16,113 INFO L290 TraceCheckUtils]: 82: Hoare triple {37653#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 83: Hoare triple {37653#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 84: Hoare triple {37653#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 85: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___5~0#1); {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 86: Hoare triple {37653#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 87: Hoare triple {37653#false} assume 1 == ~t7_pc~0; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 88: Hoare triple {37653#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 89: Hoare triple {37653#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 90: Hoare triple {37653#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {37653#false} is VALID [2022-02-21 04:23:16,114 INFO L290 TraceCheckUtils]: 91: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___6~0#1); {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 92: Hoare triple {37653#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 93: Hoare triple {37653#false} assume !(1 == ~t8_pc~0); {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 94: Hoare triple {37653#false} is_transmit8_triggered_~__retres1~8#1 := 0; {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 95: Hoare triple {37653#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 96: Hoare triple {37653#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 97: Hoare triple {37653#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 98: Hoare triple {37653#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 99: Hoare triple {37653#false} assume 1 == ~t9_pc~0; {37653#false} is VALID [2022-02-21 04:23:16,115 INFO L290 TraceCheckUtils]: 100: Hoare triple {37653#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 101: Hoare triple {37653#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 102: Hoare triple {37653#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 103: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___8~0#1); {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 104: Hoare triple {37653#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 105: Hoare triple {37653#false} assume !(1 == ~t10_pc~0); {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 106: Hoare triple {37653#false} is_transmit10_triggered_~__retres1~10#1 := 0; {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 107: Hoare triple {37653#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {37653#false} is VALID [2022-02-21 04:23:16,116 INFO L290 TraceCheckUtils]: 108: Hoare triple {37653#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 109: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___9~0#1); {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 110: Hoare triple {37653#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 111: Hoare triple {37653#false} assume 1 == ~t11_pc~0; {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 112: Hoare triple {37653#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 113: Hoare triple {37653#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 114: Hoare triple {37653#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 115: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___10~0#1); {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 116: Hoare triple {37653#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {37653#false} is VALID [2022-02-21 04:23:16,117 INFO L290 TraceCheckUtils]: 117: Hoare triple {37653#false} assume !(1 == ~t12_pc~0); {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 118: Hoare triple {37653#false} is_transmit12_triggered_~__retres1~12#1 := 0; {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 119: Hoare triple {37653#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 120: Hoare triple {37653#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 121: Hoare triple {37653#false} assume !(0 != activate_threads_~tmp___11~0#1); {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 122: Hoare triple {37653#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 123: Hoare triple {37653#false} assume !(1 == ~M_E~0); {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 124: Hoare triple {37653#false} assume !(1 == ~T1_E~0); {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 125: Hoare triple {37653#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,118 INFO L290 TraceCheckUtils]: 126: Hoare triple {37653#false} assume !(1 == ~T3_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 127: Hoare triple {37653#false} assume !(1 == ~T4_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 128: Hoare triple {37653#false} assume !(1 == ~T5_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 129: Hoare triple {37653#false} assume !(1 == ~T6_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 130: Hoare triple {37653#false} assume !(1 == ~T7_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 131: Hoare triple {37653#false} assume !(1 == ~T8_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 132: Hoare triple {37653#false} assume !(1 == ~T9_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 133: Hoare triple {37653#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 134: Hoare triple {37653#false} assume !(1 == ~T11_E~0); {37653#false} is VALID [2022-02-21 04:23:16,119 INFO L290 TraceCheckUtils]: 135: Hoare triple {37653#false} assume !(1 == ~T12_E~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 136: Hoare triple {37653#false} assume !(1 == ~E_M~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 137: Hoare triple {37653#false} assume !(1 == ~E_1~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 138: Hoare triple {37653#false} assume !(1 == ~E_2~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 139: Hoare triple {37653#false} assume !(1 == ~E_3~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 140: Hoare triple {37653#false} assume !(1 == ~E_4~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 141: Hoare triple {37653#false} assume 1 == ~E_5~0;~E_5~0 := 2; {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 142: Hoare triple {37653#false} assume !(1 == ~E_6~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 143: Hoare triple {37653#false} assume !(1 == ~E_7~0); {37653#false} is VALID [2022-02-21 04:23:16,120 INFO L290 TraceCheckUtils]: 144: Hoare triple {37653#false} assume !(1 == ~E_8~0); {37653#false} is VALID [2022-02-21 04:23:16,121 INFO L290 TraceCheckUtils]: 145: Hoare triple {37653#false} assume !(1 == ~E_9~0); {37653#false} is VALID [2022-02-21 04:23:16,121 INFO L290 TraceCheckUtils]: 146: Hoare triple {37653#false} assume !(1 == ~E_10~0); {37653#false} is VALID [2022-02-21 04:23:16,121 INFO L290 TraceCheckUtils]: 147: Hoare triple {37653#false} assume !(1 == ~E_11~0); {37653#false} is VALID [2022-02-21 04:23:16,121 INFO L290 TraceCheckUtils]: 148: Hoare triple {37653#false} assume !(1 == ~E_12~0); {37653#false} is VALID [2022-02-21 04:23:16,121 INFO L290 TraceCheckUtils]: 149: Hoare triple {37653#false} assume { :end_inline_reset_delta_events } true; {37653#false} is VALID [2022-02-21 04:23:16,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,122 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,122 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497272830] [2022-02-21 04:23:16,122 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497272830] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,122 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,122 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,122 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [877907003] [2022-02-21 04:23:16,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,123 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:16,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:16,123 INFO L85 PathProgramCache]: Analyzing trace with hash 954423445, now seen corresponding path program 1 times [2022-02-21 04:23:16,123 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:16,127 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903237066] [2022-02-21 04:23:16,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:16,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:16,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:16,156 INFO L290 TraceCheckUtils]: 0: Hoare triple {37655#true} assume !false; {37655#true} is VALID [2022-02-21 04:23:16,156 INFO L290 TraceCheckUtils]: 1: Hoare triple {37655#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37655#true} is VALID [2022-02-21 04:23:16,156 INFO L290 TraceCheckUtils]: 2: Hoare triple {37655#true} assume !false; {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 3: Hoare triple {37655#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 4: Hoare triple {37655#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 5: Hoare triple {37655#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 6: Hoare triple {37655#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 7: Hoare triple {37655#true} assume !(0 != eval_~tmp~0#1); {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 8: Hoare triple {37655#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 9: Hoare triple {37655#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {37655#true} is VALID [2022-02-21 04:23:16,157 INFO L290 TraceCheckUtils]: 10: Hoare triple {37655#true} assume 0 == ~M_E~0;~M_E~0 := 1; {37655#true} is VALID [2022-02-21 04:23:16,158 INFO L290 TraceCheckUtils]: 11: Hoare triple {37655#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {37655#true} is VALID [2022-02-21 04:23:16,158 INFO L290 TraceCheckUtils]: 12: Hoare triple {37655#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {37655#true} is VALID [2022-02-21 04:23:16,158 INFO L290 TraceCheckUtils]: 13: Hoare triple {37655#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {37655#true} is VALID [2022-02-21 04:23:16,158 INFO L290 TraceCheckUtils]: 14: Hoare triple {37655#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {37655#true} is VALID [2022-02-21 04:23:16,158 INFO L290 TraceCheckUtils]: 15: Hoare triple {37655#true} assume !(0 == ~T5_E~0); {37655#true} is VALID [2022-02-21 04:23:16,158 INFO L290 TraceCheckUtils]: 16: Hoare triple {37655#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,159 INFO L290 TraceCheckUtils]: 17: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,159 INFO L290 TraceCheckUtils]: 18: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,159 INFO L290 TraceCheckUtils]: 19: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,159 INFO L290 TraceCheckUtils]: 20: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,160 INFO L290 TraceCheckUtils]: 21: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,160 INFO L290 TraceCheckUtils]: 22: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,160 INFO L290 TraceCheckUtils]: 23: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,161 INFO L290 TraceCheckUtils]: 24: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,161 INFO L290 TraceCheckUtils]: 25: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,161 INFO L290 TraceCheckUtils]: 26: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,161 INFO L290 TraceCheckUtils]: 27: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,162 INFO L290 TraceCheckUtils]: 28: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,162 INFO L290 TraceCheckUtils]: 29: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,162 INFO L290 TraceCheckUtils]: 30: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,162 INFO L290 TraceCheckUtils]: 31: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,163 INFO L290 TraceCheckUtils]: 32: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,163 INFO L290 TraceCheckUtils]: 33: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,163 INFO L290 TraceCheckUtils]: 34: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,164 INFO L290 TraceCheckUtils]: 35: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,164 INFO L290 TraceCheckUtils]: 36: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,164 INFO L290 TraceCheckUtils]: 37: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,164 INFO L290 TraceCheckUtils]: 38: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,165 INFO L290 TraceCheckUtils]: 39: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,165 INFO L290 TraceCheckUtils]: 40: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,165 INFO L290 TraceCheckUtils]: 41: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,165 INFO L290 TraceCheckUtils]: 42: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,166 INFO L290 TraceCheckUtils]: 43: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,166 INFO L290 TraceCheckUtils]: 44: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,166 INFO L290 TraceCheckUtils]: 45: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,167 INFO L290 TraceCheckUtils]: 46: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,167 INFO L290 TraceCheckUtils]: 47: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,167 INFO L290 TraceCheckUtils]: 48: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,167 INFO L290 TraceCheckUtils]: 49: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,168 INFO L290 TraceCheckUtils]: 50: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,168 INFO L290 TraceCheckUtils]: 51: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,168 INFO L290 TraceCheckUtils]: 52: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,168 INFO L290 TraceCheckUtils]: 53: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,169 INFO L290 TraceCheckUtils]: 54: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,169 INFO L290 TraceCheckUtils]: 55: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,169 INFO L290 TraceCheckUtils]: 56: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,170 INFO L290 TraceCheckUtils]: 57: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,170 INFO L290 TraceCheckUtils]: 58: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,170 INFO L290 TraceCheckUtils]: 59: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,170 INFO L290 TraceCheckUtils]: 60: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,171 INFO L290 TraceCheckUtils]: 61: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,171 INFO L290 TraceCheckUtils]: 62: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,171 INFO L290 TraceCheckUtils]: 63: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,171 INFO L290 TraceCheckUtils]: 64: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,172 INFO L290 TraceCheckUtils]: 65: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,172 INFO L290 TraceCheckUtils]: 66: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,172 INFO L290 TraceCheckUtils]: 67: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,173 INFO L290 TraceCheckUtils]: 68: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,173 INFO L290 TraceCheckUtils]: 69: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,173 INFO L290 TraceCheckUtils]: 70: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,173 INFO L290 TraceCheckUtils]: 71: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,174 INFO L290 TraceCheckUtils]: 72: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,174 INFO L290 TraceCheckUtils]: 73: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,174 INFO L290 TraceCheckUtils]: 74: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,175 INFO L290 TraceCheckUtils]: 75: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,175 INFO L290 TraceCheckUtils]: 76: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,175 INFO L290 TraceCheckUtils]: 77: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,175 INFO L290 TraceCheckUtils]: 78: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,176 INFO L290 TraceCheckUtils]: 79: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,176 INFO L290 TraceCheckUtils]: 80: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,176 INFO L290 TraceCheckUtils]: 81: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,176 INFO L290 TraceCheckUtils]: 82: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,177 INFO L290 TraceCheckUtils]: 83: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,177 INFO L290 TraceCheckUtils]: 84: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,177 INFO L290 TraceCheckUtils]: 85: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,178 INFO L290 TraceCheckUtils]: 86: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,178 INFO L290 TraceCheckUtils]: 87: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,178 INFO L290 TraceCheckUtils]: 88: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,178 INFO L290 TraceCheckUtils]: 89: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,179 INFO L290 TraceCheckUtils]: 90: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,179 INFO L290 TraceCheckUtils]: 91: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,179 INFO L290 TraceCheckUtils]: 92: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,180 INFO L290 TraceCheckUtils]: 93: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,180 INFO L290 TraceCheckUtils]: 94: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,180 INFO L290 TraceCheckUtils]: 95: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,180 INFO L290 TraceCheckUtils]: 96: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,181 INFO L290 TraceCheckUtils]: 97: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,181 INFO L290 TraceCheckUtils]: 98: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,181 INFO L290 TraceCheckUtils]: 99: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,181 INFO L290 TraceCheckUtils]: 100: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,182 INFO L290 TraceCheckUtils]: 101: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,182 INFO L290 TraceCheckUtils]: 102: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,182 INFO L290 TraceCheckUtils]: 103: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t11_pc~0); {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,183 INFO L290 TraceCheckUtils]: 104: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,183 INFO L290 TraceCheckUtils]: 105: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,183 INFO L290 TraceCheckUtils]: 106: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,183 INFO L290 TraceCheckUtils]: 107: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,184 INFO L290 TraceCheckUtils]: 108: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,184 INFO L290 TraceCheckUtils]: 109: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,184 INFO L290 TraceCheckUtils]: 110: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,185 INFO L290 TraceCheckUtils]: 111: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,185 INFO L290 TraceCheckUtils]: 112: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,185 INFO L290 TraceCheckUtils]: 113: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,185 INFO L290 TraceCheckUtils]: 114: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,186 INFO L290 TraceCheckUtils]: 115: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,186 INFO L290 TraceCheckUtils]: 116: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,186 INFO L290 TraceCheckUtils]: 117: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,186 INFO L290 TraceCheckUtils]: 118: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,187 INFO L290 TraceCheckUtils]: 119: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,187 INFO L290 TraceCheckUtils]: 120: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {37657#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:16,187 INFO L290 TraceCheckUtils]: 121: Hoare triple {37657#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {37656#false} is VALID [2022-02-21 04:23:16,187 INFO L290 TraceCheckUtils]: 122: Hoare triple {37656#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 123: Hoare triple {37656#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 124: Hoare triple {37656#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 125: Hoare triple {37656#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 126: Hoare triple {37656#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 127: Hoare triple {37656#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 128: Hoare triple {37656#false} assume 1 == ~E_M~0;~E_M~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 129: Hoare triple {37656#false} assume !(1 == ~E_1~0); {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 130: Hoare triple {37656#false} assume 1 == ~E_2~0;~E_2~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,188 INFO L290 TraceCheckUtils]: 131: Hoare triple {37656#false} assume 1 == ~E_3~0;~E_3~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 132: Hoare triple {37656#false} assume 1 == ~E_4~0;~E_4~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 133: Hoare triple {37656#false} assume 1 == ~E_5~0;~E_5~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 134: Hoare triple {37656#false} assume 1 == ~E_6~0;~E_6~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 135: Hoare triple {37656#false} assume 1 == ~E_7~0;~E_7~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 136: Hoare triple {37656#false} assume 1 == ~E_8~0;~E_8~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 137: Hoare triple {37656#false} assume !(1 == ~E_9~0); {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 138: Hoare triple {37656#false} assume 1 == ~E_10~0;~E_10~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 139: Hoare triple {37656#false} assume 1 == ~E_11~0;~E_11~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,189 INFO L290 TraceCheckUtils]: 140: Hoare triple {37656#false} assume 1 == ~E_12~0;~E_12~0 := 2; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 141: Hoare triple {37656#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 142: Hoare triple {37656#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 143: Hoare triple {37656#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 144: Hoare triple {37656#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 145: Hoare triple {37656#false} assume !(0 == start_simulation_~tmp~3#1); {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 146: Hoare triple {37656#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 147: Hoare triple {37656#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 148: Hoare triple {37656#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {37656#false} is VALID [2022-02-21 04:23:16,190 INFO L290 TraceCheckUtils]: 149: Hoare triple {37656#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {37656#false} is VALID [2022-02-21 04:23:16,191 INFO L290 TraceCheckUtils]: 150: Hoare triple {37656#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {37656#false} is VALID [2022-02-21 04:23:16,191 INFO L290 TraceCheckUtils]: 151: Hoare triple {37656#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {37656#false} is VALID [2022-02-21 04:23:16,191 INFO L290 TraceCheckUtils]: 152: Hoare triple {37656#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {37656#false} is VALID [2022-02-21 04:23:16,191 INFO L290 TraceCheckUtils]: 153: Hoare triple {37656#false} assume !(0 != start_simulation_~tmp___0~1#1); {37656#false} is VALID [2022-02-21 04:23:16,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:16,192 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:16,192 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903237066] [2022-02-21 04:23:16,192 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1903237066] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:16,192 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:16,192 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:16,192 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449300251] [2022-02-21 04:23:16,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:16,193 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:16,193 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:16,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:16,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:16,194 INFO L87 Difference]: Start difference. First operand 1790 states and 2651 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,425 INFO L93 Difference]: Finished difference Result 1790 states and 2650 transitions. [2022-02-21 04:23:17,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:17,425 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,501 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:17,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,578 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:17,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2650 transitions. [2022-02-21 04:23:17,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:17,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:17,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:17,672 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-02-21 04:23:17,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:17,687 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:17,689 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2650 transitions. Second operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,690 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2650 transitions. Second operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,692 INFO L87 Difference]: Start difference. First operand 1790 states and 2650 transitions. Second operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,756 INFO L93 Difference]: Finished difference Result 1790 states and 2650 transitions. [2022-02-21 04:23:17,757 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,759 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:17,759 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:17,761 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,762 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:17,827 INFO L93 Difference]: Finished difference Result 1790 states and 2650 transitions. [2022-02-21 04:23:17,828 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,829 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:17,830 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:17,830 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:17,830 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:17,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4804469273743017) internal successors, (2650), 1789 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:17,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2650 transitions. [2022-02-21 04:23:17,896 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-02-21 04:23:17,896 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2650 transitions. [2022-02-21 04:23:17,896 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:23:17,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2650 transitions. [2022-02-21 04:23:17,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:17,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:17,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:17,901 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:17,901 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:17,901 INFO L791 eck$LassoCheckResult]: Stem: 40292#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39716#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39686#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39687#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 40948#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39995#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39448#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39449#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40720#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40859#L878-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 41225#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 41226#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 40205#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40206#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 40746#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 40666#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40667#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40819#L1206 assume !(0 == ~M_E~0); 40184#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40185#L1211-1 assume !(0 == ~T2_E~0); 41078#L1216-1 assume !(0 == ~T3_E~0); 39977#L1221-1 assume !(0 == ~T4_E~0); 39978#L1226-1 assume !(0 == ~T5_E~0); 39640#L1231-1 assume !(0 == ~T6_E~0); 39641#L1236-1 assume !(0 == ~T7_E~0); 41109#L1241-1 assume !(0 == ~T8_E~0); 40039#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40040#L1251-1 assume !(0 == ~T10_E~0); 40260#L1256-1 assume !(0 == ~T11_E~0); 39460#L1261-1 assume !(0 == ~T12_E~0); 39461#L1266-1 assume !(0 == ~E_M~0); 41212#L1271-1 assume !(0 == ~E_1~0); 40847#L1276-1 assume !(0 == ~E_2~0); 40848#L1281-1 assume !(0 == ~E_3~0); 40773#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 39881#L1291-1 assume !(0 == ~E_5~0); 39882#L1296-1 assume !(0 == ~E_6~0); 40588#L1301-1 assume !(0 == ~E_7~0); 40589#L1306-1 assume !(0 == ~E_8~0); 41021#L1311-1 assume !(0 == ~E_9~0); 39842#L1316-1 assume !(0 == ~E_10~0); 39843#L1321-1 assume !(0 == ~E_11~0); 40605#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39706#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39707#L598 assume 1 == ~m_pc~0; 39766#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39767#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41091#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41183#L1497 assume !(0 != activate_threads_~tmp~1#1); 41184#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41140#L617 assume !(1 == ~t1_pc~0); 40062#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40063#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39922#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39923#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40683#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40684#L636 assume 1 == ~t2_pc~0; 40031#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40032#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39862#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39863#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 40719#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40382#L655 assume !(1 == ~t3_pc~0); 40383#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41096#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39736#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39737#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 41213#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41214#L674 assume 1 == ~t4_pc~0; 39556#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39557#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40854#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39864#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 39865#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40379#L693 assume !(1 == ~t5_pc~0); 40542#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40186#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40187#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41023#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 40272#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40209#L712 assume 1 == ~t6_pc~0; 40210#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40637#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40638#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40924#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 40735#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40733#L731 assume 1 == ~t7_pc~0; 39710#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39711#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39905#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40842#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 40961#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39820#L750 assume !(1 == ~t8_pc~0); 39491#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39490#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40006#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41036#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40143#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40144#L769 assume 1 == ~t9_pc~0; 40679#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39664#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39665#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40448#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 40900#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40981#L788 assume !(1 == ~t10_pc~0); 40556#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40557#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40788#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40789#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 39816#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39817#L807 assume 1 == ~t11_pc~0; 40990#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40568#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40721#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41132#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 41237#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41080#L826 assume !(1 == ~t12_pc~0); 40212#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40213#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40741#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41172#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 40372#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40281#L1344 assume !(1 == ~M_E~0); 40282#L1344-2 assume !(1 == ~T1_E~0); 40423#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40595#L1354-1 assume !(1 == ~T3_E~0); 40596#L1359-1 assume !(1 == ~T4_E~0); 40970#L1364-1 assume !(1 == ~T5_E~0); 39924#L1369-1 assume !(1 == ~T6_E~0); 39925#L1374-1 assume !(1 == ~T7_E~0); 40601#L1379-1 assume !(1 == ~T8_E~0); 40602#L1384-1 assume !(1 == ~T9_E~0); 40665#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41111#L1394-1 assume !(1 == ~T11_E~0); 41112#L1399-1 assume !(1 == ~T12_E~0); 41191#L1404-1 assume !(1 == ~E_M~0); 40043#L1409-1 assume !(1 == ~E_1~0); 40044#L1414-1 assume !(1 == ~E_2~0); 40881#L1419-1 assume !(1 == ~E_3~0); 39677#L1424-1 assume !(1 == ~E_4~0); 39678#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40612#L1434-1 assume !(1 == ~E_6~0); 41130#L1439-1 assume !(1 == ~E_7~0); 39732#L1444-1 assume !(1 == ~E_8~0); 39733#L1449-1 assume !(1 == ~E_9~0); 40148#L1454-1 assume !(1 == ~E_10~0); 40149#L1459-1 assume !(1 == ~E_11~0); 40699#L1464-1 assume !(1 == ~E_12~0); 40700#L1469-1 assume { :end_inline_reset_delta_events } true; 40747#L1815-2 [2022-02-21 04:23:17,901 INFO L793 eck$LassoCheckResult]: Loop: 40747#L1815-2 assume !false; 40901#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40570#L1181 assume !false; 40641#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40593#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39451#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40180#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40731#L1008 assume !(0 != eval_~tmp~0#1); 40732#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39670#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39671#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41231#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40698#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39804#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39805#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40395#L1226-3 assume !(0 == ~T5_E~0); 39868#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39869#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40181#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41168#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41071#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40807#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39826#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39827#L1266-3 assume !(0 == ~E_M~0); 39866#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39867#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40339#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40340#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40877#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40878#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41220#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41188#L1306-3 assume !(0 == ~E_8~0); 40464#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39750#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39751#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39828#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40563#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40888#L598-42 assume !(1 == ~m_pc~0); 40889#L598-44 is_master_triggered_~__retres1~0#1 := 0; 41003#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39906#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39907#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 41189#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40619#L617-42 assume 1 == ~t1_pc~0; 40391#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40256#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40257#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40671#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39971#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39972#L636-42 assume !(1 == ~t2_pc~0); 40435#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40436#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40786#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40787#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40966#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40828#L655-42 assume !(1 == ~t3_pc~0); 40408#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 40409#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40041#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40042#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41095#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41040#L674-42 assume 1 == ~t4_pc~0; 41041#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40736#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39625#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39626#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40540#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40541#L693-42 assume 1 == ~t5_pc~0; 40796#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40797#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40857#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40852#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40853#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40155#L712-42 assume !(1 == ~t6_pc~0); 40156#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 40482#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40690#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40691#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40264#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40265#L731-42 assume 1 == ~t7_pc~0; 40128#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39964#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41031#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40172#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40173#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39876#L750-42 assume 1 == ~t8_pc~0; 39877#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40451#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40874#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39769#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39770#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40539#L769-42 assume 1 == ~t9_pc~0; 40361#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40362#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41045#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41110#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 39973#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39974#L788-42 assume 1 == ~t10_pc~0; 40547#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40761#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40491#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40492#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41229#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41207#L807-42 assume 1 == ~t11_pc~0; 40896#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39578#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39717#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39718#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39719#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39968#L826-42 assume 1 == ~t12_pc~0; 39969#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40161#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40953#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39958#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39959#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40810#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40811#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40737#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40118#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40119#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40751#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41209#L1369-3 assume !(1 == ~T6_E~0); 41129#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39883#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39884#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40116#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40117#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40415#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41138#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41101#L1409-3 assume !(1 == ~E_1~0); 41102#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41167#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40947#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39784#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39785#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40750#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39724#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39725#L1449-3 assume !(1 == ~E_9~0); 39834#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40744#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40745#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41126#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40624#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39623#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39624#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40240#L1834 assume !(0 == start_simulation_~tmp~3#1); 40860#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40883#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40317#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40496#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 40708#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41116#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39609#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39610#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 40747#L1815-2 [2022-02-21 04:23:17,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:17,902 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-02-21 04:23:17,902 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:17,902 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317706471] [2022-02-21 04:23:17,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:17,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:17,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:17,924 INFO L290 TraceCheckUtils]: 0: Hoare triple {44821#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {44821#true} is VALID [2022-02-21 04:23:17,924 INFO L290 TraceCheckUtils]: 1: Hoare triple {44821#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,925 INFO L290 TraceCheckUtils]: 2: Hoare triple {44823#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,925 INFO L290 TraceCheckUtils]: 3: Hoare triple {44823#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,925 INFO L290 TraceCheckUtils]: 4: Hoare triple {44823#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,926 INFO L290 TraceCheckUtils]: 5: Hoare triple {44823#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,926 INFO L290 TraceCheckUtils]: 6: Hoare triple {44823#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,926 INFO L290 TraceCheckUtils]: 7: Hoare triple {44823#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,927 INFO L290 TraceCheckUtils]: 8: Hoare triple {44823#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,927 INFO L290 TraceCheckUtils]: 9: Hoare triple {44823#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {44823#(= ~t6_i~0 1)} is VALID [2022-02-21 04:23:17,927 INFO L290 TraceCheckUtils]: 10: Hoare triple {44823#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,927 INFO L290 TraceCheckUtils]: 11: Hoare triple {44822#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 12: Hoare triple {44822#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 13: Hoare triple {44822#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 14: Hoare triple {44822#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 15: Hoare triple {44822#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 16: Hoare triple {44822#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 17: Hoare triple {44822#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 18: Hoare triple {44822#false} assume !(0 == ~M_E~0); {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 19: Hoare triple {44822#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {44822#false} is VALID [2022-02-21 04:23:17,928 INFO L290 TraceCheckUtils]: 20: Hoare triple {44822#false} assume !(0 == ~T2_E~0); {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 21: Hoare triple {44822#false} assume !(0 == ~T3_E~0); {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 22: Hoare triple {44822#false} assume !(0 == ~T4_E~0); {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 23: Hoare triple {44822#false} assume !(0 == ~T5_E~0); {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 24: Hoare triple {44822#false} assume !(0 == ~T6_E~0); {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 25: Hoare triple {44822#false} assume !(0 == ~T7_E~0); {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 26: Hoare triple {44822#false} assume !(0 == ~T8_E~0); {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 27: Hoare triple {44822#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {44822#false} is VALID [2022-02-21 04:23:17,929 INFO L290 TraceCheckUtils]: 28: Hoare triple {44822#false} assume !(0 == ~T10_E~0); {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 29: Hoare triple {44822#false} assume !(0 == ~T11_E~0); {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 30: Hoare triple {44822#false} assume !(0 == ~T12_E~0); {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 31: Hoare triple {44822#false} assume !(0 == ~E_M~0); {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 32: Hoare triple {44822#false} assume !(0 == ~E_1~0); {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 33: Hoare triple {44822#false} assume !(0 == ~E_2~0); {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 34: Hoare triple {44822#false} assume !(0 == ~E_3~0); {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 35: Hoare triple {44822#false} assume 0 == ~E_4~0;~E_4~0 := 1; {44822#false} is VALID [2022-02-21 04:23:17,930 INFO L290 TraceCheckUtils]: 36: Hoare triple {44822#false} assume !(0 == ~E_5~0); {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 37: Hoare triple {44822#false} assume !(0 == ~E_6~0); {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 38: Hoare triple {44822#false} assume !(0 == ~E_7~0); {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 39: Hoare triple {44822#false} assume !(0 == ~E_8~0); {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 40: Hoare triple {44822#false} assume !(0 == ~E_9~0); {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 41: Hoare triple {44822#false} assume !(0 == ~E_10~0); {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 42: Hoare triple {44822#false} assume !(0 == ~E_11~0); {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 43: Hoare triple {44822#false} assume 0 == ~E_12~0;~E_12~0 := 1; {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 44: Hoare triple {44822#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44822#false} is VALID [2022-02-21 04:23:17,931 INFO L290 TraceCheckUtils]: 45: Hoare triple {44822#false} assume 1 == ~m_pc~0; {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 46: Hoare triple {44822#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 47: Hoare triple {44822#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 48: Hoare triple {44822#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 49: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp~1#1); {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 50: Hoare triple {44822#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 51: Hoare triple {44822#false} assume !(1 == ~t1_pc~0); {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 52: Hoare triple {44822#false} is_transmit1_triggered_~__retres1~1#1 := 0; {44822#false} is VALID [2022-02-21 04:23:17,932 INFO L290 TraceCheckUtils]: 53: Hoare triple {44822#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 54: Hoare triple {44822#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 55: Hoare triple {44822#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 56: Hoare triple {44822#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 57: Hoare triple {44822#false} assume 1 == ~t2_pc~0; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 58: Hoare triple {44822#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 59: Hoare triple {44822#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 60: Hoare triple {44822#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 61: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___1~0#1); {44822#false} is VALID [2022-02-21 04:23:17,933 INFO L290 TraceCheckUtils]: 62: Hoare triple {44822#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 63: Hoare triple {44822#false} assume !(1 == ~t3_pc~0); {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 64: Hoare triple {44822#false} is_transmit3_triggered_~__retres1~3#1 := 0; {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 65: Hoare triple {44822#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 66: Hoare triple {44822#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 67: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___2~0#1); {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 68: Hoare triple {44822#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 69: Hoare triple {44822#false} assume 1 == ~t4_pc~0; {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 70: Hoare triple {44822#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {44822#false} is VALID [2022-02-21 04:23:17,934 INFO L290 TraceCheckUtils]: 71: Hoare triple {44822#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 72: Hoare triple {44822#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 73: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___3~0#1); {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 74: Hoare triple {44822#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 75: Hoare triple {44822#false} assume !(1 == ~t5_pc~0); {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 76: Hoare triple {44822#false} is_transmit5_triggered_~__retres1~5#1 := 0; {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 77: Hoare triple {44822#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 78: Hoare triple {44822#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {44822#false} is VALID [2022-02-21 04:23:17,935 INFO L290 TraceCheckUtils]: 79: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___4~0#1); {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 80: Hoare triple {44822#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 81: Hoare triple {44822#false} assume 1 == ~t6_pc~0; {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 82: Hoare triple {44822#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 83: Hoare triple {44822#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 84: Hoare triple {44822#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 85: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___5~0#1); {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 86: Hoare triple {44822#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 87: Hoare triple {44822#false} assume 1 == ~t7_pc~0; {44822#false} is VALID [2022-02-21 04:23:17,936 INFO L290 TraceCheckUtils]: 88: Hoare triple {44822#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 89: Hoare triple {44822#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 90: Hoare triple {44822#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 91: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___6~0#1); {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 92: Hoare triple {44822#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 93: Hoare triple {44822#false} assume !(1 == ~t8_pc~0); {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 94: Hoare triple {44822#false} is_transmit8_triggered_~__retres1~8#1 := 0; {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 95: Hoare triple {44822#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {44822#false} is VALID [2022-02-21 04:23:17,937 INFO L290 TraceCheckUtils]: 96: Hoare triple {44822#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 97: Hoare triple {44822#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 98: Hoare triple {44822#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 99: Hoare triple {44822#false} assume 1 == ~t9_pc~0; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 100: Hoare triple {44822#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 101: Hoare triple {44822#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 102: Hoare triple {44822#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 103: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___8~0#1); {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 104: Hoare triple {44822#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {44822#false} is VALID [2022-02-21 04:23:17,938 INFO L290 TraceCheckUtils]: 105: Hoare triple {44822#false} assume !(1 == ~t10_pc~0); {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 106: Hoare triple {44822#false} is_transmit10_triggered_~__retres1~10#1 := 0; {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 107: Hoare triple {44822#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 108: Hoare triple {44822#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 109: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___9~0#1); {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 110: Hoare triple {44822#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 111: Hoare triple {44822#false} assume 1 == ~t11_pc~0; {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 112: Hoare triple {44822#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 113: Hoare triple {44822#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {44822#false} is VALID [2022-02-21 04:23:17,939 INFO L290 TraceCheckUtils]: 114: Hoare triple {44822#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 115: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___10~0#1); {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 116: Hoare triple {44822#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 117: Hoare triple {44822#false} assume !(1 == ~t12_pc~0); {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 118: Hoare triple {44822#false} is_transmit12_triggered_~__retres1~12#1 := 0; {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 119: Hoare triple {44822#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 120: Hoare triple {44822#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 121: Hoare triple {44822#false} assume !(0 != activate_threads_~tmp___11~0#1); {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 122: Hoare triple {44822#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44822#false} is VALID [2022-02-21 04:23:17,940 INFO L290 TraceCheckUtils]: 123: Hoare triple {44822#false} assume !(1 == ~M_E~0); {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 124: Hoare triple {44822#false} assume !(1 == ~T1_E~0); {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 125: Hoare triple {44822#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 126: Hoare triple {44822#false} assume !(1 == ~T3_E~0); {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 127: Hoare triple {44822#false} assume !(1 == ~T4_E~0); {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 128: Hoare triple {44822#false} assume !(1 == ~T5_E~0); {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 129: Hoare triple {44822#false} assume !(1 == ~T6_E~0); {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 130: Hoare triple {44822#false} assume !(1 == ~T7_E~0); {44822#false} is VALID [2022-02-21 04:23:17,941 INFO L290 TraceCheckUtils]: 131: Hoare triple {44822#false} assume !(1 == ~T8_E~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 132: Hoare triple {44822#false} assume !(1 == ~T9_E~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 133: Hoare triple {44822#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 134: Hoare triple {44822#false} assume !(1 == ~T11_E~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 135: Hoare triple {44822#false} assume !(1 == ~T12_E~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 136: Hoare triple {44822#false} assume !(1 == ~E_M~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 137: Hoare triple {44822#false} assume !(1 == ~E_1~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 138: Hoare triple {44822#false} assume !(1 == ~E_2~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 139: Hoare triple {44822#false} assume !(1 == ~E_3~0); {44822#false} is VALID [2022-02-21 04:23:17,942 INFO L290 TraceCheckUtils]: 140: Hoare triple {44822#false} assume !(1 == ~E_4~0); {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 141: Hoare triple {44822#false} assume 1 == ~E_5~0;~E_5~0 := 2; {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 142: Hoare triple {44822#false} assume !(1 == ~E_6~0); {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 143: Hoare triple {44822#false} assume !(1 == ~E_7~0); {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 144: Hoare triple {44822#false} assume !(1 == ~E_8~0); {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 145: Hoare triple {44822#false} assume !(1 == ~E_9~0); {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 146: Hoare triple {44822#false} assume !(1 == ~E_10~0); {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 147: Hoare triple {44822#false} assume !(1 == ~E_11~0); {44822#false} is VALID [2022-02-21 04:23:17,943 INFO L290 TraceCheckUtils]: 148: Hoare triple {44822#false} assume !(1 == ~E_12~0); {44822#false} is VALID [2022-02-21 04:23:17,944 INFO L290 TraceCheckUtils]: 149: Hoare triple {44822#false} assume { :end_inline_reset_delta_events } true; {44822#false} is VALID [2022-02-21 04:23:17,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:17,944 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:17,944 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317706471] [2022-02-21 04:23:17,944 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317706471] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:17,944 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:17,945 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:17,945 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754760443] [2022-02-21 04:23:17,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:17,945 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:17,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:17,946 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 1 times [2022-02-21 04:23:17,946 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:17,946 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13435206] [2022-02-21 04:23:17,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:17,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:17,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:17,973 INFO L290 TraceCheckUtils]: 0: Hoare triple {44824#true} assume !false; {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 1: Hoare triple {44824#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 2: Hoare triple {44824#true} assume !false; {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 3: Hoare triple {44824#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 4: Hoare triple {44824#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 5: Hoare triple {44824#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 6: Hoare triple {44824#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 7: Hoare triple {44824#true} assume !(0 != eval_~tmp~0#1); {44824#true} is VALID [2022-02-21 04:23:17,974 INFO L290 TraceCheckUtils]: 8: Hoare triple {44824#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {44824#true} is VALID [2022-02-21 04:23:17,976 INFO L290 TraceCheckUtils]: 9: Hoare triple {44824#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {44824#true} is VALID [2022-02-21 04:23:17,976 INFO L290 TraceCheckUtils]: 10: Hoare triple {44824#true} assume 0 == ~M_E~0;~M_E~0 := 1; {44824#true} is VALID [2022-02-21 04:23:17,976 INFO L290 TraceCheckUtils]: 11: Hoare triple {44824#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {44824#true} is VALID [2022-02-21 04:23:17,976 INFO L290 TraceCheckUtils]: 12: Hoare triple {44824#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {44824#true} is VALID [2022-02-21 04:23:17,976 INFO L290 TraceCheckUtils]: 13: Hoare triple {44824#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {44824#true} is VALID [2022-02-21 04:23:17,976 INFO L290 TraceCheckUtils]: 14: Hoare triple {44824#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {44824#true} is VALID [2022-02-21 04:23:17,977 INFO L290 TraceCheckUtils]: 15: Hoare triple {44824#true} assume !(0 == ~T5_E~0); {44824#true} is VALID [2022-02-21 04:23:17,977 INFO L290 TraceCheckUtils]: 16: Hoare triple {44824#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,977 INFO L290 TraceCheckUtils]: 17: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,977 INFO L290 TraceCheckUtils]: 18: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,978 INFO L290 TraceCheckUtils]: 19: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,978 INFO L290 TraceCheckUtils]: 20: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,978 INFO L290 TraceCheckUtils]: 21: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,979 INFO L290 TraceCheckUtils]: 22: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,979 INFO L290 TraceCheckUtils]: 23: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,979 INFO L290 TraceCheckUtils]: 24: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,979 INFO L290 TraceCheckUtils]: 25: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,980 INFO L290 TraceCheckUtils]: 26: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,980 INFO L290 TraceCheckUtils]: 27: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,980 INFO L290 TraceCheckUtils]: 28: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,981 INFO L290 TraceCheckUtils]: 29: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,981 INFO L290 TraceCheckUtils]: 30: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,981 INFO L290 TraceCheckUtils]: 31: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,981 INFO L290 TraceCheckUtils]: 32: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,982 INFO L290 TraceCheckUtils]: 33: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,982 INFO L290 TraceCheckUtils]: 34: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,982 INFO L290 TraceCheckUtils]: 35: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,982 INFO L290 TraceCheckUtils]: 36: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,983 INFO L290 TraceCheckUtils]: 37: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,983 INFO L290 TraceCheckUtils]: 38: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,983 INFO L290 TraceCheckUtils]: 39: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,984 INFO L290 TraceCheckUtils]: 40: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,984 INFO L290 TraceCheckUtils]: 41: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,984 INFO L290 TraceCheckUtils]: 42: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,984 INFO L290 TraceCheckUtils]: 43: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,985 INFO L290 TraceCheckUtils]: 44: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,985 INFO L290 TraceCheckUtils]: 45: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,985 INFO L290 TraceCheckUtils]: 46: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,985 INFO L290 TraceCheckUtils]: 47: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,986 INFO L290 TraceCheckUtils]: 48: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,986 INFO L290 TraceCheckUtils]: 49: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,986 INFO L290 TraceCheckUtils]: 50: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,987 INFO L290 TraceCheckUtils]: 51: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,987 INFO L290 TraceCheckUtils]: 52: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,987 INFO L290 TraceCheckUtils]: 53: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,987 INFO L290 TraceCheckUtils]: 54: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,988 INFO L290 TraceCheckUtils]: 55: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,988 INFO L290 TraceCheckUtils]: 56: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,988 INFO L290 TraceCheckUtils]: 57: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,989 INFO L290 TraceCheckUtils]: 58: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,989 INFO L290 TraceCheckUtils]: 59: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,989 INFO L290 TraceCheckUtils]: 60: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,989 INFO L290 TraceCheckUtils]: 61: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,990 INFO L290 TraceCheckUtils]: 62: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,990 INFO L290 TraceCheckUtils]: 63: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,990 INFO L290 TraceCheckUtils]: 64: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,990 INFO L290 TraceCheckUtils]: 65: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,991 INFO L290 TraceCheckUtils]: 66: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,991 INFO L290 TraceCheckUtils]: 67: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,991 INFO L290 TraceCheckUtils]: 68: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,992 INFO L290 TraceCheckUtils]: 69: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,992 INFO L290 TraceCheckUtils]: 70: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,992 INFO L290 TraceCheckUtils]: 71: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,992 INFO L290 TraceCheckUtils]: 72: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,993 INFO L290 TraceCheckUtils]: 73: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,993 INFO L290 TraceCheckUtils]: 74: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,993 INFO L290 TraceCheckUtils]: 75: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,994 INFO L290 TraceCheckUtils]: 76: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,994 INFO L290 TraceCheckUtils]: 77: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,994 INFO L290 TraceCheckUtils]: 78: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,994 INFO L290 TraceCheckUtils]: 79: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,995 INFO L290 TraceCheckUtils]: 80: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,995 INFO L290 TraceCheckUtils]: 81: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,995 INFO L290 TraceCheckUtils]: 82: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,995 INFO L290 TraceCheckUtils]: 83: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,996 INFO L290 TraceCheckUtils]: 84: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,996 INFO L290 TraceCheckUtils]: 85: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,996 INFO L290 TraceCheckUtils]: 86: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,997 INFO L290 TraceCheckUtils]: 87: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,997 INFO L290 TraceCheckUtils]: 88: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,997 INFO L290 TraceCheckUtils]: 89: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,997 INFO L290 TraceCheckUtils]: 90: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,998 INFO L290 TraceCheckUtils]: 91: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,998 INFO L290 TraceCheckUtils]: 92: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,998 INFO L290 TraceCheckUtils]: 93: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,999 INFO L290 TraceCheckUtils]: 94: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,999 INFO L290 TraceCheckUtils]: 95: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,999 INFO L290 TraceCheckUtils]: 96: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:17,999 INFO L290 TraceCheckUtils]: 97: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,000 INFO L290 TraceCheckUtils]: 98: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,000 INFO L290 TraceCheckUtils]: 99: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,000 INFO L290 TraceCheckUtils]: 100: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,001 INFO L290 TraceCheckUtils]: 101: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,001 INFO L290 TraceCheckUtils]: 102: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,001 INFO L290 TraceCheckUtils]: 103: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,001 INFO L290 TraceCheckUtils]: 104: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,002 INFO L290 TraceCheckUtils]: 105: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,002 INFO L290 TraceCheckUtils]: 106: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,002 INFO L290 TraceCheckUtils]: 107: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,002 INFO L290 TraceCheckUtils]: 108: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,003 INFO L290 TraceCheckUtils]: 109: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,003 INFO L290 TraceCheckUtils]: 110: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,003 INFO L290 TraceCheckUtils]: 111: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,004 INFO L290 TraceCheckUtils]: 112: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,004 INFO L290 TraceCheckUtils]: 113: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,004 INFO L290 TraceCheckUtils]: 114: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,004 INFO L290 TraceCheckUtils]: 115: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,005 INFO L290 TraceCheckUtils]: 116: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,005 INFO L290 TraceCheckUtils]: 117: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,005 INFO L290 TraceCheckUtils]: 118: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,006 INFO L290 TraceCheckUtils]: 119: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,006 INFO L290 TraceCheckUtils]: 120: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {44826#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:18,006 INFO L290 TraceCheckUtils]: 121: Hoare triple {44826#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {44825#false} is VALID [2022-02-21 04:23:18,006 INFO L290 TraceCheckUtils]: 122: Hoare triple {44825#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,006 INFO L290 TraceCheckUtils]: 123: Hoare triple {44825#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,006 INFO L290 TraceCheckUtils]: 124: Hoare triple {44825#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 125: Hoare triple {44825#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 126: Hoare triple {44825#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 127: Hoare triple {44825#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 128: Hoare triple {44825#false} assume 1 == ~E_M~0;~E_M~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 129: Hoare triple {44825#false} assume !(1 == ~E_1~0); {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 130: Hoare triple {44825#false} assume 1 == ~E_2~0;~E_2~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 131: Hoare triple {44825#false} assume 1 == ~E_3~0;~E_3~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 132: Hoare triple {44825#false} assume 1 == ~E_4~0;~E_4~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,007 INFO L290 TraceCheckUtils]: 133: Hoare triple {44825#false} assume 1 == ~E_5~0;~E_5~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 134: Hoare triple {44825#false} assume 1 == ~E_6~0;~E_6~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 135: Hoare triple {44825#false} assume 1 == ~E_7~0;~E_7~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 136: Hoare triple {44825#false} assume 1 == ~E_8~0;~E_8~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 137: Hoare triple {44825#false} assume !(1 == ~E_9~0); {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 138: Hoare triple {44825#false} assume 1 == ~E_10~0;~E_10~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 139: Hoare triple {44825#false} assume 1 == ~E_11~0;~E_11~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 140: Hoare triple {44825#false} assume 1 == ~E_12~0;~E_12~0 := 2; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 141: Hoare triple {44825#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {44825#false} is VALID [2022-02-21 04:23:18,008 INFO L290 TraceCheckUtils]: 142: Hoare triple {44825#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 143: Hoare triple {44825#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 144: Hoare triple {44825#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 145: Hoare triple {44825#false} assume !(0 == start_simulation_~tmp~3#1); {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 146: Hoare triple {44825#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 147: Hoare triple {44825#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 148: Hoare triple {44825#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 149: Hoare triple {44825#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {44825#false} is VALID [2022-02-21 04:23:18,009 INFO L290 TraceCheckUtils]: 150: Hoare triple {44825#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {44825#false} is VALID [2022-02-21 04:23:18,010 INFO L290 TraceCheckUtils]: 151: Hoare triple {44825#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {44825#false} is VALID [2022-02-21 04:23:18,010 INFO L290 TraceCheckUtils]: 152: Hoare triple {44825#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {44825#false} is VALID [2022-02-21 04:23:18,010 INFO L290 TraceCheckUtils]: 153: Hoare triple {44825#false} assume !(0 != start_simulation_~tmp___0~1#1); {44825#false} is VALID [2022-02-21 04:23:18,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:18,010 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:18,010 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [13435206] [2022-02-21 04:23:18,011 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [13435206] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:18,011 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:18,011 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:18,011 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722885612] [2022-02-21 04:23:18,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:18,011 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:18,011 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:18,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:18,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:18,013 INFO L87 Difference]: Start difference. First operand 1790 states and 2650 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,313 INFO L93 Difference]: Finished difference Result 1790 states and 2649 transitions. [2022-02-21 04:23:19,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:19,313 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,400 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:19,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:19,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2649 transitions. [2022-02-21 04:23:19,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:19,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:19,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:19,557 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-02-21 04:23:19,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:19,570 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:19,572 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2649 transitions. Second operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,573 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2649 transitions. Second operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,574 INFO L87 Difference]: Start difference. First operand 1790 states and 2649 transitions. Second operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,640 INFO L93 Difference]: Finished difference Result 1790 states and 2649 transitions. [2022-02-21 04:23:19,640 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,642 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,642 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,643 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,644 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:19,709 INFO L93 Difference]: Finished difference Result 1790 states and 2649 transitions. [2022-02-21 04:23:19,709 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,711 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:19,711 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:19,711 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:19,711 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:19,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4798882681564245) internal successors, (2649), 1789 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:19,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2649 transitions. [2022-02-21 04:23:19,776 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-02-21 04:23:19,777 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2649 transitions. [2022-02-21 04:23:19,777 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:23:19,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2649 transitions. [2022-02-21 04:23:19,779 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:19,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:19,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:19,781 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:19,781 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:19,781 INFO L791 eck$LassoCheckResult]: Stem: 47463#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 46887#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46860#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46861#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 48117#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47164#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46617#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46618#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47889#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48028#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48394#L883-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 48395#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 47376#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47377#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 47915#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 47835#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 47836#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47988#L1206 assume !(0 == ~M_E~0); 47353#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47354#L1211-1 assume !(0 == ~T2_E~0); 48247#L1216-1 assume !(0 == ~T3_E~0); 47146#L1221-1 assume !(0 == ~T4_E~0); 47147#L1226-1 assume !(0 == ~T5_E~0); 46811#L1231-1 assume !(0 == ~T6_E~0); 46812#L1236-1 assume !(0 == ~T7_E~0); 48278#L1241-1 assume !(0 == ~T8_E~0); 47208#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47209#L1251-1 assume !(0 == ~T10_E~0); 47429#L1256-1 assume !(0 == ~T11_E~0); 46629#L1261-1 assume !(0 == ~T12_E~0); 46630#L1266-1 assume !(0 == ~E_M~0); 48381#L1271-1 assume !(0 == ~E_1~0); 48016#L1276-1 assume !(0 == ~E_2~0); 48017#L1281-1 assume !(0 == ~E_3~0); 47944#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47050#L1291-1 assume !(0 == ~E_5~0); 47051#L1296-1 assume !(0 == ~E_6~0); 47757#L1301-1 assume !(0 == ~E_7~0); 47758#L1306-1 assume !(0 == ~E_8~0); 48190#L1311-1 assume !(0 == ~E_9~0); 47011#L1316-1 assume !(0 == ~E_10~0); 47012#L1321-1 assume !(0 == ~E_11~0); 47774#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 46877#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46878#L598 assume 1 == ~m_pc~0; 46935#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46936#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48260#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48352#L1497 assume !(0 != activate_threads_~tmp~1#1); 48353#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48309#L617 assume !(1 == ~t1_pc~0); 47231#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47232#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47091#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47092#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47852#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47853#L636 assume 1 == ~t2_pc~0; 47200#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47201#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47031#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47032#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 47888#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47552#L655 assume !(1 == ~t3_pc~0); 47553#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48265#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46905#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46906#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 48382#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48383#L674 assume 1 == ~t4_pc~0; 46725#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46726#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48023#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47035#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 47036#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47548#L693 assume !(1 == ~t5_pc~0); 47711#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47358#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47359#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48192#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 47441#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47378#L712 assume 1 == ~t6_pc~0; 47379#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47806#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47807#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48093#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 47904#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47902#L731 assume 1 == ~t7_pc~0; 46879#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46880#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47076#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48012#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 48130#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46989#L750 assume !(1 == ~t8_pc~0); 46660#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46659#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47175#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48205#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47312#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47313#L769 assume 1 == ~t9_pc~0; 47850#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46833#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46834#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47617#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 48069#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48150#L788 assume !(1 == ~t10_pc~0); 47725#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47726#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47959#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47960#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 46987#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46988#L807 assume 1 == ~t11_pc~0; 48159#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47737#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47890#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48301#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 48406#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48249#L826 assume !(1 == ~t12_pc~0); 47383#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47384#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47910#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48341#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 47541#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47450#L1344 assume !(1 == ~M_E~0); 47451#L1344-2 assume !(1 == ~T1_E~0); 47592#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47765#L1354-1 assume !(1 == ~T3_E~0); 47766#L1359-1 assume !(1 == ~T4_E~0); 48139#L1364-1 assume !(1 == ~T5_E~0); 47093#L1369-1 assume !(1 == ~T6_E~0); 47094#L1374-1 assume !(1 == ~T7_E~0); 47772#L1379-1 assume !(1 == ~T8_E~0); 47773#L1384-1 assume !(1 == ~T9_E~0); 47834#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48280#L1394-1 assume !(1 == ~T11_E~0); 48281#L1399-1 assume !(1 == ~T12_E~0); 48360#L1404-1 assume !(1 == ~E_M~0); 47212#L1409-1 assume !(1 == ~E_1~0); 47213#L1414-1 assume !(1 == ~E_2~0); 48050#L1419-1 assume !(1 == ~E_3~0); 46846#L1424-1 assume !(1 == ~E_4~0); 46847#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 47784#L1434-1 assume !(1 == ~E_6~0); 48299#L1439-1 assume !(1 == ~E_7~0); 46901#L1444-1 assume !(1 == ~E_8~0); 46902#L1449-1 assume !(1 == ~E_9~0); 47317#L1454-1 assume !(1 == ~E_10~0); 47318#L1459-1 assume !(1 == ~E_11~0); 47868#L1464-1 assume !(1 == ~E_12~0); 47869#L1469-1 assume { :end_inline_reset_delta_events } true; 47916#L1815-2 [2022-02-21 04:23:19,781 INFO L793 eck$LassoCheckResult]: Loop: 47916#L1815-2 assume !false; 48070#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47739#L1181 assume !false; 47810#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47762#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46620#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47350#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47900#L1008 assume !(0 != eval_~tmp~0#1); 47901#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46841#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46842#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48400#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47867#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46973#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46974#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47564#L1226-3 assume !(0 == ~T5_E~0); 47037#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47038#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47349#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48337#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48240#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47976#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46995#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46996#L1266-3 assume !(0 == ~E_M~0); 47033#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47034#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47508#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47509#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48046#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48047#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48389#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48357#L1306-3 assume !(0 == ~E_8~0); 47633#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46919#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46920#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46997#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47731#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48057#L598-42 assume !(1 == ~m_pc~0); 48058#L598-44 is_master_triggered_~__retres1~0#1 := 0; 48172#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47074#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47075#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 48358#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47788#L617-42 assume 1 == ~t1_pc~0; 47560#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47425#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47426#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47840#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47140#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47141#L636-42 assume !(1 == ~t2_pc~0); 47604#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47605#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47955#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47956#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48135#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47997#L655-42 assume !(1 == ~t3_pc~0); 47577#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 47578#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47210#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47211#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48264#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48209#L674-42 assume 1 == ~t4_pc~0; 48210#L675-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47905#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46794#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46795#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47709#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47710#L693-42 assume 1 == ~t5_pc~0; 47965#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47966#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48026#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48021#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48022#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47324#L712-42 assume !(1 == ~t6_pc~0); 47325#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 47651#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47859#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47860#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47433#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47434#L731-42 assume 1 == ~t7_pc~0; 47297#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47133#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48200#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47341#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47342#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47045#L750-42 assume 1 == ~t8_pc~0; 47046#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47620#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48043#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46938#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46939#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47708#L769-42 assume 1 == ~t9_pc~0; 47530#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47531#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48214#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48279#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 47142#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47143#L788-42 assume 1 == ~t10_pc~0; 47716#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47930#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47660#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47661#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48398#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48376#L807-42 assume 1 == ~t11_pc~0; 48065#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46747#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46885#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46886#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46888#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47137#L826-42 assume 1 == ~t12_pc~0; 47138#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47330#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48122#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47127#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47128#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47979#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47980#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47906#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47287#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47288#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47920#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48378#L1369-3 assume !(1 == ~T6_E~0); 48298#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47052#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47053#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47285#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47286#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47584#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48307#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48270#L1409-3 assume !(1 == ~E_1~0); 48271#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48336#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48116#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46953#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46954#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47919#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46893#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46894#L1449-3 assume !(1 == ~E_9~0); 47003#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47913#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47914#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48295#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47793#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46792#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46793#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47409#L1834 assume !(0 == start_simulation_~tmp~3#1); 48029#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48052#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47486#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47665#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47877#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48285#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46778#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46779#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 47916#L1815-2 [2022-02-21 04:23:19,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:19,782 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-02-21 04:23:19,782 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:19,782 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695760754] [2022-02-21 04:23:19,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:19,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:19,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,802 INFO L290 TraceCheckUtils]: 0: Hoare triple {51990#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {51990#true} is VALID [2022-02-21 04:23:19,802 INFO L290 TraceCheckUtils]: 1: Hoare triple {51990#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,802 INFO L290 TraceCheckUtils]: 2: Hoare triple {51992#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,803 INFO L290 TraceCheckUtils]: 3: Hoare triple {51992#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,803 INFO L290 TraceCheckUtils]: 4: Hoare triple {51992#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,803 INFO L290 TraceCheckUtils]: 5: Hoare triple {51992#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,804 INFO L290 TraceCheckUtils]: 6: Hoare triple {51992#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,804 INFO L290 TraceCheckUtils]: 7: Hoare triple {51992#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,804 INFO L290 TraceCheckUtils]: 8: Hoare triple {51992#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,804 INFO L290 TraceCheckUtils]: 9: Hoare triple {51992#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,805 INFO L290 TraceCheckUtils]: 10: Hoare triple {51992#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {51992#(= ~t7_i~0 1)} is VALID [2022-02-21 04:23:19,805 INFO L290 TraceCheckUtils]: 11: Hoare triple {51992#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,805 INFO L290 TraceCheckUtils]: 12: Hoare triple {51991#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,805 INFO L290 TraceCheckUtils]: 13: Hoare triple {51991#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {51991#false} is VALID [2022-02-21 04:23:19,805 INFO L290 TraceCheckUtils]: 14: Hoare triple {51991#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,805 INFO L290 TraceCheckUtils]: 15: Hoare triple {51991#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,805 INFO L290 TraceCheckUtils]: 16: Hoare triple {51991#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 17: Hoare triple {51991#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 18: Hoare triple {51991#false} assume !(0 == ~M_E~0); {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 19: Hoare triple {51991#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 20: Hoare triple {51991#false} assume !(0 == ~T2_E~0); {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 21: Hoare triple {51991#false} assume !(0 == ~T3_E~0); {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 22: Hoare triple {51991#false} assume !(0 == ~T4_E~0); {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 23: Hoare triple {51991#false} assume !(0 == ~T5_E~0); {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 24: Hoare triple {51991#false} assume !(0 == ~T6_E~0); {51991#false} is VALID [2022-02-21 04:23:19,806 INFO L290 TraceCheckUtils]: 25: Hoare triple {51991#false} assume !(0 == ~T7_E~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 26: Hoare triple {51991#false} assume !(0 == ~T8_E~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 27: Hoare triple {51991#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 28: Hoare triple {51991#false} assume !(0 == ~T10_E~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 29: Hoare triple {51991#false} assume !(0 == ~T11_E~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 30: Hoare triple {51991#false} assume !(0 == ~T12_E~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 31: Hoare triple {51991#false} assume !(0 == ~E_M~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 32: Hoare triple {51991#false} assume !(0 == ~E_1~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 33: Hoare triple {51991#false} assume !(0 == ~E_2~0); {51991#false} is VALID [2022-02-21 04:23:19,807 INFO L290 TraceCheckUtils]: 34: Hoare triple {51991#false} assume !(0 == ~E_3~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 35: Hoare triple {51991#false} assume 0 == ~E_4~0;~E_4~0 := 1; {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 36: Hoare triple {51991#false} assume !(0 == ~E_5~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 37: Hoare triple {51991#false} assume !(0 == ~E_6~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 38: Hoare triple {51991#false} assume !(0 == ~E_7~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 39: Hoare triple {51991#false} assume !(0 == ~E_8~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 40: Hoare triple {51991#false} assume !(0 == ~E_9~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 41: Hoare triple {51991#false} assume !(0 == ~E_10~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 42: Hoare triple {51991#false} assume !(0 == ~E_11~0); {51991#false} is VALID [2022-02-21 04:23:19,808 INFO L290 TraceCheckUtils]: 43: Hoare triple {51991#false} assume 0 == ~E_12~0;~E_12~0 := 1; {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 44: Hoare triple {51991#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 45: Hoare triple {51991#false} assume 1 == ~m_pc~0; {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 46: Hoare triple {51991#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 47: Hoare triple {51991#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 48: Hoare triple {51991#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 49: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp~1#1); {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 50: Hoare triple {51991#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 51: Hoare triple {51991#false} assume !(1 == ~t1_pc~0); {51991#false} is VALID [2022-02-21 04:23:19,809 INFO L290 TraceCheckUtils]: 52: Hoare triple {51991#false} is_transmit1_triggered_~__retres1~1#1 := 0; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 53: Hoare triple {51991#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 54: Hoare triple {51991#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 55: Hoare triple {51991#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 56: Hoare triple {51991#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 57: Hoare triple {51991#false} assume 1 == ~t2_pc~0; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 58: Hoare triple {51991#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 59: Hoare triple {51991#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 60: Hoare triple {51991#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51991#false} is VALID [2022-02-21 04:23:19,810 INFO L290 TraceCheckUtils]: 61: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___1~0#1); {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 62: Hoare triple {51991#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 63: Hoare triple {51991#false} assume !(1 == ~t3_pc~0); {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 64: Hoare triple {51991#false} is_transmit3_triggered_~__retres1~3#1 := 0; {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 65: Hoare triple {51991#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 66: Hoare triple {51991#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 67: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___2~0#1); {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 68: Hoare triple {51991#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51991#false} is VALID [2022-02-21 04:23:19,811 INFO L290 TraceCheckUtils]: 69: Hoare triple {51991#false} assume 1 == ~t4_pc~0; {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 70: Hoare triple {51991#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 71: Hoare triple {51991#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 72: Hoare triple {51991#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 73: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___3~0#1); {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 74: Hoare triple {51991#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 75: Hoare triple {51991#false} assume !(1 == ~t5_pc~0); {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 76: Hoare triple {51991#false} is_transmit5_triggered_~__retres1~5#1 := 0; {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 77: Hoare triple {51991#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51991#false} is VALID [2022-02-21 04:23:19,812 INFO L290 TraceCheckUtils]: 78: Hoare triple {51991#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 79: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___4~0#1); {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 80: Hoare triple {51991#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 81: Hoare triple {51991#false} assume 1 == ~t6_pc~0; {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 82: Hoare triple {51991#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 83: Hoare triple {51991#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 84: Hoare triple {51991#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 85: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___5~0#1); {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 86: Hoare triple {51991#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51991#false} is VALID [2022-02-21 04:23:19,813 INFO L290 TraceCheckUtils]: 87: Hoare triple {51991#false} assume 1 == ~t7_pc~0; {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 88: Hoare triple {51991#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 89: Hoare triple {51991#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 90: Hoare triple {51991#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 91: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___6~0#1); {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 92: Hoare triple {51991#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 93: Hoare triple {51991#false} assume !(1 == ~t8_pc~0); {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 94: Hoare triple {51991#false} is_transmit8_triggered_~__retres1~8#1 := 0; {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 95: Hoare triple {51991#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51991#false} is VALID [2022-02-21 04:23:19,814 INFO L290 TraceCheckUtils]: 96: Hoare triple {51991#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 97: Hoare triple {51991#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 98: Hoare triple {51991#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 99: Hoare triple {51991#false} assume 1 == ~t9_pc~0; {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 100: Hoare triple {51991#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 101: Hoare triple {51991#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 102: Hoare triple {51991#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 103: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___8~0#1); {51991#false} is VALID [2022-02-21 04:23:19,815 INFO L290 TraceCheckUtils]: 104: Hoare triple {51991#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 105: Hoare triple {51991#false} assume !(1 == ~t10_pc~0); {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 106: Hoare triple {51991#false} is_transmit10_triggered_~__retres1~10#1 := 0; {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 107: Hoare triple {51991#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 108: Hoare triple {51991#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 109: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___9~0#1); {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 110: Hoare triple {51991#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 111: Hoare triple {51991#false} assume 1 == ~t11_pc~0; {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 112: Hoare triple {51991#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {51991#false} is VALID [2022-02-21 04:23:19,816 INFO L290 TraceCheckUtils]: 113: Hoare triple {51991#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 114: Hoare triple {51991#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 115: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___10~0#1); {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 116: Hoare triple {51991#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 117: Hoare triple {51991#false} assume !(1 == ~t12_pc~0); {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 118: Hoare triple {51991#false} is_transmit12_triggered_~__retres1~12#1 := 0; {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 119: Hoare triple {51991#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 120: Hoare triple {51991#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 121: Hoare triple {51991#false} assume !(0 != activate_threads_~tmp___11~0#1); {51991#false} is VALID [2022-02-21 04:23:19,817 INFO L290 TraceCheckUtils]: 122: Hoare triple {51991#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 123: Hoare triple {51991#false} assume !(1 == ~M_E~0); {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 124: Hoare triple {51991#false} assume !(1 == ~T1_E~0); {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 125: Hoare triple {51991#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 126: Hoare triple {51991#false} assume !(1 == ~T3_E~0); {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 127: Hoare triple {51991#false} assume !(1 == ~T4_E~0); {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 128: Hoare triple {51991#false} assume !(1 == ~T5_E~0); {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 129: Hoare triple {51991#false} assume !(1 == ~T6_E~0); {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 130: Hoare triple {51991#false} assume !(1 == ~T7_E~0); {51991#false} is VALID [2022-02-21 04:23:19,818 INFO L290 TraceCheckUtils]: 131: Hoare triple {51991#false} assume !(1 == ~T8_E~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 132: Hoare triple {51991#false} assume !(1 == ~T9_E~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 133: Hoare triple {51991#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 134: Hoare triple {51991#false} assume !(1 == ~T11_E~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 135: Hoare triple {51991#false} assume !(1 == ~T12_E~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 136: Hoare triple {51991#false} assume !(1 == ~E_M~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 137: Hoare triple {51991#false} assume !(1 == ~E_1~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 138: Hoare triple {51991#false} assume !(1 == ~E_2~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 139: Hoare triple {51991#false} assume !(1 == ~E_3~0); {51991#false} is VALID [2022-02-21 04:23:19,819 INFO L290 TraceCheckUtils]: 140: Hoare triple {51991#false} assume !(1 == ~E_4~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 141: Hoare triple {51991#false} assume 1 == ~E_5~0;~E_5~0 := 2; {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 142: Hoare triple {51991#false} assume !(1 == ~E_6~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 143: Hoare triple {51991#false} assume !(1 == ~E_7~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 144: Hoare triple {51991#false} assume !(1 == ~E_8~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 145: Hoare triple {51991#false} assume !(1 == ~E_9~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 146: Hoare triple {51991#false} assume !(1 == ~E_10~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 147: Hoare triple {51991#false} assume !(1 == ~E_11~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 148: Hoare triple {51991#false} assume !(1 == ~E_12~0); {51991#false} is VALID [2022-02-21 04:23:19,820 INFO L290 TraceCheckUtils]: 149: Hoare triple {51991#false} assume { :end_inline_reset_delta_events } true; {51991#false} is VALID [2022-02-21 04:23:19,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,821 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,821 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695760754] [2022-02-21 04:23:19,821 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695760754] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,821 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,821 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,822 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548219497] [2022-02-21 04:23:19,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,822 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:19,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:19,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1380802157, now seen corresponding path program 2 times [2022-02-21 04:23:19,823 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:19,823 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814740009] [2022-02-21 04:23:19,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:19,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:19,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:19,846 INFO L290 TraceCheckUtils]: 0: Hoare triple {51993#true} assume !false; {51993#true} is VALID [2022-02-21 04:23:19,846 INFO L290 TraceCheckUtils]: 1: Hoare triple {51993#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {51993#true} is VALID [2022-02-21 04:23:19,846 INFO L290 TraceCheckUtils]: 2: Hoare triple {51993#true} assume !false; {51993#true} is VALID [2022-02-21 04:23:19,846 INFO L290 TraceCheckUtils]: 3: Hoare triple {51993#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {51993#true} is VALID [2022-02-21 04:23:19,846 INFO L290 TraceCheckUtils]: 4: Hoare triple {51993#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 5: Hoare triple {51993#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 6: Hoare triple {51993#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 7: Hoare triple {51993#true} assume !(0 != eval_~tmp~0#1); {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 8: Hoare triple {51993#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 9: Hoare triple {51993#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 10: Hoare triple {51993#true} assume 0 == ~M_E~0;~M_E~0 := 1; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 11: Hoare triple {51993#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 12: Hoare triple {51993#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {51993#true} is VALID [2022-02-21 04:23:19,847 INFO L290 TraceCheckUtils]: 13: Hoare triple {51993#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {51993#true} is VALID [2022-02-21 04:23:19,848 INFO L290 TraceCheckUtils]: 14: Hoare triple {51993#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {51993#true} is VALID [2022-02-21 04:23:19,848 INFO L290 TraceCheckUtils]: 15: Hoare triple {51993#true} assume !(0 == ~T5_E~0); {51993#true} is VALID [2022-02-21 04:23:19,848 INFO L290 TraceCheckUtils]: 16: Hoare triple {51993#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,848 INFO L290 TraceCheckUtils]: 17: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,849 INFO L290 TraceCheckUtils]: 18: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,849 INFO L290 TraceCheckUtils]: 19: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,849 INFO L290 TraceCheckUtils]: 20: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,849 INFO L290 TraceCheckUtils]: 21: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,850 INFO L290 TraceCheckUtils]: 22: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,850 INFO L290 TraceCheckUtils]: 23: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,850 INFO L290 TraceCheckUtils]: 24: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,850 INFO L290 TraceCheckUtils]: 25: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,851 INFO L290 TraceCheckUtils]: 26: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,851 INFO L290 TraceCheckUtils]: 27: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,851 INFO L290 TraceCheckUtils]: 28: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,852 INFO L290 TraceCheckUtils]: 29: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,852 INFO L290 TraceCheckUtils]: 30: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,852 INFO L290 TraceCheckUtils]: 31: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,852 INFO L290 TraceCheckUtils]: 32: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,853 INFO L290 TraceCheckUtils]: 33: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,853 INFO L290 TraceCheckUtils]: 34: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,853 INFO L290 TraceCheckUtils]: 35: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,853 INFO L290 TraceCheckUtils]: 36: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,854 INFO L290 TraceCheckUtils]: 37: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,854 INFO L290 TraceCheckUtils]: 38: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,854 INFO L290 TraceCheckUtils]: 39: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,855 INFO L290 TraceCheckUtils]: 40: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,855 INFO L290 TraceCheckUtils]: 41: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,855 INFO L290 TraceCheckUtils]: 42: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,855 INFO L290 TraceCheckUtils]: 43: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,856 INFO L290 TraceCheckUtils]: 44: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,856 INFO L290 TraceCheckUtils]: 45: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,856 INFO L290 TraceCheckUtils]: 46: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,856 INFO L290 TraceCheckUtils]: 47: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,857 INFO L290 TraceCheckUtils]: 48: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,857 INFO L290 TraceCheckUtils]: 49: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,857 INFO L290 TraceCheckUtils]: 50: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,858 INFO L290 TraceCheckUtils]: 51: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,858 INFO L290 TraceCheckUtils]: 52: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,858 INFO L290 TraceCheckUtils]: 53: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,858 INFO L290 TraceCheckUtils]: 54: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,859 INFO L290 TraceCheckUtils]: 55: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,859 INFO L290 TraceCheckUtils]: 56: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,859 INFO L290 TraceCheckUtils]: 57: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,859 INFO L290 TraceCheckUtils]: 58: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,860 INFO L290 TraceCheckUtils]: 59: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,860 INFO L290 TraceCheckUtils]: 60: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,860 INFO L290 TraceCheckUtils]: 61: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t4_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,861 INFO L290 TraceCheckUtils]: 62: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,861 INFO L290 TraceCheckUtils]: 63: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,861 INFO L290 TraceCheckUtils]: 64: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,861 INFO L290 TraceCheckUtils]: 65: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,862 INFO L290 TraceCheckUtils]: 66: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,862 INFO L290 TraceCheckUtils]: 67: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,862 INFO L290 TraceCheckUtils]: 68: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,862 INFO L290 TraceCheckUtils]: 69: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,863 INFO L290 TraceCheckUtils]: 70: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,863 INFO L290 TraceCheckUtils]: 71: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,863 INFO L290 TraceCheckUtils]: 72: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,864 INFO L290 TraceCheckUtils]: 73: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,864 INFO L290 TraceCheckUtils]: 74: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,864 INFO L290 TraceCheckUtils]: 75: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,864 INFO L290 TraceCheckUtils]: 76: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,865 INFO L290 TraceCheckUtils]: 77: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,865 INFO L290 TraceCheckUtils]: 78: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,865 INFO L290 TraceCheckUtils]: 79: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,865 INFO L290 TraceCheckUtils]: 80: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,866 INFO L290 TraceCheckUtils]: 81: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,866 INFO L290 TraceCheckUtils]: 82: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,866 INFO L290 TraceCheckUtils]: 83: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,867 INFO L290 TraceCheckUtils]: 84: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,867 INFO L290 TraceCheckUtils]: 85: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,867 INFO L290 TraceCheckUtils]: 86: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,867 INFO L290 TraceCheckUtils]: 87: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,868 INFO L290 TraceCheckUtils]: 88: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,868 INFO L290 TraceCheckUtils]: 89: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,868 INFO L290 TraceCheckUtils]: 90: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,868 INFO L290 TraceCheckUtils]: 91: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,869 INFO L290 TraceCheckUtils]: 92: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,869 INFO L290 TraceCheckUtils]: 93: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,869 INFO L290 TraceCheckUtils]: 94: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,870 INFO L290 TraceCheckUtils]: 95: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,870 INFO L290 TraceCheckUtils]: 96: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,870 INFO L290 TraceCheckUtils]: 97: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,870 INFO L290 TraceCheckUtils]: 98: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,871 INFO L290 TraceCheckUtils]: 99: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,871 INFO L290 TraceCheckUtils]: 100: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,871 INFO L290 TraceCheckUtils]: 101: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,871 INFO L290 TraceCheckUtils]: 102: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,872 INFO L290 TraceCheckUtils]: 103: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,872 INFO L290 TraceCheckUtils]: 104: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,872 INFO L290 TraceCheckUtils]: 105: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,873 INFO L290 TraceCheckUtils]: 106: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,873 INFO L290 TraceCheckUtils]: 107: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,873 INFO L290 TraceCheckUtils]: 108: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,873 INFO L290 TraceCheckUtils]: 109: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,874 INFO L290 TraceCheckUtils]: 110: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,874 INFO L290 TraceCheckUtils]: 111: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,874 INFO L290 TraceCheckUtils]: 112: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,874 INFO L290 TraceCheckUtils]: 113: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,875 INFO L290 TraceCheckUtils]: 114: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,875 INFO L290 TraceCheckUtils]: 115: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,875 INFO L290 TraceCheckUtils]: 116: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,875 INFO L290 TraceCheckUtils]: 117: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,876 INFO L290 TraceCheckUtils]: 118: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,876 INFO L290 TraceCheckUtils]: 119: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,876 INFO L290 TraceCheckUtils]: 120: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {51995#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 121: Hoare triple {51995#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {51994#false} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 122: Hoare triple {51994#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 123: Hoare triple {51994#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 124: Hoare triple {51994#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 125: Hoare triple {51994#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 126: Hoare triple {51994#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 127: Hoare triple {51994#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,877 INFO L290 TraceCheckUtils]: 128: Hoare triple {51994#false} assume 1 == ~E_M~0;~E_M~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 129: Hoare triple {51994#false} assume !(1 == ~E_1~0); {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 130: Hoare triple {51994#false} assume 1 == ~E_2~0;~E_2~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 131: Hoare triple {51994#false} assume 1 == ~E_3~0;~E_3~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 132: Hoare triple {51994#false} assume 1 == ~E_4~0;~E_4~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 133: Hoare triple {51994#false} assume 1 == ~E_5~0;~E_5~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 134: Hoare triple {51994#false} assume 1 == ~E_6~0;~E_6~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 135: Hoare triple {51994#false} assume 1 == ~E_7~0;~E_7~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 136: Hoare triple {51994#false} assume 1 == ~E_8~0;~E_8~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,878 INFO L290 TraceCheckUtils]: 137: Hoare triple {51994#false} assume !(1 == ~E_9~0); {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 138: Hoare triple {51994#false} assume 1 == ~E_10~0;~E_10~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 139: Hoare triple {51994#false} assume 1 == ~E_11~0;~E_11~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 140: Hoare triple {51994#false} assume 1 == ~E_12~0;~E_12~0 := 2; {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 141: Hoare triple {51994#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 142: Hoare triple {51994#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 143: Hoare triple {51994#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 144: Hoare triple {51994#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 145: Hoare triple {51994#false} assume !(0 == start_simulation_~tmp~3#1); {51994#false} is VALID [2022-02-21 04:23:19,879 INFO L290 TraceCheckUtils]: 146: Hoare triple {51994#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {51994#false} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 147: Hoare triple {51994#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {51994#false} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 148: Hoare triple {51994#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {51994#false} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 149: Hoare triple {51994#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {51994#false} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 150: Hoare triple {51994#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {51994#false} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 151: Hoare triple {51994#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {51994#false} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 152: Hoare triple {51994#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {51994#false} is VALID [2022-02-21 04:23:19,880 INFO L290 TraceCheckUtils]: 153: Hoare triple {51994#false} assume !(0 != start_simulation_~tmp___0~1#1); {51994#false} is VALID [2022-02-21 04:23:19,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:19,881 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:19,881 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814740009] [2022-02-21 04:23:19,881 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814740009] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:19,881 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:19,881 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:19,881 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070422509] [2022-02-21 04:23:19,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:19,882 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:19,882 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:19,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:19,882 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:19,883 INFO L87 Difference]: Start difference. First operand 1790 states and 2649 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,063 INFO L93 Difference]: Finished difference Result 1790 states and 2648 transitions. [2022-02-21 04:23:21,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:21,063 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,158 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:21,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:21,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2648 transitions. [2022-02-21 04:23:21,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:21,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:21,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:21,320 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-02-21 04:23:21,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:21,338 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:21,340 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2648 transitions. Second operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,341 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2648 transitions. Second operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,342 INFO L87 Difference]: Start difference. First operand 1790 states and 2648 transitions. Second operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,415 INFO L93 Difference]: Finished difference Result 1790 states and 2648 transitions. [2022-02-21 04:23:21,416 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,417 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,417 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,419 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,420 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:21,491 INFO L93 Difference]: Finished difference Result 1790 states and 2648 transitions. [2022-02-21 04:23:21,491 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,493 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:21,493 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:21,493 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:21,493 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:21,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4793296089385475) internal successors, (2648), 1789 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:21,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2648 transitions. [2022-02-21 04:23:21,561 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-02-21 04:23:21,561 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2648 transitions. [2022-02-21 04:23:21,561 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:23:21,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2648 transitions. [2022-02-21 04:23:21,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:21,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:21,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:21,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:21,566 INFO L791 eck$LassoCheckResult]: Stem: 54630#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 54631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 54056#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54024#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54025#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 55286#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54333#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53786#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53787#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55058#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55197#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55563#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55564#L888-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 54545#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54546#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 55084#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 55004#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 55005#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55157#L1206 assume !(0 == ~M_E~0); 54522#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54523#L1211-1 assume !(0 == ~T2_E~0); 55416#L1216-1 assume !(0 == ~T3_E~0); 54315#L1221-1 assume !(0 == ~T4_E~0); 54316#L1226-1 assume !(0 == ~T5_E~0); 53978#L1231-1 assume !(0 == ~T6_E~0); 53979#L1236-1 assume !(0 == ~T7_E~0); 55447#L1241-1 assume !(0 == ~T8_E~0); 54377#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54378#L1251-1 assume !(0 == ~T10_E~0); 54598#L1256-1 assume !(0 == ~T11_E~0); 53798#L1261-1 assume !(0 == ~T12_E~0); 53799#L1266-1 assume !(0 == ~E_M~0); 55550#L1271-1 assume !(0 == ~E_1~0); 55185#L1276-1 assume !(0 == ~E_2~0); 55186#L1281-1 assume !(0 == ~E_3~0); 55111#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 54219#L1291-1 assume !(0 == ~E_5~0); 54220#L1296-1 assume !(0 == ~E_6~0); 54926#L1301-1 assume !(0 == ~E_7~0); 54927#L1306-1 assume !(0 == ~E_8~0); 55359#L1311-1 assume !(0 == ~E_9~0); 54180#L1316-1 assume !(0 == ~E_10~0); 54181#L1321-1 assume !(0 == ~E_11~0); 54943#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 54044#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54045#L598 assume 1 == ~m_pc~0; 54104#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 54105#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55429#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55521#L1497 assume !(0 != activate_threads_~tmp~1#1); 55522#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55478#L617 assume !(1 == ~t1_pc~0); 54400#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54401#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54260#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54261#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55021#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55022#L636 assume 1 == ~t2_pc~0; 54369#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54370#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54200#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54201#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 55057#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54720#L655 assume !(1 == ~t3_pc~0); 54721#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55434#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54074#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54075#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 55551#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55552#L674 assume 1 == ~t4_pc~0; 53894#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53895#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55192#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54202#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 54203#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54717#L693 assume !(1 == ~t5_pc~0); 54880#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54525#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54526#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55361#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 54610#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54547#L712 assume 1 == ~t6_pc~0; 54548#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54975#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54976#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55262#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 55073#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55071#L731 assume 1 == ~t7_pc~0; 54048#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54049#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54243#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55180#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 55299#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54158#L750 assume !(1 == ~t8_pc~0); 53829#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 53828#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54344#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55374#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54481#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54482#L769 assume 1 == ~t9_pc~0; 55019#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54002#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54003#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54786#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 55238#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55319#L788 assume !(1 == ~t10_pc~0); 54894#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 54895#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55127#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55128#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 54154#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54155#L807 assume 1 == ~t11_pc~0; 55328#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54906#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55059#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55470#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 55575#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 55418#L826 assume !(1 == ~t12_pc~0); 54550#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54551#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55079#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55510#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 54710#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54619#L1344 assume !(1 == ~M_E~0); 54620#L1344-2 assume !(1 == ~T1_E~0); 54761#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54934#L1354-1 assume !(1 == ~T3_E~0); 54935#L1359-1 assume !(1 == ~T4_E~0); 55308#L1364-1 assume !(1 == ~T5_E~0); 54262#L1369-1 assume !(1 == ~T6_E~0); 54263#L1374-1 assume !(1 == ~T7_E~0); 54941#L1379-1 assume !(1 == ~T8_E~0); 54942#L1384-1 assume !(1 == ~T9_E~0); 55003#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55449#L1394-1 assume !(1 == ~T11_E~0); 55450#L1399-1 assume !(1 == ~T12_E~0); 55529#L1404-1 assume !(1 == ~E_M~0); 54381#L1409-1 assume !(1 == ~E_1~0); 54382#L1414-1 assume !(1 == ~E_2~0); 55219#L1419-1 assume !(1 == ~E_3~0); 54015#L1424-1 assume !(1 == ~E_4~0); 54016#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54950#L1434-1 assume !(1 == ~E_6~0); 55468#L1439-1 assume !(1 == ~E_7~0); 54070#L1444-1 assume !(1 == ~E_8~0); 54071#L1449-1 assume !(1 == ~E_9~0); 54486#L1454-1 assume !(1 == ~E_10~0); 54487#L1459-1 assume !(1 == ~E_11~0); 55037#L1464-1 assume !(1 == ~E_12~0); 55038#L1469-1 assume { :end_inline_reset_delta_events } true; 55085#L1815-2 [2022-02-21 04:23:21,567 INFO L793 eck$LassoCheckResult]: Loop: 55085#L1815-2 assume !false; 55239#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54908#L1181 assume !false; 54979#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54931#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53789#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54518#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 55069#L1008 assume !(0 != eval_~tmp~0#1); 55070#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54010#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54011#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55569#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55036#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54142#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54143#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54733#L1226-3 assume !(0 == ~T5_E~0); 54206#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54207#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54519#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55507#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55409#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55145#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54164#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54165#L1266-3 assume !(0 == ~E_M~0); 54204#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54205#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54677#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54678#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55215#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55216#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55558#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 55526#L1306-3 assume !(0 == ~E_8~0); 54802#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54088#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 54089#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54166#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54901#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55226#L598-42 assume !(1 == ~m_pc~0); 55227#L598-44 is_master_triggered_~__retres1~0#1 := 0; 55341#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54244#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54245#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 55527#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54957#L617-42 assume 1 == ~t1_pc~0; 54730#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54594#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54595#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55009#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54309#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54310#L636-42 assume !(1 == ~t2_pc~0); 54773#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 54774#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55124#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55125#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55304#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55166#L655-42 assume !(1 == ~t3_pc~0); 54750#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 54751#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54379#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54380#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55433#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55378#L674-42 assume !(1 == ~t4_pc~0); 55152#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 55074#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53963#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53964#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54878#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54879#L693-42 assume 1 == ~t5_pc~0; 55137#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55138#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55195#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55190#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55191#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54493#L712-42 assume !(1 == ~t6_pc~0); 54494#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54821#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55028#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55029#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54602#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54603#L731-42 assume 1 == ~t7_pc~0; 54464#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54299#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55369#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54510#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54511#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54211#L750-42 assume 1 == ~t8_pc~0; 54212#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54789#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55212#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54107#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54108#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54877#L769-42 assume 1 == ~t9_pc~0; 54697#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54698#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55383#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55448#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 54311#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54312#L788-42 assume 1 == ~t10_pc~0; 54885#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55096#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54829#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54830#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55567#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55543#L807-42 assume 1 == ~t11_pc~0; 55234#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53916#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54054#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54055#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54057#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54306#L826-42 assume 1 == ~t12_pc~0; 54307#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54499#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55291#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54296#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54297#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55148#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55149#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55075#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54456#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54457#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55089#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55547#L1369-3 assume !(1 == ~T6_E~0); 55467#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54221#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54222#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54454#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54455#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54753#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55476#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55439#L1409-3 assume !(1 == ~E_1~0); 55440#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55505#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55285#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54122#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54123#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55088#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54060#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54061#L1449-3 assume !(1 == ~E_9~0); 54172#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 55081#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 55082#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 55464#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54962#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53961#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53962#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 54578#L1834 assume !(0 == start_simulation_~tmp~3#1); 55198#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 55221#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54655#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54834#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55046#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55454#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53947#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53948#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 55085#L1815-2 [2022-02-21 04:23:21,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,567 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-02-21 04:23:21,568 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,568 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227483017] [2022-02-21 04:23:21,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,586 INFO L290 TraceCheckUtils]: 0: Hoare triple {59159#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {59159#true} is VALID [2022-02-21 04:23:21,586 INFO L290 TraceCheckUtils]: 1: Hoare triple {59159#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,586 INFO L290 TraceCheckUtils]: 2: Hoare triple {59161#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,587 INFO L290 TraceCheckUtils]: 3: Hoare triple {59161#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,587 INFO L290 TraceCheckUtils]: 4: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,587 INFO L290 TraceCheckUtils]: 5: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,587 INFO L290 TraceCheckUtils]: 6: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,588 INFO L290 TraceCheckUtils]: 7: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,588 INFO L290 TraceCheckUtils]: 8: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,588 INFO L290 TraceCheckUtils]: 9: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,588 INFO L290 TraceCheckUtils]: 10: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,589 INFO L290 TraceCheckUtils]: 11: Hoare triple {59161#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {59161#(= ~t8_i~0 1)} is VALID [2022-02-21 04:23:21,589 INFO L290 TraceCheckUtils]: 12: Hoare triple {59161#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {59160#false} is VALID [2022-02-21 04:23:21,589 INFO L290 TraceCheckUtils]: 13: Hoare triple {59160#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {59160#false} is VALID [2022-02-21 04:23:21,589 INFO L290 TraceCheckUtils]: 14: Hoare triple {59160#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {59160#false} is VALID [2022-02-21 04:23:21,589 INFO L290 TraceCheckUtils]: 15: Hoare triple {59160#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {59160#false} is VALID [2022-02-21 04:23:21,589 INFO L290 TraceCheckUtils]: 16: Hoare triple {59160#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 17: Hoare triple {59160#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 18: Hoare triple {59160#false} assume !(0 == ~M_E~0); {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 19: Hoare triple {59160#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 20: Hoare triple {59160#false} assume !(0 == ~T2_E~0); {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 21: Hoare triple {59160#false} assume !(0 == ~T3_E~0); {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 22: Hoare triple {59160#false} assume !(0 == ~T4_E~0); {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 23: Hoare triple {59160#false} assume !(0 == ~T5_E~0); {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 24: Hoare triple {59160#false} assume !(0 == ~T6_E~0); {59160#false} is VALID [2022-02-21 04:23:21,590 INFO L290 TraceCheckUtils]: 25: Hoare triple {59160#false} assume !(0 == ~T7_E~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 26: Hoare triple {59160#false} assume !(0 == ~T8_E~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 27: Hoare triple {59160#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 28: Hoare triple {59160#false} assume !(0 == ~T10_E~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 29: Hoare triple {59160#false} assume !(0 == ~T11_E~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 30: Hoare triple {59160#false} assume !(0 == ~T12_E~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 31: Hoare triple {59160#false} assume !(0 == ~E_M~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 32: Hoare triple {59160#false} assume !(0 == ~E_1~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 33: Hoare triple {59160#false} assume !(0 == ~E_2~0); {59160#false} is VALID [2022-02-21 04:23:21,591 INFO L290 TraceCheckUtils]: 34: Hoare triple {59160#false} assume !(0 == ~E_3~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 35: Hoare triple {59160#false} assume 0 == ~E_4~0;~E_4~0 := 1; {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 36: Hoare triple {59160#false} assume !(0 == ~E_5~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 37: Hoare triple {59160#false} assume !(0 == ~E_6~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 38: Hoare triple {59160#false} assume !(0 == ~E_7~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 39: Hoare triple {59160#false} assume !(0 == ~E_8~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 40: Hoare triple {59160#false} assume !(0 == ~E_9~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 41: Hoare triple {59160#false} assume !(0 == ~E_10~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 42: Hoare triple {59160#false} assume !(0 == ~E_11~0); {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 43: Hoare triple {59160#false} assume 0 == ~E_12~0;~E_12~0 := 1; {59160#false} is VALID [2022-02-21 04:23:21,592 INFO L290 TraceCheckUtils]: 44: Hoare triple {59160#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 45: Hoare triple {59160#false} assume 1 == ~m_pc~0; {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 46: Hoare triple {59160#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 47: Hoare triple {59160#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 48: Hoare triple {59160#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 49: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp~1#1); {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 50: Hoare triple {59160#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 51: Hoare triple {59160#false} assume !(1 == ~t1_pc~0); {59160#false} is VALID [2022-02-21 04:23:21,593 INFO L290 TraceCheckUtils]: 52: Hoare triple {59160#false} is_transmit1_triggered_~__retres1~1#1 := 0; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 53: Hoare triple {59160#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 54: Hoare triple {59160#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 55: Hoare triple {59160#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 56: Hoare triple {59160#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 57: Hoare triple {59160#false} assume 1 == ~t2_pc~0; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 58: Hoare triple {59160#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 59: Hoare triple {59160#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 60: Hoare triple {59160#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59160#false} is VALID [2022-02-21 04:23:21,594 INFO L290 TraceCheckUtils]: 61: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___1~0#1); {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 62: Hoare triple {59160#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 63: Hoare triple {59160#false} assume !(1 == ~t3_pc~0); {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 64: Hoare triple {59160#false} is_transmit3_triggered_~__retres1~3#1 := 0; {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 65: Hoare triple {59160#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 66: Hoare triple {59160#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 67: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___2~0#1); {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 68: Hoare triple {59160#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 69: Hoare triple {59160#false} assume 1 == ~t4_pc~0; {59160#false} is VALID [2022-02-21 04:23:21,595 INFO L290 TraceCheckUtils]: 70: Hoare triple {59160#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 71: Hoare triple {59160#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 72: Hoare triple {59160#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 73: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___3~0#1); {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 74: Hoare triple {59160#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 75: Hoare triple {59160#false} assume !(1 == ~t5_pc~0); {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 76: Hoare triple {59160#false} is_transmit5_triggered_~__retres1~5#1 := 0; {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 77: Hoare triple {59160#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 78: Hoare triple {59160#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 79: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___4~0#1); {59160#false} is VALID [2022-02-21 04:23:21,596 INFO L290 TraceCheckUtils]: 80: Hoare triple {59160#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 81: Hoare triple {59160#false} assume 1 == ~t6_pc~0; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 82: Hoare triple {59160#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 83: Hoare triple {59160#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 84: Hoare triple {59160#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 85: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___5~0#1); {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 86: Hoare triple {59160#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 87: Hoare triple {59160#false} assume 1 == ~t7_pc~0; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 88: Hoare triple {59160#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {59160#false} is VALID [2022-02-21 04:23:21,597 INFO L290 TraceCheckUtils]: 89: Hoare triple {59160#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 90: Hoare triple {59160#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 91: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___6~0#1); {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 92: Hoare triple {59160#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 93: Hoare triple {59160#false} assume !(1 == ~t8_pc~0); {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 94: Hoare triple {59160#false} is_transmit8_triggered_~__retres1~8#1 := 0; {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 95: Hoare triple {59160#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 96: Hoare triple {59160#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {59160#false} is VALID [2022-02-21 04:23:21,598 INFO L290 TraceCheckUtils]: 97: Hoare triple {59160#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {59160#false} is VALID [2022-02-21 04:23:21,599 INFO L290 TraceCheckUtils]: 98: Hoare triple {59160#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {59160#false} is VALID [2022-02-21 04:23:21,599 INFO L290 TraceCheckUtils]: 99: Hoare triple {59160#false} assume 1 == ~t9_pc~0; {59160#false} is VALID [2022-02-21 04:23:21,599 INFO L290 TraceCheckUtils]: 100: Hoare triple {59160#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {59160#false} is VALID [2022-02-21 04:23:21,599 INFO L290 TraceCheckUtils]: 101: Hoare triple {59160#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {59160#false} is VALID [2022-02-21 04:23:21,599 INFO L290 TraceCheckUtils]: 102: Hoare triple {59160#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {59160#false} is VALID [2022-02-21 04:23:21,599 INFO L290 TraceCheckUtils]: 103: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___8~0#1); {59160#false} is VALID [2022-02-21 04:23:21,599 INFO L290 TraceCheckUtils]: 104: Hoare triple {59160#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 105: Hoare triple {59160#false} assume !(1 == ~t10_pc~0); {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 106: Hoare triple {59160#false} is_transmit10_triggered_~__retres1~10#1 := 0; {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 107: Hoare triple {59160#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 108: Hoare triple {59160#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 109: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___9~0#1); {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 110: Hoare triple {59160#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 111: Hoare triple {59160#false} assume 1 == ~t11_pc~0; {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 112: Hoare triple {59160#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {59160#false} is VALID [2022-02-21 04:23:21,600 INFO L290 TraceCheckUtils]: 113: Hoare triple {59160#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 114: Hoare triple {59160#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 115: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___10~0#1); {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 116: Hoare triple {59160#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 117: Hoare triple {59160#false} assume !(1 == ~t12_pc~0); {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 118: Hoare triple {59160#false} is_transmit12_triggered_~__retres1~12#1 := 0; {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 119: Hoare triple {59160#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 120: Hoare triple {59160#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 121: Hoare triple {59160#false} assume !(0 != activate_threads_~tmp___11~0#1); {59160#false} is VALID [2022-02-21 04:23:21,601 INFO L290 TraceCheckUtils]: 122: Hoare triple {59160#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 123: Hoare triple {59160#false} assume !(1 == ~M_E~0); {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 124: Hoare triple {59160#false} assume !(1 == ~T1_E~0); {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 125: Hoare triple {59160#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 126: Hoare triple {59160#false} assume !(1 == ~T3_E~0); {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 127: Hoare triple {59160#false} assume !(1 == ~T4_E~0); {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 128: Hoare triple {59160#false} assume !(1 == ~T5_E~0); {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 129: Hoare triple {59160#false} assume !(1 == ~T6_E~0); {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 130: Hoare triple {59160#false} assume !(1 == ~T7_E~0); {59160#false} is VALID [2022-02-21 04:23:21,602 INFO L290 TraceCheckUtils]: 131: Hoare triple {59160#false} assume !(1 == ~T8_E~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 132: Hoare triple {59160#false} assume !(1 == ~T9_E~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 133: Hoare triple {59160#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 134: Hoare triple {59160#false} assume !(1 == ~T11_E~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 135: Hoare triple {59160#false} assume !(1 == ~T12_E~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 136: Hoare triple {59160#false} assume !(1 == ~E_M~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 137: Hoare triple {59160#false} assume !(1 == ~E_1~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 138: Hoare triple {59160#false} assume !(1 == ~E_2~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 139: Hoare triple {59160#false} assume !(1 == ~E_3~0); {59160#false} is VALID [2022-02-21 04:23:21,603 INFO L290 TraceCheckUtils]: 140: Hoare triple {59160#false} assume !(1 == ~E_4~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 141: Hoare triple {59160#false} assume 1 == ~E_5~0;~E_5~0 := 2; {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 142: Hoare triple {59160#false} assume !(1 == ~E_6~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 143: Hoare triple {59160#false} assume !(1 == ~E_7~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 144: Hoare triple {59160#false} assume !(1 == ~E_8~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 145: Hoare triple {59160#false} assume !(1 == ~E_9~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 146: Hoare triple {59160#false} assume !(1 == ~E_10~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 147: Hoare triple {59160#false} assume !(1 == ~E_11~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 148: Hoare triple {59160#false} assume !(1 == ~E_12~0); {59160#false} is VALID [2022-02-21 04:23:21,604 INFO L290 TraceCheckUtils]: 149: Hoare triple {59160#false} assume { :end_inline_reset_delta_events } true; {59160#false} is VALID [2022-02-21 04:23:21,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,605 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,605 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227483017] [2022-02-21 04:23:21,605 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227483017] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,605 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,605 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,606 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907282660] [2022-02-21 04:23:21,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,606 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:21,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:21,606 INFO L85 PathProgramCache]: Analyzing trace with hash -263617196, now seen corresponding path program 1 times [2022-02-21 04:23:21,607 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:21,607 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956895311] [2022-02-21 04:23:21,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:21,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:21,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:21,631 INFO L290 TraceCheckUtils]: 0: Hoare triple {59162#true} assume !false; {59162#true} is VALID [2022-02-21 04:23:21,631 INFO L290 TraceCheckUtils]: 1: Hoare triple {59162#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {59162#true} is VALID [2022-02-21 04:23:21,631 INFO L290 TraceCheckUtils]: 2: Hoare triple {59162#true} assume !false; {59162#true} is VALID [2022-02-21 04:23:21,631 INFO L290 TraceCheckUtils]: 3: Hoare triple {59162#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {59162#true} is VALID [2022-02-21 04:23:21,631 INFO L290 TraceCheckUtils]: 4: Hoare triple {59162#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {59162#true} is VALID [2022-02-21 04:23:21,631 INFO L290 TraceCheckUtils]: 5: Hoare triple {59162#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 6: Hoare triple {59162#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 7: Hoare triple {59162#true} assume !(0 != eval_~tmp~0#1); {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 8: Hoare triple {59162#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 9: Hoare triple {59162#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 10: Hoare triple {59162#true} assume 0 == ~M_E~0;~M_E~0 := 1; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 11: Hoare triple {59162#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 12: Hoare triple {59162#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 13: Hoare triple {59162#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {59162#true} is VALID [2022-02-21 04:23:21,632 INFO L290 TraceCheckUtils]: 14: Hoare triple {59162#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {59162#true} is VALID [2022-02-21 04:23:21,633 INFO L290 TraceCheckUtils]: 15: Hoare triple {59162#true} assume !(0 == ~T5_E~0); {59162#true} is VALID [2022-02-21 04:23:21,633 INFO L290 TraceCheckUtils]: 16: Hoare triple {59162#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,633 INFO L290 TraceCheckUtils]: 17: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,633 INFO L290 TraceCheckUtils]: 18: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,634 INFO L290 TraceCheckUtils]: 19: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,634 INFO L290 TraceCheckUtils]: 20: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,634 INFO L290 TraceCheckUtils]: 21: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,635 INFO L290 TraceCheckUtils]: 22: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,635 INFO L290 TraceCheckUtils]: 23: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,635 INFO L290 TraceCheckUtils]: 24: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,636 INFO L290 TraceCheckUtils]: 25: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,636 INFO L290 TraceCheckUtils]: 26: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,636 INFO L290 TraceCheckUtils]: 27: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,636 INFO L290 TraceCheckUtils]: 28: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,637 INFO L290 TraceCheckUtils]: 29: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,637 INFO L290 TraceCheckUtils]: 30: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,637 INFO L290 TraceCheckUtils]: 31: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,637 INFO L290 TraceCheckUtils]: 32: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,638 INFO L290 TraceCheckUtils]: 33: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,638 INFO L290 TraceCheckUtils]: 34: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,638 INFO L290 TraceCheckUtils]: 35: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,638 INFO L290 TraceCheckUtils]: 36: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,639 INFO L290 TraceCheckUtils]: 37: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,639 INFO L290 TraceCheckUtils]: 38: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,639 INFO L290 TraceCheckUtils]: 39: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,639 INFO L290 TraceCheckUtils]: 40: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,640 INFO L290 TraceCheckUtils]: 41: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,640 INFO L290 TraceCheckUtils]: 42: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,640 INFO L290 TraceCheckUtils]: 43: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,641 INFO L290 TraceCheckUtils]: 44: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,641 INFO L290 TraceCheckUtils]: 45: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,641 INFO L290 TraceCheckUtils]: 46: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,641 INFO L290 TraceCheckUtils]: 47: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,642 INFO L290 TraceCheckUtils]: 48: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,642 INFO L290 TraceCheckUtils]: 49: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,642 INFO L290 TraceCheckUtils]: 50: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,642 INFO L290 TraceCheckUtils]: 51: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,643 INFO L290 TraceCheckUtils]: 52: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,643 INFO L290 TraceCheckUtils]: 53: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,643 INFO L290 TraceCheckUtils]: 54: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,643 INFO L290 TraceCheckUtils]: 55: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,644 INFO L290 TraceCheckUtils]: 56: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,644 INFO L290 TraceCheckUtils]: 57: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,644 INFO L290 TraceCheckUtils]: 58: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,645 INFO L290 TraceCheckUtils]: 59: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,645 INFO L290 TraceCheckUtils]: 60: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,645 INFO L290 TraceCheckUtils]: 61: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,645 INFO L290 TraceCheckUtils]: 62: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,646 INFO L290 TraceCheckUtils]: 63: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,646 INFO L290 TraceCheckUtils]: 64: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,646 INFO L290 TraceCheckUtils]: 65: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,646 INFO L290 TraceCheckUtils]: 66: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,647 INFO L290 TraceCheckUtils]: 67: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,647 INFO L290 TraceCheckUtils]: 68: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,647 INFO L290 TraceCheckUtils]: 69: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,647 INFO L290 TraceCheckUtils]: 70: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,648 INFO L290 TraceCheckUtils]: 71: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,648 INFO L290 TraceCheckUtils]: 72: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,648 INFO L290 TraceCheckUtils]: 73: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,648 INFO L290 TraceCheckUtils]: 74: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,649 INFO L290 TraceCheckUtils]: 75: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,649 INFO L290 TraceCheckUtils]: 76: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,649 INFO L290 TraceCheckUtils]: 77: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,650 INFO L290 TraceCheckUtils]: 78: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,650 INFO L290 TraceCheckUtils]: 79: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,650 INFO L290 TraceCheckUtils]: 80: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,650 INFO L290 TraceCheckUtils]: 81: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,651 INFO L290 TraceCheckUtils]: 82: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,651 INFO L290 TraceCheckUtils]: 83: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,651 INFO L290 TraceCheckUtils]: 84: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,651 INFO L290 TraceCheckUtils]: 85: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,652 INFO L290 TraceCheckUtils]: 86: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,652 INFO L290 TraceCheckUtils]: 87: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,652 INFO L290 TraceCheckUtils]: 88: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,652 INFO L290 TraceCheckUtils]: 89: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,653 INFO L290 TraceCheckUtils]: 90: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,653 INFO L290 TraceCheckUtils]: 91: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,653 INFO L290 TraceCheckUtils]: 92: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,653 INFO L290 TraceCheckUtils]: 93: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,654 INFO L290 TraceCheckUtils]: 94: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,654 INFO L290 TraceCheckUtils]: 95: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,654 INFO L290 TraceCheckUtils]: 96: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,654 INFO L290 TraceCheckUtils]: 97: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,655 INFO L290 TraceCheckUtils]: 98: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,655 INFO L290 TraceCheckUtils]: 99: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,655 INFO L290 TraceCheckUtils]: 100: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,656 INFO L290 TraceCheckUtils]: 101: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,656 INFO L290 TraceCheckUtils]: 102: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,656 INFO L290 TraceCheckUtils]: 103: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,656 INFO L290 TraceCheckUtils]: 104: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,657 INFO L290 TraceCheckUtils]: 105: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,657 INFO L290 TraceCheckUtils]: 106: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,657 INFO L290 TraceCheckUtils]: 107: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,657 INFO L290 TraceCheckUtils]: 108: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,658 INFO L290 TraceCheckUtils]: 109: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,658 INFO L290 TraceCheckUtils]: 110: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,658 INFO L290 TraceCheckUtils]: 111: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,658 INFO L290 TraceCheckUtils]: 112: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,659 INFO L290 TraceCheckUtils]: 113: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,659 INFO L290 TraceCheckUtils]: 114: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,659 INFO L290 TraceCheckUtils]: 115: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,660 INFO L290 TraceCheckUtils]: 116: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,660 INFO L290 TraceCheckUtils]: 117: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,660 INFO L290 TraceCheckUtils]: 118: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,660 INFO L290 TraceCheckUtils]: 119: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,661 INFO L290 TraceCheckUtils]: 120: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {59164#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:21,661 INFO L290 TraceCheckUtils]: 121: Hoare triple {59164#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {59163#false} is VALID [2022-02-21 04:23:21,661 INFO L290 TraceCheckUtils]: 122: Hoare triple {59163#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,661 INFO L290 TraceCheckUtils]: 123: Hoare triple {59163#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,661 INFO L290 TraceCheckUtils]: 124: Hoare triple {59163#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,661 INFO L290 TraceCheckUtils]: 125: Hoare triple {59163#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,661 INFO L290 TraceCheckUtils]: 126: Hoare triple {59163#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 127: Hoare triple {59163#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 128: Hoare triple {59163#false} assume 1 == ~E_M~0;~E_M~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 129: Hoare triple {59163#false} assume !(1 == ~E_1~0); {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 130: Hoare triple {59163#false} assume 1 == ~E_2~0;~E_2~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 131: Hoare triple {59163#false} assume 1 == ~E_3~0;~E_3~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 132: Hoare triple {59163#false} assume 1 == ~E_4~0;~E_4~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 133: Hoare triple {59163#false} assume 1 == ~E_5~0;~E_5~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 134: Hoare triple {59163#false} assume 1 == ~E_6~0;~E_6~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,662 INFO L290 TraceCheckUtils]: 135: Hoare triple {59163#false} assume 1 == ~E_7~0;~E_7~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 136: Hoare triple {59163#false} assume 1 == ~E_8~0;~E_8~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 137: Hoare triple {59163#false} assume !(1 == ~E_9~0); {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 138: Hoare triple {59163#false} assume 1 == ~E_10~0;~E_10~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 139: Hoare triple {59163#false} assume 1 == ~E_11~0;~E_11~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 140: Hoare triple {59163#false} assume 1 == ~E_12~0;~E_12~0 := 2; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 141: Hoare triple {59163#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 142: Hoare triple {59163#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 143: Hoare triple {59163#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {59163#false} is VALID [2022-02-21 04:23:21,663 INFO L290 TraceCheckUtils]: 144: Hoare triple {59163#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 145: Hoare triple {59163#false} assume !(0 == start_simulation_~tmp~3#1); {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 146: Hoare triple {59163#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 147: Hoare triple {59163#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 148: Hoare triple {59163#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 149: Hoare triple {59163#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 150: Hoare triple {59163#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 151: Hoare triple {59163#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 152: Hoare triple {59163#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {59163#false} is VALID [2022-02-21 04:23:21,664 INFO L290 TraceCheckUtils]: 153: Hoare triple {59163#false} assume !(0 != start_simulation_~tmp___0~1#1); {59163#false} is VALID [2022-02-21 04:23:21,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:21,665 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:21,665 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956895311] [2022-02-21 04:23:21,665 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956895311] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:21,665 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:21,665 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:21,666 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684118813] [2022-02-21 04:23:21,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:21,666 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:21,666 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:21,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:21,667 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:21,667 INFO L87 Difference]: Start difference. First operand 1790 states and 2648 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:22,754 INFO L93 Difference]: Finished difference Result 1790 states and 2647 transitions. [2022-02-21 04:23:22,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:22,754 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:22,852 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:22,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2647 transitions. [2022-02-21 04:23:22,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:23,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2647 transitions. [2022-02-21 04:23:23,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:23,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:23,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2647 transitions. [2022-02-21 04:23:23,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:23,042 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-02-21 04:23:23,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2647 transitions. [2022-02-21 04:23:23,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:23,083 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:23,085 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2647 transitions. Second operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,086 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2647 transitions. Second operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,087 INFO L87 Difference]: Start difference. First operand 1790 states and 2647 transitions. Second operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:23,161 INFO L93 Difference]: Finished difference Result 1790 states and 2647 transitions. [2022-02-21 04:23:23,161 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2647 transitions. [2022-02-21 04:23:23,163 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:23,163 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:23,165 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2647 transitions. [2022-02-21 04:23:23,181 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2647 transitions. [2022-02-21 04:23:23,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:23,258 INFO L93 Difference]: Finished difference Result 1790 states and 2647 transitions. [2022-02-21 04:23:23,258 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2647 transitions. [2022-02-21 04:23:23,259 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:23,260 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:23,260 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:23,260 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:23,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4787709497206705) internal successors, (2647), 1789 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:23,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2647 transitions. [2022-02-21 04:23:23,327 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-02-21 04:23:23,327 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2647 transitions. [2022-02-21 04:23:23,327 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:23:23,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2647 transitions. [2022-02-21 04:23:23,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:23,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:23,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:23,336 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:23,336 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:23,351 INFO L791 eck$LassoCheckResult]: Stem: 61799#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61800#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 61223#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61193#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61194#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 62455#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61502#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60955#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60956#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62227#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62366#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62732#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62733#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 61712#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61713#L898-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 62253#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 62173#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 62174#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62326#L1206 assume !(0 == ~M_E~0); 61691#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61692#L1211-1 assume !(0 == ~T2_E~0); 62585#L1216-1 assume !(0 == ~T3_E~0); 61484#L1221-1 assume !(0 == ~T4_E~0); 61485#L1226-1 assume !(0 == ~T5_E~0); 61147#L1231-1 assume !(0 == ~T6_E~0); 61148#L1236-1 assume !(0 == ~T7_E~0); 62616#L1241-1 assume !(0 == ~T8_E~0); 61546#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 61547#L1251-1 assume !(0 == ~T10_E~0); 61767#L1256-1 assume !(0 == ~T11_E~0); 60967#L1261-1 assume !(0 == ~T12_E~0); 60968#L1266-1 assume !(0 == ~E_M~0); 62719#L1271-1 assume !(0 == ~E_1~0); 62354#L1276-1 assume !(0 == ~E_2~0); 62355#L1281-1 assume !(0 == ~E_3~0); 62280#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 61388#L1291-1 assume !(0 == ~E_5~0); 61389#L1296-1 assume !(0 == ~E_6~0); 62095#L1301-1 assume !(0 == ~E_7~0); 62096#L1306-1 assume !(0 == ~E_8~0); 62528#L1311-1 assume !(0 == ~E_9~0); 61349#L1316-1 assume !(0 == ~E_10~0); 61350#L1321-1 assume !(0 == ~E_11~0); 62112#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61213#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61214#L598 assume 1 == ~m_pc~0; 61273#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61274#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62598#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62690#L1497 assume !(0 != activate_threads_~tmp~1#1); 62691#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62647#L617 assume !(1 == ~t1_pc~0); 61569#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61570#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61429#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61430#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62190#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62191#L636 assume 1 == ~t2_pc~0; 61538#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61539#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61369#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61370#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 62226#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61889#L655 assume !(1 == ~t3_pc~0); 61890#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62603#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61243#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61244#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 62720#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62721#L674 assume 1 == ~t4_pc~0; 61063#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61064#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62361#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61371#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 61372#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61886#L693 assume !(1 == ~t5_pc~0); 62049#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61693#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61694#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62530#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 61779#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61716#L712 assume 1 == ~t6_pc~0; 61717#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62144#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62145#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62431#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 62242#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62240#L731 assume 1 == ~t7_pc~0; 61217#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61218#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61412#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62349#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 62468#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61327#L750 assume !(1 == ~t8_pc~0); 60998#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 60997#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61513#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62543#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61650#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61651#L769 assume 1 == ~t9_pc~0; 62186#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61171#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61172#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61955#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 62407#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62488#L788 assume !(1 == ~t10_pc~0); 62063#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62064#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62295#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62296#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 61323#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61324#L807 assume 1 == ~t11_pc~0; 62497#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62075#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62228#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62639#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 62744#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62587#L826 assume !(1 == ~t12_pc~0); 61719#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 61720#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62248#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62679#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 61879#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61788#L1344 assume !(1 == ~M_E~0); 61789#L1344-2 assume !(1 == ~T1_E~0); 61930#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62102#L1354-1 assume !(1 == ~T3_E~0); 62103#L1359-1 assume !(1 == ~T4_E~0); 62477#L1364-1 assume !(1 == ~T5_E~0); 61431#L1369-1 assume !(1 == ~T6_E~0); 61432#L1374-1 assume !(1 == ~T7_E~0); 62108#L1379-1 assume !(1 == ~T8_E~0); 62109#L1384-1 assume !(1 == ~T9_E~0); 62172#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62618#L1394-1 assume !(1 == ~T11_E~0); 62619#L1399-1 assume !(1 == ~T12_E~0); 62698#L1404-1 assume !(1 == ~E_M~0); 61550#L1409-1 assume !(1 == ~E_1~0); 61551#L1414-1 assume !(1 == ~E_2~0); 62388#L1419-1 assume !(1 == ~E_3~0); 61184#L1424-1 assume !(1 == ~E_4~0); 61185#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 62119#L1434-1 assume !(1 == ~E_6~0); 62637#L1439-1 assume !(1 == ~E_7~0); 61239#L1444-1 assume !(1 == ~E_8~0); 61240#L1449-1 assume !(1 == ~E_9~0); 61655#L1454-1 assume !(1 == ~E_10~0); 61656#L1459-1 assume !(1 == ~E_11~0); 62206#L1464-1 assume !(1 == ~E_12~0); 62207#L1469-1 assume { :end_inline_reset_delta_events } true; 62254#L1815-2 [2022-02-21 04:23:23,352 INFO L793 eck$LassoCheckResult]: Loop: 62254#L1815-2 assume !false; 62408#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62077#L1181 assume !false; 62148#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 62100#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60958#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 61687#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 62238#L1008 assume !(0 != eval_~tmp~0#1); 62239#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61177#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61178#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62738#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62205#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61311#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61312#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61902#L1226-3 assume !(0 == ~T5_E~0); 61375#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61376#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61688#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62675#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62578#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62314#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61333#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 61334#L1266-3 assume !(0 == ~E_M~0); 61373#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61374#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61846#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61847#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62384#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62385#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62727#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62695#L1306-3 assume !(0 == ~E_8~0); 61971#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61257#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 61258#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 61335#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62070#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62395#L598-42 assume !(1 == ~m_pc~0); 62396#L598-44 is_master_triggered_~__retres1~0#1 := 0; 62510#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61413#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61414#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 62696#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62126#L617-42 assume 1 == ~t1_pc~0; 61898#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61763#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61764#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62178#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61478#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61479#L636-42 assume !(1 == ~t2_pc~0); 61942#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 61943#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62293#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62294#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62473#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62335#L655-42 assume 1 == ~t3_pc~0; 62336#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 61916#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61548#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61549#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62602#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62547#L674-42 assume !(1 == ~t4_pc~0); 62321#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 62243#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61132#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61133#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62047#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62048#L693-42 assume !(1 == ~t5_pc~0); 62305#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 62304#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62364#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62359#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62360#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61662#L712-42 assume 1 == ~t6_pc~0; 61664#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61989#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62197#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62198#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61771#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61772#L731-42 assume 1 == ~t7_pc~0; 61635#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61471#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62538#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61679#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61680#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61383#L750-42 assume 1 == ~t8_pc~0; 61384#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61958#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62381#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61276#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61277#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62046#L769-42 assume 1 == ~t9_pc~0; 61868#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61869#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62552#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62617#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 61480#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61481#L788-42 assume 1 == ~t10_pc~0; 62054#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 62268#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61998#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61999#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62736#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62714#L807-42 assume 1 == ~t11_pc~0; 62403#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61085#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61224#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61225#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 61226#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61475#L826-42 assume 1 == ~t12_pc~0; 61476#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61668#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62460#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61465#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61466#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62317#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62318#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62244#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61625#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61626#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62258#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62716#L1369-3 assume !(1 == ~T6_E~0); 62636#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61390#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61391#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61623#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61624#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61922#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62645#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62608#L1409-3 assume !(1 == ~E_1~0); 62609#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62674#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62454#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61291#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61292#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62257#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61231#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61232#L1449-3 assume !(1 == ~E_9~0); 61341#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 62251#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 62252#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 62633#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 62131#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 61130#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 61131#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 61747#L1834 assume !(0 == start_simulation_~tmp~3#1); 62367#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 62390#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 61824#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 62003#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 62215#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 62623#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61116#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 61117#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 62254#L1815-2 [2022-02-21 04:23:23,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:23,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-02-21 04:23:23,352 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:23,353 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091157542] [2022-02-21 04:23:23,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:23,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:23,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,392 INFO L290 TraceCheckUtils]: 0: Hoare triple {66328#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {66328#true} is VALID [2022-02-21 04:23:23,393 INFO L290 TraceCheckUtils]: 1: Hoare triple {66328#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,393 INFO L290 TraceCheckUtils]: 2: Hoare triple {66330#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,393 INFO L290 TraceCheckUtils]: 3: Hoare triple {66330#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,393 INFO L290 TraceCheckUtils]: 4: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,394 INFO L290 TraceCheckUtils]: 5: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,394 INFO L290 TraceCheckUtils]: 6: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,394 INFO L290 TraceCheckUtils]: 7: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,394 INFO L290 TraceCheckUtils]: 8: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,395 INFO L290 TraceCheckUtils]: 9: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,395 INFO L290 TraceCheckUtils]: 10: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,395 INFO L290 TraceCheckUtils]: 11: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,396 INFO L290 TraceCheckUtils]: 12: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,396 INFO L290 TraceCheckUtils]: 13: Hoare triple {66330#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {66330#(= ~t10_i~0 1)} is VALID [2022-02-21 04:23:23,396 INFO L290 TraceCheckUtils]: 14: Hoare triple {66330#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {66329#false} is VALID [2022-02-21 04:23:23,396 INFO L290 TraceCheckUtils]: 15: Hoare triple {66329#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {66329#false} is VALID [2022-02-21 04:23:23,396 INFO L290 TraceCheckUtils]: 16: Hoare triple {66329#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {66329#false} is VALID [2022-02-21 04:23:23,396 INFO L290 TraceCheckUtils]: 17: Hoare triple {66329#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 18: Hoare triple {66329#false} assume !(0 == ~M_E~0); {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 19: Hoare triple {66329#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 20: Hoare triple {66329#false} assume !(0 == ~T2_E~0); {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 21: Hoare triple {66329#false} assume !(0 == ~T3_E~0); {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 22: Hoare triple {66329#false} assume !(0 == ~T4_E~0); {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 23: Hoare triple {66329#false} assume !(0 == ~T5_E~0); {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 24: Hoare triple {66329#false} assume !(0 == ~T6_E~0); {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 25: Hoare triple {66329#false} assume !(0 == ~T7_E~0); {66329#false} is VALID [2022-02-21 04:23:23,397 INFO L290 TraceCheckUtils]: 26: Hoare triple {66329#false} assume !(0 == ~T8_E~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 27: Hoare triple {66329#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 28: Hoare triple {66329#false} assume !(0 == ~T10_E~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 29: Hoare triple {66329#false} assume !(0 == ~T11_E~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 30: Hoare triple {66329#false} assume !(0 == ~T12_E~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 31: Hoare triple {66329#false} assume !(0 == ~E_M~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 32: Hoare triple {66329#false} assume !(0 == ~E_1~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 33: Hoare triple {66329#false} assume !(0 == ~E_2~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 34: Hoare triple {66329#false} assume !(0 == ~E_3~0); {66329#false} is VALID [2022-02-21 04:23:23,398 INFO L290 TraceCheckUtils]: 35: Hoare triple {66329#false} assume 0 == ~E_4~0;~E_4~0 := 1; {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 36: Hoare triple {66329#false} assume !(0 == ~E_5~0); {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 37: Hoare triple {66329#false} assume !(0 == ~E_6~0); {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 38: Hoare triple {66329#false} assume !(0 == ~E_7~0); {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 39: Hoare triple {66329#false} assume !(0 == ~E_8~0); {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 40: Hoare triple {66329#false} assume !(0 == ~E_9~0); {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 41: Hoare triple {66329#false} assume !(0 == ~E_10~0); {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 42: Hoare triple {66329#false} assume !(0 == ~E_11~0); {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 43: Hoare triple {66329#false} assume 0 == ~E_12~0;~E_12~0 := 1; {66329#false} is VALID [2022-02-21 04:23:23,399 INFO L290 TraceCheckUtils]: 44: Hoare triple {66329#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 45: Hoare triple {66329#false} assume 1 == ~m_pc~0; {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 46: Hoare triple {66329#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 47: Hoare triple {66329#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 48: Hoare triple {66329#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 49: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp~1#1); {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 50: Hoare triple {66329#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 51: Hoare triple {66329#false} assume !(1 == ~t1_pc~0); {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 52: Hoare triple {66329#false} is_transmit1_triggered_~__retres1~1#1 := 0; {66329#false} is VALID [2022-02-21 04:23:23,400 INFO L290 TraceCheckUtils]: 53: Hoare triple {66329#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 54: Hoare triple {66329#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 55: Hoare triple {66329#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 56: Hoare triple {66329#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 57: Hoare triple {66329#false} assume 1 == ~t2_pc~0; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 58: Hoare triple {66329#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 59: Hoare triple {66329#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 60: Hoare triple {66329#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 61: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___1~0#1); {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 62: Hoare triple {66329#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66329#false} is VALID [2022-02-21 04:23:23,401 INFO L290 TraceCheckUtils]: 63: Hoare triple {66329#false} assume !(1 == ~t3_pc~0); {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 64: Hoare triple {66329#false} is_transmit3_triggered_~__retres1~3#1 := 0; {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 65: Hoare triple {66329#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 66: Hoare triple {66329#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 67: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___2~0#1); {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 68: Hoare triple {66329#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 69: Hoare triple {66329#false} assume 1 == ~t4_pc~0; {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 70: Hoare triple {66329#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 71: Hoare triple {66329#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66329#false} is VALID [2022-02-21 04:23:23,402 INFO L290 TraceCheckUtils]: 72: Hoare triple {66329#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 73: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___3~0#1); {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 74: Hoare triple {66329#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 75: Hoare triple {66329#false} assume !(1 == ~t5_pc~0); {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 76: Hoare triple {66329#false} is_transmit5_triggered_~__retres1~5#1 := 0; {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 77: Hoare triple {66329#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 78: Hoare triple {66329#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 79: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___4~0#1); {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 80: Hoare triple {66329#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66329#false} is VALID [2022-02-21 04:23:23,403 INFO L290 TraceCheckUtils]: 81: Hoare triple {66329#false} assume 1 == ~t6_pc~0; {66329#false} is VALID [2022-02-21 04:23:23,404 INFO L290 TraceCheckUtils]: 82: Hoare triple {66329#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66329#false} is VALID [2022-02-21 04:23:23,404 INFO L290 TraceCheckUtils]: 83: Hoare triple {66329#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66329#false} is VALID [2022-02-21 04:23:23,404 INFO L290 TraceCheckUtils]: 84: Hoare triple {66329#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66329#false} is VALID [2022-02-21 04:23:23,404 INFO L290 TraceCheckUtils]: 85: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___5~0#1); {66329#false} is VALID [2022-02-21 04:23:23,406 INFO L290 TraceCheckUtils]: 86: Hoare triple {66329#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66329#false} is VALID [2022-02-21 04:23:23,406 INFO L290 TraceCheckUtils]: 87: Hoare triple {66329#false} assume 1 == ~t7_pc~0; {66329#false} is VALID [2022-02-21 04:23:23,406 INFO L290 TraceCheckUtils]: 88: Hoare triple {66329#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {66329#false} is VALID [2022-02-21 04:23:23,406 INFO L290 TraceCheckUtils]: 89: Hoare triple {66329#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 90: Hoare triple {66329#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 91: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___6~0#1); {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 92: Hoare triple {66329#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 93: Hoare triple {66329#false} assume !(1 == ~t8_pc~0); {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 94: Hoare triple {66329#false} is_transmit8_triggered_~__retres1~8#1 := 0; {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 95: Hoare triple {66329#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 96: Hoare triple {66329#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 97: Hoare triple {66329#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {66329#false} is VALID [2022-02-21 04:23:23,407 INFO L290 TraceCheckUtils]: 98: Hoare triple {66329#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 99: Hoare triple {66329#false} assume 1 == ~t9_pc~0; {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 100: Hoare triple {66329#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 101: Hoare triple {66329#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 102: Hoare triple {66329#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 103: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___8~0#1); {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 104: Hoare triple {66329#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 105: Hoare triple {66329#false} assume !(1 == ~t10_pc~0); {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 106: Hoare triple {66329#false} is_transmit10_triggered_~__retres1~10#1 := 0; {66329#false} is VALID [2022-02-21 04:23:23,408 INFO L290 TraceCheckUtils]: 107: Hoare triple {66329#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66329#false} is VALID [2022-02-21 04:23:23,409 INFO L290 TraceCheckUtils]: 108: Hoare triple {66329#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66329#false} is VALID [2022-02-21 04:23:23,409 INFO L290 TraceCheckUtils]: 109: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___9~0#1); {66329#false} is VALID [2022-02-21 04:23:23,423 INFO L290 TraceCheckUtils]: 110: Hoare triple {66329#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66329#false} is VALID [2022-02-21 04:23:23,423 INFO L290 TraceCheckUtils]: 111: Hoare triple {66329#false} assume 1 == ~t11_pc~0; {66329#false} is VALID [2022-02-21 04:23:23,423 INFO L290 TraceCheckUtils]: 112: Hoare triple {66329#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {66329#false} is VALID [2022-02-21 04:23:23,423 INFO L290 TraceCheckUtils]: 113: Hoare triple {66329#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 114: Hoare triple {66329#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 115: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___10~0#1); {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 116: Hoare triple {66329#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 117: Hoare triple {66329#false} assume !(1 == ~t12_pc~0); {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 118: Hoare triple {66329#false} is_transmit12_triggered_~__retres1~12#1 := 0; {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 119: Hoare triple {66329#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 120: Hoare triple {66329#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 121: Hoare triple {66329#false} assume !(0 != activate_threads_~tmp___11~0#1); {66329#false} is VALID [2022-02-21 04:23:23,424 INFO L290 TraceCheckUtils]: 122: Hoare triple {66329#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 123: Hoare triple {66329#false} assume !(1 == ~M_E~0); {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 124: Hoare triple {66329#false} assume !(1 == ~T1_E~0); {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 125: Hoare triple {66329#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 126: Hoare triple {66329#false} assume !(1 == ~T3_E~0); {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 127: Hoare triple {66329#false} assume !(1 == ~T4_E~0); {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 128: Hoare triple {66329#false} assume !(1 == ~T5_E~0); {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 129: Hoare triple {66329#false} assume !(1 == ~T6_E~0); {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 130: Hoare triple {66329#false} assume !(1 == ~T7_E~0); {66329#false} is VALID [2022-02-21 04:23:23,425 INFO L290 TraceCheckUtils]: 131: Hoare triple {66329#false} assume !(1 == ~T8_E~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 132: Hoare triple {66329#false} assume !(1 == ~T9_E~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 133: Hoare triple {66329#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 134: Hoare triple {66329#false} assume !(1 == ~T11_E~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 135: Hoare triple {66329#false} assume !(1 == ~T12_E~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 136: Hoare triple {66329#false} assume !(1 == ~E_M~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 137: Hoare triple {66329#false} assume !(1 == ~E_1~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 138: Hoare triple {66329#false} assume !(1 == ~E_2~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 139: Hoare triple {66329#false} assume !(1 == ~E_3~0); {66329#false} is VALID [2022-02-21 04:23:23,426 INFO L290 TraceCheckUtils]: 140: Hoare triple {66329#false} assume !(1 == ~E_4~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 141: Hoare triple {66329#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 142: Hoare triple {66329#false} assume !(1 == ~E_6~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 143: Hoare triple {66329#false} assume !(1 == ~E_7~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 144: Hoare triple {66329#false} assume !(1 == ~E_8~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 145: Hoare triple {66329#false} assume !(1 == ~E_9~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 146: Hoare triple {66329#false} assume !(1 == ~E_10~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 147: Hoare triple {66329#false} assume !(1 == ~E_11~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 148: Hoare triple {66329#false} assume !(1 == ~E_12~0); {66329#false} is VALID [2022-02-21 04:23:23,427 INFO L290 TraceCheckUtils]: 149: Hoare triple {66329#false} assume { :end_inline_reset_delta_events } true; {66329#false} is VALID [2022-02-21 04:23:23,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,428 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,428 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091157542] [2022-02-21 04:23:23,428 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091157542] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,428 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,428 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,429 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526333622] [2022-02-21 04:23:23,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,430 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:23,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:23,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1098284653, now seen corresponding path program 1 times [2022-02-21 04:23:23,430 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:23,430 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188561776] [2022-02-21 04:23:23,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:23,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:23,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:23,481 INFO L290 TraceCheckUtils]: 0: Hoare triple {66331#true} assume !false; {66331#true} is VALID [2022-02-21 04:23:23,481 INFO L290 TraceCheckUtils]: 1: Hoare triple {66331#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {66331#true} is VALID [2022-02-21 04:23:23,481 INFO L290 TraceCheckUtils]: 2: Hoare triple {66331#true} assume !false; {66331#true} is VALID [2022-02-21 04:23:23,481 INFO L290 TraceCheckUtils]: 3: Hoare triple {66331#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {66331#true} is VALID [2022-02-21 04:23:23,481 INFO L290 TraceCheckUtils]: 4: Hoare triple {66331#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 5: Hoare triple {66331#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 6: Hoare triple {66331#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 7: Hoare triple {66331#true} assume !(0 != eval_~tmp~0#1); {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 8: Hoare triple {66331#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 9: Hoare triple {66331#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 10: Hoare triple {66331#true} assume 0 == ~M_E~0;~M_E~0 := 1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 11: Hoare triple {66331#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 12: Hoare triple {66331#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 13: Hoare triple {66331#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 14: Hoare triple {66331#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {66331#true} is VALID [2022-02-21 04:23:23,482 INFO L290 TraceCheckUtils]: 15: Hoare triple {66331#true} assume !(0 == ~T5_E~0); {66331#true} is VALID [2022-02-21 04:23:23,483 INFO L290 TraceCheckUtils]: 16: Hoare triple {66331#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,483 INFO L290 TraceCheckUtils]: 17: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,483 INFO L290 TraceCheckUtils]: 18: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,483 INFO L290 TraceCheckUtils]: 19: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,484 INFO L290 TraceCheckUtils]: 20: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,484 INFO L290 TraceCheckUtils]: 21: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,484 INFO L290 TraceCheckUtils]: 22: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,484 INFO L290 TraceCheckUtils]: 23: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,484 INFO L290 TraceCheckUtils]: 24: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,485 INFO L290 TraceCheckUtils]: 25: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,485 INFO L290 TraceCheckUtils]: 26: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,485 INFO L290 TraceCheckUtils]: 27: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,485 INFO L290 TraceCheckUtils]: 28: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,486 INFO L290 TraceCheckUtils]: 29: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,486 INFO L290 TraceCheckUtils]: 30: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,486 INFO L290 TraceCheckUtils]: 31: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,486 INFO L290 TraceCheckUtils]: 32: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,487 INFO L290 TraceCheckUtils]: 33: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,487 INFO L290 TraceCheckUtils]: 34: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,487 INFO L290 TraceCheckUtils]: 35: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,487 INFO L290 TraceCheckUtils]: 36: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,488 INFO L290 TraceCheckUtils]: 37: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,488 INFO L290 TraceCheckUtils]: 38: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,488 INFO L290 TraceCheckUtils]: 39: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,488 INFO L290 TraceCheckUtils]: 40: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,489 INFO L290 TraceCheckUtils]: 41: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,489 INFO L290 TraceCheckUtils]: 42: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,489 INFO L290 TraceCheckUtils]: 43: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,489 INFO L290 TraceCheckUtils]: 44: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,490 INFO L290 TraceCheckUtils]: 45: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,490 INFO L290 TraceCheckUtils]: 46: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,490 INFO L290 TraceCheckUtils]: 47: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,490 INFO L290 TraceCheckUtils]: 48: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,490 INFO L290 TraceCheckUtils]: 49: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,491 INFO L290 TraceCheckUtils]: 50: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,491 INFO L290 TraceCheckUtils]: 51: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,491 INFO L290 TraceCheckUtils]: 52: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,491 INFO L290 TraceCheckUtils]: 53: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,492 INFO L290 TraceCheckUtils]: 54: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,492 INFO L290 TraceCheckUtils]: 55: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,492 INFO L290 TraceCheckUtils]: 56: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,492 INFO L290 TraceCheckUtils]: 57: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,493 INFO L290 TraceCheckUtils]: 58: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,493 INFO L290 TraceCheckUtils]: 59: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,493 INFO L290 TraceCheckUtils]: 60: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,493 INFO L290 TraceCheckUtils]: 61: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,494 INFO L290 TraceCheckUtils]: 62: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,494 INFO L290 TraceCheckUtils]: 63: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,494 INFO L290 TraceCheckUtils]: 64: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,494 INFO L290 TraceCheckUtils]: 65: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,495 INFO L290 TraceCheckUtils]: 66: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,495 INFO L290 TraceCheckUtils]: 67: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,495 INFO L290 TraceCheckUtils]: 68: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,495 INFO L290 TraceCheckUtils]: 69: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,496 INFO L290 TraceCheckUtils]: 70: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,496 INFO L290 TraceCheckUtils]: 71: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,496 INFO L290 TraceCheckUtils]: 72: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,496 INFO L290 TraceCheckUtils]: 73: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,497 INFO L290 TraceCheckUtils]: 74: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,497 INFO L290 TraceCheckUtils]: 75: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,497 INFO L290 TraceCheckUtils]: 76: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,497 INFO L290 TraceCheckUtils]: 77: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,498 INFO L290 TraceCheckUtils]: 78: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,498 INFO L290 TraceCheckUtils]: 79: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,498 INFO L290 TraceCheckUtils]: 80: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,498 INFO L290 TraceCheckUtils]: 81: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,499 INFO L290 TraceCheckUtils]: 82: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,499 INFO L290 TraceCheckUtils]: 83: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,499 INFO L290 TraceCheckUtils]: 84: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,499 INFO L290 TraceCheckUtils]: 85: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,500 INFO L290 TraceCheckUtils]: 86: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,500 INFO L290 TraceCheckUtils]: 87: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,500 INFO L290 TraceCheckUtils]: 88: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,501 INFO L290 TraceCheckUtils]: 89: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,501 INFO L290 TraceCheckUtils]: 90: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,501 INFO L290 TraceCheckUtils]: 91: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,501 INFO L290 TraceCheckUtils]: 92: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,502 INFO L290 TraceCheckUtils]: 93: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,502 INFO L290 TraceCheckUtils]: 94: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,502 INFO L290 TraceCheckUtils]: 95: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,503 INFO L290 TraceCheckUtils]: 96: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,503 INFO L290 TraceCheckUtils]: 97: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,503 INFO L290 TraceCheckUtils]: 98: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,503 INFO L290 TraceCheckUtils]: 99: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,504 INFO L290 TraceCheckUtils]: 100: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,504 INFO L290 TraceCheckUtils]: 101: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,504 INFO L290 TraceCheckUtils]: 102: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,504 INFO L290 TraceCheckUtils]: 103: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,505 INFO L290 TraceCheckUtils]: 104: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,505 INFO L290 TraceCheckUtils]: 105: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,505 INFO L290 TraceCheckUtils]: 106: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,506 INFO L290 TraceCheckUtils]: 107: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,506 INFO L290 TraceCheckUtils]: 108: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,506 INFO L290 TraceCheckUtils]: 109: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,506 INFO L290 TraceCheckUtils]: 110: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,507 INFO L290 TraceCheckUtils]: 111: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,507 INFO L290 TraceCheckUtils]: 112: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,507 INFO L290 TraceCheckUtils]: 113: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,508 INFO L290 TraceCheckUtils]: 114: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,508 INFO L290 TraceCheckUtils]: 115: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,508 INFO L290 TraceCheckUtils]: 116: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,509 INFO L290 TraceCheckUtils]: 117: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,509 INFO L290 TraceCheckUtils]: 118: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,509 INFO L290 TraceCheckUtils]: 119: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,509 INFO L290 TraceCheckUtils]: 120: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {66333#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 121: Hoare triple {66333#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {66332#false} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 122: Hoare triple {66332#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 123: Hoare triple {66332#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 124: Hoare triple {66332#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 125: Hoare triple {66332#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 126: Hoare triple {66332#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 127: Hoare triple {66332#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,510 INFO L290 TraceCheckUtils]: 128: Hoare triple {66332#false} assume 1 == ~E_M~0;~E_M~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 129: Hoare triple {66332#false} assume !(1 == ~E_1~0); {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 130: Hoare triple {66332#false} assume 1 == ~E_2~0;~E_2~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 131: Hoare triple {66332#false} assume 1 == ~E_3~0;~E_3~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 132: Hoare triple {66332#false} assume 1 == ~E_4~0;~E_4~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 133: Hoare triple {66332#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 134: Hoare triple {66332#false} assume 1 == ~E_6~0;~E_6~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 135: Hoare triple {66332#false} assume 1 == ~E_7~0;~E_7~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,511 INFO L290 TraceCheckUtils]: 136: Hoare triple {66332#false} assume 1 == ~E_8~0;~E_8~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 137: Hoare triple {66332#false} assume !(1 == ~E_9~0); {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 138: Hoare triple {66332#false} assume 1 == ~E_10~0;~E_10~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 139: Hoare triple {66332#false} assume 1 == ~E_11~0;~E_11~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 140: Hoare triple {66332#false} assume 1 == ~E_12~0;~E_12~0 := 2; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 141: Hoare triple {66332#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 142: Hoare triple {66332#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 143: Hoare triple {66332#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 144: Hoare triple {66332#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {66332#false} is VALID [2022-02-21 04:23:23,512 INFO L290 TraceCheckUtils]: 145: Hoare triple {66332#false} assume !(0 == start_simulation_~tmp~3#1); {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 146: Hoare triple {66332#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 147: Hoare triple {66332#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 148: Hoare triple {66332#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 149: Hoare triple {66332#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 150: Hoare triple {66332#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 151: Hoare triple {66332#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 152: Hoare triple {66332#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {66332#false} is VALID [2022-02-21 04:23:23,513 INFO L290 TraceCheckUtils]: 153: Hoare triple {66332#false} assume !(0 != start_simulation_~tmp___0~1#1); {66332#false} is VALID [2022-02-21 04:23:23,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:23,514 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:23,514 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188561776] [2022-02-21 04:23:23,514 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188561776] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:23,514 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:23,514 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:23,515 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1963575974] [2022-02-21 04:23:23,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:23,515 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:23,515 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:23,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:23,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:23,516 INFO L87 Difference]: Start difference. First operand 1790 states and 2647 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,580 INFO L93 Difference]: Finished difference Result 1790 states and 2646 transitions. [2022-02-21 04:23:24,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:24,580 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,666 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:24,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2646 transitions. [2022-02-21 04:23:24,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:24,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2646 transitions. [2022-02-21 04:23:24,802 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:24,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:24,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2646 transitions. [2022-02-21 04:23:24,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:24,804 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-02-21 04:23:24,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2646 transitions. [2022-02-21 04:23:24,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:24,818 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:24,819 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2646 transitions. Second operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,820 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2646 transitions. Second operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,821 INFO L87 Difference]: Start difference. First operand 1790 states and 2646 transitions. Second operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:24,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,885 INFO L93 Difference]: Finished difference Result 1790 states and 2646 transitions. [2022-02-21 04:23:24,886 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2646 transitions. [2022-02-21 04:23:24,887 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,887 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,889 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2646 transitions. [2022-02-21 04:23:24,890 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2646 transitions. [2022-02-21 04:23:24,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:24,954 INFO L93 Difference]: Finished difference Result 1790 states and 2646 transitions. [2022-02-21 04:23:24,954 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2646 transitions. [2022-02-21 04:23:24,956 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:24,956 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:24,956 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:24,956 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:24,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4782122905027932) internal successors, (2646), 1789 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:25,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2646 transitions. [2022-02-21 04:23:25,023 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-02-21 04:23:25,023 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2646 transitions. [2022-02-21 04:23:25,023 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:23:25,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2646 transitions. [2022-02-21 04:23:25,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:25,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:25,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:25,027 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:25,027 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:25,027 INFO L791 eck$LassoCheckResult]: Stem: 68968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 68969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 68392#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68362#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68363#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 69624#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68671#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68124#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68125#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69396#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69535#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69901#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69902#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68881#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68882#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69422#L903-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 69342#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 69343#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69495#L1206 assume !(0 == ~M_E~0); 68860#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68861#L1211-1 assume !(0 == ~T2_E~0); 69754#L1216-1 assume !(0 == ~T3_E~0); 68653#L1221-1 assume !(0 == ~T4_E~0); 68654#L1226-1 assume !(0 == ~T5_E~0); 68316#L1231-1 assume !(0 == ~T6_E~0); 68317#L1236-1 assume !(0 == ~T7_E~0); 69785#L1241-1 assume !(0 == ~T8_E~0); 68715#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 68716#L1251-1 assume !(0 == ~T10_E~0); 68936#L1256-1 assume !(0 == ~T11_E~0); 68136#L1261-1 assume !(0 == ~T12_E~0); 68137#L1266-1 assume !(0 == ~E_M~0); 69888#L1271-1 assume !(0 == ~E_1~0); 69523#L1276-1 assume !(0 == ~E_2~0); 69524#L1281-1 assume !(0 == ~E_3~0); 69449#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 68557#L1291-1 assume !(0 == ~E_5~0); 68558#L1296-1 assume !(0 == ~E_6~0); 69264#L1301-1 assume !(0 == ~E_7~0); 69265#L1306-1 assume !(0 == ~E_8~0); 69697#L1311-1 assume !(0 == ~E_9~0); 68518#L1316-1 assume !(0 == ~E_10~0); 68519#L1321-1 assume !(0 == ~E_11~0); 69281#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 68382#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68383#L598 assume 1 == ~m_pc~0; 68442#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 68443#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69767#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69859#L1497 assume !(0 != activate_threads_~tmp~1#1); 69860#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69816#L617 assume !(1 == ~t1_pc~0); 68738#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68739#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68598#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68599#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69359#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69360#L636 assume 1 == ~t2_pc~0; 68707#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68708#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68538#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68539#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 69395#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69058#L655 assume !(1 == ~t3_pc~0); 69059#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69772#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68412#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68413#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 69889#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69890#L674 assume 1 == ~t4_pc~0; 68232#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68233#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69530#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68540#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 68541#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69055#L693 assume !(1 == ~t5_pc~0); 69218#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68862#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68863#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69699#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 68948#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68885#L712 assume 1 == ~t6_pc~0; 68886#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69313#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69314#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69600#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 69411#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69409#L731 assume 1 == ~t7_pc~0; 68386#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68387#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68581#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69518#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 69637#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68496#L750 assume !(1 == ~t8_pc~0); 68167#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 68166#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68682#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69712#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68819#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68820#L769 assume 1 == ~t9_pc~0; 69355#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68340#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68341#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69124#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 69576#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69657#L788 assume !(1 == ~t10_pc~0); 69232#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 69233#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69464#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69465#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 68492#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68493#L807 assume 1 == ~t11_pc~0; 69666#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69244#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69397#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69808#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 69913#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69756#L826 assume !(1 == ~t12_pc~0); 68888#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 68889#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69417#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69848#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 69048#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68957#L1344 assume !(1 == ~M_E~0); 68958#L1344-2 assume !(1 == ~T1_E~0); 69099#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69271#L1354-1 assume !(1 == ~T3_E~0); 69272#L1359-1 assume !(1 == ~T4_E~0); 69646#L1364-1 assume !(1 == ~T5_E~0); 68600#L1369-1 assume !(1 == ~T6_E~0); 68601#L1374-1 assume !(1 == ~T7_E~0); 69277#L1379-1 assume !(1 == ~T8_E~0); 69278#L1384-1 assume !(1 == ~T9_E~0); 69341#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69787#L1394-1 assume !(1 == ~T11_E~0); 69788#L1399-1 assume !(1 == ~T12_E~0); 69867#L1404-1 assume !(1 == ~E_M~0); 68719#L1409-1 assume !(1 == ~E_1~0); 68720#L1414-1 assume !(1 == ~E_2~0); 69557#L1419-1 assume !(1 == ~E_3~0); 68353#L1424-1 assume !(1 == ~E_4~0); 68354#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69288#L1434-1 assume !(1 == ~E_6~0); 69806#L1439-1 assume !(1 == ~E_7~0); 68408#L1444-1 assume !(1 == ~E_8~0); 68409#L1449-1 assume !(1 == ~E_9~0); 68824#L1454-1 assume !(1 == ~E_10~0); 68825#L1459-1 assume !(1 == ~E_11~0); 69375#L1464-1 assume !(1 == ~E_12~0); 69376#L1469-1 assume { :end_inline_reset_delta_events } true; 69423#L1815-2 [2022-02-21 04:23:25,028 INFO L793 eck$LassoCheckResult]: Loop: 69423#L1815-2 assume !false; 69577#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69246#L1181 assume !false; 69317#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 69269#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 68127#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 68856#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69407#L1008 assume !(0 != eval_~tmp~0#1); 69408#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68346#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68347#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 69907#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69374#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68480#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68481#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69071#L1226-3 assume !(0 == ~T5_E~0); 68544#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68545#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68857#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69844#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69747#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 69483#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68502#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68503#L1266-3 assume !(0 == ~E_M~0); 68542#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68543#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69015#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69016#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69553#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69554#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69896#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69864#L1306-3 assume !(0 == ~E_8~0); 69140#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68426#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68427#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 68504#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 69239#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69564#L598-42 assume !(1 == ~m_pc~0); 69565#L598-44 is_master_triggered_~__retres1~0#1 := 0; 69679#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68582#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68583#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 69865#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69295#L617-42 assume 1 == ~t1_pc~0; 69067#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68932#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68933#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69347#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68647#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68648#L636-42 assume !(1 == ~t2_pc~0); 69111#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 69112#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69462#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69463#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69642#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69504#L655-42 assume 1 == ~t3_pc~0; 69505#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69085#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68717#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68718#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69771#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69716#L674-42 assume !(1 == ~t4_pc~0); 69490#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 69412#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68301#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68302#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69216#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69217#L693-42 assume 1 == ~t5_pc~0; 69472#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69473#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69533#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69528#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69529#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68831#L712-42 assume 1 == ~t6_pc~0; 68833#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69158#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69366#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69367#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 68940#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68941#L731-42 assume 1 == ~t7_pc~0; 68804#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68640#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69707#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68848#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68849#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68552#L750-42 assume 1 == ~t8_pc~0; 68553#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69127#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69550#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68445#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68446#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69215#L769-42 assume 1 == ~t9_pc~0; 69037#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69038#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69721#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69786#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 68649#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68650#L788-42 assume 1 == ~t10_pc~0; 69223#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 69437#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69167#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69168#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69905#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69883#L807-42 assume 1 == ~t11_pc~0; 69572#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68254#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68393#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68394#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68395#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68644#L826-42 assume 1 == ~t12_pc~0; 68645#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68837#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69629#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68634#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 68635#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69486#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 69487#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69413#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68794#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68795#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69427#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69885#L1369-3 assume !(1 == ~T6_E~0); 69805#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 68559#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 68560#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 68792#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 68793#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69091#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69814#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69777#L1409-3 assume !(1 == ~E_1~0); 69778#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69843#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69623#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68460#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68461#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69426#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 68400#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68401#L1449-3 assume !(1 == ~E_9~0); 68510#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69420#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69421#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69802#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 69300#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 68299#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 68300#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 68916#L1834 assume !(0 == start_simulation_~tmp~3#1); 69536#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 69559#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 68993#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 69172#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 69384#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69792#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68285#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68286#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 69423#L1815-2 [2022-02-21 04:23:25,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:25,028 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-02-21 04:23:25,028 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:25,029 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196920446] [2022-02-21 04:23:25,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:25,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:25,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:25,046 INFO L290 TraceCheckUtils]: 0: Hoare triple {73497#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {73497#true} is VALID [2022-02-21 04:23:25,046 INFO L290 TraceCheckUtils]: 1: Hoare triple {73497#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,047 INFO L290 TraceCheckUtils]: 2: Hoare triple {73499#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,047 INFO L290 TraceCheckUtils]: 3: Hoare triple {73499#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,047 INFO L290 TraceCheckUtils]: 4: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,047 INFO L290 TraceCheckUtils]: 5: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,048 INFO L290 TraceCheckUtils]: 6: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,048 INFO L290 TraceCheckUtils]: 7: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,048 INFO L290 TraceCheckUtils]: 8: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,048 INFO L290 TraceCheckUtils]: 9: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,049 INFO L290 TraceCheckUtils]: 10: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,049 INFO L290 TraceCheckUtils]: 11: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,049 INFO L290 TraceCheckUtils]: 12: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,050 INFO L290 TraceCheckUtils]: 13: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,050 INFO L290 TraceCheckUtils]: 14: Hoare triple {73499#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {73499#(= ~t11_i~0 1)} is VALID [2022-02-21 04:23:25,050 INFO L290 TraceCheckUtils]: 15: Hoare triple {73499#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {73498#false} is VALID [2022-02-21 04:23:25,050 INFO L290 TraceCheckUtils]: 16: Hoare triple {73498#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {73498#false} is VALID [2022-02-21 04:23:25,050 INFO L290 TraceCheckUtils]: 17: Hoare triple {73498#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {73498#false} is VALID [2022-02-21 04:23:25,050 INFO L290 TraceCheckUtils]: 18: Hoare triple {73498#false} assume !(0 == ~M_E~0); {73498#false} is VALID [2022-02-21 04:23:25,050 INFO L290 TraceCheckUtils]: 19: Hoare triple {73498#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 20: Hoare triple {73498#false} assume !(0 == ~T2_E~0); {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 21: Hoare triple {73498#false} assume !(0 == ~T3_E~0); {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 22: Hoare triple {73498#false} assume !(0 == ~T4_E~0); {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 23: Hoare triple {73498#false} assume !(0 == ~T5_E~0); {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 24: Hoare triple {73498#false} assume !(0 == ~T6_E~0); {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 25: Hoare triple {73498#false} assume !(0 == ~T7_E~0); {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 26: Hoare triple {73498#false} assume !(0 == ~T8_E~0); {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 27: Hoare triple {73498#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {73498#false} is VALID [2022-02-21 04:23:25,051 INFO L290 TraceCheckUtils]: 28: Hoare triple {73498#false} assume !(0 == ~T10_E~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 29: Hoare triple {73498#false} assume !(0 == ~T11_E~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 30: Hoare triple {73498#false} assume !(0 == ~T12_E~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 31: Hoare triple {73498#false} assume !(0 == ~E_M~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 32: Hoare triple {73498#false} assume !(0 == ~E_1~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 33: Hoare triple {73498#false} assume !(0 == ~E_2~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 34: Hoare triple {73498#false} assume !(0 == ~E_3~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 35: Hoare triple {73498#false} assume 0 == ~E_4~0;~E_4~0 := 1; {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 36: Hoare triple {73498#false} assume !(0 == ~E_5~0); {73498#false} is VALID [2022-02-21 04:23:25,052 INFO L290 TraceCheckUtils]: 37: Hoare triple {73498#false} assume !(0 == ~E_6~0); {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 38: Hoare triple {73498#false} assume !(0 == ~E_7~0); {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 39: Hoare triple {73498#false} assume !(0 == ~E_8~0); {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 40: Hoare triple {73498#false} assume !(0 == ~E_9~0); {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 41: Hoare triple {73498#false} assume !(0 == ~E_10~0); {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 42: Hoare triple {73498#false} assume !(0 == ~E_11~0); {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 43: Hoare triple {73498#false} assume 0 == ~E_12~0;~E_12~0 := 1; {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 44: Hoare triple {73498#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 45: Hoare triple {73498#false} assume 1 == ~m_pc~0; {73498#false} is VALID [2022-02-21 04:23:25,053 INFO L290 TraceCheckUtils]: 46: Hoare triple {73498#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 47: Hoare triple {73498#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 48: Hoare triple {73498#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 49: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp~1#1); {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 50: Hoare triple {73498#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 51: Hoare triple {73498#false} assume !(1 == ~t1_pc~0); {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 52: Hoare triple {73498#false} is_transmit1_triggered_~__retres1~1#1 := 0; {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 53: Hoare triple {73498#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 54: Hoare triple {73498#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {73498#false} is VALID [2022-02-21 04:23:25,054 INFO L290 TraceCheckUtils]: 55: Hoare triple {73498#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 56: Hoare triple {73498#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 57: Hoare triple {73498#false} assume 1 == ~t2_pc~0; {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 58: Hoare triple {73498#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 59: Hoare triple {73498#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 60: Hoare triple {73498#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 61: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___1~0#1); {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 62: Hoare triple {73498#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 63: Hoare triple {73498#false} assume !(1 == ~t3_pc~0); {73498#false} is VALID [2022-02-21 04:23:25,055 INFO L290 TraceCheckUtils]: 64: Hoare triple {73498#false} is_transmit3_triggered_~__retres1~3#1 := 0; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 65: Hoare triple {73498#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 66: Hoare triple {73498#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 67: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___2~0#1); {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 68: Hoare triple {73498#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 69: Hoare triple {73498#false} assume 1 == ~t4_pc~0; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 70: Hoare triple {73498#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 71: Hoare triple {73498#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 72: Hoare triple {73498#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {73498#false} is VALID [2022-02-21 04:23:25,056 INFO L290 TraceCheckUtils]: 73: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___3~0#1); {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 74: Hoare triple {73498#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 75: Hoare triple {73498#false} assume !(1 == ~t5_pc~0); {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 76: Hoare triple {73498#false} is_transmit5_triggered_~__retres1~5#1 := 0; {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 77: Hoare triple {73498#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 78: Hoare triple {73498#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 79: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___4~0#1); {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 80: Hoare triple {73498#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 81: Hoare triple {73498#false} assume 1 == ~t6_pc~0; {73498#false} is VALID [2022-02-21 04:23:25,057 INFO L290 TraceCheckUtils]: 82: Hoare triple {73498#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 83: Hoare triple {73498#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 84: Hoare triple {73498#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 85: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___5~0#1); {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 86: Hoare triple {73498#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 87: Hoare triple {73498#false} assume 1 == ~t7_pc~0; {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 88: Hoare triple {73498#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 89: Hoare triple {73498#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {73498#false} is VALID [2022-02-21 04:23:25,058 INFO L290 TraceCheckUtils]: 90: Hoare triple {73498#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 91: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___6~0#1); {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 92: Hoare triple {73498#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 93: Hoare triple {73498#false} assume !(1 == ~t8_pc~0); {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 94: Hoare triple {73498#false} is_transmit8_triggered_~__retres1~8#1 := 0; {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 95: Hoare triple {73498#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 96: Hoare triple {73498#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 97: Hoare triple {73498#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 98: Hoare triple {73498#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {73498#false} is VALID [2022-02-21 04:23:25,059 INFO L290 TraceCheckUtils]: 99: Hoare triple {73498#false} assume 1 == ~t9_pc~0; {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 100: Hoare triple {73498#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 101: Hoare triple {73498#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 102: Hoare triple {73498#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 103: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___8~0#1); {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 104: Hoare triple {73498#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 105: Hoare triple {73498#false} assume !(1 == ~t10_pc~0); {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 106: Hoare triple {73498#false} is_transmit10_triggered_~__retres1~10#1 := 0; {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 107: Hoare triple {73498#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {73498#false} is VALID [2022-02-21 04:23:25,060 INFO L290 TraceCheckUtils]: 108: Hoare triple {73498#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 109: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___9~0#1); {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 110: Hoare triple {73498#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 111: Hoare triple {73498#false} assume 1 == ~t11_pc~0; {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 112: Hoare triple {73498#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 113: Hoare triple {73498#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 114: Hoare triple {73498#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 115: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___10~0#1); {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 116: Hoare triple {73498#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {73498#false} is VALID [2022-02-21 04:23:25,061 INFO L290 TraceCheckUtils]: 117: Hoare triple {73498#false} assume !(1 == ~t12_pc~0); {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 118: Hoare triple {73498#false} is_transmit12_triggered_~__retres1~12#1 := 0; {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 119: Hoare triple {73498#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 120: Hoare triple {73498#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 121: Hoare triple {73498#false} assume !(0 != activate_threads_~tmp___11~0#1); {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 122: Hoare triple {73498#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 123: Hoare triple {73498#false} assume !(1 == ~M_E~0); {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 124: Hoare triple {73498#false} assume !(1 == ~T1_E~0); {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 125: Hoare triple {73498#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {73498#false} is VALID [2022-02-21 04:23:25,062 INFO L290 TraceCheckUtils]: 126: Hoare triple {73498#false} assume !(1 == ~T3_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 127: Hoare triple {73498#false} assume !(1 == ~T4_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 128: Hoare triple {73498#false} assume !(1 == ~T5_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 129: Hoare triple {73498#false} assume !(1 == ~T6_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 130: Hoare triple {73498#false} assume !(1 == ~T7_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 131: Hoare triple {73498#false} assume !(1 == ~T8_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 132: Hoare triple {73498#false} assume !(1 == ~T9_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 133: Hoare triple {73498#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 134: Hoare triple {73498#false} assume !(1 == ~T11_E~0); {73498#false} is VALID [2022-02-21 04:23:25,063 INFO L290 TraceCheckUtils]: 135: Hoare triple {73498#false} assume !(1 == ~T12_E~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 136: Hoare triple {73498#false} assume !(1 == ~E_M~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 137: Hoare triple {73498#false} assume !(1 == ~E_1~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 138: Hoare triple {73498#false} assume !(1 == ~E_2~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 139: Hoare triple {73498#false} assume !(1 == ~E_3~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 140: Hoare triple {73498#false} assume !(1 == ~E_4~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 141: Hoare triple {73498#false} assume 1 == ~E_5~0;~E_5~0 := 2; {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 142: Hoare triple {73498#false} assume !(1 == ~E_6~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 143: Hoare triple {73498#false} assume !(1 == ~E_7~0); {73498#false} is VALID [2022-02-21 04:23:25,064 INFO L290 TraceCheckUtils]: 144: Hoare triple {73498#false} assume !(1 == ~E_8~0); {73498#false} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 145: Hoare triple {73498#false} assume !(1 == ~E_9~0); {73498#false} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 146: Hoare triple {73498#false} assume !(1 == ~E_10~0); {73498#false} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 147: Hoare triple {73498#false} assume !(1 == ~E_11~0); {73498#false} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 148: Hoare triple {73498#false} assume !(1 == ~E_12~0); {73498#false} is VALID [2022-02-21 04:23:25,065 INFO L290 TraceCheckUtils]: 149: Hoare triple {73498#false} assume { :end_inline_reset_delta_events } true; {73498#false} is VALID [2022-02-21 04:23:25,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,065 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,066 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196920446] [2022-02-21 04:23:25,066 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1196920446] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,066 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,066 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,066 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035881631] [2022-02-21 04:23:25,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,066 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:25,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:25,067 INFO L85 PathProgramCache]: Analyzing trace with hash 386955538, now seen corresponding path program 1 times [2022-02-21 04:23:25,067 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:25,067 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752473431] [2022-02-21 04:23:25,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:25,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:25,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 0: Hoare triple {73500#true} assume !false; {73500#true} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 1: Hoare triple {73500#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {73500#true} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 2: Hoare triple {73500#true} assume !false; {73500#true} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 3: Hoare triple {73500#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {73500#true} is VALID [2022-02-21 04:23:25,089 INFO L290 TraceCheckUtils]: 4: Hoare triple {73500#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 5: Hoare triple {73500#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 6: Hoare triple {73500#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 7: Hoare triple {73500#true} assume !(0 != eval_~tmp~0#1); {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 8: Hoare triple {73500#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 9: Hoare triple {73500#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 10: Hoare triple {73500#true} assume 0 == ~M_E~0;~M_E~0 := 1; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 11: Hoare triple {73500#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 12: Hoare triple {73500#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {73500#true} is VALID [2022-02-21 04:23:25,090 INFO L290 TraceCheckUtils]: 13: Hoare triple {73500#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {73500#true} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 14: Hoare triple {73500#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {73500#true} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 15: Hoare triple {73500#true} assume !(0 == ~T5_E~0); {73500#true} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 16: Hoare triple {73500#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,091 INFO L290 TraceCheckUtils]: 17: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 18: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 19: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 20: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,092 INFO L290 TraceCheckUtils]: 21: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 22: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 23: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 24: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,093 INFO L290 TraceCheckUtils]: 25: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 26: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 27: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,094 INFO L290 TraceCheckUtils]: 28: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 29: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 30: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 31: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,095 INFO L290 TraceCheckUtils]: 32: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 33: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 34: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 35: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,096 INFO L290 TraceCheckUtils]: 36: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 37: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 38: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 39: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,097 INFO L290 TraceCheckUtils]: 40: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 41: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 42: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,098 INFO L290 TraceCheckUtils]: 43: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 44: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 45: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 46: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,099 INFO L290 TraceCheckUtils]: 47: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 48: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 49: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 50: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,100 INFO L290 TraceCheckUtils]: 51: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 52: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 53: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 54: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,101 INFO L290 TraceCheckUtils]: 55: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 56: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 57: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,102 INFO L290 TraceCheckUtils]: 58: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 59: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 60: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 61: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,103 INFO L290 TraceCheckUtils]: 62: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 63: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 64: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 65: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,104 INFO L290 TraceCheckUtils]: 66: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 67: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 68: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 69: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,105 INFO L290 TraceCheckUtils]: 70: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 71: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 72: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,106 INFO L290 TraceCheckUtils]: 73: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 74: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 75: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 76: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,107 INFO L290 TraceCheckUtils]: 77: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 78: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 79: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 80: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,108 INFO L290 TraceCheckUtils]: 81: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 82: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 83: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 84: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,109 INFO L290 TraceCheckUtils]: 85: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 86: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 87: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,110 INFO L290 TraceCheckUtils]: 88: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 89: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 90: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 91: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,111 INFO L290 TraceCheckUtils]: 92: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,112 INFO L290 TraceCheckUtils]: 93: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,112 INFO L290 TraceCheckUtils]: 94: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,112 INFO L290 TraceCheckUtils]: 95: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,112 INFO L290 TraceCheckUtils]: 96: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,113 INFO L290 TraceCheckUtils]: 97: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,113 INFO L290 TraceCheckUtils]: 98: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,113 INFO L290 TraceCheckUtils]: 99: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,113 INFO L290 TraceCheckUtils]: 100: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,114 INFO L290 TraceCheckUtils]: 101: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,114 INFO L290 TraceCheckUtils]: 102: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,114 INFO L290 TraceCheckUtils]: 103: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,115 INFO L290 TraceCheckUtils]: 104: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,115 INFO L290 TraceCheckUtils]: 105: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,115 INFO L290 TraceCheckUtils]: 106: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,115 INFO L290 TraceCheckUtils]: 107: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,116 INFO L290 TraceCheckUtils]: 108: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,116 INFO L290 TraceCheckUtils]: 109: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,116 INFO L290 TraceCheckUtils]: 110: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,116 INFO L290 TraceCheckUtils]: 111: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,117 INFO L290 TraceCheckUtils]: 112: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,117 INFO L290 TraceCheckUtils]: 113: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,117 INFO L290 TraceCheckUtils]: 114: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,117 INFO L290 TraceCheckUtils]: 115: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,118 INFO L290 TraceCheckUtils]: 116: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,118 INFO L290 TraceCheckUtils]: 117: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,118 INFO L290 TraceCheckUtils]: 118: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,119 INFO L290 TraceCheckUtils]: 119: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,119 INFO L290 TraceCheckUtils]: 120: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {73502#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:25,119 INFO L290 TraceCheckUtils]: 121: Hoare triple {73502#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {73501#false} is VALID [2022-02-21 04:23:25,119 INFO L290 TraceCheckUtils]: 122: Hoare triple {73501#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,119 INFO L290 TraceCheckUtils]: 123: Hoare triple {73501#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,119 INFO L290 TraceCheckUtils]: 124: Hoare triple {73501#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 125: Hoare triple {73501#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 126: Hoare triple {73501#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 127: Hoare triple {73501#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 128: Hoare triple {73501#false} assume 1 == ~E_M~0;~E_M~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 129: Hoare triple {73501#false} assume !(1 == ~E_1~0); {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 130: Hoare triple {73501#false} assume 1 == ~E_2~0;~E_2~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 131: Hoare triple {73501#false} assume 1 == ~E_3~0;~E_3~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 132: Hoare triple {73501#false} assume 1 == ~E_4~0;~E_4~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,120 INFO L290 TraceCheckUtils]: 133: Hoare triple {73501#false} assume 1 == ~E_5~0;~E_5~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 134: Hoare triple {73501#false} assume 1 == ~E_6~0;~E_6~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 135: Hoare triple {73501#false} assume 1 == ~E_7~0;~E_7~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 136: Hoare triple {73501#false} assume 1 == ~E_8~0;~E_8~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 137: Hoare triple {73501#false} assume !(1 == ~E_9~0); {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 138: Hoare triple {73501#false} assume 1 == ~E_10~0;~E_10~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 139: Hoare triple {73501#false} assume 1 == ~E_11~0;~E_11~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 140: Hoare triple {73501#false} assume 1 == ~E_12~0;~E_12~0 := 2; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 141: Hoare triple {73501#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {73501#false} is VALID [2022-02-21 04:23:25,121 INFO L290 TraceCheckUtils]: 142: Hoare triple {73501#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 143: Hoare triple {73501#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 144: Hoare triple {73501#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 145: Hoare triple {73501#false} assume !(0 == start_simulation_~tmp~3#1); {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 146: Hoare triple {73501#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 147: Hoare triple {73501#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 148: Hoare triple {73501#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 149: Hoare triple {73501#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 150: Hoare triple {73501#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {73501#false} is VALID [2022-02-21 04:23:25,122 INFO L290 TraceCheckUtils]: 151: Hoare triple {73501#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {73501#false} is VALID [2022-02-21 04:23:25,123 INFO L290 TraceCheckUtils]: 152: Hoare triple {73501#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {73501#false} is VALID [2022-02-21 04:23:25,123 INFO L290 TraceCheckUtils]: 153: Hoare triple {73501#false} assume !(0 != start_simulation_~tmp___0~1#1); {73501#false} is VALID [2022-02-21 04:23:25,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:25,123 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:25,123 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752473431] [2022-02-21 04:23:25,123 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752473431] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:25,124 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:25,124 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:25,124 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220900786] [2022-02-21 04:23:25,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:25,124 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:25,124 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:25,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:25,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:25,125 INFO L87 Difference]: Start difference. First operand 1790 states and 2646 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,401 INFO L93 Difference]: Finished difference Result 1790 states and 2645 transitions. [2022-02-21 04:23:26,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:26,401 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,491 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:26,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:26,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2645 transitions. [2022-02-21 04:23:26,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:26,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:26,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:26,631 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-02-21 04:23:26,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:26,647 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:26,649 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2645 transitions. Second operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,650 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2645 transitions. Second operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,651 INFO L87 Difference]: Start difference. First operand 1790 states and 2645 transitions. Second operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,715 INFO L93 Difference]: Finished difference Result 1790 states and 2645 transitions. [2022-02-21 04:23:26,716 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,717 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,717 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,719 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,720 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:26,784 INFO L93 Difference]: Finished difference Result 1790 states and 2645 transitions. [2022-02-21 04:23:26,784 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,786 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:26,786 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:26,786 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:26,786 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:26,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4776536312849162) internal successors, (2645), 1789 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:26,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2645 transitions. [2022-02-21 04:23:26,851 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-02-21 04:23:26,851 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2645 transitions. [2022-02-21 04:23:26,851 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:26,851 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2645 transitions. [2022-02-21 04:23:26,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:26,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:26,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:26,855 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:26,855 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:26,855 INFO L791 eck$LassoCheckResult]: Stem: 76139#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 76140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 75563#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75536#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75537#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 76793#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75840#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75293#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75294#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76565#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76704#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77070#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77071#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76052#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76053#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76591#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76511#L908-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 76512#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76664#L1206 assume !(0 == ~M_E~0); 76029#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76030#L1211-1 assume !(0 == ~T2_E~0); 76923#L1216-1 assume !(0 == ~T3_E~0); 75822#L1221-1 assume !(0 == ~T4_E~0); 75823#L1226-1 assume !(0 == ~T5_E~0); 75487#L1231-1 assume !(0 == ~T6_E~0); 75488#L1236-1 assume !(0 == ~T7_E~0); 76954#L1241-1 assume !(0 == ~T8_E~0); 75884#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 75885#L1251-1 assume !(0 == ~T10_E~0); 76105#L1256-1 assume !(0 == ~T11_E~0); 75305#L1261-1 assume !(0 == ~T12_E~0); 75306#L1266-1 assume !(0 == ~E_M~0); 77057#L1271-1 assume !(0 == ~E_1~0); 76692#L1276-1 assume !(0 == ~E_2~0); 76693#L1281-1 assume !(0 == ~E_3~0); 76620#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 75726#L1291-1 assume !(0 == ~E_5~0); 75727#L1296-1 assume !(0 == ~E_6~0); 76433#L1301-1 assume !(0 == ~E_7~0); 76434#L1306-1 assume !(0 == ~E_8~0); 76866#L1311-1 assume !(0 == ~E_9~0); 75687#L1316-1 assume !(0 == ~E_10~0); 75688#L1321-1 assume !(0 == ~E_11~0); 76450#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 75553#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75554#L598 assume 1 == ~m_pc~0; 75611#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 75612#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76936#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77028#L1497 assume !(0 != activate_threads_~tmp~1#1); 77029#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76985#L617 assume !(1 == ~t1_pc~0); 75907#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75908#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75767#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75768#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76528#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76529#L636 assume 1 == ~t2_pc~0; 75876#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75877#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75707#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75708#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 76564#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76228#L655 assume !(1 == ~t3_pc~0); 76229#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76941#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75581#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75582#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 77058#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77059#L674 assume 1 == ~t4_pc~0; 75401#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 75402#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76699#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75711#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 75712#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76224#L693 assume !(1 == ~t5_pc~0); 76387#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76034#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76035#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76868#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 76117#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76054#L712 assume 1 == ~t6_pc~0; 76055#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76482#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76483#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76769#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 76580#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76578#L731 assume 1 == ~t7_pc~0; 75555#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75556#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75752#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76688#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 76806#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75665#L750 assume !(1 == ~t8_pc~0); 75336#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75335#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75851#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76881#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75988#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75989#L769 assume 1 == ~t9_pc~0; 76526#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75509#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75510#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76293#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 76745#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76826#L788 assume !(1 == ~t10_pc~0); 76401#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76402#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76635#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76636#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 75663#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75664#L807 assume 1 == ~t11_pc~0; 76835#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76413#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76566#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76977#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 77082#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76925#L826 assume !(1 == ~t12_pc~0); 76059#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76060#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76586#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77017#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 76217#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76126#L1344 assume !(1 == ~M_E~0); 76127#L1344-2 assume !(1 == ~T1_E~0); 76268#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76441#L1354-1 assume !(1 == ~T3_E~0); 76442#L1359-1 assume !(1 == ~T4_E~0); 76815#L1364-1 assume !(1 == ~T5_E~0); 75769#L1369-1 assume !(1 == ~T6_E~0); 75770#L1374-1 assume !(1 == ~T7_E~0); 76448#L1379-1 assume !(1 == ~T8_E~0); 76449#L1384-1 assume !(1 == ~T9_E~0); 76510#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76956#L1394-1 assume !(1 == ~T11_E~0); 76957#L1399-1 assume !(1 == ~T12_E~0); 77036#L1404-1 assume !(1 == ~E_M~0); 75888#L1409-1 assume !(1 == ~E_1~0); 75889#L1414-1 assume !(1 == ~E_2~0); 76726#L1419-1 assume !(1 == ~E_3~0); 75522#L1424-1 assume !(1 == ~E_4~0); 75523#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 76460#L1434-1 assume !(1 == ~E_6~0); 76975#L1439-1 assume !(1 == ~E_7~0); 75577#L1444-1 assume !(1 == ~E_8~0); 75578#L1449-1 assume !(1 == ~E_9~0); 75993#L1454-1 assume !(1 == ~E_10~0); 75994#L1459-1 assume !(1 == ~E_11~0); 76544#L1464-1 assume !(1 == ~E_12~0); 76545#L1469-1 assume { :end_inline_reset_delta_events } true; 76592#L1815-2 [2022-02-21 04:23:26,856 INFO L793 eck$LassoCheckResult]: Loop: 76592#L1815-2 assume !false; 76746#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76415#L1181 assume !false; 76486#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76438#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 75296#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 76026#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 76576#L1008 assume !(0 != eval_~tmp~0#1); 76577#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75517#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75518#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77076#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76543#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75649#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75650#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76240#L1226-3 assume !(0 == ~T5_E~0); 75713#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75714#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76025#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 77013#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 76916#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 76652#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 75671#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 75672#L1266-3 assume !(0 == ~E_M~0); 75709#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 75710#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76184#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76185#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76722#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76723#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77065#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77033#L1306-3 assume !(0 == ~E_8~0); 76309#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 75595#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 75596#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 75673#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 76407#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76733#L598-42 assume 1 == ~m_pc~0; 76735#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76848#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75750#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75751#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 77034#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76464#L617-42 assume !(1 == ~t1_pc~0); 76237#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 76101#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76102#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76516#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75816#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75817#L636-42 assume !(1 == ~t2_pc~0); 76280#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 76281#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76631#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76632#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76811#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76673#L655-42 assume 1 == ~t3_pc~0; 76674#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76254#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75886#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75887#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76940#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76885#L674-42 assume !(1 == ~t4_pc~0); 76659#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 76581#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75470#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75471#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76385#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76386#L693-42 assume 1 == ~t5_pc~0; 76641#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76642#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76702#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76697#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76698#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76000#L712-42 assume !(1 == ~t6_pc~0); 76001#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 76327#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76535#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76536#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76109#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76110#L731-42 assume !(1 == ~t7_pc~0); 75808#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 75809#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76876#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76017#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76018#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75721#L750-42 assume !(1 == ~t8_pc~0); 75723#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 76296#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76719#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75614#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75615#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76384#L769-42 assume !(1 == ~t9_pc~0); 76208#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 76207#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76890#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76955#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 75818#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75819#L788-42 assume !(1 == ~t10_pc~0); 76393#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 76606#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76336#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76337#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77074#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77052#L807-42 assume 1 == ~t11_pc~0; 76741#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75423#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75561#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75562#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75564#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75813#L826-42 assume !(1 == ~t12_pc~0); 75815#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 76006#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76798#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75803#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 75804#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76655#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76656#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76582#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75963#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75964#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76596#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77054#L1369-3 assume !(1 == ~T6_E~0); 76974#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 75728#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75729#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75961#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75962#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76260#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 76983#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76946#L1409-3 assume !(1 == ~E_1~0); 76947#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77012#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76792#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75629#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 75630#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76595#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75569#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75570#L1449-3 assume !(1 == ~E_9~0); 75679#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 76589#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 76590#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 76971#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76469#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 75468#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 75469#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 76085#L1834 assume !(0 == start_simulation_~tmp~3#1); 76705#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 76728#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 76162#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 76341#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 76553#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76961#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75454#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 75455#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 76592#L1815-2 [2022-02-21 04:23:26,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:26,856 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-02-21 04:23:26,857 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:26,857 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210950526] [2022-02-21 04:23:26,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:26,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:26,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:26,888 INFO L290 TraceCheckUtils]: 0: Hoare triple {80666#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {80666#true} is VALID [2022-02-21 04:23:26,888 INFO L290 TraceCheckUtils]: 1: Hoare triple {80666#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,889 INFO L290 TraceCheckUtils]: 2: Hoare triple {80668#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,889 INFO L290 TraceCheckUtils]: 3: Hoare triple {80668#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,889 INFO L290 TraceCheckUtils]: 4: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,889 INFO L290 TraceCheckUtils]: 5: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,890 INFO L290 TraceCheckUtils]: 6: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,890 INFO L290 TraceCheckUtils]: 7: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,890 INFO L290 TraceCheckUtils]: 8: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,890 INFO L290 TraceCheckUtils]: 9: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,891 INFO L290 TraceCheckUtils]: 10: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,891 INFO L290 TraceCheckUtils]: 11: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,891 INFO L290 TraceCheckUtils]: 12: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,892 INFO L290 TraceCheckUtils]: 13: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,892 INFO L290 TraceCheckUtils]: 14: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,892 INFO L290 TraceCheckUtils]: 15: Hoare triple {80668#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {80668#(= ~t12_i~0 1)} is VALID [2022-02-21 04:23:26,892 INFO L290 TraceCheckUtils]: 16: Hoare triple {80668#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {80667#false} is VALID [2022-02-21 04:23:26,892 INFO L290 TraceCheckUtils]: 17: Hoare triple {80667#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 18: Hoare triple {80667#false} assume !(0 == ~M_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 19: Hoare triple {80667#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 20: Hoare triple {80667#false} assume !(0 == ~T2_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 21: Hoare triple {80667#false} assume !(0 == ~T3_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 22: Hoare triple {80667#false} assume !(0 == ~T4_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 23: Hoare triple {80667#false} assume !(0 == ~T5_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 24: Hoare triple {80667#false} assume !(0 == ~T6_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 25: Hoare triple {80667#false} assume !(0 == ~T7_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 26: Hoare triple {80667#false} assume !(0 == ~T8_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 27: Hoare triple {80667#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 28: Hoare triple {80667#false} assume !(0 == ~T10_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 29: Hoare triple {80667#false} assume !(0 == ~T11_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 30: Hoare triple {80667#false} assume !(0 == ~T12_E~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 31: Hoare triple {80667#false} assume !(0 == ~E_M~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 32: Hoare triple {80667#false} assume !(0 == ~E_1~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 33: Hoare triple {80667#false} assume !(0 == ~E_2~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 34: Hoare triple {80667#false} assume !(0 == ~E_3~0); {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 35: Hoare triple {80667#false} assume 0 == ~E_4~0;~E_4~0 := 1; {80667#false} is VALID [2022-02-21 04:23:26,893 INFO L290 TraceCheckUtils]: 36: Hoare triple {80667#false} assume !(0 == ~E_5~0); {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 37: Hoare triple {80667#false} assume !(0 == ~E_6~0); {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 38: Hoare triple {80667#false} assume !(0 == ~E_7~0); {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 39: Hoare triple {80667#false} assume !(0 == ~E_8~0); {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 40: Hoare triple {80667#false} assume !(0 == ~E_9~0); {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 41: Hoare triple {80667#false} assume !(0 == ~E_10~0); {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 42: Hoare triple {80667#false} assume !(0 == ~E_11~0); {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 43: Hoare triple {80667#false} assume 0 == ~E_12~0;~E_12~0 := 1; {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 44: Hoare triple {80667#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 45: Hoare triple {80667#false} assume 1 == ~m_pc~0; {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 46: Hoare triple {80667#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {80667#false} is VALID [2022-02-21 04:23:26,894 INFO L290 TraceCheckUtils]: 47: Hoare triple {80667#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 48: Hoare triple {80667#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 49: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp~1#1); {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 50: Hoare triple {80667#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 51: Hoare triple {80667#false} assume !(1 == ~t1_pc~0); {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 52: Hoare triple {80667#false} is_transmit1_triggered_~__retres1~1#1 := 0; {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 53: Hoare triple {80667#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 54: Hoare triple {80667#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 55: Hoare triple {80667#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {80667#false} is VALID [2022-02-21 04:23:26,895 INFO L290 TraceCheckUtils]: 56: Hoare triple {80667#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 57: Hoare triple {80667#false} assume 1 == ~t2_pc~0; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 58: Hoare triple {80667#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 59: Hoare triple {80667#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 60: Hoare triple {80667#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 61: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___1~0#1); {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 62: Hoare triple {80667#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 63: Hoare triple {80667#false} assume !(1 == ~t3_pc~0); {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 64: Hoare triple {80667#false} is_transmit3_triggered_~__retres1~3#1 := 0; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 65: Hoare triple {80667#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {80667#false} is VALID [2022-02-21 04:23:26,896 INFO L290 TraceCheckUtils]: 66: Hoare triple {80667#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 67: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___2~0#1); {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 68: Hoare triple {80667#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 69: Hoare triple {80667#false} assume 1 == ~t4_pc~0; {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 70: Hoare triple {80667#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 71: Hoare triple {80667#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 72: Hoare triple {80667#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 73: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___3~0#1); {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 74: Hoare triple {80667#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {80667#false} is VALID [2022-02-21 04:23:26,897 INFO L290 TraceCheckUtils]: 75: Hoare triple {80667#false} assume !(1 == ~t5_pc~0); {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 76: Hoare triple {80667#false} is_transmit5_triggered_~__retres1~5#1 := 0; {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 77: Hoare triple {80667#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 78: Hoare triple {80667#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 79: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___4~0#1); {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 80: Hoare triple {80667#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 81: Hoare triple {80667#false} assume 1 == ~t6_pc~0; {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 82: Hoare triple {80667#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 83: Hoare triple {80667#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {80667#false} is VALID [2022-02-21 04:23:26,898 INFO L290 TraceCheckUtils]: 84: Hoare triple {80667#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 85: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___5~0#1); {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 86: Hoare triple {80667#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 87: Hoare triple {80667#false} assume 1 == ~t7_pc~0; {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 88: Hoare triple {80667#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 89: Hoare triple {80667#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 90: Hoare triple {80667#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 91: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___6~0#1); {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 92: Hoare triple {80667#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 93: Hoare triple {80667#false} assume !(1 == ~t8_pc~0); {80667#false} is VALID [2022-02-21 04:23:26,899 INFO L290 TraceCheckUtils]: 94: Hoare triple {80667#false} is_transmit8_triggered_~__retres1~8#1 := 0; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 95: Hoare triple {80667#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 96: Hoare triple {80667#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 97: Hoare triple {80667#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 98: Hoare triple {80667#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 99: Hoare triple {80667#false} assume 1 == ~t9_pc~0; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 100: Hoare triple {80667#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 101: Hoare triple {80667#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 102: Hoare triple {80667#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {80667#false} is VALID [2022-02-21 04:23:26,900 INFO L290 TraceCheckUtils]: 103: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___8~0#1); {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 104: Hoare triple {80667#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 105: Hoare triple {80667#false} assume !(1 == ~t10_pc~0); {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 106: Hoare triple {80667#false} is_transmit10_triggered_~__retres1~10#1 := 0; {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 107: Hoare triple {80667#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 108: Hoare triple {80667#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 109: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___9~0#1); {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 110: Hoare triple {80667#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 111: Hoare triple {80667#false} assume 1 == ~t11_pc~0; {80667#false} is VALID [2022-02-21 04:23:26,901 INFO L290 TraceCheckUtils]: 112: Hoare triple {80667#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 113: Hoare triple {80667#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 114: Hoare triple {80667#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 115: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___10~0#1); {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 116: Hoare triple {80667#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 117: Hoare triple {80667#false} assume !(1 == ~t12_pc~0); {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 118: Hoare triple {80667#false} is_transmit12_triggered_~__retres1~12#1 := 0; {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 119: Hoare triple {80667#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 120: Hoare triple {80667#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {80667#false} is VALID [2022-02-21 04:23:26,902 INFO L290 TraceCheckUtils]: 121: Hoare triple {80667#false} assume !(0 != activate_threads_~tmp___11~0#1); {80667#false} is VALID [2022-02-21 04:23:26,903 INFO L290 TraceCheckUtils]: 122: Hoare triple {80667#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {80667#false} is VALID [2022-02-21 04:23:26,906 INFO L290 TraceCheckUtils]: 123: Hoare triple {80667#false} assume !(1 == ~M_E~0); {80667#false} is VALID [2022-02-21 04:23:26,906 INFO L290 TraceCheckUtils]: 124: Hoare triple {80667#false} assume !(1 == ~T1_E~0); {80667#false} is VALID [2022-02-21 04:23:26,906 INFO L290 TraceCheckUtils]: 125: Hoare triple {80667#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {80667#false} is VALID [2022-02-21 04:23:26,906 INFO L290 TraceCheckUtils]: 126: Hoare triple {80667#false} assume !(1 == ~T3_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 127: Hoare triple {80667#false} assume !(1 == ~T4_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 128: Hoare triple {80667#false} assume !(1 == ~T5_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 129: Hoare triple {80667#false} assume !(1 == ~T6_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 130: Hoare triple {80667#false} assume !(1 == ~T7_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 131: Hoare triple {80667#false} assume !(1 == ~T8_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 132: Hoare triple {80667#false} assume !(1 == ~T9_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 133: Hoare triple {80667#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 134: Hoare triple {80667#false} assume !(1 == ~T11_E~0); {80667#false} is VALID [2022-02-21 04:23:26,907 INFO L290 TraceCheckUtils]: 135: Hoare triple {80667#false} assume !(1 == ~T12_E~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 136: Hoare triple {80667#false} assume !(1 == ~E_M~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 137: Hoare triple {80667#false} assume !(1 == ~E_1~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 138: Hoare triple {80667#false} assume !(1 == ~E_2~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 139: Hoare triple {80667#false} assume !(1 == ~E_3~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 140: Hoare triple {80667#false} assume !(1 == ~E_4~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 141: Hoare triple {80667#false} assume 1 == ~E_5~0;~E_5~0 := 2; {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 142: Hoare triple {80667#false} assume !(1 == ~E_6~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 143: Hoare triple {80667#false} assume !(1 == ~E_7~0); {80667#false} is VALID [2022-02-21 04:23:26,908 INFO L290 TraceCheckUtils]: 144: Hoare triple {80667#false} assume !(1 == ~E_8~0); {80667#false} is VALID [2022-02-21 04:23:26,909 INFO L290 TraceCheckUtils]: 145: Hoare triple {80667#false} assume !(1 == ~E_9~0); {80667#false} is VALID [2022-02-21 04:23:26,909 INFO L290 TraceCheckUtils]: 146: Hoare triple {80667#false} assume !(1 == ~E_10~0); {80667#false} is VALID [2022-02-21 04:23:26,909 INFO L290 TraceCheckUtils]: 147: Hoare triple {80667#false} assume !(1 == ~E_11~0); {80667#false} is VALID [2022-02-21 04:23:26,909 INFO L290 TraceCheckUtils]: 148: Hoare triple {80667#false} assume !(1 == ~E_12~0); {80667#false} is VALID [2022-02-21 04:23:26,909 INFO L290 TraceCheckUtils]: 149: Hoare triple {80667#false} assume { :end_inline_reset_delta_events } true; {80667#false} is VALID [2022-02-21 04:23:26,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:26,909 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:26,910 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210950526] [2022-02-21 04:23:26,910 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210950526] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:26,910 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:26,910 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:26,910 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1873941743] [2022-02-21 04:23:26,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:26,910 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:26,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:26,912 INFO L85 PathProgramCache]: Analyzing trace with hash 81996120, now seen corresponding path program 1 times [2022-02-21 04:23:26,912 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:26,912 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340353734] [2022-02-21 04:23:26,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:26,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:26,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:26,942 INFO L290 TraceCheckUtils]: 0: Hoare triple {80669#true} assume !false; {80669#true} is VALID [2022-02-21 04:23:26,942 INFO L290 TraceCheckUtils]: 1: Hoare triple {80669#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {80669#true} is VALID [2022-02-21 04:23:26,942 INFO L290 TraceCheckUtils]: 2: Hoare triple {80669#true} assume !false; {80669#true} is VALID [2022-02-21 04:23:26,942 INFO L290 TraceCheckUtils]: 3: Hoare triple {80669#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {80669#true} is VALID [2022-02-21 04:23:26,942 INFO L290 TraceCheckUtils]: 4: Hoare triple {80669#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 5: Hoare triple {80669#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 6: Hoare triple {80669#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 7: Hoare triple {80669#true} assume !(0 != eval_~tmp~0#1); {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 8: Hoare triple {80669#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 9: Hoare triple {80669#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 10: Hoare triple {80669#true} assume 0 == ~M_E~0;~M_E~0 := 1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 11: Hoare triple {80669#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 12: Hoare triple {80669#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 13: Hoare triple {80669#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 14: Hoare triple {80669#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 15: Hoare triple {80669#true} assume !(0 == ~T5_E~0); {80669#true} is VALID [2022-02-21 04:23:26,943 INFO L290 TraceCheckUtils]: 16: Hoare triple {80669#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,944 INFO L290 TraceCheckUtils]: 17: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,944 INFO L290 TraceCheckUtils]: 18: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,944 INFO L290 TraceCheckUtils]: 19: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,944 INFO L290 TraceCheckUtils]: 20: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,945 INFO L290 TraceCheckUtils]: 21: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,945 INFO L290 TraceCheckUtils]: 22: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,945 INFO L290 TraceCheckUtils]: 23: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,945 INFO L290 TraceCheckUtils]: 24: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,946 INFO L290 TraceCheckUtils]: 25: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,946 INFO L290 TraceCheckUtils]: 26: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,946 INFO L290 TraceCheckUtils]: 27: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,946 INFO L290 TraceCheckUtils]: 28: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,947 INFO L290 TraceCheckUtils]: 29: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,947 INFO L290 TraceCheckUtils]: 30: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,947 INFO L290 TraceCheckUtils]: 31: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,947 INFO L290 TraceCheckUtils]: 32: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,948 INFO L290 TraceCheckUtils]: 33: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,948 INFO L290 TraceCheckUtils]: 34: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,948 INFO L290 TraceCheckUtils]: 35: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,948 INFO L290 TraceCheckUtils]: 36: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,949 INFO L290 TraceCheckUtils]: 37: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,949 INFO L290 TraceCheckUtils]: 38: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,949 INFO L290 TraceCheckUtils]: 39: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,949 INFO L290 TraceCheckUtils]: 40: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,950 INFO L290 TraceCheckUtils]: 41: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,950 INFO L290 TraceCheckUtils]: 42: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,950 INFO L290 TraceCheckUtils]: 43: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,950 INFO L290 TraceCheckUtils]: 44: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,951 INFO L290 TraceCheckUtils]: 45: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,951 INFO L290 TraceCheckUtils]: 46: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,951 INFO L290 TraceCheckUtils]: 47: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,952 INFO L290 TraceCheckUtils]: 48: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,952 INFO L290 TraceCheckUtils]: 49: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,952 INFO L290 TraceCheckUtils]: 50: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,952 INFO L290 TraceCheckUtils]: 51: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,953 INFO L290 TraceCheckUtils]: 52: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,953 INFO L290 TraceCheckUtils]: 53: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,953 INFO L290 TraceCheckUtils]: 54: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,953 INFO L290 TraceCheckUtils]: 55: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,954 INFO L290 TraceCheckUtils]: 56: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,954 INFO L290 TraceCheckUtils]: 57: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,954 INFO L290 TraceCheckUtils]: 58: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,954 INFO L290 TraceCheckUtils]: 59: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,955 INFO L290 TraceCheckUtils]: 60: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,955 INFO L290 TraceCheckUtils]: 61: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,955 INFO L290 TraceCheckUtils]: 62: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,955 INFO L290 TraceCheckUtils]: 63: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,956 INFO L290 TraceCheckUtils]: 64: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,956 INFO L290 TraceCheckUtils]: 65: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,956 INFO L290 TraceCheckUtils]: 66: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,956 INFO L290 TraceCheckUtils]: 67: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,957 INFO L290 TraceCheckUtils]: 68: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,957 INFO L290 TraceCheckUtils]: 69: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,957 INFO L290 TraceCheckUtils]: 70: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,957 INFO L290 TraceCheckUtils]: 71: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,958 INFO L290 TraceCheckUtils]: 72: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,958 INFO L290 TraceCheckUtils]: 73: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,958 INFO L290 TraceCheckUtils]: 74: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,958 INFO L290 TraceCheckUtils]: 75: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,959 INFO L290 TraceCheckUtils]: 76: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,959 INFO L290 TraceCheckUtils]: 77: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,959 INFO L290 TraceCheckUtils]: 78: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,959 INFO L290 TraceCheckUtils]: 79: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,960 INFO L290 TraceCheckUtils]: 80: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,960 INFO L290 TraceCheckUtils]: 81: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,960 INFO L290 TraceCheckUtils]: 82: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,960 INFO L290 TraceCheckUtils]: 83: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,961 INFO L290 TraceCheckUtils]: 84: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,961 INFO L290 TraceCheckUtils]: 85: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,961 INFO L290 TraceCheckUtils]: 86: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,961 INFO L290 TraceCheckUtils]: 87: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,962 INFO L290 TraceCheckUtils]: 88: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,962 INFO L290 TraceCheckUtils]: 89: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,962 INFO L290 TraceCheckUtils]: 90: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,962 INFO L290 TraceCheckUtils]: 91: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,963 INFO L290 TraceCheckUtils]: 92: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,963 INFO L290 TraceCheckUtils]: 93: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,963 INFO L290 TraceCheckUtils]: 94: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,963 INFO L290 TraceCheckUtils]: 95: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,964 INFO L290 TraceCheckUtils]: 96: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,964 INFO L290 TraceCheckUtils]: 97: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t10_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,964 INFO L290 TraceCheckUtils]: 98: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,964 INFO L290 TraceCheckUtils]: 99: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,965 INFO L290 TraceCheckUtils]: 100: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,965 INFO L290 TraceCheckUtils]: 101: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,965 INFO L290 TraceCheckUtils]: 102: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,965 INFO L290 TraceCheckUtils]: 103: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,966 INFO L290 TraceCheckUtils]: 104: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,966 INFO L290 TraceCheckUtils]: 105: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,966 INFO L290 TraceCheckUtils]: 106: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,966 INFO L290 TraceCheckUtils]: 107: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,967 INFO L290 TraceCheckUtils]: 108: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,967 INFO L290 TraceCheckUtils]: 109: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t12_pc~0); {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,967 INFO L290 TraceCheckUtils]: 110: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,967 INFO L290 TraceCheckUtils]: 111: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,968 INFO L290 TraceCheckUtils]: 112: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,968 INFO L290 TraceCheckUtils]: 113: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,968 INFO L290 TraceCheckUtils]: 114: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,968 INFO L290 TraceCheckUtils]: 115: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,969 INFO L290 TraceCheckUtils]: 116: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,969 INFO L290 TraceCheckUtils]: 117: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,969 INFO L290 TraceCheckUtils]: 118: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,969 INFO L290 TraceCheckUtils]: 119: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 120: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {80671#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 121: Hoare triple {80671#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 122: Hoare triple {80670#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 123: Hoare triple {80670#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 124: Hoare triple {80670#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 125: Hoare triple {80670#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 126: Hoare triple {80670#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 127: Hoare triple {80670#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 128: Hoare triple {80670#false} assume 1 == ~E_M~0;~E_M~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 129: Hoare triple {80670#false} assume !(1 == ~E_1~0); {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 130: Hoare triple {80670#false} assume 1 == ~E_2~0;~E_2~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,970 INFO L290 TraceCheckUtils]: 131: Hoare triple {80670#false} assume 1 == ~E_3~0;~E_3~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 132: Hoare triple {80670#false} assume 1 == ~E_4~0;~E_4~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 133: Hoare triple {80670#false} assume 1 == ~E_5~0;~E_5~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 134: Hoare triple {80670#false} assume 1 == ~E_6~0;~E_6~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 135: Hoare triple {80670#false} assume 1 == ~E_7~0;~E_7~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 136: Hoare triple {80670#false} assume 1 == ~E_8~0;~E_8~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 137: Hoare triple {80670#false} assume !(1 == ~E_9~0); {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 138: Hoare triple {80670#false} assume 1 == ~E_10~0;~E_10~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 139: Hoare triple {80670#false} assume 1 == ~E_11~0;~E_11~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 140: Hoare triple {80670#false} assume 1 == ~E_12~0;~E_12~0 := 2; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 141: Hoare triple {80670#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 142: Hoare triple {80670#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 143: Hoare triple {80670#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 144: Hoare triple {80670#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 145: Hoare triple {80670#false} assume !(0 == start_simulation_~tmp~3#1); {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 146: Hoare triple {80670#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 147: Hoare triple {80670#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 148: Hoare triple {80670#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 149: Hoare triple {80670#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {80670#false} is VALID [2022-02-21 04:23:26,971 INFO L290 TraceCheckUtils]: 150: Hoare triple {80670#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {80670#false} is VALID [2022-02-21 04:23:26,972 INFO L290 TraceCheckUtils]: 151: Hoare triple {80670#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {80670#false} is VALID [2022-02-21 04:23:26,972 INFO L290 TraceCheckUtils]: 152: Hoare triple {80670#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {80670#false} is VALID [2022-02-21 04:23:26,972 INFO L290 TraceCheckUtils]: 153: Hoare triple {80670#false} assume !(0 != start_simulation_~tmp___0~1#1); {80670#false} is VALID [2022-02-21 04:23:26,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:26,972 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:26,972 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340353734] [2022-02-21 04:23:26,972 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340353734] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:26,972 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:26,972 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:26,973 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029096198] [2022-02-21 04:23:26,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:26,973 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:26,973 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:26,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:26,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:26,974 INFO L87 Difference]: Start difference. First operand 1790 states and 2645 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,109 INFO L93 Difference]: Finished difference Result 1790 states and 2644 transitions. [2022-02-21 04:23:28,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:28,110 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,158 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:28,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:28,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2644 transitions. [2022-02-21 04:23:28,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:28,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:28,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:28,292 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-02-21 04:23:28,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:28,304 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:28,306 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2644 transitions. Second operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,307 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2644 transitions. Second operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,307 INFO L87 Difference]: Start difference. First operand 1790 states and 2644 transitions. Second operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,371 INFO L93 Difference]: Finished difference Result 1790 states and 2644 transitions. [2022-02-21 04:23:28,371 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,373 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:28,373 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:28,375 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,375 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:28,440 INFO L93 Difference]: Finished difference Result 1790 states and 2644 transitions. [2022-02-21 04:23:28,440 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,441 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:28,441 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:28,441 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:28,442 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:28,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4770949720670392) internal successors, (2644), 1789 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:28,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2644 transitions. [2022-02-21 04:23:28,507 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-02-21 04:23:28,507 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2644 transitions. [2022-02-21 04:23:28,507 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:23:28,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2644 transitions. [2022-02-21 04:23:28,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:28,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:28,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:28,511 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:28,511 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:28,511 INFO L791 eck$LassoCheckResult]: Stem: 83306#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 83307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 82732#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82700#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82701#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 83962#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83009#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82462#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82463#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83734#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83873#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84239#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84240#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83221#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 83222#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 83760#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 83680#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 83681#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83833#L1206 assume !(0 == ~M_E~0); 83198#L1206-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83199#L1211-1 assume !(0 == ~T2_E~0); 84092#L1216-1 assume !(0 == ~T3_E~0); 82991#L1221-1 assume !(0 == ~T4_E~0); 82992#L1226-1 assume !(0 == ~T5_E~0); 82654#L1231-1 assume !(0 == ~T6_E~0); 82655#L1236-1 assume !(0 == ~T7_E~0); 84123#L1241-1 assume !(0 == ~T8_E~0); 83053#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 83054#L1251-1 assume !(0 == ~T10_E~0); 83274#L1256-1 assume !(0 == ~T11_E~0); 82474#L1261-1 assume !(0 == ~T12_E~0); 82475#L1266-1 assume !(0 == ~E_M~0); 84226#L1271-1 assume !(0 == ~E_1~0); 83861#L1276-1 assume !(0 == ~E_2~0); 83862#L1281-1 assume !(0 == ~E_3~0); 83787#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 82895#L1291-1 assume !(0 == ~E_5~0); 82896#L1296-1 assume !(0 == ~E_6~0); 83602#L1301-1 assume !(0 == ~E_7~0); 83603#L1306-1 assume !(0 == ~E_8~0); 84035#L1311-1 assume !(0 == ~E_9~0); 82856#L1316-1 assume !(0 == ~E_10~0); 82857#L1321-1 assume !(0 == ~E_11~0); 83619#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 82720#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82721#L598 assume 1 == ~m_pc~0; 82780#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 82781#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84105#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84197#L1497 assume !(0 != activate_threads_~tmp~1#1); 84198#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84154#L617 assume !(1 == ~t1_pc~0); 83076#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83077#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82936#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82937#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 83697#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83698#L636 assume 1 == ~t2_pc~0; 83045#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 83046#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82876#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82877#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 83733#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83396#L655 assume !(1 == ~t3_pc~0); 83397#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84110#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82750#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82751#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 84227#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84228#L674 assume 1 == ~t4_pc~0; 82570#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82571#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83868#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82878#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 82879#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83393#L693 assume !(1 == ~t5_pc~0); 83556#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 83201#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83202#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84037#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 83286#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83223#L712 assume 1 == ~t6_pc~0; 83224#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83651#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83652#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83938#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 83749#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83747#L731 assume 1 == ~t7_pc~0; 82724#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82725#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82919#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83856#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 83975#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82834#L750 assume !(1 == ~t8_pc~0); 82505#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82504#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83020#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84050#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83157#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83158#L769 assume 1 == ~t9_pc~0; 83695#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82678#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82679#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83462#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 83914#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 83995#L788 assume !(1 == ~t10_pc~0); 83570#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 83571#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83803#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 83804#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 82830#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82831#L807 assume 1 == ~t11_pc~0; 84004#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 83582#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 83735#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84146#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 84251#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84094#L826 assume !(1 == ~t12_pc~0); 83226#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 83227#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83755#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84186#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 83386#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83295#L1344 assume !(1 == ~M_E~0); 83296#L1344-2 assume !(1 == ~T1_E~0); 83437#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83610#L1354-1 assume !(1 == ~T3_E~0); 83611#L1359-1 assume !(1 == ~T4_E~0); 83984#L1364-1 assume !(1 == ~T5_E~0); 82938#L1369-1 assume !(1 == ~T6_E~0); 82939#L1374-1 assume !(1 == ~T7_E~0); 83617#L1379-1 assume !(1 == ~T8_E~0); 83618#L1384-1 assume !(1 == ~T9_E~0); 83679#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 84125#L1394-1 assume !(1 == ~T11_E~0); 84126#L1399-1 assume !(1 == ~T12_E~0); 84205#L1404-1 assume !(1 == ~E_M~0); 83057#L1409-1 assume !(1 == ~E_1~0); 83058#L1414-1 assume !(1 == ~E_2~0); 83895#L1419-1 assume !(1 == ~E_3~0); 82691#L1424-1 assume !(1 == ~E_4~0); 82692#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 83626#L1434-1 assume !(1 == ~E_6~0); 84144#L1439-1 assume !(1 == ~E_7~0); 82746#L1444-1 assume !(1 == ~E_8~0); 82747#L1449-1 assume !(1 == ~E_9~0); 83162#L1454-1 assume !(1 == ~E_10~0); 83163#L1459-1 assume !(1 == ~E_11~0); 83713#L1464-1 assume !(1 == ~E_12~0); 83714#L1469-1 assume { :end_inline_reset_delta_events } true; 83761#L1815-2 [2022-02-21 04:23:28,512 INFO L793 eck$LassoCheckResult]: Loop: 83761#L1815-2 assume !false; 83915#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83584#L1181 assume !false; 83655#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83607#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82465#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83194#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 83745#L1008 assume !(0 != eval_~tmp~0#1); 83746#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82686#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82687#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 84245#L1206-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83712#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82818#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82819#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83409#L1226-3 assume !(0 == ~T5_E~0); 82882#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82883#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 83195#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 84183#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 84085#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 83821#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 82840#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 82841#L1266-3 assume !(0 == ~E_M~0); 82880#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 82881#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83353#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83354#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 83891#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83892#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 84234#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 84202#L1306-3 assume !(0 == ~E_8~0); 83478#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 82764#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 82765#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 82842#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 83577#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83902#L598-42 assume 1 == ~m_pc~0; 83904#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 84017#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82920#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82921#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 84203#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83633#L617-42 assume !(1 == ~t1_pc~0); 83407#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 83270#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83271#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83685#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82985#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82986#L636-42 assume !(1 == ~t2_pc~0); 83449#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 83450#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83800#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83801#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83980#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83842#L655-42 assume 1 == ~t3_pc~0; 83843#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83427#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83055#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83056#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84109#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84054#L674-42 assume !(1 == ~t4_pc~0); 83828#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 83750#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82639#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82640#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83554#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83555#L693-42 assume 1 == ~t5_pc~0; 83813#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83814#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83871#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83866#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 83867#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83169#L712-42 assume 1 == ~t6_pc~0; 83171#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83497#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83704#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83705#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 83278#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83279#L731-42 assume 1 == ~t7_pc~0; 83140#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82975#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84045#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83186#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83187#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82887#L750-42 assume !(1 == ~t8_pc~0); 82889#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 83465#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83888#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82783#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82784#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83553#L769-42 assume 1 == ~t9_pc~0; 83373#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 83374#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84059#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84124#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 82987#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82988#L788-42 assume 1 == ~t10_pc~0; 83561#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 83772#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83505#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 83506#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84243#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84219#L807-42 assume 1 == ~t11_pc~0; 83910#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82592#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82730#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82731#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 82733#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82982#L826-42 assume 1 == ~t12_pc~0; 82983#L827-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 83175#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83967#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82972#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 82973#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83824#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 83825#L1344-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 83751#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83132#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83133#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83765#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84223#L1369-3 assume !(1 == ~T6_E~0); 84143#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 82897#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 82898#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83130#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83131#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83429#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 84152#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84115#L1409-3 assume !(1 == ~E_1~0); 84116#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84181#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 83961#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82798#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82799#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 83764#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82736#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82737#L1449-3 assume !(1 == ~E_9~0); 82848#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 83757#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 83758#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 84140#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83638#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82637#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82638#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 83254#L1834 assume !(0 == start_simulation_~tmp~3#1); 83874#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83897#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83331#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83510#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 83722#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84130#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82623#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 82624#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 83761#L1815-2 [2022-02-21 04:23:28,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:28,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-02-21 04:23:28,513 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:28,513 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23921222] [2022-02-21 04:23:28,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:28,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:28,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:28,566 INFO L290 TraceCheckUtils]: 0: Hoare triple {87835#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,567 INFO L290 TraceCheckUtils]: 1: Hoare triple {87837#(<= 2 ~T1_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,567 INFO L290 TraceCheckUtils]: 2: Hoare triple {87837#(<= 2 ~T1_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,568 INFO L290 TraceCheckUtils]: 3: Hoare triple {87837#(<= 2 ~T1_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,568 INFO L290 TraceCheckUtils]: 4: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,568 INFO L290 TraceCheckUtils]: 5: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,568 INFO L290 TraceCheckUtils]: 6: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,569 INFO L290 TraceCheckUtils]: 7: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,569 INFO L290 TraceCheckUtils]: 8: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,569 INFO L290 TraceCheckUtils]: 9: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,570 INFO L290 TraceCheckUtils]: 10: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,570 INFO L290 TraceCheckUtils]: 11: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,570 INFO L290 TraceCheckUtils]: 12: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,571 INFO L290 TraceCheckUtils]: 13: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,571 INFO L290 TraceCheckUtils]: 14: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,571 INFO L290 TraceCheckUtils]: 15: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,572 INFO L290 TraceCheckUtils]: 16: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,572 INFO L290 TraceCheckUtils]: 17: Hoare triple {87837#(<= 2 ~T1_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,572 INFO L290 TraceCheckUtils]: 18: Hoare triple {87837#(<= 2 ~T1_E~0)} assume !(0 == ~M_E~0); {87837#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 19: Hoare triple {87837#(<= 2 ~T1_E~0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {87836#false} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 20: Hoare triple {87836#false} assume !(0 == ~T2_E~0); {87836#false} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 21: Hoare triple {87836#false} assume !(0 == ~T3_E~0); {87836#false} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 22: Hoare triple {87836#false} assume !(0 == ~T4_E~0); {87836#false} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 23: Hoare triple {87836#false} assume !(0 == ~T5_E~0); {87836#false} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 24: Hoare triple {87836#false} assume !(0 == ~T6_E~0); {87836#false} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 25: Hoare triple {87836#false} assume !(0 == ~T7_E~0); {87836#false} is VALID [2022-02-21 04:23:28,573 INFO L290 TraceCheckUtils]: 26: Hoare triple {87836#false} assume !(0 == ~T8_E~0); {87836#false} is VALID [2022-02-21 04:23:28,574 INFO L290 TraceCheckUtils]: 27: Hoare triple {87836#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {87836#false} is VALID [2022-02-21 04:23:28,574 INFO L290 TraceCheckUtils]: 28: Hoare triple {87836#false} assume !(0 == ~T10_E~0); {87836#false} is VALID [2022-02-21 04:23:28,574 INFO L290 TraceCheckUtils]: 29: Hoare triple {87836#false} assume !(0 == ~T11_E~0); {87836#false} is VALID [2022-02-21 04:23:28,574 INFO L290 TraceCheckUtils]: 30: Hoare triple {87836#false} assume !(0 == ~T12_E~0); {87836#false} is VALID [2022-02-21 04:23:28,574 INFO L290 TraceCheckUtils]: 31: Hoare triple {87836#false} assume !(0 == ~E_M~0); {87836#false} is VALID [2022-02-21 04:23:28,574 INFO L290 TraceCheckUtils]: 32: Hoare triple {87836#false} assume !(0 == ~E_1~0); {87836#false} is VALID [2022-02-21 04:23:28,574 INFO L290 TraceCheckUtils]: 33: Hoare triple {87836#false} assume !(0 == ~E_2~0); {87836#false} is VALID [2022-02-21 04:23:28,575 INFO L290 TraceCheckUtils]: 34: Hoare triple {87836#false} assume !(0 == ~E_3~0); {87836#false} is VALID [2022-02-21 04:23:28,575 INFO L290 TraceCheckUtils]: 35: Hoare triple {87836#false} assume 0 == ~E_4~0;~E_4~0 := 1; {87836#false} is VALID [2022-02-21 04:23:28,575 INFO L290 TraceCheckUtils]: 36: Hoare triple {87836#false} assume !(0 == ~E_5~0); {87836#false} is VALID [2022-02-21 04:23:28,575 INFO L290 TraceCheckUtils]: 37: Hoare triple {87836#false} assume !(0 == ~E_6~0); {87836#false} is VALID [2022-02-21 04:23:28,575 INFO L290 TraceCheckUtils]: 38: Hoare triple {87836#false} assume !(0 == ~E_7~0); {87836#false} is VALID [2022-02-21 04:23:28,575 INFO L290 TraceCheckUtils]: 39: Hoare triple {87836#false} assume !(0 == ~E_8~0); {87836#false} is VALID [2022-02-21 04:23:28,575 INFO L290 TraceCheckUtils]: 40: Hoare triple {87836#false} assume !(0 == ~E_9~0); {87836#false} is VALID [2022-02-21 04:23:28,576 INFO L290 TraceCheckUtils]: 41: Hoare triple {87836#false} assume !(0 == ~E_10~0); {87836#false} is VALID [2022-02-21 04:23:28,576 INFO L290 TraceCheckUtils]: 42: Hoare triple {87836#false} assume !(0 == ~E_11~0); {87836#false} is VALID [2022-02-21 04:23:28,576 INFO L290 TraceCheckUtils]: 43: Hoare triple {87836#false} assume 0 == ~E_12~0;~E_12~0 := 1; {87836#false} is VALID [2022-02-21 04:23:28,576 INFO L290 TraceCheckUtils]: 44: Hoare triple {87836#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {87836#false} is VALID [2022-02-21 04:23:28,576 INFO L290 TraceCheckUtils]: 45: Hoare triple {87836#false} assume 1 == ~m_pc~0; {87836#false} is VALID [2022-02-21 04:23:28,576 INFO L290 TraceCheckUtils]: 46: Hoare triple {87836#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {87836#false} is VALID [2022-02-21 04:23:28,576 INFO L290 TraceCheckUtils]: 47: Hoare triple {87836#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 48: Hoare triple {87836#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 49: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp~1#1); {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 50: Hoare triple {87836#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 51: Hoare triple {87836#false} assume !(1 == ~t1_pc~0); {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 52: Hoare triple {87836#false} is_transmit1_triggered_~__retres1~1#1 := 0; {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 53: Hoare triple {87836#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 54: Hoare triple {87836#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {87836#false} is VALID [2022-02-21 04:23:28,577 INFO L290 TraceCheckUtils]: 55: Hoare triple {87836#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 56: Hoare triple {87836#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 57: Hoare triple {87836#false} assume 1 == ~t2_pc~0; {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 58: Hoare triple {87836#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 59: Hoare triple {87836#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 60: Hoare triple {87836#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 61: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___1~0#1); {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 62: Hoare triple {87836#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {87836#false} is VALID [2022-02-21 04:23:28,578 INFO L290 TraceCheckUtils]: 63: Hoare triple {87836#false} assume !(1 == ~t3_pc~0); {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 64: Hoare triple {87836#false} is_transmit3_triggered_~__retres1~3#1 := 0; {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 65: Hoare triple {87836#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 66: Hoare triple {87836#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 67: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___2~0#1); {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 68: Hoare triple {87836#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 69: Hoare triple {87836#false} assume 1 == ~t4_pc~0; {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 70: Hoare triple {87836#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {87836#false} is VALID [2022-02-21 04:23:28,579 INFO L290 TraceCheckUtils]: 71: Hoare triple {87836#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 72: Hoare triple {87836#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 73: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___3~0#1); {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 74: Hoare triple {87836#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 75: Hoare triple {87836#false} assume !(1 == ~t5_pc~0); {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 76: Hoare triple {87836#false} is_transmit5_triggered_~__retres1~5#1 := 0; {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 77: Hoare triple {87836#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 78: Hoare triple {87836#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {87836#false} is VALID [2022-02-21 04:23:28,580 INFO L290 TraceCheckUtils]: 79: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___4~0#1); {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 80: Hoare triple {87836#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 81: Hoare triple {87836#false} assume 1 == ~t6_pc~0; {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 82: Hoare triple {87836#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 83: Hoare triple {87836#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 84: Hoare triple {87836#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 85: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___5~0#1); {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 86: Hoare triple {87836#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {87836#false} is VALID [2022-02-21 04:23:28,581 INFO L290 TraceCheckUtils]: 87: Hoare triple {87836#false} assume 1 == ~t7_pc~0; {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 88: Hoare triple {87836#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 89: Hoare triple {87836#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 90: Hoare triple {87836#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 91: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___6~0#1); {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 92: Hoare triple {87836#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 93: Hoare triple {87836#false} assume !(1 == ~t8_pc~0); {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 94: Hoare triple {87836#false} is_transmit8_triggered_~__retres1~8#1 := 0; {87836#false} is VALID [2022-02-21 04:23:28,582 INFO L290 TraceCheckUtils]: 95: Hoare triple {87836#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 96: Hoare triple {87836#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 97: Hoare triple {87836#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 98: Hoare triple {87836#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 99: Hoare triple {87836#false} assume 1 == ~t9_pc~0; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 100: Hoare triple {87836#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 101: Hoare triple {87836#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 102: Hoare triple {87836#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 103: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___8~0#1); {87836#false} is VALID [2022-02-21 04:23:28,583 INFO L290 TraceCheckUtils]: 104: Hoare triple {87836#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 105: Hoare triple {87836#false} assume !(1 == ~t10_pc~0); {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 106: Hoare triple {87836#false} is_transmit10_triggered_~__retres1~10#1 := 0; {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 107: Hoare triple {87836#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 108: Hoare triple {87836#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 109: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___9~0#1); {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 110: Hoare triple {87836#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 111: Hoare triple {87836#false} assume 1 == ~t11_pc~0; {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 112: Hoare triple {87836#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {87836#false} is VALID [2022-02-21 04:23:28,584 INFO L290 TraceCheckUtils]: 113: Hoare triple {87836#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 114: Hoare triple {87836#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 115: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___10~0#1); {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 116: Hoare triple {87836#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 117: Hoare triple {87836#false} assume !(1 == ~t12_pc~0); {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 118: Hoare triple {87836#false} is_transmit12_triggered_~__retres1~12#1 := 0; {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 119: Hoare triple {87836#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 120: Hoare triple {87836#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 121: Hoare triple {87836#false} assume !(0 != activate_threads_~tmp___11~0#1); {87836#false} is VALID [2022-02-21 04:23:28,585 INFO L290 TraceCheckUtils]: 122: Hoare triple {87836#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 123: Hoare triple {87836#false} assume !(1 == ~M_E~0); {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 124: Hoare triple {87836#false} assume !(1 == ~T1_E~0); {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 125: Hoare triple {87836#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 126: Hoare triple {87836#false} assume !(1 == ~T3_E~0); {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 127: Hoare triple {87836#false} assume !(1 == ~T4_E~0); {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 128: Hoare triple {87836#false} assume !(1 == ~T5_E~0); {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 129: Hoare triple {87836#false} assume !(1 == ~T6_E~0); {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 130: Hoare triple {87836#false} assume !(1 == ~T7_E~0); {87836#false} is VALID [2022-02-21 04:23:28,586 INFO L290 TraceCheckUtils]: 131: Hoare triple {87836#false} assume !(1 == ~T8_E~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 132: Hoare triple {87836#false} assume !(1 == ~T9_E~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 133: Hoare triple {87836#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 134: Hoare triple {87836#false} assume !(1 == ~T11_E~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 135: Hoare triple {87836#false} assume !(1 == ~T12_E~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 136: Hoare triple {87836#false} assume !(1 == ~E_M~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 137: Hoare triple {87836#false} assume !(1 == ~E_1~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 138: Hoare triple {87836#false} assume !(1 == ~E_2~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 139: Hoare triple {87836#false} assume !(1 == ~E_3~0); {87836#false} is VALID [2022-02-21 04:23:28,587 INFO L290 TraceCheckUtils]: 140: Hoare triple {87836#false} assume !(1 == ~E_4~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 141: Hoare triple {87836#false} assume 1 == ~E_5~0;~E_5~0 := 2; {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 142: Hoare triple {87836#false} assume !(1 == ~E_6~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 143: Hoare triple {87836#false} assume !(1 == ~E_7~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 144: Hoare triple {87836#false} assume !(1 == ~E_8~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 145: Hoare triple {87836#false} assume !(1 == ~E_9~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 146: Hoare triple {87836#false} assume !(1 == ~E_10~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 147: Hoare triple {87836#false} assume !(1 == ~E_11~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 148: Hoare triple {87836#false} assume !(1 == ~E_12~0); {87836#false} is VALID [2022-02-21 04:23:28,588 INFO L290 TraceCheckUtils]: 149: Hoare triple {87836#false} assume { :end_inline_reset_delta_events } true; {87836#false} is VALID [2022-02-21 04:23:28,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:28,589 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:28,589 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23921222] [2022-02-21 04:23:28,589 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23921222] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:28,589 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:28,589 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:28,589 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452648739] [2022-02-21 04:23:28,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:28,590 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:28,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:28,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1462815597, now seen corresponding path program 1 times [2022-02-21 04:23:28,590 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:28,591 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822218096] [2022-02-21 04:23:28,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:28,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:28,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:28,614 INFO L290 TraceCheckUtils]: 0: Hoare triple {87838#true} assume !false; {87838#true} is VALID [2022-02-21 04:23:28,614 INFO L290 TraceCheckUtils]: 1: Hoare triple {87838#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {87838#true} is VALID [2022-02-21 04:23:28,614 INFO L290 TraceCheckUtils]: 2: Hoare triple {87838#true} assume !false; {87838#true} is VALID [2022-02-21 04:23:28,614 INFO L290 TraceCheckUtils]: 3: Hoare triple {87838#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {87838#true} is VALID [2022-02-21 04:23:28,614 INFO L290 TraceCheckUtils]: 4: Hoare triple {87838#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {87838#true} is VALID [2022-02-21 04:23:28,614 INFO L290 TraceCheckUtils]: 5: Hoare triple {87838#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 6: Hoare triple {87838#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 7: Hoare triple {87838#true} assume !(0 != eval_~tmp~0#1); {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 8: Hoare triple {87838#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 9: Hoare triple {87838#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 10: Hoare triple {87838#true} assume 0 == ~M_E~0;~M_E~0 := 1; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 11: Hoare triple {87838#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 12: Hoare triple {87838#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 13: Hoare triple {87838#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {87838#true} is VALID [2022-02-21 04:23:28,615 INFO L290 TraceCheckUtils]: 14: Hoare triple {87838#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {87838#true} is VALID [2022-02-21 04:23:28,616 INFO L290 TraceCheckUtils]: 15: Hoare triple {87838#true} assume !(0 == ~T5_E~0); {87838#true} is VALID [2022-02-21 04:23:28,616 INFO L290 TraceCheckUtils]: 16: Hoare triple {87838#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,616 INFO L290 TraceCheckUtils]: 17: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,616 INFO L290 TraceCheckUtils]: 18: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,617 INFO L290 TraceCheckUtils]: 19: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,617 INFO L290 TraceCheckUtils]: 20: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,617 INFO L290 TraceCheckUtils]: 21: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,617 INFO L290 TraceCheckUtils]: 22: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,618 INFO L290 TraceCheckUtils]: 23: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,618 INFO L290 TraceCheckUtils]: 24: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,618 INFO L290 TraceCheckUtils]: 25: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,619 INFO L290 TraceCheckUtils]: 26: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,619 INFO L290 TraceCheckUtils]: 27: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,619 INFO L290 TraceCheckUtils]: 28: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,619 INFO L290 TraceCheckUtils]: 29: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,620 INFO L290 TraceCheckUtils]: 30: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,620 INFO L290 TraceCheckUtils]: 31: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,620 INFO L290 TraceCheckUtils]: 32: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,620 INFO L290 TraceCheckUtils]: 33: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,621 INFO L290 TraceCheckUtils]: 34: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,621 INFO L290 TraceCheckUtils]: 35: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,621 INFO L290 TraceCheckUtils]: 36: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,621 INFO L290 TraceCheckUtils]: 37: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,622 INFO L290 TraceCheckUtils]: 38: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,622 INFO L290 TraceCheckUtils]: 39: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,622 INFO L290 TraceCheckUtils]: 40: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,623 INFO L290 TraceCheckUtils]: 41: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,623 INFO L290 TraceCheckUtils]: 42: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,623 INFO L290 TraceCheckUtils]: 43: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,623 INFO L290 TraceCheckUtils]: 44: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,624 INFO L290 TraceCheckUtils]: 45: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,624 INFO L290 TraceCheckUtils]: 46: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,624 INFO L290 TraceCheckUtils]: 47: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,624 INFO L290 TraceCheckUtils]: 48: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,625 INFO L290 TraceCheckUtils]: 49: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,625 INFO L290 TraceCheckUtils]: 50: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,625 INFO L290 TraceCheckUtils]: 51: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,625 INFO L290 TraceCheckUtils]: 52: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,626 INFO L290 TraceCheckUtils]: 53: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,626 INFO L290 TraceCheckUtils]: 54: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,626 INFO L290 TraceCheckUtils]: 55: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,626 INFO L290 TraceCheckUtils]: 56: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,627 INFO L290 TraceCheckUtils]: 57: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,627 INFO L290 TraceCheckUtils]: 58: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,627 INFO L290 TraceCheckUtils]: 59: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,627 INFO L290 TraceCheckUtils]: 60: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,628 INFO L290 TraceCheckUtils]: 61: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,628 INFO L290 TraceCheckUtils]: 62: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,628 INFO L290 TraceCheckUtils]: 63: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,628 INFO L290 TraceCheckUtils]: 64: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,629 INFO L290 TraceCheckUtils]: 65: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,629 INFO L290 TraceCheckUtils]: 66: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,629 INFO L290 TraceCheckUtils]: 67: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,630 INFO L290 TraceCheckUtils]: 68: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,630 INFO L290 TraceCheckUtils]: 69: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,630 INFO L290 TraceCheckUtils]: 70: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,630 INFO L290 TraceCheckUtils]: 71: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,631 INFO L290 TraceCheckUtils]: 72: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,631 INFO L290 TraceCheckUtils]: 73: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,631 INFO L290 TraceCheckUtils]: 74: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,631 INFO L290 TraceCheckUtils]: 75: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,632 INFO L290 TraceCheckUtils]: 76: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,632 INFO L290 TraceCheckUtils]: 77: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,632 INFO L290 TraceCheckUtils]: 78: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,632 INFO L290 TraceCheckUtils]: 79: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,633 INFO L290 TraceCheckUtils]: 80: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,633 INFO L290 TraceCheckUtils]: 81: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,633 INFO L290 TraceCheckUtils]: 82: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,633 INFO L290 TraceCheckUtils]: 83: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,634 INFO L290 TraceCheckUtils]: 84: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,634 INFO L290 TraceCheckUtils]: 85: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,634 INFO L290 TraceCheckUtils]: 86: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,634 INFO L290 TraceCheckUtils]: 87: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,635 INFO L290 TraceCheckUtils]: 88: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,635 INFO L290 TraceCheckUtils]: 89: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,635 INFO L290 TraceCheckUtils]: 90: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,635 INFO L290 TraceCheckUtils]: 91: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,636 INFO L290 TraceCheckUtils]: 92: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,636 INFO L290 TraceCheckUtils]: 93: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,636 INFO L290 TraceCheckUtils]: 94: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,636 INFO L290 TraceCheckUtils]: 95: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,637 INFO L290 TraceCheckUtils]: 96: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,637 INFO L290 TraceCheckUtils]: 97: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,637 INFO L290 TraceCheckUtils]: 98: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,638 INFO L290 TraceCheckUtils]: 99: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,638 INFO L290 TraceCheckUtils]: 100: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,638 INFO L290 TraceCheckUtils]: 101: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,638 INFO L290 TraceCheckUtils]: 102: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,639 INFO L290 TraceCheckUtils]: 103: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,639 INFO L290 TraceCheckUtils]: 104: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,639 INFO L290 TraceCheckUtils]: 105: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,639 INFO L290 TraceCheckUtils]: 106: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,640 INFO L290 TraceCheckUtils]: 107: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,640 INFO L290 TraceCheckUtils]: 108: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,640 INFO L290 TraceCheckUtils]: 109: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t12_pc~0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,640 INFO L290 TraceCheckUtils]: 110: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,641 INFO L290 TraceCheckUtils]: 111: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,641 INFO L290 TraceCheckUtils]: 112: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,641 INFO L290 TraceCheckUtils]: 113: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,641 INFO L290 TraceCheckUtils]: 114: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,642 INFO L290 TraceCheckUtils]: 115: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,642 INFO L290 TraceCheckUtils]: 116: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,642 INFO L290 TraceCheckUtils]: 117: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,642 INFO L290 TraceCheckUtils]: 118: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,643 INFO L290 TraceCheckUtils]: 119: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,643 INFO L290 TraceCheckUtils]: 120: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {87840#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:28,643 INFO L290 TraceCheckUtils]: 121: Hoare triple {87840#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {87839#false} is VALID [2022-02-21 04:23:28,643 INFO L290 TraceCheckUtils]: 122: Hoare triple {87839#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 123: Hoare triple {87839#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 124: Hoare triple {87839#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 125: Hoare triple {87839#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 126: Hoare triple {87839#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 127: Hoare triple {87839#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 128: Hoare triple {87839#false} assume 1 == ~E_M~0;~E_M~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 129: Hoare triple {87839#false} assume !(1 == ~E_1~0); {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 130: Hoare triple {87839#false} assume 1 == ~E_2~0;~E_2~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,644 INFO L290 TraceCheckUtils]: 131: Hoare triple {87839#false} assume 1 == ~E_3~0;~E_3~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 132: Hoare triple {87839#false} assume 1 == ~E_4~0;~E_4~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 133: Hoare triple {87839#false} assume 1 == ~E_5~0;~E_5~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 134: Hoare triple {87839#false} assume 1 == ~E_6~0;~E_6~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 135: Hoare triple {87839#false} assume 1 == ~E_7~0;~E_7~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 136: Hoare triple {87839#false} assume 1 == ~E_8~0;~E_8~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 137: Hoare triple {87839#false} assume !(1 == ~E_9~0); {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 138: Hoare triple {87839#false} assume 1 == ~E_10~0;~E_10~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 139: Hoare triple {87839#false} assume 1 == ~E_11~0;~E_11~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,645 INFO L290 TraceCheckUtils]: 140: Hoare triple {87839#false} assume 1 == ~E_12~0;~E_12~0 := 2; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 141: Hoare triple {87839#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 142: Hoare triple {87839#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 143: Hoare triple {87839#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 144: Hoare triple {87839#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 145: Hoare triple {87839#false} assume !(0 == start_simulation_~tmp~3#1); {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 146: Hoare triple {87839#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 147: Hoare triple {87839#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 148: Hoare triple {87839#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 149: Hoare triple {87839#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {87839#false} is VALID [2022-02-21 04:23:28,646 INFO L290 TraceCheckUtils]: 150: Hoare triple {87839#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {87839#false} is VALID [2022-02-21 04:23:28,647 INFO L290 TraceCheckUtils]: 151: Hoare triple {87839#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {87839#false} is VALID [2022-02-21 04:23:28,647 INFO L290 TraceCheckUtils]: 152: Hoare triple {87839#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {87839#false} is VALID [2022-02-21 04:23:28,647 INFO L290 TraceCheckUtils]: 153: Hoare triple {87839#false} assume !(0 != start_simulation_~tmp___0~1#1); {87839#false} is VALID [2022-02-21 04:23:28,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:28,647 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:28,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822218096] [2022-02-21 04:23:28,648 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822218096] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:28,648 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:28,648 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:28,648 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504308803] [2022-02-21 04:23:28,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:28,648 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:28,648 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:28,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:28,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:28,649 INFO L87 Difference]: Start difference. First operand 1790 states and 2644 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,522 INFO L93 Difference]: Finished difference Result 1790 states and 2639 transitions. [2022-02-21 04:23:29,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:23:29,523 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,612 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:29,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:29,748 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1790 states and 2639 transitions. [2022-02-21 04:23:29,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1790 [2022-02-21 04:23:29,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1790 [2022-02-21 04:23:29,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:29,751 INFO L681 BuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-02-21 04:23:29,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1790. [2022-02-21 04:23:29,763 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:29,765 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1790 states and 2639 transitions. Second operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,766 INFO L74 IsIncluded]: Start isIncluded. First operand 1790 states and 2639 transitions. Second operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,767 INFO L87 Difference]: Start difference. First operand 1790 states and 2639 transitions. Second operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,836 INFO L93 Difference]: Finished difference Result 1790 states and 2639 transitions. [2022-02-21 04:23:29,836 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,837 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,838 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,840 INFO L74 IsIncluded]: Start isIncluded. First operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,841 INFO L87 Difference]: Start difference. First operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:29,906 INFO L93 Difference]: Finished difference Result 1790 states and 2639 transitions. [2022-02-21 04:23:29,907 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,908 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:29,908 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:29,908 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:29,909 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:29,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1790 states, 1790 states have (on average 1.4743016759776537) internal successors, (2639), 1789 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:29,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 2639 transitions. [2022-02-21 04:23:29,975 INFO L704 BuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-02-21 04:23:29,975 INFO L587 BuchiCegarLoop]: Abstraction has 1790 states and 2639 transitions. [2022-02-21 04:23:29,976 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:23:29,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1790 states and 2639 transitions. [2022-02-21 04:23:29,978 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1627 [2022-02-21 04:23:29,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:29,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:29,980 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,980 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:29,980 INFO L791 eck$LassoCheckResult]: Stem: 90475#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 90476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 89899#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89869#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89870#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 91131#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 90178#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89631#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89632#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90903#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91042#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 91408#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 91409#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 90388#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 90389#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 90929#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 90849#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 90850#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91002#L1206 assume !(0 == ~M_E~0); 90367#L1206-2 assume !(0 == ~T1_E~0); 90368#L1211-1 assume !(0 == ~T2_E~0); 91261#L1216-1 assume !(0 == ~T3_E~0); 90160#L1221-1 assume !(0 == ~T4_E~0); 90161#L1226-1 assume !(0 == ~T5_E~0); 89823#L1231-1 assume !(0 == ~T6_E~0); 89824#L1236-1 assume !(0 == ~T7_E~0); 91292#L1241-1 assume !(0 == ~T8_E~0); 90222#L1246-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 90223#L1251-1 assume !(0 == ~T10_E~0); 90443#L1256-1 assume !(0 == ~T11_E~0); 89643#L1261-1 assume !(0 == ~T12_E~0); 89644#L1266-1 assume !(0 == ~E_M~0); 91395#L1271-1 assume !(0 == ~E_1~0); 91030#L1276-1 assume !(0 == ~E_2~0); 91031#L1281-1 assume !(0 == ~E_3~0); 90956#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 90064#L1291-1 assume !(0 == ~E_5~0); 90065#L1296-1 assume !(0 == ~E_6~0); 90771#L1301-1 assume !(0 == ~E_7~0); 90772#L1306-1 assume !(0 == ~E_8~0); 91204#L1311-1 assume !(0 == ~E_9~0); 90025#L1316-1 assume !(0 == ~E_10~0); 90026#L1321-1 assume !(0 == ~E_11~0); 90788#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 89889#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89890#L598 assume 1 == ~m_pc~0; 89949#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 89950#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91274#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 91366#L1497 assume !(0 != activate_threads_~tmp~1#1); 91367#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91323#L617 assume !(1 == ~t1_pc~0); 90245#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 90246#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90105#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 90106#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 90866#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90867#L636 assume 1 == ~t2_pc~0; 90214#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 90215#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90045#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90046#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 90902#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90565#L655 assume !(1 == ~t3_pc~0); 90566#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91279#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89919#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89920#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 91396#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91397#L674 assume 1 == ~t4_pc~0; 89739#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89740#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91037#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 90047#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 90048#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90562#L693 assume !(1 == ~t5_pc~0); 90725#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 90369#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90370#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91206#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 90455#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90392#L712 assume 1 == ~t6_pc~0; 90393#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 90820#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90821#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 91107#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 90918#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90916#L731 assume 1 == ~t7_pc~0; 89893#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 89894#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90088#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 91025#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 91144#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 90003#L750 assume !(1 == ~t8_pc~0); 89674#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 89673#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 90189#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91219#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 90326#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 90327#L769 assume 1 == ~t9_pc~0; 90862#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89847#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89848#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 90631#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 91083#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91164#L788 assume !(1 == ~t10_pc~0); 90739#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 90740#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 90971#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 90972#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 89999#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 90000#L807 assume 1 == ~t11_pc~0; 91173#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 90751#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 90904#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 91315#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 91420#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 91263#L826 assume !(1 == ~t12_pc~0); 90395#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 90396#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 90924#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 91355#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 90555#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90464#L1344 assume !(1 == ~M_E~0); 90465#L1344-2 assume !(1 == ~T1_E~0); 90606#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90778#L1354-1 assume !(1 == ~T3_E~0); 90779#L1359-1 assume !(1 == ~T4_E~0); 91153#L1364-1 assume !(1 == ~T5_E~0); 90107#L1369-1 assume !(1 == ~T6_E~0); 90108#L1374-1 assume !(1 == ~T7_E~0); 90784#L1379-1 assume !(1 == ~T8_E~0); 90785#L1384-1 assume !(1 == ~T9_E~0); 90848#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 91294#L1394-1 assume !(1 == ~T11_E~0); 91295#L1399-1 assume !(1 == ~T12_E~0); 91374#L1404-1 assume !(1 == ~E_M~0); 90226#L1409-1 assume !(1 == ~E_1~0); 90227#L1414-1 assume !(1 == ~E_2~0); 91064#L1419-1 assume !(1 == ~E_3~0); 89860#L1424-1 assume !(1 == ~E_4~0); 89861#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 90795#L1434-1 assume !(1 == ~E_6~0); 91313#L1439-1 assume !(1 == ~E_7~0); 89915#L1444-1 assume !(1 == ~E_8~0); 89916#L1449-1 assume !(1 == ~E_9~0); 90331#L1454-1 assume !(1 == ~E_10~0); 90332#L1459-1 assume !(1 == ~E_11~0); 90882#L1464-1 assume !(1 == ~E_12~0); 90883#L1469-1 assume { :end_inline_reset_delta_events } true; 90930#L1815-2 [2022-02-21 04:23:29,980 INFO L793 eck$LassoCheckResult]: Loop: 90930#L1815-2 assume !false; 91084#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90753#L1181 assume !false; 90824#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 90776#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 89634#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 90363#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 90914#L1008 assume !(0 != eval_~tmp~0#1); 90915#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89853#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89854#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 91414#L1206-5 assume !(0 == ~T1_E~0); 90881#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89987#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89988#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90578#L1226-3 assume !(0 == ~T5_E~0); 90051#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 90052#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 90364#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 91351#L1246-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 91254#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 90990#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 90009#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 90010#L1266-3 assume !(0 == ~E_M~0); 90049#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 90050#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90522#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90523#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 91060#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91061#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 91403#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 91371#L1306-3 assume !(0 == ~E_8~0); 90647#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 89933#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 89934#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 90011#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 90746#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91071#L598-42 assume 1 == ~m_pc~0; 91073#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 91186#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90089#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 90090#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 91372#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90802#L617-42 assume !(1 == ~t1_pc~0); 90575#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 90439#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90440#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 90854#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 90154#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90155#L636-42 assume !(1 == ~t2_pc~0); 90618#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 90619#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90969#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 90970#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 91149#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91011#L655-42 assume 1 == ~t3_pc~0; 91012#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 90592#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90224#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 90225#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 91278#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91223#L674-42 assume !(1 == ~t4_pc~0); 90997#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 90919#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89808#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89809#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 90723#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90724#L693-42 assume 1 == ~t5_pc~0; 90979#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 90980#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91040#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91035#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 91036#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90338#L712-42 assume !(1 == ~t6_pc~0); 90339#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 90665#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90873#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 90874#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 90447#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90448#L731-42 assume !(1 == ~t7_pc~0); 90146#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 90147#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91214#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 90355#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 90356#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 90059#L750-42 assume !(1 == ~t8_pc~0); 90061#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 90634#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91057#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 89952#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 89953#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 90722#L769-42 assume 1 == ~t9_pc~0; 90544#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 90545#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 91228#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 91293#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 90156#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 90157#L788-42 assume !(1 == ~t10_pc~0); 90731#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 90944#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 90674#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 90675#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 91412#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 91390#L807-42 assume !(1 == ~t11_pc~0); 89760#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 89761#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 89900#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 89901#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 89902#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 90151#L826-42 assume !(1 == ~t12_pc~0); 90153#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 90344#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 91136#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 90141#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 90142#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90993#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 90994#L1344-5 assume !(1 == ~T1_E~0); 90920#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90301#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90302#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90934#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 91392#L1369-3 assume !(1 == ~T6_E~0); 91312#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 90066#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 90067#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90299#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 90300#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 90598#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 91321#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 91284#L1409-3 assume !(1 == ~E_1~0); 91285#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 91350#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 91130#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89967#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89968#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 90933#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89907#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89908#L1449-3 assume !(1 == ~E_9~0); 90017#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 90927#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 90928#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 91309#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 90807#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 89806#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 89807#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 90423#L1834 assume !(0 == start_simulation_~tmp~3#1); 91043#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 91066#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 90500#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 90679#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 90891#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 91299#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89792#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 89793#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 90930#L1815-2 [2022-02-21 04:23:29,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:29,981 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-02-21 04:23:29,981 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:29,981 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479036468] [2022-02-21 04:23:29,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:29,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:29,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:30,007 INFO L290 TraceCheckUtils]: 0: Hoare triple {95004#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,008 INFO L290 TraceCheckUtils]: 1: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,008 INFO L290 TraceCheckUtils]: 2: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,008 INFO L290 TraceCheckUtils]: 3: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,008 INFO L290 TraceCheckUtils]: 4: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,009 INFO L290 TraceCheckUtils]: 5: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,009 INFO L290 TraceCheckUtils]: 6: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,009 INFO L290 TraceCheckUtils]: 7: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,009 INFO L290 TraceCheckUtils]: 8: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,010 INFO L290 TraceCheckUtils]: 9: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,010 INFO L290 TraceCheckUtils]: 10: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,010 INFO L290 TraceCheckUtils]: 11: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,011 INFO L290 TraceCheckUtils]: 12: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,011 INFO L290 TraceCheckUtils]: 13: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,011 INFO L290 TraceCheckUtils]: 14: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,011 INFO L290 TraceCheckUtils]: 15: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,012 INFO L290 TraceCheckUtils]: 16: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,012 INFO L290 TraceCheckUtils]: 17: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {95006#(= ~T9_E~0 ~M_E~0)} is VALID [2022-02-21 04:23:30,012 INFO L290 TraceCheckUtils]: 18: Hoare triple {95006#(= ~T9_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,012 INFO L290 TraceCheckUtils]: 19: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T1_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,013 INFO L290 TraceCheckUtils]: 20: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T2_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,013 INFO L290 TraceCheckUtils]: 21: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T3_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,013 INFO L290 TraceCheckUtils]: 22: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T4_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,014 INFO L290 TraceCheckUtils]: 23: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T5_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,014 INFO L290 TraceCheckUtils]: 24: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T6_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,014 INFO L290 TraceCheckUtils]: 25: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T7_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,014 INFO L290 TraceCheckUtils]: 26: Hoare triple {95007#(not (= ~T9_E~0 0))} assume !(0 == ~T8_E~0); {95007#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 27: Hoare triple {95007#(not (= ~T9_E~0 0))} assume 0 == ~T9_E~0;~T9_E~0 := 1; {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 28: Hoare triple {95005#false} assume !(0 == ~T10_E~0); {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 29: Hoare triple {95005#false} assume !(0 == ~T11_E~0); {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 30: Hoare triple {95005#false} assume !(0 == ~T12_E~0); {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 31: Hoare triple {95005#false} assume !(0 == ~E_M~0); {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 32: Hoare triple {95005#false} assume !(0 == ~E_1~0); {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 33: Hoare triple {95005#false} assume !(0 == ~E_2~0); {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 34: Hoare triple {95005#false} assume !(0 == ~E_3~0); {95005#false} is VALID [2022-02-21 04:23:30,015 INFO L290 TraceCheckUtils]: 35: Hoare triple {95005#false} assume 0 == ~E_4~0;~E_4~0 := 1; {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 36: Hoare triple {95005#false} assume !(0 == ~E_5~0); {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 37: Hoare triple {95005#false} assume !(0 == ~E_6~0); {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 38: Hoare triple {95005#false} assume !(0 == ~E_7~0); {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 39: Hoare triple {95005#false} assume !(0 == ~E_8~0); {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 40: Hoare triple {95005#false} assume !(0 == ~E_9~0); {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 41: Hoare triple {95005#false} assume !(0 == ~E_10~0); {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 42: Hoare triple {95005#false} assume !(0 == ~E_11~0); {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 43: Hoare triple {95005#false} assume 0 == ~E_12~0;~E_12~0 := 1; {95005#false} is VALID [2022-02-21 04:23:30,016 INFO L290 TraceCheckUtils]: 44: Hoare triple {95005#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 45: Hoare triple {95005#false} assume 1 == ~m_pc~0; {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 46: Hoare triple {95005#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 47: Hoare triple {95005#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 48: Hoare triple {95005#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 49: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp~1#1); {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 50: Hoare triple {95005#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 51: Hoare triple {95005#false} assume !(1 == ~t1_pc~0); {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 52: Hoare triple {95005#false} is_transmit1_triggered_~__retres1~1#1 := 0; {95005#false} is VALID [2022-02-21 04:23:30,017 INFO L290 TraceCheckUtils]: 53: Hoare triple {95005#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 54: Hoare triple {95005#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 55: Hoare triple {95005#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 56: Hoare triple {95005#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 57: Hoare triple {95005#false} assume 1 == ~t2_pc~0; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 58: Hoare triple {95005#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 59: Hoare triple {95005#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 60: Hoare triple {95005#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 61: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___1~0#1); {95005#false} is VALID [2022-02-21 04:23:30,018 INFO L290 TraceCheckUtils]: 62: Hoare triple {95005#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 63: Hoare triple {95005#false} assume !(1 == ~t3_pc~0); {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 64: Hoare triple {95005#false} is_transmit3_triggered_~__retres1~3#1 := 0; {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 65: Hoare triple {95005#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 66: Hoare triple {95005#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 67: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___2~0#1); {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 68: Hoare triple {95005#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 69: Hoare triple {95005#false} assume 1 == ~t4_pc~0; {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 70: Hoare triple {95005#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {95005#false} is VALID [2022-02-21 04:23:30,019 INFO L290 TraceCheckUtils]: 71: Hoare triple {95005#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 72: Hoare triple {95005#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 73: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___3~0#1); {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 74: Hoare triple {95005#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 75: Hoare triple {95005#false} assume !(1 == ~t5_pc~0); {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 76: Hoare triple {95005#false} is_transmit5_triggered_~__retres1~5#1 := 0; {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 77: Hoare triple {95005#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 78: Hoare triple {95005#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 79: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___4~0#1); {95005#false} is VALID [2022-02-21 04:23:30,020 INFO L290 TraceCheckUtils]: 80: Hoare triple {95005#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 81: Hoare triple {95005#false} assume 1 == ~t6_pc~0; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 82: Hoare triple {95005#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 83: Hoare triple {95005#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 84: Hoare triple {95005#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 85: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___5~0#1); {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 86: Hoare triple {95005#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 87: Hoare triple {95005#false} assume 1 == ~t7_pc~0; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 88: Hoare triple {95005#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {95005#false} is VALID [2022-02-21 04:23:30,021 INFO L290 TraceCheckUtils]: 89: Hoare triple {95005#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 90: Hoare triple {95005#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 91: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___6~0#1); {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 92: Hoare triple {95005#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 93: Hoare triple {95005#false} assume !(1 == ~t8_pc~0); {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 94: Hoare triple {95005#false} is_transmit8_triggered_~__retres1~8#1 := 0; {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 95: Hoare triple {95005#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 96: Hoare triple {95005#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 97: Hoare triple {95005#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {95005#false} is VALID [2022-02-21 04:23:30,022 INFO L290 TraceCheckUtils]: 98: Hoare triple {95005#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 99: Hoare triple {95005#false} assume 1 == ~t9_pc~0; {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 100: Hoare triple {95005#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 101: Hoare triple {95005#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 102: Hoare triple {95005#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 103: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___8~0#1); {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 104: Hoare triple {95005#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 105: Hoare triple {95005#false} assume !(1 == ~t10_pc~0); {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 106: Hoare triple {95005#false} is_transmit10_triggered_~__retres1~10#1 := 0; {95005#false} is VALID [2022-02-21 04:23:30,023 INFO L290 TraceCheckUtils]: 107: Hoare triple {95005#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 108: Hoare triple {95005#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 109: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___9~0#1); {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 110: Hoare triple {95005#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 111: Hoare triple {95005#false} assume 1 == ~t11_pc~0; {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 112: Hoare triple {95005#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 113: Hoare triple {95005#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 114: Hoare triple {95005#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 115: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___10~0#1); {95005#false} is VALID [2022-02-21 04:23:30,024 INFO L290 TraceCheckUtils]: 116: Hoare triple {95005#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 117: Hoare triple {95005#false} assume !(1 == ~t12_pc~0); {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 118: Hoare triple {95005#false} is_transmit12_triggered_~__retres1~12#1 := 0; {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 119: Hoare triple {95005#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 120: Hoare triple {95005#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 121: Hoare triple {95005#false} assume !(0 != activate_threads_~tmp___11~0#1); {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 122: Hoare triple {95005#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 123: Hoare triple {95005#false} assume !(1 == ~M_E~0); {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 124: Hoare triple {95005#false} assume !(1 == ~T1_E~0); {95005#false} is VALID [2022-02-21 04:23:30,025 INFO L290 TraceCheckUtils]: 125: Hoare triple {95005#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 126: Hoare triple {95005#false} assume !(1 == ~T3_E~0); {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 127: Hoare triple {95005#false} assume !(1 == ~T4_E~0); {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 128: Hoare triple {95005#false} assume !(1 == ~T5_E~0); {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 129: Hoare triple {95005#false} assume !(1 == ~T6_E~0); {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 130: Hoare triple {95005#false} assume !(1 == ~T7_E~0); {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 131: Hoare triple {95005#false} assume !(1 == ~T8_E~0); {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 132: Hoare triple {95005#false} assume !(1 == ~T9_E~0); {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 133: Hoare triple {95005#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {95005#false} is VALID [2022-02-21 04:23:30,026 INFO L290 TraceCheckUtils]: 134: Hoare triple {95005#false} assume !(1 == ~T11_E~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 135: Hoare triple {95005#false} assume !(1 == ~T12_E~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 136: Hoare triple {95005#false} assume !(1 == ~E_M~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 137: Hoare triple {95005#false} assume !(1 == ~E_1~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 138: Hoare triple {95005#false} assume !(1 == ~E_2~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 139: Hoare triple {95005#false} assume !(1 == ~E_3~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 140: Hoare triple {95005#false} assume !(1 == ~E_4~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 141: Hoare triple {95005#false} assume 1 == ~E_5~0;~E_5~0 := 2; {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 142: Hoare triple {95005#false} assume !(1 == ~E_6~0); {95005#false} is VALID [2022-02-21 04:23:30,027 INFO L290 TraceCheckUtils]: 143: Hoare triple {95005#false} assume !(1 == ~E_7~0); {95005#false} is VALID [2022-02-21 04:23:30,028 INFO L290 TraceCheckUtils]: 144: Hoare triple {95005#false} assume !(1 == ~E_8~0); {95005#false} is VALID [2022-02-21 04:23:30,028 INFO L290 TraceCheckUtils]: 145: Hoare triple {95005#false} assume !(1 == ~E_9~0); {95005#false} is VALID [2022-02-21 04:23:30,028 INFO L290 TraceCheckUtils]: 146: Hoare triple {95005#false} assume !(1 == ~E_10~0); {95005#false} is VALID [2022-02-21 04:23:30,028 INFO L290 TraceCheckUtils]: 147: Hoare triple {95005#false} assume !(1 == ~E_11~0); {95005#false} is VALID [2022-02-21 04:23:30,028 INFO L290 TraceCheckUtils]: 148: Hoare triple {95005#false} assume !(1 == ~E_12~0); {95005#false} is VALID [2022-02-21 04:23:30,028 INFO L290 TraceCheckUtils]: 149: Hoare triple {95005#false} assume { :end_inline_reset_delta_events } true; {95005#false} is VALID [2022-02-21 04:23:30,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:30,029 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:30,029 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479036468] [2022-02-21 04:23:30,029 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479036468] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:30,029 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:30,029 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:30,029 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575575324] [2022-02-21 04:23:30,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:30,030 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:30,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:30,030 INFO L85 PathProgramCache]: Analyzing trace with hash 1096388760, now seen corresponding path program 1 times [2022-02-21 04:23:30,030 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:30,030 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817890108] [2022-02-21 04:23:30,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:30,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:30,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:30,054 INFO L290 TraceCheckUtils]: 0: Hoare triple {95008#true} assume !false; {95008#true} is VALID [2022-02-21 04:23:30,055 INFO L290 TraceCheckUtils]: 1: Hoare triple {95008#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {95008#true} is VALID [2022-02-21 04:23:30,055 INFO L290 TraceCheckUtils]: 2: Hoare triple {95008#true} assume !false; {95008#true} is VALID [2022-02-21 04:23:30,055 INFO L290 TraceCheckUtils]: 3: Hoare triple {95008#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {95008#true} is VALID [2022-02-21 04:23:30,055 INFO L290 TraceCheckUtils]: 4: Hoare triple {95008#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {95008#true} is VALID [2022-02-21 04:23:30,055 INFO L290 TraceCheckUtils]: 5: Hoare triple {95008#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {95008#true} is VALID [2022-02-21 04:23:30,055 INFO L290 TraceCheckUtils]: 6: Hoare triple {95008#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {95008#true} is VALID [2022-02-21 04:23:30,055 INFO L290 TraceCheckUtils]: 7: Hoare triple {95008#true} assume !(0 != eval_~tmp~0#1); {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 8: Hoare triple {95008#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 9: Hoare triple {95008#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 10: Hoare triple {95008#true} assume 0 == ~M_E~0;~M_E~0 := 1; {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 11: Hoare triple {95008#true} assume !(0 == ~T1_E~0); {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 12: Hoare triple {95008#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 13: Hoare triple {95008#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 14: Hoare triple {95008#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {95008#true} is VALID [2022-02-21 04:23:30,056 INFO L290 TraceCheckUtils]: 15: Hoare triple {95008#true} assume !(0 == ~T5_E~0); {95008#true} is VALID [2022-02-21 04:23:30,057 INFO L290 TraceCheckUtils]: 16: Hoare triple {95008#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,057 INFO L290 TraceCheckUtils]: 17: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,057 INFO L290 TraceCheckUtils]: 18: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,058 INFO L290 TraceCheckUtils]: 19: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,058 INFO L290 TraceCheckUtils]: 20: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,058 INFO L290 TraceCheckUtils]: 21: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,059 INFO L290 TraceCheckUtils]: 22: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,059 INFO L290 TraceCheckUtils]: 23: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,059 INFO L290 TraceCheckUtils]: 24: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,060 INFO L290 TraceCheckUtils]: 25: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,060 INFO L290 TraceCheckUtils]: 26: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,060 INFO L290 TraceCheckUtils]: 27: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,060 INFO L290 TraceCheckUtils]: 28: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,061 INFO L290 TraceCheckUtils]: 29: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,061 INFO L290 TraceCheckUtils]: 30: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,061 INFO L290 TraceCheckUtils]: 31: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,061 INFO L290 TraceCheckUtils]: 32: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,062 INFO L290 TraceCheckUtils]: 33: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,062 INFO L290 TraceCheckUtils]: 34: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,062 INFO L290 TraceCheckUtils]: 35: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,063 INFO L290 TraceCheckUtils]: 36: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,063 INFO L290 TraceCheckUtils]: 37: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,063 INFO L290 TraceCheckUtils]: 38: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,063 INFO L290 TraceCheckUtils]: 39: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,064 INFO L290 TraceCheckUtils]: 40: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,064 INFO L290 TraceCheckUtils]: 41: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,064 INFO L290 TraceCheckUtils]: 42: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,065 INFO L290 TraceCheckUtils]: 43: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,065 INFO L290 TraceCheckUtils]: 44: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,065 INFO L290 TraceCheckUtils]: 45: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,065 INFO L290 TraceCheckUtils]: 46: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,066 INFO L290 TraceCheckUtils]: 47: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,066 INFO L290 TraceCheckUtils]: 48: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,066 INFO L290 TraceCheckUtils]: 49: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,066 INFO L290 TraceCheckUtils]: 50: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,067 INFO L290 TraceCheckUtils]: 51: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,067 INFO L290 TraceCheckUtils]: 52: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,067 INFO L290 TraceCheckUtils]: 53: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,068 INFO L290 TraceCheckUtils]: 54: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,068 INFO L290 TraceCheckUtils]: 55: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,068 INFO L290 TraceCheckUtils]: 56: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,068 INFO L290 TraceCheckUtils]: 57: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,069 INFO L290 TraceCheckUtils]: 58: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,069 INFO L290 TraceCheckUtils]: 59: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,069 INFO L290 TraceCheckUtils]: 60: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,070 INFO L290 TraceCheckUtils]: 61: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,070 INFO L290 TraceCheckUtils]: 62: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,070 INFO L290 TraceCheckUtils]: 63: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,070 INFO L290 TraceCheckUtils]: 64: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,071 INFO L290 TraceCheckUtils]: 65: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,071 INFO L290 TraceCheckUtils]: 66: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,071 INFO L290 TraceCheckUtils]: 67: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,072 INFO L290 TraceCheckUtils]: 68: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,072 INFO L290 TraceCheckUtils]: 69: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,072 INFO L290 TraceCheckUtils]: 70: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,072 INFO L290 TraceCheckUtils]: 71: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,073 INFO L290 TraceCheckUtils]: 72: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,073 INFO L290 TraceCheckUtils]: 73: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,073 INFO L290 TraceCheckUtils]: 74: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,073 INFO L290 TraceCheckUtils]: 75: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,074 INFO L290 TraceCheckUtils]: 76: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,074 INFO L290 TraceCheckUtils]: 77: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,074 INFO L290 TraceCheckUtils]: 78: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,075 INFO L290 TraceCheckUtils]: 79: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,075 INFO L290 TraceCheckUtils]: 80: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,075 INFO L290 TraceCheckUtils]: 81: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,075 INFO L290 TraceCheckUtils]: 82: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,076 INFO L290 TraceCheckUtils]: 83: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,076 INFO L290 TraceCheckUtils]: 84: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,076 INFO L290 TraceCheckUtils]: 85: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,077 INFO L290 TraceCheckUtils]: 86: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,077 INFO L290 TraceCheckUtils]: 87: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,077 INFO L290 TraceCheckUtils]: 88: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,077 INFO L290 TraceCheckUtils]: 89: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,078 INFO L290 TraceCheckUtils]: 90: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,078 INFO L290 TraceCheckUtils]: 91: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,078 INFO L290 TraceCheckUtils]: 92: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,078 INFO L290 TraceCheckUtils]: 93: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,079 INFO L290 TraceCheckUtils]: 94: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,079 INFO L290 TraceCheckUtils]: 95: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,079 INFO L290 TraceCheckUtils]: 96: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,080 INFO L290 TraceCheckUtils]: 97: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t10_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,080 INFO L290 TraceCheckUtils]: 98: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,080 INFO L290 TraceCheckUtils]: 99: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,080 INFO L290 TraceCheckUtils]: 100: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,081 INFO L290 TraceCheckUtils]: 101: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,081 INFO L290 TraceCheckUtils]: 102: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,081 INFO L290 TraceCheckUtils]: 103: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t11_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,082 INFO L290 TraceCheckUtils]: 104: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,082 INFO L290 TraceCheckUtils]: 105: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,082 INFO L290 TraceCheckUtils]: 106: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,082 INFO L290 TraceCheckUtils]: 107: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,083 INFO L290 TraceCheckUtils]: 108: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,083 INFO L290 TraceCheckUtils]: 109: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t12_pc~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,083 INFO L290 TraceCheckUtils]: 110: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,084 INFO L290 TraceCheckUtils]: 111: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,084 INFO L290 TraceCheckUtils]: 112: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,084 INFO L290 TraceCheckUtils]: 113: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,084 INFO L290 TraceCheckUtils]: 114: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,085 INFO L290 TraceCheckUtils]: 115: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,085 INFO L290 TraceCheckUtils]: 116: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T1_E~0); {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,085 INFO L290 TraceCheckUtils]: 117: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,085 INFO L290 TraceCheckUtils]: 118: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,086 INFO L290 TraceCheckUtils]: 119: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,086 INFO L290 TraceCheckUtils]: 120: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {95010#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:30,087 INFO L290 TraceCheckUtils]: 121: Hoare triple {95010#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {95009#false} is VALID [2022-02-21 04:23:30,087 INFO L290 TraceCheckUtils]: 122: Hoare triple {95009#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,087 INFO L290 TraceCheckUtils]: 123: Hoare triple {95009#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,087 INFO L290 TraceCheckUtils]: 124: Hoare triple {95009#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,087 INFO L290 TraceCheckUtils]: 125: Hoare triple {95009#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 126: Hoare triple {95009#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 127: Hoare triple {95009#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 128: Hoare triple {95009#false} assume 1 == ~E_M~0;~E_M~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 129: Hoare triple {95009#false} assume !(1 == ~E_1~0); {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 130: Hoare triple {95009#false} assume 1 == ~E_2~0;~E_2~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 131: Hoare triple {95009#false} assume 1 == ~E_3~0;~E_3~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 132: Hoare triple {95009#false} assume 1 == ~E_4~0;~E_4~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 133: Hoare triple {95009#false} assume 1 == ~E_5~0;~E_5~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 134: Hoare triple {95009#false} assume 1 == ~E_6~0;~E_6~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,088 INFO L290 TraceCheckUtils]: 135: Hoare triple {95009#false} assume 1 == ~E_7~0;~E_7~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 136: Hoare triple {95009#false} assume 1 == ~E_8~0;~E_8~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 137: Hoare triple {95009#false} assume !(1 == ~E_9~0); {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 138: Hoare triple {95009#false} assume 1 == ~E_10~0;~E_10~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 139: Hoare triple {95009#false} assume 1 == ~E_11~0;~E_11~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 140: Hoare triple {95009#false} assume 1 == ~E_12~0;~E_12~0 := 2; {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 141: Hoare triple {95009#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 142: Hoare triple {95009#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {95009#false} is VALID [2022-02-21 04:23:30,089 INFO L290 TraceCheckUtils]: 143: Hoare triple {95009#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 144: Hoare triple {95009#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 145: Hoare triple {95009#false} assume !(0 == start_simulation_~tmp~3#1); {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 146: Hoare triple {95009#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 147: Hoare triple {95009#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 148: Hoare triple {95009#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 149: Hoare triple {95009#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 150: Hoare triple {95009#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 151: Hoare triple {95009#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {95009#false} is VALID [2022-02-21 04:23:30,090 INFO L290 TraceCheckUtils]: 152: Hoare triple {95009#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {95009#false} is VALID [2022-02-21 04:23:30,091 INFO L290 TraceCheckUtils]: 153: Hoare triple {95009#false} assume !(0 != start_simulation_~tmp___0~1#1); {95009#false} is VALID [2022-02-21 04:23:30,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:30,096 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:30,096 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817890108] [2022-02-21 04:23:30,096 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817890108] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:30,097 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:30,097 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:30,097 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929737219] [2022-02-21 04:23:30,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:30,097 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:30,097 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:30,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:30,098 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:30,098 INFO L87 Difference]: Start difference. First operand 1790 states and 2639 transitions. cyclomatic complexity: 850 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:32,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:32,976 INFO L93 Difference]: Finished difference Result 3324 states and 4886 transitions. [2022-02-21 04:23:32,976 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:32,976 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,030 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:33,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3324 states and 4886 transitions. [2022-02-21 04:23:33,305 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2022-02-21 04:23:33,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3324 states to 3324 states and 4886 transitions. [2022-02-21 04:23:33,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3324 [2022-02-21 04:23:33,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3324 [2022-02-21 04:23:33,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3324 states and 4886 transitions. [2022-02-21 04:23:33,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:33,578 INFO L681 BuchiCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-02-21 04:23:33,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3324 states and 4886 transitions. [2022-02-21 04:23:33,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3324 to 3324. [2022-02-21 04:23:33,611 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:33,614 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3324 states and 4886 transitions. Second operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,617 INFO L74 IsIncluded]: Start isIncluded. First operand 3324 states and 4886 transitions. Second operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,618 INFO L87 Difference]: Start difference. First operand 3324 states and 4886 transitions. Second operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:33,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:33,846 INFO L93 Difference]: Finished difference Result 3324 states and 4886 transitions. [2022-02-21 04:23:33,846 INFO L276 IsEmpty]: Start isEmpty. Operand 3324 states and 4886 transitions. [2022-02-21 04:23:33,849 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:33,849 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:33,853 INFO L74 IsIncluded]: Start isIncluded. First operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3324 states and 4886 transitions. [2022-02-21 04:23:33,855 INFO L87 Difference]: Start difference. First operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3324 states and 4886 transitions. [2022-02-21 04:23:34,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:34,084 INFO L93 Difference]: Finished difference Result 3324 states and 4886 transitions. [2022-02-21 04:23:34,084 INFO L276 IsEmpty]: Start isEmpty. Operand 3324 states and 4886 transitions. [2022-02-21 04:23:34,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:34,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:34,087 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:34,087 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:34,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3324 states, 3324 states have (on average 1.4699157641395908) internal successors, (4886), 3323 states have internal predecessors, (4886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:34,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3324 states to 3324 states and 4886 transitions. [2022-02-21 04:23:34,332 INFO L704 BuchiCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-02-21 04:23:34,333 INFO L587 BuchiCegarLoop]: Abstraction has 3324 states and 4886 transitions. [2022-02-21 04:23:34,333 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:23:34,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3324 states and 4886 transitions. [2022-02-21 04:23:34,339 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3135 [2022-02-21 04:23:34,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:34,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:34,341 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,341 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:34,341 INFO L791 eck$LassoCheckResult]: Stem: 99183#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 99184#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 98605#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98575#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98576#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 99845#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98884#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98337#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98338#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 99612#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 99754#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 100124#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100125#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 99095#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 99096#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 99638#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 99558#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 99559#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99714#L1206 assume !(0 == ~M_E~0); 99074#L1206-2 assume !(0 == ~T1_E~0); 99075#L1211-1 assume !(0 == ~T2_E~0); 99976#L1216-1 assume !(0 == ~T3_E~0); 98866#L1221-1 assume !(0 == ~T4_E~0); 98867#L1226-1 assume !(0 == ~T5_E~0); 98529#L1231-1 assume !(0 == ~T6_E~0); 98530#L1236-1 assume !(0 == ~T7_E~0); 100007#L1241-1 assume !(0 == ~T8_E~0); 98928#L1246-1 assume !(0 == ~T9_E~0); 98929#L1251-1 assume !(0 == ~T10_E~0); 99150#L1256-1 assume !(0 == ~T11_E~0); 98349#L1261-1 assume !(0 == ~T12_E~0); 98350#L1266-1 assume !(0 == ~E_M~0); 100111#L1271-1 assume !(0 == ~E_1~0); 99742#L1276-1 assume !(0 == ~E_2~0); 99743#L1281-1 assume !(0 == ~E_3~0); 99668#L1286-1 assume 0 == ~E_4~0;~E_4~0 := 1; 98770#L1291-1 assume !(0 == ~E_5~0); 98771#L1296-1 assume !(0 == ~E_6~0); 99479#L1301-1 assume !(0 == ~E_7~0); 99480#L1306-1 assume !(0 == ~E_8~0); 99918#L1311-1 assume !(0 == ~E_9~0); 98731#L1316-1 assume !(0 == ~E_10~0); 98732#L1321-1 assume !(0 == ~E_11~0); 99496#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 98595#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98596#L598 assume 1 == ~m_pc~0; 98655#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 98656#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99989#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100082#L1497 assume !(0 != activate_threads_~tmp~1#1); 100083#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100039#L617 assume !(1 == ~t1_pc~0); 98951#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98952#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98811#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 98812#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99575#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99576#L636 assume 1 == ~t2_pc~0; 98920#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 98921#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98751#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98752#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 99611#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99273#L655 assume !(1 == ~t3_pc~0); 99274#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 99994#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98625#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98626#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 100112#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100113#L674 assume 1 == ~t4_pc~0; 98445#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 98446#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99749#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98753#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 98754#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99270#L693 assume !(1 == ~t5_pc~0); 99433#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 99076#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99077#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99920#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 99162#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99099#L712 assume 1 == ~t6_pc~0; 99100#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99528#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99529#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 99821#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 99627#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99625#L731 assume 1 == ~t7_pc~0; 98599#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 98600#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98794#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99737#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 99858#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98709#L750 assume !(1 == ~t8_pc~0); 98380#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 98379#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98895#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99933#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99032#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99033#L769 assume 1 == ~t9_pc~0; 99573#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98553#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98554#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 99339#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 99797#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 99878#L788 assume !(1 == ~t10_pc~0); 99447#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 99448#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 99683#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99684#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 98705#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98706#L807 assume 1 == ~t11_pc~0; 99887#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 99459#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99613#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 100031#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 100139#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 99978#L826 assume !(1 == ~t12_pc~0); 99102#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 99103#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 99633#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 100071#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 99263#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99171#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 99172#L1344-2 assume !(1 == ~T1_E~0); 100186#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100185#L1354-1 assume !(1 == ~T3_E~0); 100184#L1359-1 assume !(1 == ~T4_E~0); 100183#L1364-1 assume !(1 == ~T5_E~0); 100182#L1369-1 assume !(1 == ~T6_E~0); 100181#L1374-1 assume !(1 == ~T7_E~0); 100180#L1379-1 assume !(1 == ~T8_E~0); 100179#L1384-1 assume !(1 == ~T9_E~0); 99556#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100178#L1394-1 assume !(1 == ~T11_E~0); 100177#L1399-1 assume !(1 == ~T12_E~0); 100176#L1404-1 assume !(1 == ~E_M~0); 100175#L1409-1 assume !(1 == ~E_1~0); 100174#L1414-1 assume !(1 == ~E_2~0); 100173#L1419-1 assume !(1 == ~E_3~0); 100172#L1424-1 assume !(1 == ~E_4~0); 100171#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 100170#L1434-1 assume !(1 == ~E_6~0); 100169#L1439-1 assume !(1 == ~E_7~0); 100168#L1444-1 assume !(1 == ~E_8~0); 100167#L1449-1 assume !(1 == ~E_9~0); 100166#L1454-1 assume !(1 == ~E_10~0); 100165#L1459-1 assume !(1 == ~E_11~0); 100164#L1464-1 assume !(1 == ~E_12~0); 100163#L1469-1 assume { :end_inline_reset_delta_events } true; 100161#L1815-2 [2022-02-21 04:23:34,342 INFO L793 eck$LassoCheckResult]: Loop: 100161#L1815-2 assume !false; 100160#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100156#L1181 assume !false; 100155#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 100152#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 99069#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 99070#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 99623#L1008 assume !(0 != eval_~tmp~0#1); 99624#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98559#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98560#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 100140#L1206-5 assume !(0 == ~T1_E~0); 100364#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 100363#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100362#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100361#L1226-3 assume !(0 == ~T5_E~0); 100360#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100359#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 100358#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 100357#L1246-3 assume !(0 == ~T9_E~0); 100356#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 100355#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 100354#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 100353#L1266-3 assume !(0 == ~E_M~0); 100352#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100351#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100350#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100349#L1286-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100348#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100347#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100346#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 100345#L1306-3 assume !(0 == ~E_8~0); 100344#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 100343#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 100342#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 100341#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 100340#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100339#L598-42 assume 1 == ~m_pc~0; 100337#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100336#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100335#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100334#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 100333#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100332#L617-42 assume !(1 == ~t1_pc~0); 100331#L617-44 is_transmit1_triggered_~__retres1~1#1 := 0; 100329#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100328#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100327#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100326#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100325#L636-42 assume 1 == ~t2_pc~0; 100323#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 100322#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100321#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100320#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100319#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100318#L655-42 assume !(1 == ~t3_pc~0); 100317#L655-44 is_transmit3_triggered_~__retres1~3#1 := 0; 100315#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100314#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100313#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100312#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100311#L674-42 assume !(1 == ~t4_pc~0); 100309#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 100308#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100307#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100306#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100305#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100304#L693-42 assume !(1 == ~t5_pc~0); 100303#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 100301#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100300#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100299#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100298#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100297#L712-42 assume !(1 == ~t6_pc~0); 100295#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 100294#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100293#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100292#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100291#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100290#L731-42 assume !(1 == ~t7_pc~0); 100289#L731-44 is_transmit7_triggered_~__retres1~7#1 := 0; 100287#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100286#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100285#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 100284#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100283#L750-42 assume !(1 == ~t8_pc~0); 100281#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 100280#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100279#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100278#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 100277#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100276#L769-42 assume !(1 == ~t9_pc~0); 100275#L769-44 is_transmit9_triggered_~__retres1~9#1 := 0; 100273#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100272#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100271#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 100270#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100269#L788-42 assume 1 == ~t10_pc~0; 99653#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 99654#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 99382#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99383#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 100128#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100106#L807-42 assume 1 == ~t11_pc~0; 99793#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 98467#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98606#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98607#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 98608#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 98857#L826-42 assume !(1 == ~t12_pc~0); 98859#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 99050#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 99850#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 98847#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 98848#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99705#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 99706#L1344-5 assume !(1 == ~T1_E~0); 99629#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99007#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99008#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99643#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100108#L1369-3 assume !(1 == ~T6_E~0); 100028#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98772#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 98773#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 99005#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 99006#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99306#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 100037#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 99999#L1409-3 assume !(1 == ~E_1~0); 100000#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100066#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 99844#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98673#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98674#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 99642#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 98613#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 98614#L1449-3 assume !(1 == ~E_9~0); 98723#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 99636#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 99637#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 100024#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 100025#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 100207#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 100206#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 100205#L1834 assume !(0 == start_simulation_~tmp~3#1); 99755#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 100200#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 100191#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 100190#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 100189#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100188#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100187#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 100162#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 100161#L1815-2 [2022-02-21 04:23:34,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2022-02-21 04:23:34,343 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,343 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103426984] [2022-02-21 04:23:34,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,371 INFO L290 TraceCheckUtils]: 0: Hoare triple {108312#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,372 INFO L290 TraceCheckUtils]: 1: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,372 INFO L290 TraceCheckUtils]: 2: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,373 INFO L290 TraceCheckUtils]: 3: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,373 INFO L290 TraceCheckUtils]: 4: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,373 INFO L290 TraceCheckUtils]: 5: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,373 INFO L290 TraceCheckUtils]: 6: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,374 INFO L290 TraceCheckUtils]: 7: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,374 INFO L290 TraceCheckUtils]: 8: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,374 INFO L290 TraceCheckUtils]: 9: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,375 INFO L290 TraceCheckUtils]: 10: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,375 INFO L290 TraceCheckUtils]: 11: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,375 INFO L290 TraceCheckUtils]: 12: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,376 INFO L290 TraceCheckUtils]: 13: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,376 INFO L290 TraceCheckUtils]: 14: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,376 INFO L290 TraceCheckUtils]: 15: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,376 INFO L290 TraceCheckUtils]: 16: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,377 INFO L290 TraceCheckUtils]: 17: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {108314#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:23:34,377 INFO L290 TraceCheckUtils]: 18: Hoare triple {108314#(= ~E_4~0 ~M_E~0)} assume !(0 == ~M_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,377 INFO L290 TraceCheckUtils]: 19: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T1_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,378 INFO L290 TraceCheckUtils]: 20: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T2_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,378 INFO L290 TraceCheckUtils]: 21: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T3_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,378 INFO L290 TraceCheckUtils]: 22: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T4_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,379 INFO L290 TraceCheckUtils]: 23: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T5_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,379 INFO L290 TraceCheckUtils]: 24: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T6_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,379 INFO L290 TraceCheckUtils]: 25: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T7_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,380 INFO L290 TraceCheckUtils]: 26: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T8_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,380 INFO L290 TraceCheckUtils]: 27: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T9_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,380 INFO L290 TraceCheckUtils]: 28: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T10_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,380 INFO L290 TraceCheckUtils]: 29: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T11_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,381 INFO L290 TraceCheckUtils]: 30: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~T12_E~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,381 INFO L290 TraceCheckUtils]: 31: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~E_M~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,381 INFO L290 TraceCheckUtils]: 32: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~E_1~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,382 INFO L290 TraceCheckUtils]: 33: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~E_2~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,382 INFO L290 TraceCheckUtils]: 34: Hoare triple {108315#(not (= ~E_4~0 0))} assume !(0 == ~E_3~0); {108315#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:23:34,382 INFO L290 TraceCheckUtils]: 35: Hoare triple {108315#(not (= ~E_4~0 0))} assume 0 == ~E_4~0;~E_4~0 := 1; {108313#false} is VALID [2022-02-21 04:23:34,382 INFO L290 TraceCheckUtils]: 36: Hoare triple {108313#false} assume !(0 == ~E_5~0); {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 37: Hoare triple {108313#false} assume !(0 == ~E_6~0); {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 38: Hoare triple {108313#false} assume !(0 == ~E_7~0); {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 39: Hoare triple {108313#false} assume !(0 == ~E_8~0); {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 40: Hoare triple {108313#false} assume !(0 == ~E_9~0); {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 41: Hoare triple {108313#false} assume !(0 == ~E_10~0); {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 42: Hoare triple {108313#false} assume !(0 == ~E_11~0); {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 43: Hoare triple {108313#false} assume 0 == ~E_12~0;~E_12~0 := 1; {108313#false} is VALID [2022-02-21 04:23:34,383 INFO L290 TraceCheckUtils]: 44: Hoare triple {108313#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108313#false} is VALID [2022-02-21 04:23:34,384 INFO L290 TraceCheckUtils]: 45: Hoare triple {108313#false} assume 1 == ~m_pc~0; {108313#false} is VALID [2022-02-21 04:23:34,384 INFO L290 TraceCheckUtils]: 46: Hoare triple {108313#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {108313#false} is VALID [2022-02-21 04:23:34,384 INFO L290 TraceCheckUtils]: 47: Hoare triple {108313#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108313#false} is VALID [2022-02-21 04:23:34,384 INFO L290 TraceCheckUtils]: 48: Hoare triple {108313#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108313#false} is VALID [2022-02-21 04:23:34,384 INFO L290 TraceCheckUtils]: 49: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp~1#1); {108313#false} is VALID [2022-02-21 04:23:34,384 INFO L290 TraceCheckUtils]: 50: Hoare triple {108313#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108313#false} is VALID [2022-02-21 04:23:34,384 INFO L290 TraceCheckUtils]: 51: Hoare triple {108313#false} assume !(1 == ~t1_pc~0); {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 52: Hoare triple {108313#false} is_transmit1_triggered_~__retres1~1#1 := 0; {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 53: Hoare triple {108313#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 54: Hoare triple {108313#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 55: Hoare triple {108313#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {108313#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 57: Hoare triple {108313#false} assume 1 == ~t2_pc~0; {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 58: Hoare triple {108313#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {108313#false} is VALID [2022-02-21 04:23:34,385 INFO L290 TraceCheckUtils]: 59: Hoare triple {108313#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108313#false} is VALID [2022-02-21 04:23:34,386 INFO L290 TraceCheckUtils]: 60: Hoare triple {108313#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108313#false} is VALID [2022-02-21 04:23:34,386 INFO L290 TraceCheckUtils]: 61: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___1~0#1); {108313#false} is VALID [2022-02-21 04:23:34,386 INFO L290 TraceCheckUtils]: 62: Hoare triple {108313#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108313#false} is VALID [2022-02-21 04:23:34,386 INFO L290 TraceCheckUtils]: 63: Hoare triple {108313#false} assume !(1 == ~t3_pc~0); {108313#false} is VALID [2022-02-21 04:23:34,386 INFO L290 TraceCheckUtils]: 64: Hoare triple {108313#false} is_transmit3_triggered_~__retres1~3#1 := 0; {108313#false} is VALID [2022-02-21 04:23:34,386 INFO L290 TraceCheckUtils]: 65: Hoare triple {108313#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108313#false} is VALID [2022-02-21 04:23:34,386 INFO L290 TraceCheckUtils]: 66: Hoare triple {108313#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 67: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___2~0#1); {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 68: Hoare triple {108313#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 69: Hoare triple {108313#false} assume 1 == ~t4_pc~0; {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 70: Hoare triple {108313#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 71: Hoare triple {108313#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 72: Hoare triple {108313#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 73: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___3~0#1); {108313#false} is VALID [2022-02-21 04:23:34,387 INFO L290 TraceCheckUtils]: 74: Hoare triple {108313#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 75: Hoare triple {108313#false} assume !(1 == ~t5_pc~0); {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 76: Hoare triple {108313#false} is_transmit5_triggered_~__retres1~5#1 := 0; {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 77: Hoare triple {108313#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 78: Hoare triple {108313#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 79: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___4~0#1); {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 80: Hoare triple {108313#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 81: Hoare triple {108313#false} assume 1 == ~t6_pc~0; {108313#false} is VALID [2022-02-21 04:23:34,388 INFO L290 TraceCheckUtils]: 82: Hoare triple {108313#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 83: Hoare triple {108313#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 84: Hoare triple {108313#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 85: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___5~0#1); {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 86: Hoare triple {108313#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 87: Hoare triple {108313#false} assume 1 == ~t7_pc~0; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 88: Hoare triple {108313#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 89: Hoare triple {108313#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 90: Hoare triple {108313#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {108313#false} is VALID [2022-02-21 04:23:34,389 INFO L290 TraceCheckUtils]: 91: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___6~0#1); {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 92: Hoare triple {108313#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 93: Hoare triple {108313#false} assume !(1 == ~t8_pc~0); {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 94: Hoare triple {108313#false} is_transmit8_triggered_~__retres1~8#1 := 0; {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 95: Hoare triple {108313#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 96: Hoare triple {108313#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 97: Hoare triple {108313#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 98: Hoare triple {108313#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 99: Hoare triple {108313#false} assume 1 == ~t9_pc~0; {108313#false} is VALID [2022-02-21 04:23:34,390 INFO L290 TraceCheckUtils]: 100: Hoare triple {108313#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 101: Hoare triple {108313#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 102: Hoare triple {108313#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 103: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___8~0#1); {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 104: Hoare triple {108313#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 105: Hoare triple {108313#false} assume !(1 == ~t10_pc~0); {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 106: Hoare triple {108313#false} is_transmit10_triggered_~__retres1~10#1 := 0; {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 107: Hoare triple {108313#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 108: Hoare triple {108313#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {108313#false} is VALID [2022-02-21 04:23:34,391 INFO L290 TraceCheckUtils]: 109: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___9~0#1); {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 110: Hoare triple {108313#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 111: Hoare triple {108313#false} assume 1 == ~t11_pc~0; {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 112: Hoare triple {108313#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 113: Hoare triple {108313#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 114: Hoare triple {108313#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 115: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___10~0#1); {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 116: Hoare triple {108313#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 117: Hoare triple {108313#false} assume !(1 == ~t12_pc~0); {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 118: Hoare triple {108313#false} is_transmit12_triggered_~__retres1~12#1 := 0; {108313#false} is VALID [2022-02-21 04:23:34,392 INFO L290 TraceCheckUtils]: 119: Hoare triple {108313#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 120: Hoare triple {108313#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 121: Hoare triple {108313#false} assume !(0 != activate_threads_~tmp___11~0#1); {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 122: Hoare triple {108313#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 123: Hoare triple {108313#false} assume 1 == ~M_E~0;~M_E~0 := 2; {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 124: Hoare triple {108313#false} assume !(1 == ~T1_E~0); {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 125: Hoare triple {108313#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 126: Hoare triple {108313#false} assume !(1 == ~T3_E~0); {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 127: Hoare triple {108313#false} assume !(1 == ~T4_E~0); {108313#false} is VALID [2022-02-21 04:23:34,393 INFO L290 TraceCheckUtils]: 128: Hoare triple {108313#false} assume !(1 == ~T5_E~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 129: Hoare triple {108313#false} assume !(1 == ~T6_E~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 130: Hoare triple {108313#false} assume !(1 == ~T7_E~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 131: Hoare triple {108313#false} assume !(1 == ~T8_E~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 132: Hoare triple {108313#false} assume !(1 == ~T9_E~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 133: Hoare triple {108313#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 134: Hoare triple {108313#false} assume !(1 == ~T11_E~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 135: Hoare triple {108313#false} assume !(1 == ~T12_E~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 136: Hoare triple {108313#false} assume !(1 == ~E_M~0); {108313#false} is VALID [2022-02-21 04:23:34,394 INFO L290 TraceCheckUtils]: 137: Hoare triple {108313#false} assume !(1 == ~E_1~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 138: Hoare triple {108313#false} assume !(1 == ~E_2~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 139: Hoare triple {108313#false} assume !(1 == ~E_3~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 140: Hoare triple {108313#false} assume !(1 == ~E_4~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 141: Hoare triple {108313#false} assume 1 == ~E_5~0;~E_5~0 := 2; {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 142: Hoare triple {108313#false} assume !(1 == ~E_6~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 143: Hoare triple {108313#false} assume !(1 == ~E_7~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 144: Hoare triple {108313#false} assume !(1 == ~E_8~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 145: Hoare triple {108313#false} assume !(1 == ~E_9~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 146: Hoare triple {108313#false} assume !(1 == ~E_10~0); {108313#false} is VALID [2022-02-21 04:23:34,395 INFO L290 TraceCheckUtils]: 147: Hoare triple {108313#false} assume !(1 == ~E_11~0); {108313#false} is VALID [2022-02-21 04:23:34,396 INFO L290 TraceCheckUtils]: 148: Hoare triple {108313#false} assume !(1 == ~E_12~0); {108313#false} is VALID [2022-02-21 04:23:34,396 INFO L290 TraceCheckUtils]: 149: Hoare triple {108313#false} assume { :end_inline_reset_delta_events } true; {108313#false} is VALID [2022-02-21 04:23:34,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,396 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,396 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103426984] [2022-02-21 04:23:34,396 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1103426984] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,397 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,397 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:34,397 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951893137] [2022-02-21 04:23:34,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,397 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:34,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:34,398 INFO L85 PathProgramCache]: Analyzing trace with hash 1049578138, now seen corresponding path program 1 times [2022-02-21 04:23:34,398 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:34,398 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835949095] [2022-02-21 04:23:34,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:34,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:34,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:34,448 INFO L290 TraceCheckUtils]: 0: Hoare triple {108316#true} assume !false; {108316#true} is VALID [2022-02-21 04:23:34,448 INFO L290 TraceCheckUtils]: 1: Hoare triple {108316#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {108316#true} is VALID [2022-02-21 04:23:34,448 INFO L290 TraceCheckUtils]: 2: Hoare triple {108316#true} assume !false; {108316#true} is VALID [2022-02-21 04:23:34,448 INFO L290 TraceCheckUtils]: 3: Hoare triple {108316#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {108316#true} is VALID [2022-02-21 04:23:34,448 INFO L290 TraceCheckUtils]: 4: Hoare triple {108316#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {108316#true} is VALID [2022-02-21 04:23:34,448 INFO L290 TraceCheckUtils]: 5: Hoare triple {108316#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {108316#true} is VALID [2022-02-21 04:23:34,448 INFO L290 TraceCheckUtils]: 6: Hoare triple {108316#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 7: Hoare triple {108316#true} assume !(0 != eval_~tmp~0#1); {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 8: Hoare triple {108316#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 9: Hoare triple {108316#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 10: Hoare triple {108316#true} assume 0 == ~M_E~0;~M_E~0 := 1; {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 11: Hoare triple {108316#true} assume !(0 == ~T1_E~0); {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 12: Hoare triple {108316#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 13: Hoare triple {108316#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 14: Hoare triple {108316#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {108316#true} is VALID [2022-02-21 04:23:34,449 INFO L290 TraceCheckUtils]: 15: Hoare triple {108316#true} assume !(0 == ~T5_E~0); {108316#true} is VALID [2022-02-21 04:23:34,450 INFO L290 TraceCheckUtils]: 16: Hoare triple {108316#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,450 INFO L290 TraceCheckUtils]: 17: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,450 INFO L290 TraceCheckUtils]: 18: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,450 INFO L290 TraceCheckUtils]: 19: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~T9_E~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,451 INFO L290 TraceCheckUtils]: 20: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,451 INFO L290 TraceCheckUtils]: 21: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,451 INFO L290 TraceCheckUtils]: 22: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,452 INFO L290 TraceCheckUtils]: 23: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,452 INFO L290 TraceCheckUtils]: 24: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,452 INFO L290 TraceCheckUtils]: 25: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,452 INFO L290 TraceCheckUtils]: 26: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,453 INFO L290 TraceCheckUtils]: 27: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,453 INFO L290 TraceCheckUtils]: 28: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,453 INFO L290 TraceCheckUtils]: 29: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,453 INFO L290 TraceCheckUtils]: 30: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,454 INFO L290 TraceCheckUtils]: 31: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,454 INFO L290 TraceCheckUtils]: 32: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,454 INFO L290 TraceCheckUtils]: 33: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,454 INFO L290 TraceCheckUtils]: 34: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,455 INFO L290 TraceCheckUtils]: 35: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,455 INFO L290 TraceCheckUtils]: 36: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,455 INFO L290 TraceCheckUtils]: 37: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,455 INFO L290 TraceCheckUtils]: 38: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,456 INFO L290 TraceCheckUtils]: 39: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,456 INFO L290 TraceCheckUtils]: 40: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,456 INFO L290 TraceCheckUtils]: 41: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,456 INFO L290 TraceCheckUtils]: 42: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,457 INFO L290 TraceCheckUtils]: 43: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t1_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,457 INFO L290 TraceCheckUtils]: 44: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,457 INFO L290 TraceCheckUtils]: 45: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,457 INFO L290 TraceCheckUtils]: 46: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,458 INFO L290 TraceCheckUtils]: 47: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,458 INFO L290 TraceCheckUtils]: 48: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,458 INFO L290 TraceCheckUtils]: 49: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,458 INFO L290 TraceCheckUtils]: 50: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,459 INFO L290 TraceCheckUtils]: 51: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,459 INFO L290 TraceCheckUtils]: 52: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,459 INFO L290 TraceCheckUtils]: 53: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,459 INFO L290 TraceCheckUtils]: 54: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,460 INFO L290 TraceCheckUtils]: 55: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t3_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,460 INFO L290 TraceCheckUtils]: 56: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,460 INFO L290 TraceCheckUtils]: 57: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,461 INFO L290 TraceCheckUtils]: 58: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,461 INFO L290 TraceCheckUtils]: 59: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,461 INFO L290 TraceCheckUtils]: 60: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,461 INFO L290 TraceCheckUtils]: 61: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,462 INFO L290 TraceCheckUtils]: 62: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,462 INFO L290 TraceCheckUtils]: 63: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,462 INFO L290 TraceCheckUtils]: 64: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,462 INFO L290 TraceCheckUtils]: 65: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,463 INFO L290 TraceCheckUtils]: 66: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,463 INFO L290 TraceCheckUtils]: 67: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,463 INFO L290 TraceCheckUtils]: 68: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,463 INFO L290 TraceCheckUtils]: 69: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,464 INFO L290 TraceCheckUtils]: 70: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,464 INFO L290 TraceCheckUtils]: 71: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,464 INFO L290 TraceCheckUtils]: 72: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,464 INFO L290 TraceCheckUtils]: 73: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,465 INFO L290 TraceCheckUtils]: 74: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,465 INFO L290 TraceCheckUtils]: 75: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,465 INFO L290 TraceCheckUtils]: 76: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,465 INFO L290 TraceCheckUtils]: 77: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,466 INFO L290 TraceCheckUtils]: 78: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,466 INFO L290 TraceCheckUtils]: 79: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t7_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,466 INFO L290 TraceCheckUtils]: 80: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,466 INFO L290 TraceCheckUtils]: 81: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,467 INFO L290 TraceCheckUtils]: 82: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,467 INFO L290 TraceCheckUtils]: 83: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,467 INFO L290 TraceCheckUtils]: 84: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,468 INFO L290 TraceCheckUtils]: 85: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,468 INFO L290 TraceCheckUtils]: 86: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,468 INFO L290 TraceCheckUtils]: 87: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,468 INFO L290 TraceCheckUtils]: 88: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,469 INFO L290 TraceCheckUtils]: 89: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,469 INFO L290 TraceCheckUtils]: 90: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,469 INFO L290 TraceCheckUtils]: 91: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t9_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,469 INFO L290 TraceCheckUtils]: 92: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,470 INFO L290 TraceCheckUtils]: 93: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,470 INFO L290 TraceCheckUtils]: 94: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,470 INFO L290 TraceCheckUtils]: 95: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,470 INFO L290 TraceCheckUtils]: 96: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,471 INFO L290 TraceCheckUtils]: 97: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,471 INFO L290 TraceCheckUtils]: 98: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,471 INFO L290 TraceCheckUtils]: 99: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,471 INFO L290 TraceCheckUtils]: 100: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,472 INFO L290 TraceCheckUtils]: 101: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,472 INFO L290 TraceCheckUtils]: 102: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,472 INFO L290 TraceCheckUtils]: 103: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,472 INFO L290 TraceCheckUtils]: 104: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,473 INFO L290 TraceCheckUtils]: 105: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,473 INFO L290 TraceCheckUtils]: 106: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,473 INFO L290 TraceCheckUtils]: 107: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,473 INFO L290 TraceCheckUtils]: 108: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,474 INFO L290 TraceCheckUtils]: 109: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t12_pc~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,474 INFO L290 TraceCheckUtils]: 110: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,474 INFO L290 TraceCheckUtils]: 111: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,474 INFO L290 TraceCheckUtils]: 112: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,475 INFO L290 TraceCheckUtils]: 113: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,475 INFO L290 TraceCheckUtils]: 114: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,475 INFO L290 TraceCheckUtils]: 115: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,476 INFO L290 TraceCheckUtils]: 116: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T1_E~0); {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,476 INFO L290 TraceCheckUtils]: 117: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,476 INFO L290 TraceCheckUtils]: 118: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,476 INFO L290 TraceCheckUtils]: 119: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 120: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {108318#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 121: Hoare triple {108318#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {108317#false} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 122: Hoare triple {108317#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 123: Hoare triple {108317#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 124: Hoare triple {108317#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 125: Hoare triple {108317#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 126: Hoare triple {108317#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,477 INFO L290 TraceCheckUtils]: 127: Hoare triple {108317#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 128: Hoare triple {108317#false} assume 1 == ~E_M~0;~E_M~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 129: Hoare triple {108317#false} assume !(1 == ~E_1~0); {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 130: Hoare triple {108317#false} assume 1 == ~E_2~0;~E_2~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 131: Hoare triple {108317#false} assume 1 == ~E_3~0;~E_3~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 132: Hoare triple {108317#false} assume 1 == ~E_4~0;~E_4~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 133: Hoare triple {108317#false} assume 1 == ~E_5~0;~E_5~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 134: Hoare triple {108317#false} assume 1 == ~E_6~0;~E_6~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 135: Hoare triple {108317#false} assume 1 == ~E_7~0;~E_7~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,478 INFO L290 TraceCheckUtils]: 136: Hoare triple {108317#false} assume 1 == ~E_8~0;~E_8~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 137: Hoare triple {108317#false} assume !(1 == ~E_9~0); {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 138: Hoare triple {108317#false} assume 1 == ~E_10~0;~E_10~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 139: Hoare triple {108317#false} assume 1 == ~E_11~0;~E_11~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 140: Hoare triple {108317#false} assume 1 == ~E_12~0;~E_12~0 := 2; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 141: Hoare triple {108317#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 142: Hoare triple {108317#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 143: Hoare triple {108317#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 144: Hoare triple {108317#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {108317#false} is VALID [2022-02-21 04:23:34,479 INFO L290 TraceCheckUtils]: 145: Hoare triple {108317#false} assume !(0 == start_simulation_~tmp~3#1); {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 146: Hoare triple {108317#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 147: Hoare triple {108317#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 148: Hoare triple {108317#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 149: Hoare triple {108317#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 150: Hoare triple {108317#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 151: Hoare triple {108317#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 152: Hoare triple {108317#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {108317#false} is VALID [2022-02-21 04:23:34,480 INFO L290 TraceCheckUtils]: 153: Hoare triple {108317#false} assume !(0 != start_simulation_~tmp___0~1#1); {108317#false} is VALID [2022-02-21 04:23:34,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:34,481 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:34,481 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1835949095] [2022-02-21 04:23:34,481 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1835949095] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:34,481 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:34,481 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:34,481 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080097266] [2022-02-21 04:23:34,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:34,482 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:34,482 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:34,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:34,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:34,482 INFO L87 Difference]: Start difference. First operand 3324 states and 4886 transitions. cyclomatic complexity: 1564 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:38,364 INFO L93 Difference]: Finished difference Result 6182 states and 9069 transitions. [2022-02-21 04:23:38,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:38,364 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:38,456 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:38,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6182 states and 9069 transitions. [2022-02-21 04:23:39,256 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5965 [2022-02-21 04:23:40,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6182 states to 6182 states and 9069 transitions. [2022-02-21 04:23:40,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6182 [2022-02-21 04:23:40,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6182 [2022-02-21 04:23:40,203 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6182 states and 9069 transitions. [2022-02-21 04:23:40,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:40,207 INFO L681 BuchiCegarLoop]: Abstraction has 6182 states and 9069 transitions. [2022-02-21 04:23:40,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6182 states and 9069 transitions. [2022-02-21 04:23:40,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6182 to 6180. [2022-02-21 04:23:40,267 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:40,272 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6182 states and 9069 transitions. Second operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:40,276 INFO L74 IsIncluded]: Start isIncluded. First operand 6182 states and 9069 transitions. Second operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:40,280 INFO L87 Difference]: Start difference. First operand 6182 states and 9069 transitions. Second operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:41,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:41,084 INFO L93 Difference]: Finished difference Result 6182 states and 9069 transitions. [2022-02-21 04:23:41,084 INFO L276 IsEmpty]: Start isEmpty. Operand 6182 states and 9069 transitions. [2022-02-21 04:23:41,091 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:41,091 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:41,097 INFO L74 IsIncluded]: Start isIncluded. First operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6182 states and 9069 transitions. [2022-02-21 04:23:41,101 INFO L87 Difference]: Start difference. First operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6182 states and 9069 transitions. [2022-02-21 04:23:41,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:41,922 INFO L93 Difference]: Finished difference Result 6182 states and 9069 transitions. [2022-02-21 04:23:41,922 INFO L276 IsEmpty]: Start isEmpty. Operand 6182 states and 9069 transitions. [2022-02-21 04:23:41,930 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:41,930 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:41,930 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:23:41,931 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:23:41,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6180 states, 6180 states have (on average 1.4671521035598705) internal successors, (9067), 6179 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:42,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6180 states to 6180 states and 9067 transitions. [2022-02-21 04:23:42,831 INFO L704 BuchiCegarLoop]: Abstraction has 6180 states and 9067 transitions. [2022-02-21 04:23:42,831 INFO L587 BuchiCegarLoop]: Abstraction has 6180 states and 9067 transitions. [2022-02-21 04:23:42,831 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:23:42,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6180 states and 9067 transitions. [2022-02-21 04:23:42,840 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5965 [2022-02-21 04:23:42,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:42,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:42,841 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:42,842 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:42,842 INFO L791 eck$LassoCheckResult]: Stem: 115349#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 115350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 114772#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 114742#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114743#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 116016#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115051#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114503#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114504#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115782#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115924#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116325#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 116326#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 115261#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115262#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 115808#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 115728#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 115729#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115882#L1206 assume !(0 == ~M_E~0); 115240#L1206-2 assume !(0 == ~T1_E~0); 115241#L1211-1 assume !(0 == ~T2_E~0); 116156#L1216-1 assume !(0 == ~T3_E~0); 115033#L1221-1 assume !(0 == ~T4_E~0); 115034#L1226-1 assume !(0 == ~T5_E~0); 114695#L1231-1 assume !(0 == ~T6_E~0); 114696#L1236-1 assume !(0 == ~T7_E~0); 116191#L1241-1 assume !(0 == ~T8_E~0); 115095#L1246-1 assume !(0 == ~T9_E~0); 115096#L1251-1 assume !(0 == ~T10_E~0); 115316#L1256-1 assume !(0 == ~T11_E~0); 114515#L1261-1 assume !(0 == ~T12_E~0); 114516#L1266-1 assume !(0 == ~E_M~0); 116309#L1271-1 assume !(0 == ~E_1~0); 115912#L1276-1 assume !(0 == ~E_2~0); 115913#L1281-1 assume !(0 == ~E_3~0); 115835#L1286-1 assume !(0 == ~E_4~0); 114937#L1291-1 assume !(0 == ~E_5~0); 114938#L1296-1 assume !(0 == ~E_6~0); 115648#L1301-1 assume !(0 == ~E_7~0); 115649#L1306-1 assume !(0 == ~E_8~0); 116093#L1311-1 assume !(0 == ~E_9~0); 114898#L1316-1 assume !(0 == ~E_10~0); 114899#L1321-1 assume !(0 == ~E_11~0); 115665#L1326-1 assume 0 == ~E_12~0;~E_12~0 := 1; 114762#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114763#L598 assume 1 == ~m_pc~0; 114822#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 114823#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116173#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116271#L1497 assume !(0 != activate_threads_~tmp~1#1); 116272#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116223#L617 assume !(1 == ~t1_pc~0); 115118#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115119#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114978#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114979#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115745#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115746#L636 assume 1 == ~t2_pc~0; 115087#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 115088#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114918#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114919#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 115781#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115440#L655 assume !(1 == ~t3_pc~0); 115441#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116178#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114792#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114793#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 116310#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116311#L674 assume 1 == ~t4_pc~0; 114611#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114612#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 115919#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114920#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 114921#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 115437#L693 assume !(1 == ~t5_pc~0); 115601#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 115242#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115243#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116095#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 115328#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 115265#L712 assume 1 == ~t6_pc~0; 115266#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 115698#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 115699#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 115992#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 115797#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115795#L731 assume 1 == ~t7_pc~0; 114766#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 114767#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 114961#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115905#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 116031#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114876#L750 assume !(1 == ~t8_pc~0); 114546#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 114545#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115062#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 116108#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 115199#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 115200#L769 assume 1 == ~t9_pc~0; 115741#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 114719#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 114720#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 115506#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 115968#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116053#L788 assume !(1 == ~t10_pc~0); 115615#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 115616#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 115850#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 115851#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 114872#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 114873#L807 assume 1 == ~t11_pc~0; 116062#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 115627#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115783#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 116215#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 116343#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 116159#L826 assume !(1 == ~t12_pc~0); 115268#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 115269#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 115803#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 116255#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 115430#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115337#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 115338#L1344-2 assume !(1 == ~T1_E~0); 115481#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 115655#L1354-1 assume !(1 == ~T3_E~0); 115656#L1359-1 assume !(1 == ~T4_E~0); 116318#L1364-1 assume !(1 == ~T5_E~0); 116319#L1369-1 assume !(1 == ~T6_E~0); 116021#L1374-1 assume !(1 == ~T7_E~0); 116022#L1379-1 assume !(1 == ~T8_E~0); 115726#L1384-1 assume !(1 == ~T9_E~0); 115727#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 116342#L1394-1 assume !(1 == ~T11_E~0); 116332#L1399-1 assume !(1 == ~T12_E~0); 116333#L1404-1 assume !(1 == ~E_M~0); 115099#L1409-1 assume !(1 == ~E_1~0); 115100#L1414-1 assume !(1 == ~E_2~0); 115946#L1419-1 assume !(1 == ~E_3~0); 115947#L1424-1 assume !(1 == ~E_4~0); 116404#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 116402#L1434-1 assume !(1 == ~E_6~0); 116400#L1439-1 assume !(1 == ~E_7~0); 116397#L1444-1 assume !(1 == ~E_8~0); 116395#L1449-1 assume !(1 == ~E_9~0); 116393#L1454-1 assume !(1 == ~E_10~0); 116391#L1459-1 assume !(1 == ~E_11~0); 116389#L1464-1 assume !(1 == ~E_12~0); 116385#L1469-1 assume { :end_inline_reset_delta_events } true; 116377#L1815-2 [2022-02-21 04:23:42,842 INFO L793 eck$LassoCheckResult]: Loop: 116377#L1815-2 assume !false; 116371#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116366#L1181 assume !false; 116365#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 116362#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116351#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 116350#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 116348#L1008 assume !(0 != eval_~tmp~0#1); 116347#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116346#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116344#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 116345#L1206-5 assume !(0 == ~T1_E~0); 118200#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 118198#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118196#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 118194#L1226-3 assume !(0 == ~T5_E~0); 118192#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 118190#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 118188#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 118186#L1246-3 assume !(0 == ~T9_E~0); 118184#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 118182#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 118180#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 118178#L1266-3 assume !(0 == ~E_M~0); 118105#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 118103#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 118101#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 118099#L1286-3 assume !(0 == ~E_4~0); 118098#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 118096#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 118094#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 118092#L1306-3 assume !(0 == ~E_8~0); 118090#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 118048#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 117973#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117872#L1326-3 assume 0 == ~E_12~0;~E_12~0 := 1; 117870#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117795#L598-42 assume !(1 == ~m_pc~0); 117753#L598-44 is_master_triggered_~__retres1~0#1 := 0; 117750#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117684#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117682#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 117618#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117616#L617-42 assume 1 == ~t1_pc~0; 117613#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 117486#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117482#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117480#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117478#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117473#L636-42 assume !(1 == ~t2_pc~0); 117472#L636-44 is_transmit2_triggered_~__retres1~2#1 := 0; 117468#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117466#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117464#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117462#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117460#L655-42 assume 1 == ~t3_pc~0; 117457#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 117405#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117288#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117250#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117241#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117234#L674-42 assume !(1 == ~t4_pc~0); 117227#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 117225#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117223#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117222#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117221#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117220#L693-42 assume !(1 == ~t5_pc~0); 117219#L693-44 is_transmit5_triggered_~__retres1~5#1 := 0; 117204#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117202#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117200#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 117197#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117195#L712-42 assume 1 == ~t6_pc~0; 117193#L713-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 117190#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117188#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117186#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 117184#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117182#L731-42 assume 1 == ~t7_pc~0; 117179#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 117177#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117175#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117173#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 117171#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117169#L750-42 assume 1 == ~t8_pc~0; 117167#L751-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117164#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117162#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117160#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 117158#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117156#L769-42 assume 1 == ~t9_pc~0; 117153#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 117151#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117149#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117147#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 117145#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117143#L788-42 assume !(1 == ~t10_pc~0); 117141#L788-44 is_transmit10_triggered_~__retres1~10#1 := 0; 117138#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 117136#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 117134#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 117132#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117129#L807-42 assume 1 == ~t11_pc~0; 117127#L808-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117124#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117122#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 117120#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 117118#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 117115#L826-42 assume !(1 == ~t12_pc~0); 117113#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 117110#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117108#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 117106#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 117104#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117101#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 115873#L1344-5 assume !(1 == ~T1_E~0); 117098#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117096#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117094#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117092#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116872#L1369-3 assume !(1 == ~T6_E~0); 116850#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116825#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 116804#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 116801#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 116800#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 116798#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 116775#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116773#L1409-3 assume !(1 == ~E_1~0); 116771#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116258#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116259#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116721#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116719#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116718#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 116717#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 116715#L1449-3 assume !(1 == ~E_9~0); 116714#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 116647#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 116614#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 116611#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 116594#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116580#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 116577#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 116574#L1834 assume !(0 == start_simulation_~tmp~3#1); 115925#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 116563#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116552#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 116546#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 116539#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116533#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116528#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 116384#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 116377#L1815-2 [2022-02-21 04:23:42,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:42,843 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2022-02-21 04:23:42,843 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:42,844 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317573639] [2022-02-21 04:23:42,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:42,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:42,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:42,891 INFO L290 TraceCheckUtils]: 0: Hoare triple {133050#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,891 INFO L290 TraceCheckUtils]: 1: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,892 INFO L290 TraceCheckUtils]: 2: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,892 INFO L290 TraceCheckUtils]: 3: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,892 INFO L290 TraceCheckUtils]: 4: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,892 INFO L290 TraceCheckUtils]: 5: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,893 INFO L290 TraceCheckUtils]: 6: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,893 INFO L290 TraceCheckUtils]: 7: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,893 INFO L290 TraceCheckUtils]: 8: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,894 INFO L290 TraceCheckUtils]: 9: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,894 INFO L290 TraceCheckUtils]: 10: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,894 INFO L290 TraceCheckUtils]: 11: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,894 INFO L290 TraceCheckUtils]: 12: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,895 INFO L290 TraceCheckUtils]: 13: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,895 INFO L290 TraceCheckUtils]: 14: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,895 INFO L290 TraceCheckUtils]: 15: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,895 INFO L290 TraceCheckUtils]: 16: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,896 INFO L290 TraceCheckUtils]: 17: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {133052#(= ~E_12~0 ~M_E~0)} is VALID [2022-02-21 04:23:42,896 INFO L290 TraceCheckUtils]: 18: Hoare triple {133052#(= ~E_12~0 ~M_E~0)} assume !(0 == ~M_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,896 INFO L290 TraceCheckUtils]: 19: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T1_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,896 INFO L290 TraceCheckUtils]: 20: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T2_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,897 INFO L290 TraceCheckUtils]: 21: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T3_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,897 INFO L290 TraceCheckUtils]: 22: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T4_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,897 INFO L290 TraceCheckUtils]: 23: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T5_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,897 INFO L290 TraceCheckUtils]: 24: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T6_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,898 INFO L290 TraceCheckUtils]: 25: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T7_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,898 INFO L290 TraceCheckUtils]: 26: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T8_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,898 INFO L290 TraceCheckUtils]: 27: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T9_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,898 INFO L290 TraceCheckUtils]: 28: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T10_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,899 INFO L290 TraceCheckUtils]: 29: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T11_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,899 INFO L290 TraceCheckUtils]: 30: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~T12_E~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,899 INFO L290 TraceCheckUtils]: 31: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_M~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,899 INFO L290 TraceCheckUtils]: 32: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_1~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,900 INFO L290 TraceCheckUtils]: 33: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_2~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,900 INFO L290 TraceCheckUtils]: 34: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_3~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,900 INFO L290 TraceCheckUtils]: 35: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_4~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,900 INFO L290 TraceCheckUtils]: 36: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_5~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,901 INFO L290 TraceCheckUtils]: 37: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_6~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,901 INFO L290 TraceCheckUtils]: 38: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_7~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,901 INFO L290 TraceCheckUtils]: 39: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_8~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,901 INFO L290 TraceCheckUtils]: 40: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_9~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,902 INFO L290 TraceCheckUtils]: 41: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_10~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,902 INFO L290 TraceCheckUtils]: 42: Hoare triple {133053#(not (= ~E_12~0 0))} assume !(0 == ~E_11~0); {133053#(not (= ~E_12~0 0))} is VALID [2022-02-21 04:23:42,902 INFO L290 TraceCheckUtils]: 43: Hoare triple {133053#(not (= ~E_12~0 0))} assume 0 == ~E_12~0;~E_12~0 := 1; {133051#false} is VALID [2022-02-21 04:23:42,902 INFO L290 TraceCheckUtils]: 44: Hoare triple {133051#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {133051#false} is VALID [2022-02-21 04:23:42,902 INFO L290 TraceCheckUtils]: 45: Hoare triple {133051#false} assume 1 == ~m_pc~0; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 46: Hoare triple {133051#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 47: Hoare triple {133051#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 48: Hoare triple {133051#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 49: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp~1#1); {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 50: Hoare triple {133051#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 51: Hoare triple {133051#false} assume !(1 == ~t1_pc~0); {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 52: Hoare triple {133051#false} is_transmit1_triggered_~__retres1~1#1 := 0; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 53: Hoare triple {133051#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 54: Hoare triple {133051#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {133051#false} is VALID [2022-02-21 04:23:42,903 INFO L290 TraceCheckUtils]: 55: Hoare triple {133051#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 56: Hoare triple {133051#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 57: Hoare triple {133051#false} assume 1 == ~t2_pc~0; {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 58: Hoare triple {133051#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 59: Hoare triple {133051#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 60: Hoare triple {133051#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 61: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___1~0#1); {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 62: Hoare triple {133051#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 63: Hoare triple {133051#false} assume !(1 == ~t3_pc~0); {133051#false} is VALID [2022-02-21 04:23:42,904 INFO L290 TraceCheckUtils]: 64: Hoare triple {133051#false} is_transmit3_triggered_~__retres1~3#1 := 0; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 65: Hoare triple {133051#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 66: Hoare triple {133051#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 67: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___2~0#1); {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 68: Hoare triple {133051#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 69: Hoare triple {133051#false} assume 1 == ~t4_pc~0; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 70: Hoare triple {133051#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 71: Hoare triple {133051#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 72: Hoare triple {133051#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 73: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___3~0#1); {133051#false} is VALID [2022-02-21 04:23:42,905 INFO L290 TraceCheckUtils]: 74: Hoare triple {133051#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 75: Hoare triple {133051#false} assume !(1 == ~t5_pc~0); {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 76: Hoare triple {133051#false} is_transmit5_triggered_~__retres1~5#1 := 0; {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 77: Hoare triple {133051#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 78: Hoare triple {133051#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 79: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___4~0#1); {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 80: Hoare triple {133051#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 81: Hoare triple {133051#false} assume 1 == ~t6_pc~0; {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 82: Hoare triple {133051#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {133051#false} is VALID [2022-02-21 04:23:42,906 INFO L290 TraceCheckUtils]: 83: Hoare triple {133051#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 84: Hoare triple {133051#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 85: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___5~0#1); {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 86: Hoare triple {133051#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 87: Hoare triple {133051#false} assume 1 == ~t7_pc~0; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 88: Hoare triple {133051#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 89: Hoare triple {133051#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 90: Hoare triple {133051#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 91: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___6~0#1); {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 92: Hoare triple {133051#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {133051#false} is VALID [2022-02-21 04:23:42,907 INFO L290 TraceCheckUtils]: 93: Hoare triple {133051#false} assume !(1 == ~t8_pc~0); {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 94: Hoare triple {133051#false} is_transmit8_triggered_~__retres1~8#1 := 0; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 95: Hoare triple {133051#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 96: Hoare triple {133051#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 97: Hoare triple {133051#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 98: Hoare triple {133051#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 99: Hoare triple {133051#false} assume 1 == ~t9_pc~0; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 100: Hoare triple {133051#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 101: Hoare triple {133051#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {133051#false} is VALID [2022-02-21 04:23:42,908 INFO L290 TraceCheckUtils]: 102: Hoare triple {133051#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 103: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___8~0#1); {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 104: Hoare triple {133051#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 105: Hoare triple {133051#false} assume !(1 == ~t10_pc~0); {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 106: Hoare triple {133051#false} is_transmit10_triggered_~__retres1~10#1 := 0; {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 107: Hoare triple {133051#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 108: Hoare triple {133051#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 109: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___9~0#1); {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 110: Hoare triple {133051#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 111: Hoare triple {133051#false} assume 1 == ~t11_pc~0; {133051#false} is VALID [2022-02-21 04:23:42,909 INFO L290 TraceCheckUtils]: 112: Hoare triple {133051#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 113: Hoare triple {133051#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 114: Hoare triple {133051#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 115: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___10~0#1); {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 116: Hoare triple {133051#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 117: Hoare triple {133051#false} assume !(1 == ~t12_pc~0); {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 118: Hoare triple {133051#false} is_transmit12_triggered_~__retres1~12#1 := 0; {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 119: Hoare triple {133051#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 120: Hoare triple {133051#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {133051#false} is VALID [2022-02-21 04:23:42,910 INFO L290 TraceCheckUtils]: 121: Hoare triple {133051#false} assume !(0 != activate_threads_~tmp___11~0#1); {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 122: Hoare triple {133051#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 123: Hoare triple {133051#false} assume 1 == ~M_E~0;~M_E~0 := 2; {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 124: Hoare triple {133051#false} assume !(1 == ~T1_E~0); {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 125: Hoare triple {133051#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 126: Hoare triple {133051#false} assume !(1 == ~T3_E~0); {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 127: Hoare triple {133051#false} assume !(1 == ~T4_E~0); {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 128: Hoare triple {133051#false} assume !(1 == ~T5_E~0); {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 129: Hoare triple {133051#false} assume !(1 == ~T6_E~0); {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 130: Hoare triple {133051#false} assume !(1 == ~T7_E~0); {133051#false} is VALID [2022-02-21 04:23:42,911 INFO L290 TraceCheckUtils]: 131: Hoare triple {133051#false} assume !(1 == ~T8_E~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 132: Hoare triple {133051#false} assume !(1 == ~T9_E~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 133: Hoare triple {133051#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 134: Hoare triple {133051#false} assume !(1 == ~T11_E~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 135: Hoare triple {133051#false} assume !(1 == ~T12_E~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 136: Hoare triple {133051#false} assume !(1 == ~E_M~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 137: Hoare triple {133051#false} assume !(1 == ~E_1~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 138: Hoare triple {133051#false} assume !(1 == ~E_2~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 139: Hoare triple {133051#false} assume !(1 == ~E_3~0); {133051#false} is VALID [2022-02-21 04:23:42,912 INFO L290 TraceCheckUtils]: 140: Hoare triple {133051#false} assume !(1 == ~E_4~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 141: Hoare triple {133051#false} assume 1 == ~E_5~0;~E_5~0 := 2; {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 142: Hoare triple {133051#false} assume !(1 == ~E_6~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 143: Hoare triple {133051#false} assume !(1 == ~E_7~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 144: Hoare triple {133051#false} assume !(1 == ~E_8~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 145: Hoare triple {133051#false} assume !(1 == ~E_9~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 146: Hoare triple {133051#false} assume !(1 == ~E_10~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 147: Hoare triple {133051#false} assume !(1 == ~E_11~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 148: Hoare triple {133051#false} assume !(1 == ~E_12~0); {133051#false} is VALID [2022-02-21 04:23:42,913 INFO L290 TraceCheckUtils]: 149: Hoare triple {133051#false} assume { :end_inline_reset_delta_events } true; {133051#false} is VALID [2022-02-21 04:23:42,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:42,914 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:42,914 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317573639] [2022-02-21 04:23:42,914 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317573639] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:42,914 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:42,914 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:42,914 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532671240] [2022-02-21 04:23:42,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:42,915 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:42,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:42,915 INFO L85 PathProgramCache]: Analyzing trace with hash -1369851815, now seen corresponding path program 1 times [2022-02-21 04:23:42,915 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:42,915 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116833194] [2022-02-21 04:23:42,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:42,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:42,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:42,942 INFO L290 TraceCheckUtils]: 0: Hoare triple {133054#true} assume !false; {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 1: Hoare triple {133054#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 2: Hoare triple {133054#true} assume !false; {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 3: Hoare triple {133054#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 4: Hoare triple {133054#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 5: Hoare triple {133054#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 6: Hoare triple {133054#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 7: Hoare triple {133054#true} assume !(0 != eval_~tmp~0#1); {133054#true} is VALID [2022-02-21 04:23:42,943 INFO L290 TraceCheckUtils]: 8: Hoare triple {133054#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 9: Hoare triple {133054#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 10: Hoare triple {133054#true} assume 0 == ~M_E~0;~M_E~0 := 1; {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 11: Hoare triple {133054#true} assume !(0 == ~T1_E~0); {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 12: Hoare triple {133054#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 13: Hoare triple {133054#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 14: Hoare triple {133054#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 15: Hoare triple {133054#true} assume !(0 == ~T5_E~0); {133054#true} is VALID [2022-02-21 04:23:42,944 INFO L290 TraceCheckUtils]: 16: Hoare triple {133054#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,945 INFO L290 TraceCheckUtils]: 17: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,945 INFO L290 TraceCheckUtils]: 18: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,945 INFO L290 TraceCheckUtils]: 19: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~T9_E~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,946 INFO L290 TraceCheckUtils]: 20: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,946 INFO L290 TraceCheckUtils]: 21: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,946 INFO L290 TraceCheckUtils]: 22: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,946 INFO L290 TraceCheckUtils]: 23: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,947 INFO L290 TraceCheckUtils]: 24: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,947 INFO L290 TraceCheckUtils]: 25: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,947 INFO L290 TraceCheckUtils]: 26: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,947 INFO L290 TraceCheckUtils]: 27: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_4~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,948 INFO L290 TraceCheckUtils]: 28: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,948 INFO L290 TraceCheckUtils]: 29: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,948 INFO L290 TraceCheckUtils]: 30: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,948 INFO L290 TraceCheckUtils]: 31: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,949 INFO L290 TraceCheckUtils]: 32: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,949 INFO L290 TraceCheckUtils]: 33: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,949 INFO L290 TraceCheckUtils]: 34: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,949 INFO L290 TraceCheckUtils]: 35: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,950 INFO L290 TraceCheckUtils]: 36: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,950 INFO L290 TraceCheckUtils]: 37: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~m_pc~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,950 INFO L290 TraceCheckUtils]: 38: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,951 INFO L290 TraceCheckUtils]: 39: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,951 INFO L290 TraceCheckUtils]: 40: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,951 INFO L290 TraceCheckUtils]: 41: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,951 INFO L290 TraceCheckUtils]: 42: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,952 INFO L290 TraceCheckUtils]: 43: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,952 INFO L290 TraceCheckUtils]: 44: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,952 INFO L290 TraceCheckUtils]: 45: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,952 INFO L290 TraceCheckUtils]: 46: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,953 INFO L290 TraceCheckUtils]: 47: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,953 INFO L290 TraceCheckUtils]: 48: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,953 INFO L290 TraceCheckUtils]: 49: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t2_pc~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,953 INFO L290 TraceCheckUtils]: 50: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,954 INFO L290 TraceCheckUtils]: 51: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,954 INFO L290 TraceCheckUtils]: 52: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,954 INFO L290 TraceCheckUtils]: 53: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,955 INFO L290 TraceCheckUtils]: 54: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,955 INFO L290 TraceCheckUtils]: 55: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,955 INFO L290 TraceCheckUtils]: 56: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,955 INFO L290 TraceCheckUtils]: 57: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,956 INFO L290 TraceCheckUtils]: 58: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,956 INFO L290 TraceCheckUtils]: 59: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,956 INFO L290 TraceCheckUtils]: 60: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,956 INFO L290 TraceCheckUtils]: 61: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,957 INFO L290 TraceCheckUtils]: 62: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,957 INFO L290 TraceCheckUtils]: 63: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,957 INFO L290 TraceCheckUtils]: 64: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,957 INFO L290 TraceCheckUtils]: 65: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,958 INFO L290 TraceCheckUtils]: 66: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,958 INFO L290 TraceCheckUtils]: 67: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t5_pc~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,958 INFO L290 TraceCheckUtils]: 68: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,958 INFO L290 TraceCheckUtils]: 69: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,959 INFO L290 TraceCheckUtils]: 70: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,959 INFO L290 TraceCheckUtils]: 71: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,959 INFO L290 TraceCheckUtils]: 72: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,960 INFO L290 TraceCheckUtils]: 73: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t6_pc~0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,960 INFO L290 TraceCheckUtils]: 74: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,960 INFO L290 TraceCheckUtils]: 75: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,960 INFO L290 TraceCheckUtils]: 76: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,961 INFO L290 TraceCheckUtils]: 77: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,961 INFO L290 TraceCheckUtils]: 78: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,961 INFO L290 TraceCheckUtils]: 79: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,961 INFO L290 TraceCheckUtils]: 80: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,962 INFO L290 TraceCheckUtils]: 81: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,962 INFO L290 TraceCheckUtils]: 82: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,962 INFO L290 TraceCheckUtils]: 83: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,962 INFO L290 TraceCheckUtils]: 84: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,963 INFO L290 TraceCheckUtils]: 85: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t8_pc~0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,963 INFO L290 TraceCheckUtils]: 86: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,963 INFO L290 TraceCheckUtils]: 87: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,963 INFO L290 TraceCheckUtils]: 88: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,964 INFO L290 TraceCheckUtils]: 89: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,964 INFO L290 TraceCheckUtils]: 90: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,964 INFO L290 TraceCheckUtils]: 91: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,965 INFO L290 TraceCheckUtils]: 92: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,965 INFO L290 TraceCheckUtils]: 93: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,965 INFO L290 TraceCheckUtils]: 94: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,965 INFO L290 TraceCheckUtils]: 95: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,966 INFO L290 TraceCheckUtils]: 96: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,966 INFO L290 TraceCheckUtils]: 97: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t10_pc~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,966 INFO L290 TraceCheckUtils]: 98: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,966 INFO L290 TraceCheckUtils]: 99: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,967 INFO L290 TraceCheckUtils]: 100: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,967 INFO L290 TraceCheckUtils]: 101: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,967 INFO L290 TraceCheckUtils]: 102: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,967 INFO L290 TraceCheckUtils]: 103: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t11_pc~0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,968 INFO L290 TraceCheckUtils]: 104: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,968 INFO L290 TraceCheckUtils]: 105: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,968 INFO L290 TraceCheckUtils]: 106: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,968 INFO L290 TraceCheckUtils]: 107: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,969 INFO L290 TraceCheckUtils]: 108: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,969 INFO L290 TraceCheckUtils]: 109: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t12_pc~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,969 INFO L290 TraceCheckUtils]: 110: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,970 INFO L290 TraceCheckUtils]: 111: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,970 INFO L290 TraceCheckUtils]: 112: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,970 INFO L290 TraceCheckUtils]: 113: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,970 INFO L290 TraceCheckUtils]: 114: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,971 INFO L290 TraceCheckUtils]: 115: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,971 INFO L290 TraceCheckUtils]: 116: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T1_E~0); {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,971 INFO L290 TraceCheckUtils]: 117: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,971 INFO L290 TraceCheckUtils]: 118: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,972 INFO L290 TraceCheckUtils]: 119: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,972 INFO L290 TraceCheckUtils]: 120: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {133056#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:23:42,972 INFO L290 TraceCheckUtils]: 121: Hoare triple {133056#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {133055#false} is VALID [2022-02-21 04:23:42,972 INFO L290 TraceCheckUtils]: 122: Hoare triple {133055#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,972 INFO L290 TraceCheckUtils]: 123: Hoare triple {133055#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,972 INFO L290 TraceCheckUtils]: 124: Hoare triple {133055#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 125: Hoare triple {133055#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 126: Hoare triple {133055#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 127: Hoare triple {133055#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 128: Hoare triple {133055#false} assume 1 == ~E_M~0;~E_M~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 129: Hoare triple {133055#false} assume !(1 == ~E_1~0); {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 130: Hoare triple {133055#false} assume 1 == ~E_2~0;~E_2~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 131: Hoare triple {133055#false} assume 1 == ~E_3~0;~E_3~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 132: Hoare triple {133055#false} assume 1 == ~E_4~0;~E_4~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,973 INFO L290 TraceCheckUtils]: 133: Hoare triple {133055#false} assume 1 == ~E_5~0;~E_5~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 134: Hoare triple {133055#false} assume 1 == ~E_6~0;~E_6~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 135: Hoare triple {133055#false} assume 1 == ~E_7~0;~E_7~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 136: Hoare triple {133055#false} assume 1 == ~E_8~0;~E_8~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 137: Hoare triple {133055#false} assume !(1 == ~E_9~0); {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 138: Hoare triple {133055#false} assume 1 == ~E_10~0;~E_10~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 139: Hoare triple {133055#false} assume 1 == ~E_11~0;~E_11~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 140: Hoare triple {133055#false} assume 1 == ~E_12~0;~E_12~0 := 2; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 141: Hoare triple {133055#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {133055#false} is VALID [2022-02-21 04:23:42,974 INFO L290 TraceCheckUtils]: 142: Hoare triple {133055#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 143: Hoare triple {133055#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 144: Hoare triple {133055#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 145: Hoare triple {133055#false} assume !(0 == start_simulation_~tmp~3#1); {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 146: Hoare triple {133055#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 147: Hoare triple {133055#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 148: Hoare triple {133055#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 149: Hoare triple {133055#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 150: Hoare triple {133055#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 151: Hoare triple {133055#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {133055#false} is VALID [2022-02-21 04:23:42,975 INFO L290 TraceCheckUtils]: 152: Hoare triple {133055#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {133055#false} is VALID [2022-02-21 04:23:42,976 INFO L290 TraceCheckUtils]: 153: Hoare triple {133055#false} assume !(0 != start_simulation_~tmp___0~1#1); {133055#false} is VALID [2022-02-21 04:23:42,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:42,976 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:42,976 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116833194] [2022-02-21 04:23:42,976 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116833194] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:42,976 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:42,977 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:42,977 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883696514] [2022-02-21 04:23:42,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:42,977 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:42,977 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:42,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:23:42,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:23:42,978 INFO L87 Difference]: Start difference. First operand 6180 states and 9067 transitions. cyclomatic complexity: 2891 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:48,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:48,616 INFO L93 Difference]: Finished difference Result 11670 states and 17086 transitions. [2022-02-21 04:23:48,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:23:48,616 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:48,667 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 150 edges. 150 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:23:48,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11670 states and 17086 transitions. [2022-02-21 04:23:51,781 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11439 [2022-02-21 04:23:54,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11670 states to 11670 states and 17086 transitions. [2022-02-21 04:23:54,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11670 [2022-02-21 04:23:54,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11670 [2022-02-21 04:23:54,628 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11670 states and 17086 transitions. [2022-02-21 04:23:54,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:23:54,634 INFO L681 BuchiCegarLoop]: Abstraction has 11670 states and 17086 transitions. [2022-02-21 04:23:54,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11670 states and 17086 transitions. [2022-02-21 04:23:54,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11670 to 11666. [2022-02-21 04:23:54,731 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:23:54,743 INFO L82 GeneralOperation]: Start isEquivalent. First operand 11670 states and 17086 transitions. Second operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,755 INFO L74 IsIncluded]: Start isIncluded. First operand 11670 states and 17086 transitions. Second operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:54,767 INFO L87 Difference]: Start difference. First operand 11670 states and 17086 transitions. Second operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:57,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:23:57,657 INFO L93 Difference]: Finished difference Result 11670 states and 17086 transitions. [2022-02-21 04:23:57,657 INFO L276 IsEmpty]: Start isEmpty. Operand 11670 states and 17086 transitions. [2022-02-21 04:23:57,665 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:23:57,665 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:23:57,678 INFO L74 IsIncluded]: Start isIncluded. First operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 11670 states and 17086 transitions. [2022-02-21 04:23:57,690 INFO L87 Difference]: Start difference. First operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 11670 states and 17086 transitions. [2022-02-21 04:24:00,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:00,659 INFO L93 Difference]: Finished difference Result 11670 states and 17086 transitions. [2022-02-21 04:24:00,659 INFO L276 IsEmpty]: Start isEmpty. Operand 11670 states and 17086 transitions. [2022-02-21 04:24:00,667 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:00,667 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:00,667 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:00,668 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:00,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11666 states, 11666 states have (on average 1.4642551002914452) internal successors, (17082), 11665 states have internal predecessors, (17082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:03,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11666 states to 11666 states and 17082 transitions. [2022-02-21 04:24:03,733 INFO L704 BuchiCegarLoop]: Abstraction has 11666 states and 17082 transitions. [2022-02-21 04:24:03,733 INFO L587 BuchiCegarLoop]: Abstraction has 11666 states and 17082 transitions. [2022-02-21 04:24:03,733 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:24:03,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11666 states and 17082 transitions. [2022-02-21 04:24:03,756 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11439 [2022-02-21 04:24:03,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:03,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:03,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,758 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:03,758 INFO L791 eck$LassoCheckResult]: Stem: 145582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 145583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 144999#L1778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144969#L846 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144970#L853 assume 1 == ~m_i~0;~m_st~0 := 0; 146311#L853-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 145280#L858-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144729#L863-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144730#L868-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 146051#L873-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 146209#L878-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 146715#L883-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 146716#L888-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 145494#L893-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 145495#L898-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 146082#L903-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 145990#L908-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 145991#L913-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 146160#L1206 assume !(0 == ~M_E~0); 145472#L1206-2 assume !(0 == ~T1_E~0); 145473#L1211-1 assume !(0 == ~T2_E~0); 146484#L1216-1 assume !(0 == ~T3_E~0); 145262#L1221-1 assume !(0 == ~T4_E~0); 145263#L1226-1 assume !(0 == ~T5_E~0); 144922#L1231-1 assume !(0 == ~T6_E~0); 144923#L1236-1 assume !(0 == ~T7_E~0); 146523#L1241-1 assume !(0 == ~T8_E~0); 145325#L1246-1 assume !(0 == ~T9_E~0); 145326#L1251-1 assume !(0 == ~T10_E~0); 145549#L1256-1 assume !(0 == ~T11_E~0); 144741#L1261-1 assume !(0 == ~T12_E~0); 144742#L1266-1 assume !(0 == ~E_M~0); 146695#L1271-1 assume !(0 == ~E_1~0); 146194#L1276-1 assume !(0 == ~E_2~0); 146195#L1281-1 assume !(0 == ~E_3~0); 146110#L1286-1 assume !(0 == ~E_4~0); 145165#L1291-1 assume !(0 == ~E_5~0); 145166#L1296-1 assume !(0 == ~E_6~0); 145908#L1301-1 assume !(0 == ~E_7~0); 145909#L1306-1 assume !(0 == ~E_8~0); 146408#L1311-1 assume !(0 == ~E_9~0); 145126#L1316-1 assume !(0 == ~E_10~0); 145127#L1321-1 assume !(0 == ~E_11~0); 145927#L1326-1 assume !(0 == ~E_12~0); 144989#L1331-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144990#L598 assume 1 == ~m_pc~0; 145049#L599 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 145050#L609 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146501#L610 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 146640#L1497 assume !(0 != activate_threads_~tmp~1#1); 146641#L1497-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 146569#L617 assume !(1 == ~t1_pc~0); 145348#L617-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145349#L628 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145207#L629 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 145208#L1505 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 146007#L1505-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 146008#L636 assume 1 == ~t2_pc~0; 145317#L637 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 145318#L647 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145146#L648 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 145147#L1513 assume !(0 != activate_threads_~tmp___1~0#1); 146050#L1513-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145676#L655 assume !(1 == ~t3_pc~0); 145677#L655-2 is_transmit3_triggered_~__retres1~3#1 := 0; 146507#L666 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145019#L667 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 145020#L1521 assume !(0 != activate_threads_~tmp___2~0#1); 146696#L1521-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 146697#L674 assume 1 == ~t4_pc~0; 144838#L675 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 144839#L685 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 146201#L686 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 145148#L1529 assume !(0 != activate_threads_~tmp___3~0#1); 145149#L1529-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 145673#L693 assume !(1 == ~t5_pc~0); 145858#L693-2 is_transmit5_triggered_~__retres1~5#1 := 0; 145474#L704 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 145475#L705 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 146411#L1537 assume !(0 != activate_threads_~tmp___4~0#1); 145561#L1537-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 145498#L712 assume 1 == ~t6_pc~0; 145499#L713 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 145959#L723 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 145960#L724 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 146285#L1545 assume !(0 != activate_threads_~tmp___5~0#1); 146071#L1545-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 146068#L731 assume 1 == ~t7_pc~0; 144993#L732 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 144994#L742 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 145190#L743 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 146189#L1553 assume !(0 != activate_threads_~tmp___6~0#1); 146326#L1553-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 145104#L750 assume !(1 == ~t8_pc~0); 144772#L750-2 is_transmit8_triggered_~__retres1~8#1 := 0; 144771#L761 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 145291#L762 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 146430#L1561 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 145429#L1561-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 145430#L769 assume 1 == ~t9_pc~0; 146003#L770 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 144946#L780 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 144947#L781 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 145750#L1569 assume !(0 != activate_threads_~tmp___8~0#1); 146257#L1569-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 146354#L788 assume !(1 == ~t10_pc~0); 145872#L788-2 is_transmit10_triggered_~__retres1~10#1 := 0; 145873#L799 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 146125#L800 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 146126#L1577 assume !(0 != activate_threads_~tmp___9~0#1); 145100#L1577-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 145101#L807 assume 1 == ~t11_pc~0; 146365#L808 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 145887#L818 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 146052#L819 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 146561#L1585 assume !(0 != activate_threads_~tmp___10~0#1); 146774#L1585-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 146486#L826 assume !(1 == ~t12_pc~0); 145501#L826-2 is_transmit12_triggered_~__retres1~12#1 := 0; 145502#L837 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 146077#L838 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 146609#L1593 assume !(0 != activate_threads_~tmp___11~0#1); 145666#L1593-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145570#L1344 assume 1 == ~M_E~0;~M_E~0 := 2; 145571#L1344-2 assume !(1 == ~T1_E~0); 145722#L1349-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 145917#L1354-1 assume !(1 == ~T3_E~0); 145918#L1359-1 assume !(1 == ~T4_E~0); 146705#L1364-1 assume !(1 == ~T5_E~0); 146706#L1369-1 assume !(1 == ~T6_E~0); 146316#L1374-1 assume !(1 == ~T7_E~0); 146317#L1379-1 assume !(1 == ~T8_E~0); 145988#L1384-1 assume !(1 == ~T9_E~0); 145989#L1389-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 146526#L1394-1 assume !(1 == ~T11_E~0); 146527#L1399-1 assume !(1 == ~T12_E~0); 146655#L1404-1 assume !(1 == ~E_M~0); 145329#L1409-1 assume !(1 == ~E_1~0); 145330#L1414-1 assume !(1 == ~E_2~0); 146638#L1419-1 assume !(1 == ~E_3~0); 146957#L1424-1 assume !(1 == ~E_4~0); 146955#L1429-1 assume 1 == ~E_5~0;~E_5~0 := 2; 146953#L1434-1 assume !(1 == ~E_6~0); 146919#L1439-1 assume !(1 == ~E_7~0); 146917#L1444-1 assume !(1 == ~E_8~0); 146915#L1449-1 assume !(1 == ~E_9~0); 146883#L1454-1 assume !(1 == ~E_10~0); 146856#L1459-1 assume !(1 == ~E_11~0); 146838#L1464-1 assume !(1 == ~E_12~0); 146821#L1469-1 assume { :end_inline_reset_delta_events } true; 146813#L1815-2 [2022-02-21 04:24:03,758 INFO L793 eck$LassoCheckResult]: Loop: 146813#L1815-2 assume !false; 146807#L1816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 146802#L1181 assume !false; 146801#L1004 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 146798#L926 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 146787#L993 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 146786#L994 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 146784#L1008 assume !(0 != eval_~tmp~0#1); 146783#L1196 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146782#L846-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146780#L1206-3 assume 0 == ~M_E~0;~M_E~0 := 1; 146781#L1206-5 assume !(0 == ~T1_E~0); 154278#L1211-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 154275#L1216-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 154273#L1221-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 154271#L1226-3 assume !(0 == ~T5_E~0); 154269#L1231-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 154267#L1236-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 154265#L1241-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 154262#L1246-3 assume !(0 == ~T9_E~0); 154260#L1251-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 154258#L1256-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 154256#L1261-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 154254#L1266-3 assume !(0 == ~E_M~0); 154252#L1271-3 assume 0 == ~E_1~0;~E_1~0 := 1; 154249#L1276-3 assume 0 == ~E_2~0;~E_2~0 := 1; 154247#L1281-3 assume 0 == ~E_3~0;~E_3~0 := 1; 154245#L1286-3 assume !(0 == ~E_4~0); 154243#L1291-3 assume 0 == ~E_5~0;~E_5~0 := 1; 154241#L1296-3 assume 0 == ~E_6~0;~E_6~0 := 1; 154239#L1301-3 assume 0 == ~E_7~0;~E_7~0 := 1; 154236#L1306-3 assume !(0 == ~E_8~0); 154234#L1311-3 assume 0 == ~E_9~0;~E_9~0 := 1; 154232#L1316-3 assume 0 == ~E_10~0;~E_10~0 := 1; 154230#L1321-3 assume 0 == ~E_11~0;~E_11~0 := 1; 154228#L1326-3 assume !(0 == ~E_12~0); 154226#L1331-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154223#L598-42 assume 1 == ~m_pc~0; 154220#L599-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 154218#L609-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154216#L610-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 154214#L1497-42 assume !(0 != activate_threads_~tmp~1#1); 154212#L1497-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154209#L617-42 assume 1 == ~t1_pc~0; 154206#L618-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 154204#L628-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154202#L629-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154200#L1505-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 154198#L1505-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154195#L636-42 assume 1 == ~t2_pc~0; 154192#L637-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 154190#L647-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154188#L648-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154186#L1513-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 154184#L1513-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154181#L655-42 assume 1 == ~t3_pc~0; 154178#L656-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 154176#L666-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154174#L667-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154172#L1521-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 154170#L1521-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154167#L674-42 assume !(1 == ~t4_pc~0); 154164#L674-44 is_transmit4_triggered_~__retres1~4#1 := 0; 154162#L685-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154160#L686-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 154158#L1529-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 154156#L1529-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154153#L693-42 assume 1 == ~t5_pc~0; 154150#L694-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 154148#L704-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154146#L705-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 154144#L1537-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 154142#L1537-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154139#L712-42 assume !(1 == ~t6_pc~0); 154136#L712-44 is_transmit6_triggered_~__retres1~6#1 := 0; 154134#L723-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154132#L724-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 154130#L1545-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154128#L1545-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154126#L731-42 assume 1 == ~t7_pc~0; 154123#L732-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 154121#L742-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154119#L743-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 154117#L1553-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 154115#L1553-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154113#L750-42 assume !(1 == ~t8_pc~0); 154110#L750-44 is_transmit8_triggered_~__retres1~8#1 := 0; 154109#L761-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154108#L762-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 154107#L1561-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 154106#L1561-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 154105#L769-42 assume 1 == ~t9_pc~0; 154103#L770-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 154102#L780-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 154101#L781-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 154100#L1569-42 assume !(0 != activate_threads_~tmp___8~0#1); 154098#L1569-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 154095#L788-42 assume 1 == ~t10_pc~0; 154092#L789-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 154090#L799-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 154088#L800-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 154086#L1577-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 154084#L1577-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 154081#L807-42 assume !(1 == ~t11_pc~0); 154078#L807-44 is_transmit11_triggered_~__retres1~11#1 := 0; 154076#L818-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 154074#L819-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 154072#L1585-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 154070#L1585-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 154069#L826-42 assume !(1 == ~t12_pc~0); 154066#L826-44 is_transmit12_triggered_~__retres1~12#1 := 0; 154063#L837-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 154061#L838-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 154059#L1593-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 154057#L1593-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154055#L1344-3 assume 1 == ~M_E~0;~M_E~0 := 2; 146151#L1344-5 assume !(1 == ~T1_E~0); 154051#L1349-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 154049#L1354-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 154047#L1359-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 154045#L1364-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 154043#L1369-3 assume !(1 == ~T6_E~0); 154040#L1374-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 154038#L1379-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 154036#L1384-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 154033#L1389-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 154031#L1394-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 154029#L1399-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 154026#L1404-3 assume 1 == ~E_M~0;~E_M~0 := 2; 154024#L1409-3 assume !(1 == ~E_1~0); 154022#L1414-3 assume 1 == ~E_2~0;~E_2~0 := 2; 154020#L1419-3 assume 1 == ~E_3~0;~E_3~0 := 2; 154018#L1424-3 assume 1 == ~E_4~0;~E_4~0 := 2; 154015#L1429-3 assume 1 == ~E_5~0;~E_5~0 := 2; 154012#L1434-3 assume 1 == ~E_6~0;~E_6~0 := 2; 154010#L1439-3 assume 1 == ~E_7~0;~E_7~0 := 2; 154008#L1444-3 assume 1 == ~E_8~0;~E_8~0 := 2; 154006#L1449-3 assume !(1 == ~E_9~0); 154004#L1454-3 assume 1 == ~E_10~0;~E_10~0 := 2; 154002#L1459-3 assume 1 == ~E_11~0;~E_11~0 := 2; 146951#L1464-3 assume 1 == ~E_12~0;~E_12~0 := 2; 146947#L1469-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 146913#L926-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 146901#L993-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 146900#L994-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 146899#L1834 assume !(0 == start_simulation_~tmp~3#1); 146210#L1834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 146878#L926-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 146867#L993-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 146865#L994-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 146852#L1789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 146835#L1796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 146831#L1797 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 146820#L1847 assume !(0 != start_simulation_~tmp___0~1#1); 146813#L1815-2 [2022-02-21 04:24:03,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,759 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2022-02-21 04:24:03,759 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,759 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939729604] [2022-02-21 04:24:03,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:03,783 INFO L290 TraceCheckUtils]: 0: Hoare triple {179738#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,784 INFO L290 TraceCheckUtils]: 1: Hoare triple {179740#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,784 INFO L290 TraceCheckUtils]: 2: Hoare triple {179740#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,784 INFO L290 TraceCheckUtils]: 3: Hoare triple {179740#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,785 INFO L290 TraceCheckUtils]: 4: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,785 INFO L290 TraceCheckUtils]: 5: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,785 INFO L290 TraceCheckUtils]: 6: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,785 INFO L290 TraceCheckUtils]: 7: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,786 INFO L290 TraceCheckUtils]: 8: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,786 INFO L290 TraceCheckUtils]: 9: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,786 INFO L290 TraceCheckUtils]: 10: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,787 INFO L290 TraceCheckUtils]: 11: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,787 INFO L290 TraceCheckUtils]: 12: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,787 INFO L290 TraceCheckUtils]: 13: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,788 INFO L290 TraceCheckUtils]: 14: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,788 INFO L290 TraceCheckUtils]: 15: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,788 INFO L290 TraceCheckUtils]: 16: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,788 INFO L290 TraceCheckUtils]: 17: Hoare triple {179740#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,789 INFO L290 TraceCheckUtils]: 18: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,789 INFO L290 TraceCheckUtils]: 19: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,789 INFO L290 TraceCheckUtils]: 20: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,790 INFO L290 TraceCheckUtils]: 21: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,790 INFO L290 TraceCheckUtils]: 22: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,790 INFO L290 TraceCheckUtils]: 23: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,790 INFO L290 TraceCheckUtils]: 24: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,791 INFO L290 TraceCheckUtils]: 25: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T7_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,791 INFO L290 TraceCheckUtils]: 26: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T8_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,791 INFO L290 TraceCheckUtils]: 27: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T9_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,792 INFO L290 TraceCheckUtils]: 28: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T10_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,792 INFO L290 TraceCheckUtils]: 29: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T11_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,792 INFO L290 TraceCheckUtils]: 30: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~T12_E~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,792 INFO L290 TraceCheckUtils]: 31: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,793 INFO L290 TraceCheckUtils]: 32: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,793 INFO L290 TraceCheckUtils]: 33: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,793 INFO L290 TraceCheckUtils]: 34: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,794 INFO L290 TraceCheckUtils]: 35: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,794 INFO L290 TraceCheckUtils]: 36: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,794 INFO L290 TraceCheckUtils]: 37: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,794 INFO L290 TraceCheckUtils]: 38: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_7~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,795 INFO L290 TraceCheckUtils]: 39: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_8~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,795 INFO L290 TraceCheckUtils]: 40: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_9~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,795 INFO L290 TraceCheckUtils]: 41: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_10~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,796 INFO L290 TraceCheckUtils]: 42: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_11~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,796 INFO L290 TraceCheckUtils]: 43: Hoare triple {179740#(= ~m_pc~0 0)} assume !(0 == ~E_12~0); {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,796 INFO L290 TraceCheckUtils]: 44: Hoare triple {179740#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {179740#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:03,796 INFO L290 TraceCheckUtils]: 45: Hoare triple {179740#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 46: Hoare triple {179739#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 47: Hoare triple {179739#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 48: Hoare triple {179739#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 49: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp~1#1); {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 50: Hoare triple {179739#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 51: Hoare triple {179739#false} assume !(1 == ~t1_pc~0); {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 52: Hoare triple {179739#false} is_transmit1_triggered_~__retres1~1#1 := 0; {179739#false} is VALID [2022-02-21 04:24:03,797 INFO L290 TraceCheckUtils]: 53: Hoare triple {179739#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 54: Hoare triple {179739#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 55: Hoare triple {179739#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 56: Hoare triple {179739#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 57: Hoare triple {179739#false} assume 1 == ~t2_pc~0; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 58: Hoare triple {179739#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 59: Hoare triple {179739#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 60: Hoare triple {179739#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {179739#false} is VALID [2022-02-21 04:24:03,798 INFO L290 TraceCheckUtils]: 61: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___1~0#1); {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 62: Hoare triple {179739#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 63: Hoare triple {179739#false} assume !(1 == ~t3_pc~0); {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 64: Hoare triple {179739#false} is_transmit3_triggered_~__retres1~3#1 := 0; {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 65: Hoare triple {179739#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 66: Hoare triple {179739#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 67: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___2~0#1); {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 68: Hoare triple {179739#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {179739#false} is VALID [2022-02-21 04:24:03,799 INFO L290 TraceCheckUtils]: 69: Hoare triple {179739#false} assume 1 == ~t4_pc~0; {179739#false} is VALID [2022-02-21 04:24:03,800 INFO L290 TraceCheckUtils]: 70: Hoare triple {179739#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {179739#false} is VALID [2022-02-21 04:24:03,800 INFO L290 TraceCheckUtils]: 71: Hoare triple {179739#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {179739#false} is VALID [2022-02-21 04:24:03,800 INFO L290 TraceCheckUtils]: 72: Hoare triple {179739#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {179739#false} is VALID [2022-02-21 04:24:03,800 INFO L290 TraceCheckUtils]: 73: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___3~0#1); {179739#false} is VALID [2022-02-21 04:24:03,800 INFO L290 TraceCheckUtils]: 74: Hoare triple {179739#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {179739#false} is VALID [2022-02-21 04:24:03,800 INFO L290 TraceCheckUtils]: 75: Hoare triple {179739#false} assume !(1 == ~t5_pc~0); {179739#false} is VALID [2022-02-21 04:24:03,800 INFO L290 TraceCheckUtils]: 76: Hoare triple {179739#false} is_transmit5_triggered_~__retres1~5#1 := 0; {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 77: Hoare triple {179739#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 78: Hoare triple {179739#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 79: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___4~0#1); {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 80: Hoare triple {179739#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 81: Hoare triple {179739#false} assume 1 == ~t6_pc~0; {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 82: Hoare triple {179739#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 83: Hoare triple {179739#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {179739#false} is VALID [2022-02-21 04:24:03,801 INFO L290 TraceCheckUtils]: 84: Hoare triple {179739#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 85: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___5~0#1); {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 86: Hoare triple {179739#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 87: Hoare triple {179739#false} assume 1 == ~t7_pc~0; {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 88: Hoare triple {179739#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 89: Hoare triple {179739#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 90: Hoare triple {179739#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 91: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___6~0#1); {179739#false} is VALID [2022-02-21 04:24:03,802 INFO L290 TraceCheckUtils]: 92: Hoare triple {179739#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 93: Hoare triple {179739#false} assume !(1 == ~t8_pc~0); {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 94: Hoare triple {179739#false} is_transmit8_triggered_~__retres1~8#1 := 0; {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 95: Hoare triple {179739#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 96: Hoare triple {179739#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 97: Hoare triple {179739#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 98: Hoare triple {179739#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 99: Hoare triple {179739#false} assume 1 == ~t9_pc~0; {179739#false} is VALID [2022-02-21 04:24:03,803 INFO L290 TraceCheckUtils]: 100: Hoare triple {179739#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 101: Hoare triple {179739#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 102: Hoare triple {179739#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 103: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___8~0#1); {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 104: Hoare triple {179739#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 105: Hoare triple {179739#false} assume !(1 == ~t10_pc~0); {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 106: Hoare triple {179739#false} is_transmit10_triggered_~__retres1~10#1 := 0; {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 107: Hoare triple {179739#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {179739#false} is VALID [2022-02-21 04:24:03,804 INFO L290 TraceCheckUtils]: 108: Hoare triple {179739#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 109: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___9~0#1); {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 110: Hoare triple {179739#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 111: Hoare triple {179739#false} assume 1 == ~t11_pc~0; {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 112: Hoare triple {179739#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 113: Hoare triple {179739#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 114: Hoare triple {179739#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 115: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___10~0#1); {179739#false} is VALID [2022-02-21 04:24:03,805 INFO L290 TraceCheckUtils]: 116: Hoare triple {179739#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 117: Hoare triple {179739#false} assume !(1 == ~t12_pc~0); {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 118: Hoare triple {179739#false} is_transmit12_triggered_~__retres1~12#1 := 0; {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 119: Hoare triple {179739#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 120: Hoare triple {179739#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 121: Hoare triple {179739#false} assume !(0 != activate_threads_~tmp___11~0#1); {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 122: Hoare triple {179739#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 123: Hoare triple {179739#false} assume 1 == ~M_E~0;~M_E~0 := 2; {179739#false} is VALID [2022-02-21 04:24:03,806 INFO L290 TraceCheckUtils]: 124: Hoare triple {179739#false} assume !(1 == ~T1_E~0); {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 125: Hoare triple {179739#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 126: Hoare triple {179739#false} assume !(1 == ~T3_E~0); {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 127: Hoare triple {179739#false} assume !(1 == ~T4_E~0); {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 128: Hoare triple {179739#false} assume !(1 == ~T5_E~0); {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 129: Hoare triple {179739#false} assume !(1 == ~T6_E~0); {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 130: Hoare triple {179739#false} assume !(1 == ~T7_E~0); {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 131: Hoare triple {179739#false} assume !(1 == ~T8_E~0); {179739#false} is VALID [2022-02-21 04:24:03,807 INFO L290 TraceCheckUtils]: 132: Hoare triple {179739#false} assume !(1 == ~T9_E~0); {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 133: Hoare triple {179739#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 134: Hoare triple {179739#false} assume !(1 == ~T11_E~0); {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 135: Hoare triple {179739#false} assume !(1 == ~T12_E~0); {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 136: Hoare triple {179739#false} assume !(1 == ~E_M~0); {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 137: Hoare triple {179739#false} assume !(1 == ~E_1~0); {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 138: Hoare triple {179739#false} assume !(1 == ~E_2~0); {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 139: Hoare triple {179739#false} assume !(1 == ~E_3~0); {179739#false} is VALID [2022-02-21 04:24:03,808 INFO L290 TraceCheckUtils]: 140: Hoare triple {179739#false} assume !(1 == ~E_4~0); {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 141: Hoare triple {179739#false} assume 1 == ~E_5~0;~E_5~0 := 2; {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 142: Hoare triple {179739#false} assume !(1 == ~E_6~0); {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 143: Hoare triple {179739#false} assume !(1 == ~E_7~0); {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 144: Hoare triple {179739#false} assume !(1 == ~E_8~0); {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 145: Hoare triple {179739#false} assume !(1 == ~E_9~0); {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 146: Hoare triple {179739#false} assume !(1 == ~E_10~0); {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 147: Hoare triple {179739#false} assume !(1 == ~E_11~0); {179739#false} is VALID [2022-02-21 04:24:03,809 INFO L290 TraceCheckUtils]: 148: Hoare triple {179739#false} assume !(1 == ~E_12~0); {179739#false} is VALID [2022-02-21 04:24:03,810 INFO L290 TraceCheckUtils]: 149: Hoare triple {179739#false} assume { :end_inline_reset_delta_events } true; {179739#false} is VALID [2022-02-21 04:24:03,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:03,810 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:03,810 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939729604] [2022-02-21 04:24:03,810 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939729604] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:03,811 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:03,811 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:03,811 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603472097] [2022-02-21 04:24:03,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:03,811 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:03,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:03,812 INFO L85 PathProgramCache]: Analyzing trace with hash -615241702, now seen corresponding path program 1 times [2022-02-21 04:24:03,812 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:03,812 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938622359] [2022-02-21 04:24:03,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:03,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:03,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:03,840 INFO L290 TraceCheckUtils]: 0: Hoare triple {179741#true} assume !false; {179741#true} is VALID [2022-02-21 04:24:03,840 INFO L290 TraceCheckUtils]: 1: Hoare triple {179741#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {179741#true} is VALID [2022-02-21 04:24:03,840 INFO L290 TraceCheckUtils]: 2: Hoare triple {179741#true} assume !false; {179741#true} is VALID [2022-02-21 04:24:03,840 INFO L290 TraceCheckUtils]: 3: Hoare triple {179741#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 4: Hoare triple {179741#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 5: Hoare triple {179741#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 6: Hoare triple {179741#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 7: Hoare triple {179741#true} assume !(0 != eval_~tmp~0#1); {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 8: Hoare triple {179741#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 9: Hoare triple {179741#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 10: Hoare triple {179741#true} assume 0 == ~M_E~0;~M_E~0 := 1; {179741#true} is VALID [2022-02-21 04:24:03,841 INFO L290 TraceCheckUtils]: 11: Hoare triple {179741#true} assume !(0 == ~T1_E~0); {179741#true} is VALID [2022-02-21 04:24:03,842 INFO L290 TraceCheckUtils]: 12: Hoare triple {179741#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {179741#true} is VALID [2022-02-21 04:24:03,842 INFO L290 TraceCheckUtils]: 13: Hoare triple {179741#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {179741#true} is VALID [2022-02-21 04:24:03,842 INFO L290 TraceCheckUtils]: 14: Hoare triple {179741#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {179741#true} is VALID [2022-02-21 04:24:03,842 INFO L290 TraceCheckUtils]: 15: Hoare triple {179741#true} assume !(0 == ~T5_E~0); {179741#true} is VALID [2022-02-21 04:24:03,842 INFO L290 TraceCheckUtils]: 16: Hoare triple {179741#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,843 INFO L290 TraceCheckUtils]: 17: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,843 INFO L290 TraceCheckUtils]: 18: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,843 INFO L290 TraceCheckUtils]: 19: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~T9_E~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,843 INFO L290 TraceCheckUtils]: 20: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,844 INFO L290 TraceCheckUtils]: 21: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,844 INFO L290 TraceCheckUtils]: 22: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,844 INFO L290 TraceCheckUtils]: 23: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_M~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,844 INFO L290 TraceCheckUtils]: 24: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,845 INFO L290 TraceCheckUtils]: 25: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,845 INFO L290 TraceCheckUtils]: 26: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,845 INFO L290 TraceCheckUtils]: 27: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_4~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,846 INFO L290 TraceCheckUtils]: 28: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,846 INFO L290 TraceCheckUtils]: 29: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,846 INFO L290 TraceCheckUtils]: 30: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,846 INFO L290 TraceCheckUtils]: 31: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_8~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,847 INFO L290 TraceCheckUtils]: 32: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,847 INFO L290 TraceCheckUtils]: 33: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,847 INFO L290 TraceCheckUtils]: 34: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,848 INFO L290 TraceCheckUtils]: 35: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 == ~E_12~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,848 INFO L290 TraceCheckUtils]: 36: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,848 INFO L290 TraceCheckUtils]: 37: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~m_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,848 INFO L290 TraceCheckUtils]: 38: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,849 INFO L290 TraceCheckUtils]: 39: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,849 INFO L290 TraceCheckUtils]: 40: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,849 INFO L290 TraceCheckUtils]: 41: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp~1#1); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,850 INFO L290 TraceCheckUtils]: 42: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,850 INFO L290 TraceCheckUtils]: 43: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t1_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,850 INFO L290 TraceCheckUtils]: 44: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,850 INFO L290 TraceCheckUtils]: 45: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,851 INFO L290 TraceCheckUtils]: 46: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,851 INFO L290 TraceCheckUtils]: 47: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,851 INFO L290 TraceCheckUtils]: 48: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,852 INFO L290 TraceCheckUtils]: 49: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t2_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,852 INFO L290 TraceCheckUtils]: 50: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,852 INFO L290 TraceCheckUtils]: 51: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,853 INFO L290 TraceCheckUtils]: 52: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,853 INFO L290 TraceCheckUtils]: 53: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,853 INFO L290 TraceCheckUtils]: 54: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,854 INFO L290 TraceCheckUtils]: 55: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t3_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,854 INFO L290 TraceCheckUtils]: 56: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,854 INFO L290 TraceCheckUtils]: 57: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,854 INFO L290 TraceCheckUtils]: 58: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,855 INFO L290 TraceCheckUtils]: 59: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,855 INFO L290 TraceCheckUtils]: 60: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,855 INFO L290 TraceCheckUtils]: 61: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t4_pc~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,856 INFO L290 TraceCheckUtils]: 62: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,856 INFO L290 TraceCheckUtils]: 63: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,856 INFO L290 TraceCheckUtils]: 64: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,856 INFO L290 TraceCheckUtils]: 65: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,857 INFO L290 TraceCheckUtils]: 66: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,857 INFO L290 TraceCheckUtils]: 67: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t5_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,857 INFO L290 TraceCheckUtils]: 68: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,858 INFO L290 TraceCheckUtils]: 69: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,858 INFO L290 TraceCheckUtils]: 70: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,858 INFO L290 TraceCheckUtils]: 71: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,859 INFO L290 TraceCheckUtils]: 72: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,859 INFO L290 TraceCheckUtils]: 73: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t6_pc~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,859 INFO L290 TraceCheckUtils]: 74: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,859 INFO L290 TraceCheckUtils]: 75: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,860 INFO L290 TraceCheckUtils]: 76: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,860 INFO L290 TraceCheckUtils]: 77: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,860 INFO L290 TraceCheckUtils]: 78: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,860 INFO L290 TraceCheckUtils]: 79: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t7_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,861 INFO L290 TraceCheckUtils]: 80: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,861 INFO L290 TraceCheckUtils]: 81: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,861 INFO L290 TraceCheckUtils]: 82: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,862 INFO L290 TraceCheckUtils]: 83: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,862 INFO L290 TraceCheckUtils]: 84: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,862 INFO L290 TraceCheckUtils]: 85: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t8_pc~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,862 INFO L290 TraceCheckUtils]: 86: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,863 INFO L290 TraceCheckUtils]: 87: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,863 INFO L290 TraceCheckUtils]: 88: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,863 INFO L290 TraceCheckUtils]: 89: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,864 INFO L290 TraceCheckUtils]: 90: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,864 INFO L290 TraceCheckUtils]: 91: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t9_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,864 INFO L290 TraceCheckUtils]: 92: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,864 INFO L290 TraceCheckUtils]: 93: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,865 INFO L290 TraceCheckUtils]: 94: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,865 INFO L290 TraceCheckUtils]: 95: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(0 != activate_threads_~tmp___8~0#1); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,865 INFO L290 TraceCheckUtils]: 96: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,865 INFO L290 TraceCheckUtils]: 97: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~t10_pc~0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,866 INFO L290 TraceCheckUtils]: 98: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,866 INFO L290 TraceCheckUtils]: 99: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,866 INFO L290 TraceCheckUtils]: 100: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,867 INFO L290 TraceCheckUtils]: 101: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,868 INFO L290 TraceCheckUtils]: 102: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,868 INFO L290 TraceCheckUtils]: 103: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t11_pc~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,868 INFO L290 TraceCheckUtils]: 104: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,868 INFO L290 TraceCheckUtils]: 105: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,869 INFO L290 TraceCheckUtils]: 106: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,869 INFO L290 TraceCheckUtils]: 107: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,869 INFO L290 TraceCheckUtils]: 108: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,870 INFO L290 TraceCheckUtils]: 109: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~t12_pc~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,870 INFO L290 TraceCheckUtils]: 110: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,870 INFO L290 TraceCheckUtils]: 111: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,871 INFO L290 TraceCheckUtils]: 112: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,872 INFO L290 TraceCheckUtils]: 113: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,872 INFO L290 TraceCheckUtils]: 114: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,872 INFO L290 TraceCheckUtils]: 115: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,875 INFO L290 TraceCheckUtils]: 116: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T1_E~0); {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,875 INFO L290 TraceCheckUtils]: 117: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,875 INFO L290 TraceCheckUtils]: 118: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,876 INFO L290 TraceCheckUtils]: 119: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,876 INFO L290 TraceCheckUtils]: 120: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {179743#(= (+ (- 1) ~T6_E~0) 0)} is VALID [2022-02-21 04:24:03,876 INFO L290 TraceCheckUtils]: 121: Hoare triple {179743#(= (+ (- 1) ~T6_E~0) 0)} assume !(1 == ~T6_E~0); {179742#false} is VALID [2022-02-21 04:24:03,876 INFO L290 TraceCheckUtils]: 122: Hoare triple {179742#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 123: Hoare triple {179742#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 124: Hoare triple {179742#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 125: Hoare triple {179742#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 126: Hoare triple {179742#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 127: Hoare triple {179742#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 128: Hoare triple {179742#false} assume 1 == ~E_M~0;~E_M~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 129: Hoare triple {179742#false} assume !(1 == ~E_1~0); {179742#false} is VALID [2022-02-21 04:24:03,877 INFO L290 TraceCheckUtils]: 130: Hoare triple {179742#false} assume 1 == ~E_2~0;~E_2~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,878 INFO L290 TraceCheckUtils]: 131: Hoare triple {179742#false} assume 1 == ~E_3~0;~E_3~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,878 INFO L290 TraceCheckUtils]: 132: Hoare triple {179742#false} assume 1 == ~E_4~0;~E_4~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,878 INFO L290 TraceCheckUtils]: 133: Hoare triple {179742#false} assume 1 == ~E_5~0;~E_5~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,878 INFO L290 TraceCheckUtils]: 134: Hoare triple {179742#false} assume 1 == ~E_6~0;~E_6~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,878 INFO L290 TraceCheckUtils]: 135: Hoare triple {179742#false} assume 1 == ~E_7~0;~E_7~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,878 INFO L290 TraceCheckUtils]: 136: Hoare triple {179742#false} assume 1 == ~E_8~0;~E_8~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 137: Hoare triple {179742#false} assume !(1 == ~E_9~0); {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 138: Hoare triple {179742#false} assume 1 == ~E_10~0;~E_10~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 139: Hoare triple {179742#false} assume 1 == ~E_11~0;~E_11~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 140: Hoare triple {179742#false} assume 1 == ~E_12~0;~E_12~0 := 2; {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 141: Hoare triple {179742#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 142: Hoare triple {179742#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 143: Hoare triple {179742#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {179742#false} is VALID [2022-02-21 04:24:03,885 INFO L290 TraceCheckUtils]: 144: Hoare triple {179742#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 145: Hoare triple {179742#false} assume !(0 == start_simulation_~tmp~3#1); {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 146: Hoare triple {179742#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 147: Hoare triple {179742#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 148: Hoare triple {179742#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 149: Hoare triple {179742#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 150: Hoare triple {179742#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 151: Hoare triple {179742#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {179742#false} is VALID [2022-02-21 04:24:03,886 INFO L290 TraceCheckUtils]: 152: Hoare triple {179742#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {179742#false} is VALID [2022-02-21 04:24:03,887 INFO L290 TraceCheckUtils]: 153: Hoare triple {179742#false} assume !(0 != start_simulation_~tmp___0~1#1); {179742#false} is VALID [2022-02-21 04:24:03,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:03,888 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:03,888 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938622359] [2022-02-21 04:24:03,888 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [938622359] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:03,888 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:03,888 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:03,888 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367262343] [2022-02-21 04:24:03,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:03,889 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:03,889 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:03,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:03,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:03,890 INFO L87 Difference]: Start difference. First operand 11666 states and 17082 transitions. cyclomatic complexity: 5424 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)